JP6781745B2 - Manufacturing method of imaging device - Google Patents

Description

The present invention relates to the production how the imaging equipment.

It is known to form silicon nitride that functions as an antireflection layer on the photoelectric conversion unit in order to efficiently utilize the light incident on the photoelectric conversion unit. Patent Document 1 describes that hexachlorodisilane (HCD) is used as a raw material gas to form silicon nitride on a photoelectric conversion unit by a reduced pressure CVD (LP-CVD) method.

Japanese Unexamined Patent Publication No. 2013-84693

When silicon nitride is formed on the photoelectric conversion section using hexachlorodisilane as in Patent Document 1, the dark output characteristics of the pixels change when the photoelectric conversion section is exposed to very strong light depending on the composition of the silicon nitride. Sometimes. The dark output of the solid-state image sensor may change. An object of the present invention is to provide a technique advantageous for stabilizing the characteristics of an imaging device.

In view of the above problems, according to some embodiments, in the method of manufacturing an image pickup apparatus, a step of forming a photoelectric conversion portion on a substrate and a silicon nitride layer covering at least a part of the photoelectric conversion portion are formed. The silicon nitride layer contains chlorine, and the number of bonded nitrogen atoms among the silicon atoms contained in at least a part of the silicon nitride layer is 1 in at least a part of the silicon nitride layer. The proportion of silicon atoms that are 2, 2 or 3 and are not bonded to oxygen atoms is 20% or less, and the silicon nitride layer is hydrogen for terminating the dangling bond of the photoelectric conversion unit. A production method is provided , which is a supply source and is characterized in that the silicon nitride layer is formed by using a process gas containing hexachlorodisilane (HCD) and a nitrogen-containing gas .

The above means provide an advantageous technique for stabilizing the characteristics of the imaging device.

The figure explaining the structural example of the image pickup apparatus which concerns on embodiment of this invention, and the circuit configuration example of the pixel arranged in the imaging apparatus. The plan view and the sectional view which show the structural example of the image pickup apparatus of 1st Embodiment. The figure explaining the relationship between the chlorine concentration of a silicon nitride layer and a dark current, and the relationship between the ratio of SiNx bond of a silicon nitride layer, and the change of dark output before and after applying light. The figure explaining the relationship between the binding energy obtained as a result of XPS measurement, and the photoelectron intensity. It is a figure explaining the main example of the 1st bond type to the 5th bond type of the bond state of 5 silicon atoms for analyzing the bond state of a silicon nitride film. FIG. 4 is a diagram illustrating the relationship between binding energy and strength obtained as a result of fitting FIG. 4 with respect to a predetermined peak position. The cross-sectional view which shows the example of the manufacturing method of the image pickup apparatus of 1st Embodiment. The cross-sectional view which shows the example of the manufacturing method of the image pickup apparatus of 1st Embodiment. The cross-sectional view which shows the example of the manufacturing method of the image pickup apparatus of 1st Embodiment. The figure explaining the relationship between the ammonia / hexachlorodisilane ratio in the process gas of the film formation condition of the silicon nitride layer, and the ratio of SiNx bond of a silicon nitride layer. Sectional drawing of the image pickup apparatus of 2nd Embodiment.

Specific first embodiments and examples of the imaging apparatus according to the present invention will be described with reference to the accompanying drawings. In the following description and drawings, common reference numerals are given to common configurations across a plurality of drawings. Therefore, a common configuration will be described with reference to each other of the plurality of drawings, and the description of the configuration with a common reference numeral will be omitted as appropriate.

The configuration of the image pickup apparatus according to the first embodiment of the present invention and the manufacturing method thereof will be described with reference to FIGS. 1 to 10. FIG. 1A is a diagram showing a configuration example of the image pickup apparatus 1000 according to the first embodiment of the present invention. The image pickup apparatus 1000 includes a pixel area 1 in which a plurality of pixels 10 are arranged, and a peripheral circuit area 2 in which peripheral circuits for processing signals output from the pixels 10 are arranged. The pixel region 1 and the peripheral circuit region 2 are formed on the same substrate 100. The substrate 100 is a semiconductor substrate such as silicon. In FIG. 1A, the region surrounded by the alternate long and short dash line is the pixel region 1, and the region between the alternate long and short dash line is the peripheral circuit region 2. It can be said that the peripheral circuit region 2 is located around the pixel region 1 and is located between the pixel region 1 and the edge of the substrate 100. The pixel area 1 shown in FIG. 1A shows an example of an area sensor in which a plurality of pixels 10 are arranged in a two-dimensional array. Instead of this, the pixel region 1 may be a linear sensor in which a plurality of pixels 10 are arranged in a one-dimensional direction.

FIG. 1B is a diagram showing a circuit configuration example of each pixel 10 arranged in the pixel region 1. The pixel 10 includes a photoelectric conversion unit 11, a transfer element 12, a capacitance element 13, an amplification element 15, a reset element 16, and a selection element 17. The photoelectric conversion unit 11 converts the incident light into an electric signal. In this embodiment, the photodiode formed on the substrate 100 is used as the photoelectric conversion unit 11.

Transistors formed on the substrate 100 are used as the amplification element 15, the reset element 16, and the selection element 17, respectively. In the present specification, each transistor arranged in the pixel 10 is referred to as a pixel transistor. As the pixel transistor, an insulated gate type field-effect transistor (MISFET) can be used. For example, among the MISFETs, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) in which silicon oxide is used for the gate insulating film may be used. However, the gate insulating film is not limited to this, and may be, for example, silicon nitride. Further, for example, the gate insulating film may be a so-called high dielectric constant gate insulating film such as hafnium oxide. Further, the gate insulating film may be laminated or may be a compound such as silicon oxynitride.

The transfer element 12 has a MOS type gate structure. Therefore, when the transfer element 12 is a gate, the photoelectric conversion unit 11 is a source, and the capacitance element 13 is a drain, this structure can be regarded as a transistor. Therefore, the photoelectric conversion unit 11, the transfer element 12, and the capacitance element 13 can be called a pixel transistor.

The transfer element 12 transfers the signal charge generated by the photoelectric conversion unit 11 to the capacitance element 13. The capacitance element 13 functions as a charge-voltage conversion element that generates a voltage in the node 14 according to the capacitance and the amount of signal charge. The gate of the amplification element 15 is connected to the capacitance element 13 via the node 14. Further, the drain of the amplification element 15 is connected to the power supply line 21, and the source of the amplification element 15 is connected to the output line 22 via the selection element 17. The gates of the capacitance element 13 and the amplification element 15 are connected to the power supply line 21 via the reset element 16. By turning on the reset element 16, the potential of the node 14 corresponds to the potential of the power supply line 21. Will be reset to. Further, by turning on the selection element 17, a signal corresponding to the potential of the node 14 is output from the amplification element 15 to the output line 22. The configuration of the pixel 10 is not limited to the configuration shown in FIG. 1B, and it is sufficient that an electric signal generated by the photoelectric conversion unit 11 can be output to the peripheral circuit region 2 according to the incident light.

In the present embodiment, the pixel transistor uses a MOSFET (nMOSFET) having an n-type channel (inversion layer), but a pMOSFET having a p-type channel may be included. Further, the pixel transistor may include a transistor other than the MOSFET. For example, the amplification element 15 may be a junction field effect transistor (JFET) or a bipolar transistor.

In the following description of the present specification, the conductive type that matches the conductive type in which the charge treated as the signal charge in the pixel region 1 is a large number of carriers is the first conductive type, and the conductive type in which the charge treated as the signal charge is a minority carrier. The conductive type corresponding to is called the second conductive type. For example, when electrons are used as signal charges, the n-type is the first conductive type and the p-type is the second conductive type.

Returning to FIG. 1A again, the peripheral circuit region 2 will be described. A signal processing unit 40 for processing an electric signal generated by the pixel 10 is arranged in the peripheral circuit area 2. Further, in the peripheral circuit area 2, the output unit 50 for outputting the signal processed by the signal processing unit 40 to the outside of the image pickup apparatus 1000, the pixel area 1 in which a plurality of pixels 10 are arranged, and the signal processing unit 40 A control unit 60 for controlling the above is included. The signal processing unit 40, the output unit 50, and the control unit 60 may be referred to as peripheral circuits.

In the present embodiment, the signal processing unit 40 selects and outputs the outputs from the amplifier circuit 41 having a plurality of column amplifiers, the conversion circuit 42 having a plurality of AD converters, and the conversion circuit 42 to the output unit 50. The horizontal scanning circuit 43 of the above is included. The signal processing unit 40 can perform correlated double sampling (CDS) processing, parallel-serial conversion processing, analog-digital conversion processing, and the like. The output unit 50 includes an electrode pad and a protection circuit. The control unit 60 includes a vertical scanning circuit 61 and a timing generation circuit 62. The configuration of the peripheral circuit region 2 is not limited to this, and it is sufficient that the electric signal generated by each pixel 10 of the pixel region 1 can be appropriately processed and output to the outside of the image pickup apparatus 1000.

The peripheral circuit can be configured by using a plurality of transistors, for example, a MISFET or the like like a pixel transistor, and can be configured by a complementary MOS (CMOS) circuit including an nMOSFET and a pMOSFET. In the present specification, the transistors constituting the peripheral circuit are referred to as peripheral transistors, and when the conductive type is specified, they are referred to as peripheral nMOSFETs and peripheral pMOSFETs. Further, the peripheral circuit may include not only active elements such as transistors and diodes but also passive elements such as resistance elements and capacitive elements.

Next, the structure of the image pickup apparatus 1000 of the present embodiment will be described with reference to FIG. 2A and 2B are a plan view and a cross-sectional view showing a part of the pixel region 1 and the peripheral circuit region 2, respectively.

In FIG. 2A, the region 101 corresponds to the photoelectric conversion unit 11, the region 103 corresponds to the capacitance element 13 and the node 14 for detecting the electric charge, and the region 106 corresponds to the drain region of the reset element 16. The region 104 corresponds to the source region of the amplification element 15, the region 105 corresponds to the drain region of the amplification element 15, and the region 107 corresponds to the source of the selection element 17. Further, the region 103 also serves as the source of the reset element 16, and the region 104 also serves as the drain region of the selection element 17. The gate electrode 111 corresponds to the gate of the transfer element 12, the gate electrode 120 corresponds to the gate of the reset element 16, the gate electrode 112 corresponds to the gate of the amplification element 15, and the gate electrode 131 corresponds to the gate of the selection element 17. The regions 108 and 109 correspond to the source / drain regions of the peripheral nMOSFET or the peripheral pMOSFET, respectively. Further, the gate electrodes 121 and 122 correspond to the gates of the peripheral nMOSFET or the peripheral pMOSFET. In this embodiment, each gate electrode is made of polysilicon (polycrystalline silicon). Further, in the present embodiment, the gate electrode 121 and the gate electrode 122 are integrally formed, but they may be formed independently of each other. Regions 103 to 109 corresponding to the respective gate electrodes and source / drain regions are connected to wiring (not shown) via conductive members 311, 312, 313, and 314 embedded in contact holes 301, 302, 303, and 304. Will be done.

In FIG. 2A, the reference contact area 102 of the pixel 10 may be arranged in the pixel area 1. The reference contact region 102 supplies a reference potential such as a ground potential to the pixel 10 via wiring (not shown). By arranging the plurality of reference contact regions 102 in the pixel region 1, it is possible to suppress the variation in the reference potential in the pixel region 1 and suppress the occurrence of shading in the captured image.

Further, in FIG. 2A, a resistance element 110 may be arranged in the peripheral circuit region 2. The resistance element 110 is an impurity region formed on the substrate 100, and by providing contacts at both ends of the impurity region, resistance can be obtained according to the impurity concentration, the distance between the contacts, and the width of the impurity region. In the present embodiment, the impurity region of the resistance element 110 is an n-type impurity region of the first conductive type formed in the p-type well of the second conductive type. Instead, the impurity region of the resistance element 110 may be a p-type impurity region formed in the n-type well. Further, a resistance element composed of an n-type impurity region and a resistance element composed of a p-type impurity region may coexist. A passive element other than the resistance element 110, such as a capacitive element or a resistance element having a MOS structure made of polysilicon, may be arranged in the peripheral circuit region 2.

In the present embodiment, the regions 101, 103, the regions 104, 105, 106, 107 corresponding to the source / drain regions of the pixel transistors, the reference contact region 102, and the regions 108 corresponding to the source / drain regions of the peripheral nMOSFETs are n-type. It is an impurity region of. Further, the region 109 corresponding to the source / drain region of the peripheral pMOSFET is a p-type impurity region.

FIG. 2B shows a cross-sectional view taken along the line AB shown in FIG. 2A. The substrate 100 is a semiconductor substrate such as silicon as described above. The substrate 100 is divided into a plurality of active regions by the element separation region 99. The device separation region 99 may be composed of an insulator for device separation formed by a shallow trench isolation (STI) method, a selective oxidation (LOCOS) method, or the like. Impurity regions are formed in each active region, and each impurity region constitutes a semiconductor device. Therefore, an impurity region (for example, a p-type impurity region) for performing pn junction separation may be provided as the element separation region.

In the active region of the substrate 100, wells having a conductive type corresponding to the conductive type of each element are arranged. A p-type well 118 is arranged in the pixel area 1, and a p-type well 129 and an n-type well 130 are arranged in the peripheral circuit area 2, respectively. Further, in the reference contact region 102 shown in FIG. 2A, a p-type impurity region having a higher impurity concentration than the p-type well 118 is arranged. A reference potential is supplied to the well 118 from the wiring connected to the reference contact region 102 via the reference contact region 102.

Next, the cross-sectional structure of the pixel region 1 and the peripheral circuit region 2 will be described with reference to FIG. 2 (b). In FIG. 2B and FIGS. 7 to 8 described later, the pixel region 1 and the peripheral circuit region 2 are shown adjacent to each other for explanation. First, the cross-sectional structure of the pixel region 1 will be described. An n-type storage region 115 constituting the photoelectric conversion unit 11 is arranged in the region 101. The storage region 115 forms a pn junction together with the p-type well 118, and functions as a photodiode of the photoelectric conversion unit 11. A p-type surface region 119 for forming the photoelectric conversion unit 11 into an embedded photodiode is arranged between the storage region 115 and the surface of the substrate 100. An impurity region 116 constituting the capacitive element 13 is arranged in the region 103. The impurity region 116 is a floating diffusion region. An n-type impurity region 117 is arranged as a source / drain region of the amplification element 15, the reset element 16, and the selection element 17, respectively. Although the cross section of the amplification element 15 is shown in FIG. 2B, the reset element 16 and the selection element 17 may have the same configuration.

The gate insulating film of the element such as the gate insulating films 113, 114 and other pixel transistors of the pixel 10 is mainly made of silicon oxide, but a small amount (for example, less than 10%) is obtained by the plasma nitriding method or the thermoacid nitriding method. It can be silicon oxide containing nitrogen. Since silicon oxide containing nitrogen has a higher dielectric constant than pure silicon oxide, the driving ability of the transistor can be improved. However, the configuration of the gate insulating film is not limited to this, and the gate insulating film may be pure silicon oxide or silicon nitride. Further, as described above, a high dielectric constant material such as hafnium oxide may be used, or a compound or a laminated film of these materials may be used. The upper surfaces of the gate electrodes 111 and 112 arranged on the substrate 100 via the gate insulating films 113 and 114 are covered with insulating layers 201 and 202 containing silicon oxide or silicon nitride.

An insulating film 210 including a silicon oxide layer 211 and a silicon nitride layer 212 is arranged on the pixel region 1. The silicon oxide layer 211 is an insulating layer containing silicon and oxygen. The silicon nitride layer 212 is an insulating layer containing chlorine as well as silicon and nitrogen. The silicon nitride layer 212 may further contain oxygen. The insulating film 210 covers the upper surfaces of the gate electrodes 111 and 112 via the insulating layers 201 and 202, and covers the side surfaces of the gate electrodes 111 and 112 without passing through the insulating layers 201 and 202. That is, the silicon nitride layer 212 extends from above the photoelectric conversion unit 11 onto the amplification element 15. The silicon nitride layer 212, which will be described later, has an advantageous effect not only on improving the characteristics of the photoelectric conversion unit 11 but also on improving the characteristics of the amplification element 15. Although the insulating film 210 is not shown in FIG. 2B, it also covers the upper surfaces and side surfaces of the gate electrodes 120 and 131. Further, the insulating film 210 covers the region 101 constituting the photoelectric conversion unit 11 and the regions 103 to 107 corresponding to the source / drain regions of the respective pixel transistors. In this case, the distance between the lower surface of the portion of the silicon nitride layer 212 that covers the region 101 constituting the photoelectric conversion unit 11 and the surface of the substrate 100 is greater than the distance between the upper surface of the gate electrode of the pixel transistor and the surface of the substrate 100. Also becomes smaller. The smaller the distance between the silicon nitride layer 212 and the substrate 100, the greater the influence of the composition of the silicon nitride layer 212. The distance between the silicon nitride layer 212 and the substrate 100 can be relatively defined by comparison with the upper surface of the gate electrode as described above. The distance between the silicon nitride layer 212 and the substrate 100 is typically less than 100 nm and may be less than 50 nm or less than 25 nm.

The insulating film 210 is a laminated film of the silicon oxide layer 211 and the silicon nitride layer 212. The silicon oxide layer 211 and the silicon nitride layer 212 have an interface in contact with each other. In the present embodiment, the silicon oxide layer 211 is in contact with the side surfaces of the gate electrodes 111, 112, 120, 131, but is different between the silicon oxide layer 211 and the side surfaces of the gate electrodes 111, 112, 120, 131. Layers may be sandwiched. Further, the silicon oxide layer 211 is in contact with the region 101 constituting the photoelectric conversion unit 11 and the regions 103 to 107 corresponding to the source / drain regions of the respective pixel transistors, and constitutes an interface with the substrate 100. , Another layer may intervene.

It is a laminated film of a silicon oxide layer 211 having a refractive index of about 1.4 to 1.5 for light having a wavelength of 633 nm and a silicon nitride layer 212 having a refractive index of about 1.9 to 2.1 for the same light. The insulating film 210 covers the region 101 constituting the photoelectric conversion unit 11. As a result, the insulating film 210 can be used as an antireflection layer for light incident on the photoelectric conversion unit 11. In order to obtain good antireflection properties, the thickness of the silicon nitride layer 212 may be greater than or equal to the thickness of the silicon oxide layer 211. Further, the thickness of the silicon nitride layer 212 may be larger than the thickness of the silicon oxide layer 211.

A protective film 240 is arranged on the insulating film 210 so as to cover the insulating film 210. The protective film 240 may be a single-layer film or a laminated film of an insulator such as silicon oxide or silicon nitride. A silicon oxide layer 221 is arranged on the protective film 240 so as to cover the protective film 240. An insulating film 230 is arranged on the silicon oxide layer 221 so as to cover the silicon oxide layer 221. The insulating film 230 can be, for example, silicate glass such as BPSG, BSG, PSG, or silicon oxide. The upper surface of the insulating film 230 is a flat surface that does not substantially reflect the unevenness of the underlying surface.

Contact holes 301 and 303 penetrating the insulating film 230, the silicon oxide layer 221 and the protective film 240 and the insulating film 210 are formed. Conductive members 311 and 313 for electrically connecting the wiring (not shown) and the pixel transistor are arranged in the contact holes 301 and 303. In the configuration shown in FIG. 2A, the conductive member 311 is connected to the regions 103 to 107 corresponding to the source / drain region of the pixel transistor and the reference contact region 102, respectively, and the conductive member 313 has the gate electrodes 111 and 112, respectively. It is connected to 120 and 131, respectively. The conductive members 311 and 313 are contact plugs mainly composed of a metal such as tungsten.

Here, the concentration of chlorine contained in the silicon nitride layer 212 of the insulating film 210 and the bonding state of silicon will be described. The present inventors have experimentally found that the characteristics of the image pickup apparatus change depending on the concentration of chlorine contained in the silicon nitride layer 212. Specifically, when the silicon nitride layer 212 containing chlorine covers the region 101, the dangling bond of the photoelectric conversion unit 11 is terminated by hydrogen or chlorine contained in the silicon nitride layer 212, and the dark current of the image pickup apparatus 1000 is reduced. Can be made to. Since the silicon nitride layer 212 reduces the interface state of the transistor channel with respect to the amplification element 15 covered by the silicon nitride layer 212, the noise characteristics of the amplification element 15 can be improved.

The relationship between the chlorine concentration of the silicon nitride layer 212 and the dark current will be described with reference to FIG. 3A. The horizontal axis of FIG. 3A shows the chlorine concentration of the silicon nitride layer 212, and the vertical axis shows the value of dark current. The values on the vertical axis are standardized so that the value of the dark current when the chlorine concentration is 0 atomic% is 1. From FIG. 3A, it can be seen that the dark current of the photoelectric conversion unit 11 decreases as the chlorine concentration of the silicon nitride layer 212 increases. Therefore, by including chlorine in the silicon nitride layer 212, the level of dark current can be reduced as compared with the case where chlorine is not contained in the silicon nitride layer 212. Therefore, in the present embodiment, the silicon nitride layer 212 contains chlorine. When chlorine is significantly contained in the silicon nitride layer 212, the typical chlorine concentration is 0.1 atomic% or more, and more typically 0.3 atomic% or more. The chlorine concentration of the silicon nitride layer 212 may be less than 1 atomic%. In order to reduce the dark current, the chlorine concentration of the silicon nitride layer 212 may be 1atomic% or more, 2atomic% or more, or 3atomic% or more. Further, when the chlorine concentration of the silicon nitride layer 212 becomes extremely high, the stability and the transmittance decrease. Therefore, the chlorine concentration of the silicon nitride layer 212 may be 10 atomic% or less, or 6 atomic% or less. May be good. In particular, when the chlorine concentration is higher than 3atomic%, the light absorption coefficient (k value) of the incident light at a wavelength of 450 nm increases, so that the chlorine concentration may be 3atomic% or less.

Further, the inventors have experimentally found that the characteristics of the image pickup apparatus also change depending on the bonding state of silicon contained in the silicon nitride layer 212 of the insulating film 210. A silicon atom (Si atom) having one, two or three bonded nitrogen atoms (N atoms) and not bonded to an oxygen atom (O atom) is called a SiNx bond. When the ratio of SiNx bonds among the silicon atoms contained in the silicon nitride layer 212 increases, the ratio of dangling bonds contained in the silicon nitride layer 212 increases. In the following description, the silicon nitride layer 212 covering the region 101 functions as a charge trap layer and absorbs photoelectrons generated by incident light. Due to the absorption of photoelectrons, the region of the silicon nitride layer 212 that receives light toward the photoelectric conversion unit 11 deteriorates, and the output characteristics of the image pickup apparatus 1000 change in the subsequent photographing.

FIG. 3B is a diagram for explaining the relationship between the ratio of SiNx bonds in the silicon nitride layer 212 and the amount of change in dark output before and after exposure to light. The horizontal axis of FIG. 3B shows the ratio of SiNx coupling, and the vertical axis shows the value obtained by subtracting the dark output (current value) before shining light from the dark output (current value) after shining light. The values on the vertical axis are standardized so that the amount of change is 1 when the ratio of SiNx bonds is 25%. The circle plot is the amount of change in the dark output of the red pixel (that is, the pixel that detects red light; the same applies to other colors), the triangular plot is the amount of change in the dark output of the green pixel, and the square plot is the amount of change in the blue pixel. The amount of change in the dark output of is shown. From FIG. 3B, it can be seen that when the ratio of SiNx binding is 20% or less, the amount of change in dark output is significantly reduced as compared with the case where the ratio of SiNx binding is larger than 20%. Specifically, when the amount of change in dark current when the ratio of SiNx coupling is 25% is 1, the amount of change in dark current is almost the same when the ratio of SiNx coupling is 0% or more and 20% or less. It becomes 0. Therefore, in the present embodiment, the ratio of SiNx binding is set to 0% or more and 20% or less.

X-ray Photoelectron Spectroscopy (XPS) can be used to measure the bonding state of silicon atoms. XPS is a method for obtaining knowledge about the types, abundances, and chemical states of elements on the sample surface from the kinetic energy distribution of photoelectrons emitted by soft X-ray irradiation. In XPS, the binding energy of the sample surface irradiated with X-rays can be known by analyzing the kinetic energy distribution of photoelectrons, and the element on the sample surface can be identified from the binding energy peculiar to the element.

FIG. 4A is a diagram for explaining the intensity distribution of binding energies obtained by analyzing silicon nitride films (sample 1 and sample 2) formed under different conditions with respect to Si2p orbitals by XPS (narrow scan mode). The horizontal axis of FIG. 4A shows the binding energy, and the vertical axis shows the strength. FIG. 4B is an enlarged view of a part of FIG. 4A.

Comparing the peak positions of the binding energies of Sample 1 and Sample 2, the peak position of the binding energy of Sample 1 is about 101.55 eV, and the peak position of the binding energy of Sample 2 is about 101.65 eV. In order to analyze the bonding state of silicon atoms from this result, in the case of a silicon nitride film, peak separation is typically performed by five types of peaks. Specifically, in order to analyze the bonding state of the silicon nitride film, the following five types are fitted by the least squares method, and the area ratios are compared. FIG. 5 is a diagram showing the main examples of the five bond types, and only the bond hand of the central silicon atom is shown. Examples of binding types are not limited to those shown in FIG.

-First bond type: A silicon atom that is bonded only to other silicon atoms.
The peak position of the binding energy is about 99.4 eV. FIG. 5A shows a main example of the first binding type. In this example, the silicon atom is bonded to each of the four hands of the silicon atom.

-Second bond type: A silicon atom having one, two or three bonded nitrogen atoms and not bonded to an oxygen atom (SiNx bond described above).
The peak position of the binding energy is about 101.0 eV. FIG. 5B shows a main example of the second binding type. In the left example, attached nitrogen atom to each of the three bonds of the silicon atoms, the silicon atoms to the remaining one bond, a carbon atom, a fluorine atom, or a chlorine atom or a hydrogen atom is bonded, Or the remaining one bond is a dangling bond . In the middle example, the nitrogen atom is bonded to each of the two bonds of silicon atoms, each of the remaining two bonds, silicon atoms, carbon atoms, a fluorine atom, bonded to a chlorine atom or a hydrogen atom Or it is a dangling bond . What is connected to the remaining two bonds may be the same or different from each other. For example, silicon atoms are connected to one bond may be connected carbon atoms in another bond. The same applies to the other binding examples shown below. On the right, the nitrogen atom is bonded to one bond of silicon atom, each of the remaining three bonds, silicon atoms, carbon atoms, a fluorine atom, or bound to a chlorine atom or a hydrogen atom, Or it is a dangling bond .

-Third bond type: A silicon atom that is bonded to four nitrogen atoms.
The peak position of the binding energy is about 101.8 eV. FIG. 5C shows a main example of the third binding type. In this example, a nitrogen atom is attached to each of the four hands of the silicon atom.

-Fourth bond type: A silicon atom that is bonded to at least one oxygen atom and at least one nitrogen atom.
The peak position of the binding energy is about 102.7 eV. FIG. 5D shows a main example of the fourth bond type. In this example, a nitrogen atom is attached to one hand of a silicon atom, an oxygen atom is attached to another hand, and a silicon atom, a carbon atom, a fluorine atom, a chlorine atom, and a hydrogen are attached to each of the other two hands. Atoms or dangling bonds are bonded.

-Fifth bond type: A silicon atom that is bonded to four oxygen atoms.
The peak position of the binding energy is about 103.6 eV. FIG. 5 (e) shows a main example of the fifth binding type. In this example, an oxygen atom is attached to each of the four hands of the silicon atom.

In FIG. 6, legends 1 to 5 represent first-bond type to fifth-join type, respectively. The values at these peak positions are typical examples, and the values may be slightly different. For example, a silicon atom having a peak position of binding energy higher than 100.5 eV and lower than 101.4 eV may be used as the second binding type. Further, the number of binding energies used for peak separation is not limited to five. If the silicon nitride film has other bonds that are expected to be present, binding energy corresponding to the other bonds may be added to the fitting. A known relationship between the binding state and the corresponding binding energy may be used. In the present embodiment, 20% of the silicon atoms contained in the silicon nitride layer 212 have a peak position of binding energy measured by X-ray photoelectron spectroscopy higher than 100.5 eV and lower than 101.4 eV. Make sure that: As a result, the ratio of SiNx coupling can be reduced to 20% or less, and the amount of change in dark current can be made almost zero.

FIG. 6A shows the results derived for Sample 1 by the above-mentioned fitting method. It can be seen that the second bond type silicon atom occupies an area ratio of about 24% of the whole. From this result, it can be seen that the ratio of SiNx bonds to the silicon atoms contained in the silicon nitride film of sample 1 is about 24%. FIG. 6B is the result derived from the sample 2 by the above-mentioned fitting method. It can be seen that when fitting a plurality of waveforms having different binding energy peak positions, the ratio of the waveform corresponding to the second binding type silicon atom to the total area of the plurality of waveforms is about 16%. .. From this result, it can be seen that the ratio of SiNx bonds to the silicon atoms contained in the silicon nitride film of sample 2 is about 16%. Although XPS has been described as a method for measuring the bonded state of silicon atoms, the bonded state of silicon atoms may be measured by an equivalent measuring method, not limited to XPS.

Next, the cross-sectional structure of the peripheral circuit region 2 will be described. An n-type impurity region 125, an n-type impurity region 126, and a silicide layer 134 are arranged in a region 108 corresponding to the source / drain region of the peripheral nMOSFET. The impurity region 125 has a higher impurity concentration than the impurity region 126. The silicide layer 134 covers the impurity region 125. A p-type impurity region 127, a p-type impurity region 128, and a silicide layer 135 are arranged in a region 109 corresponding to a source / drain region of a peripheral pMOSFET. The impurity region 127 has a higher impurity concentration than the impurity region 128. The silicide layer 135 covers the impurity region 127. As described above, the peripheral transistor has a lightly Doped Drain (LDD) structure due to the high-concentration impurity regions 125 and 127 and the low-concentration impurity regions 126 and 128.

The gate electrodes 121 and 122 are arranged on the substrate 100 via the gate insulating films 123 and 124. In the present embodiment, the gate insulating film is silicon oxide containing silicon oxide as a main material and a trace amount (for example, less than 10%) of nitrogen by plasma nitriding method or thermoacid nitriding method, like the pixel transistor of pixel 10. .. The thickness of the gate insulating films 123 and 124 of the peripheral transistor may be equal to or less than the thickness of the gate insulating films 113 and 114 of the pixel transistor. For example, the thicknesses of the gate insulating films 113 and 114 may be 5.0 nm or more and 10 nm or less, and the thicknesses of the gate insulating films 123 and 124 may be 1.0 nm or more and 5.0 nm or less. By making the thickness of the gate insulating film different between the pixel transistor and the peripheral transistor, it is possible to improve the withstand voltage of the pixel transistor and the drive speed of the peripheral transistor at the same time. Silicide layers 132 and 133 that form a part of the gate electrodes 121 and 122 are arranged on the upper surfaces of the gate electrodes 121 and 122. As described above, the peripheral transistor can have a salicide (Self ALIgned siliCIDE) structure in which the silicide layers 132, 133, 134, and 135 are formed. As the metal component constituting the VDD layer, titanium, nickel, cobalt, tungsten, molybdenum, tantalum, chromium, palladium, platinum and the like can be used.

The side surfaces of the gate electrodes 121 and 122 of the peripheral transistor are covered with the sidewall 215. The sidewall 215 also covers the low concentration impurity regions 126, 128 of the regions 108, 109. In the present embodiment, the sidewall 215 has a laminated structure including a silicon oxide layer 213 and a silicon nitride layer 214. The silicon oxide layer 213 is located between the silicon nitride layer 214 and the gate electrodes 121 and 122, and between the silicon nitride layer 214 and the regions 108 and 109. The silicon oxide layer 213 and the silicon nitride layer 214 have an interface in contact with each other.

An insulating film 220 including a silicon oxide layer 221 and a silicon nitride layer 222 (second silicon nitride layer) is arranged on the peripheral circuit region 2. In the present embodiment, the insulating film 220 is a laminated film of the silicon oxide layer 221 and the silicon nitride layer 222. The silicon oxide layer 211 and the silicon nitride layer 212 have an interface in contact with each other. However, the insulating film 220 may be a single-layer film of the silicon nitride layer 222. The silicon oxide layer 221 is located between the silicon nitride layer 214 and the silicon nitride layer 222. The silicon nitride layer 214 and the silicon oxide layer 221 have an interface in contact with each other. That is, the sidewall 215 and the insulating film 220 have an interface in contact with each other. Further, the insulating film 220 covers the silicide layers 134 and 135 of the regions 108 and 109. The insulating film 220 and the silicide layers 134 and 135 of the regions 108 and 109 have an interface in contact with each other. In the present embodiment, the VDD layers 134 and 135 are arranged, but the VDD layers 134 and 135 may not be arranged. In this case, the insulating film 220 covers the high-concentration impurity regions 125 and 127. The insulating film 220 and the high-concentration impurity regions 125 and 127 have interfaces in contact with each other. The insulating film 230 is arranged on the insulating film 220 as in the pixel region 1. Contact holes 302 and 304 penetrating the insulating film 220 including the insulating film 230, the silicon oxide layer 221 and the silicon nitride layer 222 are formed. In the contact holes 302 and 304, conductive members 312 and 314 that electrically connect the wiring (not shown) and the region 108 which is the source / drain region of the peripheral transistor and the gate electrodes 121 and 122 are arranged. Like the conductive members 311 and 313, the conductive members 312 and 314 are contact plugs mainly composed of a metal such as tungsten.

A wiring pattern (not shown) including wiring connected to the conductive members 311, 312, 313, and 314 is arranged on the insulating film 230. As for the wiring pattern, a plurality of wiring patterns may be laminated via the interlayer insulating film. The wiring pattern can be composed of metals such as aluminum and copper. Further, a color filter (not shown), a microlens (not shown), or the like may be arranged on the side of the light receiving surface of the substrate 100 on which the light is incident. Since these configurations can be formed by using existing techniques, description thereof will be omitted here. The image pickup device 1000 is housed in a package, for example, and an image pickup system such as a device or an information terminal incorporating this package can be constructed.

Next, a method of manufacturing the image pickup apparatus 1000 will be described with reference to FIGS. 7 to 9. 7 to 9 are cross-sectional views of the image pickup apparatus 1000 in each manufacturing process. First, as shown in FIG. 7A, a pixel transistor and a peripheral transistor are formed. In the step of forming the pixel transistor and the peripheral transistor, the element separation region 99 is formed on the substrate 100 by using the STI method, the LOCOS method, or the like. The substrate 100 may be a silicon wafer cut out from a silicon ingot, or a wafer in which a single crystal silicon layer is epitaxially grown on the silicon wafer. After forming the element separation region 99, the second conductive type (p type) wells 118 and 129 and the first conductive type (n type) wells 130 are formed.

After the wells 118, 129, and 130 are formed, the gate insulating films 113, 114, 123, 124 are formed, and polysilicon is formed on the gate insulating films 113, 114, 123, 124. The gate insulating films 113, 114, 123, 124 may be formed simultaneously in the pixel region 1 and the peripheral circuit region 2. Further, as described above, in order to make the film thickness different between the pixel region 1 and the peripheral circuit region 2, they may be formed by using different steps. Next, impurities are implanted into each portion of the polysilicon gate electrode according to the conductive type of the corresponding transistor by using an ion implantation method or the like. After injection of impurities, insulating layers 201, 202, 203, 204 serving as a hard mask are formed on each portion of polysilicon gate electrodes 111, 112, 121, 122. Then, the polysilicon of the opening is etched using the insulating layers 201, 202, 203, and 204 as masks. By this step, n-type gate electrodes 111, 112, 121 and p-type gate electrodes 122 are formed.

Next, an n-type storage region 115 and a p-type surface region 119 are formed. Further, an impurity region 116 of the region 103 and an n-type impurity region 117 having a single drain structure serving as a source / drain region of the pixel transistor are formed. Further, a low-concentration n-type impurity region 126 and a p-type impurity region 128 of the LDD structure of the peripheral transistor are formed. The dose amount when forming the impurity regions 116 and 117 of the pixel 10 may be 5 × 10 ^{12 to} 5 × 10 ¹⁴ (ions / cm ² ), and further, 1 × 10 ¹³ to 1 × 10 ¹⁴ (1 × 10 ¹³ to 1 × 10 ¹⁴ ). It may be ions / cm ² ). Further, the dose amount when forming the low-concentration impurity regions 126 and 128 constituting the LDD structure may be 5 × 10 ^{12 to} 5 × 10 ¹⁴ (ions / cm ² ), and further, 1 × 10 ^It may be ¹³ to 1 × 10 ¹⁴ (ions / cm ² ). Therefore, the impurities in the impurity regions 116 and 117 and the impurity regions 126 may be injected in parallel. Further, the order of injecting impurities into the accumulation region 115, the impurity region 116, 117, 126, 128, and the surface region 119 may be any order.

Next, as shown in FIG. 7B, an insulating film 210 including the silicon oxide layer 211 and the silicon nitride layer 212 is formed. The insulating film 210 includes the upper surfaces and side surfaces of the gate electrodes 111, 112, 121, 122, and regions 103, 104, 105, 108, 109 and regions 101, which are source / drain regions of the pixel transistors and peripheral transistors, respectively. cover. Impurity regions 116, 117, 126, 128 are formed in the source / drain region by the step shown in FIG. 7A, respectively, and the insulating film 210 covers the impurity regions 116, 117, 126, 128, respectively. Become.

The insulating film 210 is a laminated film of the silicon oxide layer 211 and the silicon nitride layer 212, and the silicon oxide layer 211 and the silicon nitride layer 212 are formed so as to be in contact with each other. The step of forming the insulating film 210 includes a step of forming the silicon oxide layer 211 and a step of forming the silicon nitride layer 212. As described above, since the insulating film 210 is used as an antireflection layer, it covers at least the region 101 to be the photoelectric conversion unit 11, and in order to obtain good antireflection characteristics, the thickness of the silicon nitride layer 212 is set to the silicon oxide layer. It may be thicker than 211. For example, the thickness of the silicon oxide layer 211 may be 5 nm or more and 20 nm or less, and the thickness of the silicon nitride layer 212 may be 20 nm or more and 100 nm or less.

In this embodiment, the silicon oxide layer 211 and the silicon nitride layer 212 are formed by using a chemical vapor deposition (CVD) method. The silicon oxide layer 211 is formed by using a reduced pressure CVD (LPCVD) method, which is a thermal CVD method in which the pressure (deposition pressure) of a process gas containing a source gas such as TEOS is set in the range of 20 Pa or more and 200 Pa or less. .. At this time, the film formation temperature (substrate temperature) may be in the range of 500 ° C. or higher and 800 ° C. or lower. Here, the process gas means the entire gas in the film forming chamber including at least the source gas and the carrier gas added as needed. As the carrier gas, a rare gas such as helium or argon, nitrogen or the like can be used. Further, the film forming pressure means the pressure (total pressure) of the process gas in the film forming chamber.

The silicon nitride layer 212 is formed by the LPCVD method using, for example, a process gas containing ammonia (NH ₃ ) and hexachlorodisilane (HCD) as a source gas. At this time, the pressure of the process gas (deposition pressure) may be in the range of 20 Pa or more and 200 Pa or less, and the film formation temperature (substrate temperature) may be in the range of 500 ° C or more and 800 ° C or less. Ammonia is an example of a nitrogen-containing gas, and other nitrogen-containing gases may be used.

As described above, in order to reduce the dark current and its output change, the silicon nitride layer 212 used as the antireflection film contains chlorine, and the ratio of SiNx bonds in the silicon atoms to the silicon nitride layer 212 is 20% or less. It is good to be. A method for forming such a silicon nitride layer 212 will be described below.

FIG. 10 is a diagram illustrating the relationship between the ammonia (NH ₃ ) / hexachlorodisilane (HCD) ratio in the process gas used for producing the silicon nitride layer 212 and the ratio of SiNx bonds in the silicon nitride layer 212. The horizontal axis of FIG. 10 shows the ammonia / hexachlorodisilane ratio in the process gas, and the vertical axis shows the ratio of SiNx bonds. As can be read from FIG. 10, when the ammonia / hexachlorodisilane ratio is 60 or more, the ratio of SiNx bonds is 20%. Therefore, in order to reduce the SiNx bond of the silicon nitride layer 212 to 20% or less, the ammonia (NH ₃ ) / hexachlorodisilane (HCD) ratio is preferably 60 or more. The upper limit of this ratio is not specified, but may be less than 120, for example. In order to make the ammonia / hexachlorodisilane ratio 60 or more, for example, the following film forming conditions can be adopted.

Film formation temperature: 550 to 650 ° C
HCD: 10-40 sccm
NH ₃ : 1000-3000 sccm
Film formation pressure: 20 to 30 Pa
In the above example, ammonia was used as the nitrogen-containing gas. Generally, when the nitrogen-containing gas / hexachlorodisilane ratio in the process gas is 60 or more, the ratio of SiNx bonds is 20%.

The ratio of SiNx bonds can be changed by increasing or decreasing the flow rates of HCD and NH ₃ in the process gas. In addition to increasing or decreasing the flow rates of HCD and NH ₃ , it is possible to reduce the ratio of SiNx bonds by increasing the number of silicon atoms bonded to oxygen atoms. Specifically, the process gas for forming the silicon nitride layer 212 may further include an oxygen-containing gas. Further, the silicon nitride layer 212 may be formed by forming a silicon nitride film using a process gas containing hexachlorodisilane and then annealing the silicon nitride film with an oxygen-containing gas. By such an annealing treatment, it is possible to reduce the proportion of silicon atoms.

Here, the silicon nitride layer 212 formed by using a process gas containing hexachlorodisilane (HCD) and ammonia (NH ₃ ) in the source gas is as shown in Patent Document 1 in addition to silicon, nitrogen and chlorine. Contains a lot of hydrogen. Therefore, the silicon nitride layer 212 can serve as a hydrogen supply source for terminating the dangling bond of the pixel transistor. Further, at least when the silicon nitride layer 212 is formed, the composition ratio of chlorine in the silicon nitride layer 212 may be lower than the composition ratio of each of silicon, nitrogen and hydrogen. In other words, the composition ratio of hydrogen in the silicon nitride layer 212 may be higher than the composition ratio of chlorine in the silicon nitride layer 212. The composition ratio of hydrogen in the silicon nitride layer 212 may be higher or lower than the composition ratio of silicon and the composition ratio of nitrogen in the silicon nitride layer 212. Since hydrogen is a light element, hydrogen in the silicon nitride layer 212 does not have to be included in the stoichiometric composition of the silicon nitride layer 212.

After forming the insulating film 210, sidewalls 215 are formed on the side surfaces of the gate electrodes 121 and 122 of the peripheral transistors. First, as shown in FIG. 7B, a mask pattern 410 is formed on the insulating film 210 by using, for example, a photoresist. The mask pattern 410 is formed so as to cover at least a part of the region 101 that becomes the photoelectric conversion unit 11 of the pixel region 1. By covering at least a part of the region 101 with the mask pattern 410, the silicon nitride layer 212 having a SiNx bond ratio of 20% or less and containing chlorine remains on at least a part of the region 101. In the present embodiment, the mask pattern 410 covers the pixel region 1 including the regions 101, 103, 104, 105 and has an opening in the peripheral circuit region 2. Next, the insulating film 210 at the opening of the mask pattern 410 is etched (etched back). By removing the mask pattern 410 after etching, sidewalls 215 covering the side surfaces of the gate electrodes 121 and 122 of the peripheral transistors shown in FIG. 7C are formed. The sidewall 215 can be a laminate of the silicon oxide layer 213 and the silicon nitride layer 214 (third silicon nitride layer). The silicon oxide layer 213 is a part of the silicon oxide layer 211 of the insulating film 210, and the silicon nitride layer 214 is a part of the silicon nitride layer 212 of the insulating film 210. Therefore, the ratio of SiNx bonds and the chlorine concentration are equal to each other in the silicon nitride layer 212 and the silicon nitride layer 214.

In the etching for forming the sidewall 215, the regions forming the impurity regions 125 and 127 out of the regions 108 are exposed. Further, in this etching step, the region where the resistance element 110 shown in FIG. 2A is formed is exposed.

During the etching forming the sidewall 215, the mask pattern 410 covers the region 101, so that the upper portion of the insulating film 210 over the region 101 remains. As a result, damage to the photoelectric conversion unit 11 during etching can be suppressed, and noise generated in the photoelectric conversion unit 11 can be reduced. Further, by covering the gate electrodes 111 and 112 and the regions 103 and 104 with the mask pattern 410, the insulating film 210 arranged on the channel regions 141 and 142 and the source / drain region of the pixel transistor remains. As a result, damage during etching to the pixel transistors can be suppressed, and noise generated in each pixel transistor can be reduced.

In the etching for forming the sidewall 215, after the region forming the impurity region 125, 127 of the region 108 is exposed, a self-aligned high-concentration impurity region 125, 127 is formed along the side surface of the sidewall 215. To do. A mask pattern covering the pixel region 1 and the peripheral pMOSFET is formed, and n-type impurities are implanted using the mask pattern, the gate electrode 121, and the sidewall 215 as masks by an ion implantation method or the like. As a result, the impurity region 125 of the peripheral nMOSFET is formed. Further, a mask pattern covering the pixel region 1 and the peripheral nMOSFET is formed, and the p-type impurities are implanted by using the mask pattern, the gate electrode 122, and the sidewall 215 as masks by an ion implantation method or the like. As a result, the impurity region 127 of the peripheral pMOSFET is formed. The order in which the impurity region 125 and the impurity region 127 are formed is arbitrary. The dose amount for forming the high-concentration impurity regions 125 and 127 constituting the LDD structure may be 5 × 10 ^{14 to} 5 × 10 ¹⁶ (ions / cm ² ), and further, 1 × 10 ¹⁵ to 1 × 10. It may be 1 × 10 ¹⁶ (ions / cm ² ). The dose amount when forming the impurity regions 125 and 127 is higher than the dose amount when forming the impurity regions 126 and 128 described above. As a result, the impurity concentration in the impurity regions 125 and 127 is higher than the impurity concentration in the impurity regions 126 and 128.

When forming at least one of the impurity region 125 and the impurity region 127, impurities may be injected into the region for forming the resistance element 110 at the same time. As a result, the resistance element 110 as a diffusion resistance is formed. The impurity concentration is low in the dose amount when forming the impurity regions 126 and 128, and there is a possibility that the resistance value of the resistance element 110 cannot be lowered to a practical range. On the other hand, the dose amount when forming the impurity regions 125 and 127 can form the impurity region of the resistance element 110 having a practical resistance value. Therefore, the region where the resistance element 110 is formed is exposed during the etching for forming the sidewall 215, and the impurity region of the resistance element 110 is formed at the same time as the impurity is injected into the impurity region 125 or the impurity region 127.

After forming the LDD structure of the peripheral transistor, the protective film 240 is formed so as to cover the pixel region 1 and the peripheral circuit region 2 as shown in FIG. 8A. For the protective film 240, for example, silicon oxide or the like is used, and the thickness is about 30 nm or more and about 130 nm or less. After forming the protective film 240, a mask pattern 420 that covers the pixel region 1 is formed using a photoresist or the like. After forming the mask pattern 420, the protective film 240 at the opening portion of the mask pattern 420 is etched. By this etching, the portion of the protective film 240 located above the regions 108 and 109 and the portion located above the gate electrodes 121 and 122 are removed. At this time, the portion of the protective film 240 located above the pixel region 1 and the portion located above the resistance element 110 are left. Following the etching of the protective film 240, the insulating layers 203 and 204 covering the upper surfaces of the gate electrodes 121 and 122 are removed. The etching of the insulating layers 203 and 204 may be performed at the same time as the etching of the protective film 240, or may be performed separately. After etching the protective film 240 and the insulating layers 203 and 204, the mask pattern 420 is removed.

Next, as shown in FIG. 8B, the metal film 250 is formed by using a sputtering method, a CVD method, or the like so as to cover the substrate 100. The metal film 250 is formed so as to be in contact with the upper surfaces of the regions 108 and 109 and the gate electrodes 121 and 122, and contains a metal for silicating the upper surfaces of the regions 108 and 109 and the gate electrodes 121 and 122. Further, the metal film 250 is in contact with the protective film 240 on the pixel region 1 and the resistance element 110 that are not silicinated. The metal film 250 may have a laminated structure of a metal for silicidation and a metal compound for suppressing oxidation of the metal. For example, the metal film 250 may be a laminated film of cobalt and titanium nitride for suppressing the oxidation of cobalt.

After the metal film 250 is formed, the substrate 100 is heated to about 500 ° C. to react the metal film 250 with the regions 108 and 109 in contact with the metal film 250 and the gate electrodes 121 and 122. As a result, the silicide layers 132, 133, 134, and 135 in the mono silicide state are formed. After that, the unreacted metal film 250 located on the protective film 240 and the sidewall 215 is removed. Further, when a layer of a metal compound for suppressing the oxidation of the metal is formed on the metal film 250, the layer of the metal compound is also removed. After removing the unreacted metal film 250, the substrate 100 is heated to about 800 ° C., which is higher than the temperature used in the first silicidization, and the VDD layers 132, 133, 134, and 135 are changed from the mono silicide state to the die silicide state. Change to. In the present embodiment, heating is performed twice at different temperatures, but the silicide layers 132, 133, 134, and 135 may be formed by heating once. The conditions for silicidation may be appropriately selected depending on the type of metal for forming silicide and the like.

In the silicidizing step, in the pixel region 1 or the resistance element 110 in which the protective film 240 remains, the metal film 250 does not come into contact with the substrate 100 or the gate electrode, so that the silicide layer is not formed. The protective film 240 thus functions as a silicide block. Since the silicide layer can cause noise in the pixel region 1, the pixel region 1 is covered with the protective film 240 at the time of silicidation. In particular, the region 101 that becomes the photoelectric conversion unit 11, the region 103 that becomes the node 14 for detecting the electric charge, and the regions 104 and 105 that become the source / drain regions of the amplification element 15 are not silicidized. Further, the resistance element 110 is also protected by the protective film 240 because the resistance value may become too small. After forming the silicide layers 132, 133, 134, 135, the protective film 240 may be removed. Further, in order to avoid unnecessary damage to the pixel region 1, it is not necessary to remove the protective film 240. In the present embodiment, the protective film 240 remains as shown in FIG. 8 (c).

After forming the silicide layers 132, 133, 134, and 135, the insulating film 220 including the silicon oxide layer 221 and the silicon nitride layer 222 is formed as shown in FIG. 9A. The insulating film 220 includes the upper surfaces of the gate electrodes 111, 112, 121, 122, the sidewall 215, and regions 103, 104, 105, 108, 109, and regions 101, which are source / drain regions of the pixel transistor and the peripheral transistor, respectively. And cover.

The insulating film 220 is a laminated film of the silicon oxide layer 221 and the silicon nitride layer 222. The silicon oxide layer 221 and the silicon nitride layer 222 are formed so as to be in contact with each other. The step of forming the insulating film 220 includes a step of forming the silicon oxide layer 221 and a step of forming the silicon nitride layer 222. The thickness of the silicon nitride layer 222 may be greater than or equal to the thickness of the silicon oxide layer 221. The thickness of the silicon nitride layer 222 may be at least twice the thickness of the silicon oxide layer 221. For example, the thickness of the silicon oxide layer 211 may be 10 nm or more and 30 nm or less, and the thickness of the silicon nitride layer 212 may be 20 nm or more and 100 nm or less.

The silicon oxide layer 211 uses a quasi-normal pressure CVD (SA-CVD) method, which is a thermal CVD method in which the pressure (deposition pressure) of a process gas containing a source gas such as TEOS is in the range of 200 Pa or more and 600 Pa or less. Is formed. At this time, the film formation temperature (substrate temperature) may be in the range of 400 ° C. or higher and 500 ° C. or lower. As described above, both the silicon oxide layer 211 and the silicon oxide layer 221 can be formed by using the thermal CVD method.

The silicon nitride layer 222 is formed by the LPCVD method using, for example, a process gas containing ammonia (NH ₃ ) and hexachlorodisilane (HCD) as a source gas. At this time, the pressure of the process gas (deposition pressure) may be in the range of 20 Pa or more and 200 Pa or less, and the film formation temperature (substrate temperature) may be in the range of 500 ° C or more and 800 ° C or less.

The silicon nitride layer 222 can also function as a chlorine supply film that stably supplies chlorine to peripheral transistors. The thick silicon nitride layer 222 can contain abundant chlorine, and the thin silicon oxide layer 221 can appropriately permeate chlorine. Further, as described above, the silicon nitride layer 222 formed by using a process gas containing hexachlorodisilane (HCD) and ammonia (NH ₃ ) in the source gas contains a large amount of hydrogen. Therefore, it is possible to form a peripheral transistor having excellent noise characteristics.

After forming the insulating film 220, as shown in FIG. 9A, a mask pattern 430 is formed using a photoresist or the like so as to cover the portion located in the peripheral circuit region 2 of the insulating film 220. Next, the portion of the silicon nitride layer 212 arranged in the pixel region 1 is removed by etching through the opening of the mask pattern 430. The portion of the silicon nitride layer 212 from which the silicon nitride layer 212 is removed is a portion of the silicon nitride layer 212 located above the photoelectric conversion unit 11, the transfer element 12, the capacitance element 13, the amplification element 15, the reset element 16, and the selection element 17. Including. At this time, the silicon oxide layer 221 can function as an etching stopper when the silicon nitride layer 222 covering the pixel region 1 is removed by etching. The silicon oxide layer 221 can also function as a protective layer that protects the pixel region 1 from damage caused by etching. The silicon nitride layer 222 arranged on at least the photoelectric conversion unit 11 in the pixel region 1 is removed.

Next, the insulating film 230 is formed so as to cover the pixel region 1 and the peripheral circuit region 2. The insulating film 230 is a single-layer film of silicon oxide formed by a plasma CVD method such as a high density plasma (HPD) CVD method. The insulating film 230 can be formed from any material such as a BPSG film, a BSG film, and a PSG film. Further, the film is not limited to a single-layer film and may be a multi-layer film.

Then, as shown in FIG. 9B, the surface of the insulating film 230 is flattened. As a flattening method, a chemical mechanical polishing (CMP) method, a reflow method, an etchback method, or the like is used. These methods may be used in combination. The thickness of the insulating film 230 before flattening can be, for example, in the range of 200 nm or more and 1700 nm or less. In the present embodiment, since the portion of the silicon nitride layer 222 located above the pixel region 1 is removed by the above step, the height difference between the underlying pixel region 1 of the insulating film 230 and the peripheral circuit region 2 is small. .. Therefore, the thickness of the insulating film 230 after flattening can be set to 1000 nm or less. For example, the thickness of the insulating film 230 may be 450 nm or more and 850 nm or less. By reducing the thickness of the insulating film 230, it is possible to reduce the resistance of the contact plug and improve the sensitivity. Here, the thickness of the insulating film 230 after flattening may be larger than the thickness of the insulating film 210 and the insulating film 220.

After the insulating film 230 is flattened, the conductive members 311, 312, 313, and 314 for electrically connecting the pixel transistor or the peripheral transistor and the wiring are formed. First, in the pixel region 1, the contact hole 301 for providing the conductive member 311 by opening the insulating film 230 by anisotropic dry etching through the opening of the mask pattern using a photoresist or the like covering the insulating film 230. To form. When forming the contact hole 301, the silicon nitride layer 212 of the insulating film 210 may be used as an etching stopper in the pixel region 1. The contact hole 301 is provided so as to penetrate the insulating film 230, the silicon oxide layer 221 and the protective film 240, the silicon nitride layer 212, and the silicon oxide layer 211. The contact hole 301 exposes the source / drain region and the reference contact region 102 of the capacitance element 13, the amplification element 15, the reset element 16, and the selection element 17, respectively.

In parallel with the formation of the contact hole 301, the contact hole 303 that exposes the gate electrodes of the capacitance element 13, the amplification element 15, the reset element 16, and the selection element 17 is formed. The contact hole 303 for providing the conductive member 313 penetrates the insulating film 230, the silicon oxide layer 221 and the protective film 240, the silicon nitride layer 212, and the silicon oxide layer 211. Further, the contact hole for providing the conductive member 313 also penetrates the insulating layers 201 and 202. In order to reduce the contact resistance of the contact plug, impurities may be injected into the impurity region of the substrate 100 and the gate electrode through the contact hole.

Prior to the formation of the contact hole 301, the silicon nitride layer 222 located above the pixel region 1 is removed as described above. Therefore, the silicon nitride layer does not exist in the layer above the silicon nitride layer 212 used as the etch stopper. Therefore, when forming the contact hole 301, it is possible to prevent the silicon nitride layer other than the silicon nitride layer 212 from being hindered from forming the contact hole 301.

Next, as shown in FIG. 9C, in the peripheral circuit region 2, the insulating film 230 is differentiated by using a mask pattern 440 that covers the insulating film 230 and has an opening in the region forming the contact holes 302 and 304. Opened by anisotropic dry etching. As a result, contact holes 302 and 304 for providing the conductive members 312 and 314 are formed. When forming the contact hole 302, the silicon nitride layer 222 of the insulating film 220 can be used as an etching stopper in the peripheral circuit region 2. The contact holes 302 and 304 are provided so as to penetrate the insulating film 230, the silicon nitride layer 222, and the silicon oxide layer 221. The contact hole 302 exposes the silicide layers 134 and 135 located in the regions 108 and 109 which are the source and drain regions of the peripheral transistors. In parallel with the formation of the contact hole 302, the contact hole 304 that exposes the VDD layers 132 and 133 of the gate electrodes 121 and 122 for providing the conductive member 314 is formed.

After opening the contact holes 301, 302, 303, 304, the contact holes 301, 302, 303, 304 are filled with a conductor such as metal to form conductive members 311, 312, 313, 314 that function as contact plugs. Will be done. The contact holes 301, 302, 303, 304 can be filled with the conductive members all at once.

The steps of forming the contact holes 301 and 303 in the pixel area 1 and filling the conductive members 311 and 313 and the steps of forming the contact holes 302 and 304 in the peripheral circuit area 2 and filling the conductive members 312 and 314 are separate. It may be a process. By separating the process of forming the contact plug in the pixel region 1 and the peripheral circuit region 2, the metal contained in the silicide layers 132, 133, 134, and 135 can be removed from the pixel region 1 via the contact holes 301 and 303. Contamination of impurity regions can be suppressed. Either of the order of forming the contact hole between the pixel region 1 and the peripheral circuit region 2 and forming the contact plug by filling the conductive member may come first.

By the above steps, the structures shown in FIGS. 2A and 2B can be obtained. After that, a wiring pattern, a color filter, a microlens, and the like are formed to complete the image pickup apparatus 1000. Further, a hydrogen annealing process may be added to promote the supply of hydrogen to the pixel transistor and the peripheral transistor in a state where the peripheral transistor is covered with the insulating film 220. The hydrogen annealing treatment means that the surface of the substrate 100 is hydrogen-terminated by heating the substrate 100 in a hydrogen atmosphere. The hydrogen annealing treatment may be performed after the conductive members 311, 312, 313, and 314 are formed and then the wiring pattern is further formed.

Although the first embodiment according to the present invention has been shown above, it goes without saying that the present invention is not limited to these first embodiments, and the above-described first embodiment is not deviated from the gist of the present invention. Can be changed and combined as appropriate. For example, in the above-described first embodiment, the present invention has been described by taking an imaging device as an example among semiconductor devices. However, the present invention can be applied not only to an imaging device but also to an arithmetic device, a storage device, a control device, a signal processing device, a detection device, a display device, and the like as long as it is a semiconductor device including an insulated gate type field effect transistor. it can.

Hereinafter, as an application example of the image pickup apparatus according to the first embodiment described above, an apparatus in which the image pickup apparatus 1000 is incorporated will be exemplified. The concept of equipment includes not only electronic devices such as cameras whose main purpose is shooting, but also devices having auxiliary shooting functions, such as electronic devices such as personal computers and mobile terminals, automobiles, ships, and aircraft. Transportation equipment such as is also included. By using the imaging device 1000 according to the embodiment of the present invention as a transportation device, it is possible to reduce changes in characteristics with respect to strong light such as sunlight. Therefore, in designing, manufacturing, and selling the transportation equipment, it is effective to adopt the mounting of the imaging device according to the embodiment of the present invention in order to increase the value of the transportation equipment. The device in which the image pickup apparatus 1000 is incorporated includes the image pickup apparatus 1000 according to the present invention exemplified as the first embodiment described above, and a processing unit that processes information based on a signal output from the image pickup apparatus 1000. The processing unit may include a processor that processes digital data that is image data. The processor can calculate the defocus amount based on the signal from the pixel having the focus detection function of the image pickup apparatus 1000, and perform a process for controlling the focus adjustment of the image pickup lens based on this. The A / D converter that generates the above image data can be provided on the substrate 100, or a substrate including the A / D converter may be laminated on the substrate 100 and this laminated body may be used as the image pickup apparatus 1000. A / D converter may be provided separately from the image pickup apparatus 1000. In the device in which the image pickup device 1000 is incorporated, the data obtained from the image pickup device 1000 can be displayed on the display device included in the device or stored in the storage device included in the device. Further, in the device in which the image pickup device 1000 is incorporated, a mechanical device such as a motor included in the device can be driven based on the data obtained from the image pickup device 1000.

Next, the manufacturing method of the second embodiment of the present invention will be described with reference to FIG. The second embodiment is different from the first embodiment in that it has a waveguide for increasing the light incident on the photoelectric conversion unit 11, and is common to the first embodiment in other respects. In the second embodiment, the silicon nitride layer 222 is left on the photoelectric conversion unit 11, and the silicon nitride layer 223 is used as an etching stop film for forming a waveguide.

After forming the insulating film 220, a mask pattern is formed by using a photoresist or the like so as to cover a part of the pixel region 1 of the insulating film 220 and the portion located in the peripheral circuit region 2. Next, the portion of the silicon nitride layer 212 arranged in the pixel region 1 is etched and removed through the opening of the mask pattern. A silicon nitride layer 223 arranged on at least the photoelectric conversion unit 11 in the pixel region 1 is formed.

Next, a plurality of interlayer insulating films 231, a contact plug, a first wiring layer 315, and a second wiring layer 316 including a via plug are formed. The plurality of interlayer insulating films 231 are formed by alternately laminating, for example, silicon oxide layers and silicon nitride layers. The plurality of interlayer insulating films 231 can be used as a cladding of the waveguide. The first wiring layer 315 and the second wiring layer 316 can be formed by the damascene method, for example, with a material containing copper as a main component, but may be formed with another material such as aluminum.

Next, an opening 501 is formed in the plurality of interlayer insulating films 231. The opening 501 is formed, for example, by forming a mask pattern having an opening in a region corresponding to the photoelectric conversion unit 11 on a plurality of interlayer insulating films 231 and etching the plurality of interlayer insulating films 231 using the mask pattern. Will be done. This etching is, for example, anisotropic etching. Specifically, the plasma etching process is performed on the plurality of interlayer insulating films 231 until the silicon nitride layer 223 is exposed. The silicon nitride layer 223 is a film for reducing plasma damage to the photoelectric conversion unit 11 during etching, and also functions as an etching stop film.

Next, the opening 501 is filled with a transparent material having a refractive index higher than that of the plurality of interlayer insulating films 231 to be clad, thereby forming a core portion of the waveguide for guiding light to the photoelectric conversion unit 11. .. Here, silicon nitride having a higher refractive index than silicon oxide, which is the main material constituting the plurality of interlayer insulating films 231, is formed in the opening 501, but silicon oxide may also be used. Specifically, silicon nitride is deposited on the entire surface by a high-density plasma CVD method (High Density Plasma-CVD method), whereby silicon nitride is filled in the opening 501. Silicon nitride formed in a portion other than the opening 501 can be removed by, for example, chemical mechanical polishing or plasma etching. After that, the wiring pattern, color filter, microlens, etc. are formed to complete the imaging device.

1: Pixel region, 11: Photoelectric conversion unit, 100: Substrate, 212: Silicon nitride layer, 1000: Imaging device

Claims (6)

It is a manufacturing method of an image pickup device.
The process of forming a photoelectric conversion part on the substrate and
It comprises a step of forming a silicon nitride layer covering at least a part of the photoelectric conversion part.
The silicon nitride layer contains chlorine and
In at least a part of the silicon nitride layer, among the silicon atoms contained in the at least part, the number of bonded nitrogen atoms is 1, 2, or 3, and the silicon atoms are bonded to oxygen atoms. the proportion of free silicon atoms Ri der than 20%,
The silicon nitride layer is a hydrogen supply source for terminating the dangling bond of the photoelectric conversion unit.
A production method characterized in that the silicon nitride layer is formed by using a process gas containing hexachlorodisilane (HCD) and a nitrogen-containing gas . It is a manufacturing method of an image pickup device.
The process of forming a photoelectric conversion part on the substrate and
It comprises a step of forming a silicon nitride layer covering at least a part of the photoelectric conversion part.
The silicon nitride layer contains chlorine and
The intensity distribution of the binding energy obtained by measuring the silicon nitride layer by X-ray photoelectron spectroscopy includes a first waveform in which the peak position of the binding energy is in the range of 100.5 eV to 101.4 eV, and is different from each other. when brought into fitting a plurality of waveforms having a peak position of the binding energy state, and are percentage less than 20% of the area of the first waveform to the total area of the plurality of waveforms,
The silicon nitride layer is a hydrogen supply source for terminating the dangling bond of the photoelectric conversion unit.
A production method characterized in that the silicon nitride layer is formed by using a process gas containing hexachlorodisilane (HCD) and a nitrogen-containing gas . The production method according to claim 1 or 2 , wherein the nitrogen-containing gas / hexachlorodisilane ratio in the process gas is 60 or more. The process gas further contains ammonia and
The production method according to claim 1 or 2 , wherein the ammonia / hexachlorodisilane ratio in the process gas is 60 or more. The production method according to claim 1 or 2 , wherein the process gas further contains an oxygen-containing gas . The step of forming the silicon nitride layer is
And forming a film of the film using the process gas,
Forming the silicon nitride layer by annealing the film with an oxygen-containing gas, and
The production method according to any one of claims 1 to 5 , wherein the production method comprises.