JP6755935B2 - 共有メモリコントローラおよびそれを使用する方法 - Google Patents

共有メモリコントローラおよびそれを使用する方法 Download PDF

Info

Publication number
JP6755935B2
JP6755935B2 JP2018501260A JP2018501260A JP6755935B2 JP 6755935 B2 JP6755935 B2 JP 6755935B2 JP 2018501260 A JP2018501260 A JP 2018501260A JP 2018501260 A JP2018501260 A JP 2018501260A JP 6755935 B2 JP6755935 B2 JP 6755935B2
Authority
JP
Japan
Prior art keywords
beat
transaction
command
memory access
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018501260A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018521419A (ja
Inventor
ルアン ハオ
ルアン ハオ
ギャザラー アラン
ギャザラー アラン
ヤン ビン
ヤン ビン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of JP2018521419A publication Critical patent/JP2018521419A/ja
Application granted granted Critical
Publication of JP6755935B2 publication Critical patent/JP6755935B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Software Systems (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP2018501260A 2015-07-13 2016-06-14 共有メモリコントローラおよびそれを使用する方法 Active JP6755935B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/797,620 2015-07-13
US14/797,620 US10353747B2 (en) 2015-07-13 2015-07-13 Shared memory controller and method of using same
PCT/CN2016/085754 WO2017008607A1 (en) 2015-07-13 2016-06-14 Shared memory controller and method of using same

Publications (2)

Publication Number Publication Date
JP2018521419A JP2018521419A (ja) 2018-08-02
JP6755935B2 true JP6755935B2 (ja) 2020-09-16

Family

ID=57757780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018501260A Active JP6755935B2 (ja) 2015-07-13 2016-06-14 共有メモリコントローラおよびそれを使用する方法

Country Status (5)

Country Link
US (1) US10353747B2 (zh)
EP (1) EP3311288B1 (zh)
JP (1) JP6755935B2 (zh)
CN (1) CN107835989B (zh)
WO (1) WO2017008607A1 (zh)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10200581B2 (en) * 2016-03-31 2019-02-05 Peter G. Hartwell Heads down intelligent display and processing
US10331588B2 (en) * 2016-09-07 2019-06-25 Pure Storage, Inc. Ensuring the appropriate utilization of system resources using weighted workload based, time-independent scheduling
US11481261B1 (en) 2016-09-07 2022-10-25 Pure Storage, Inc. Preventing extended latency in a storage system
US11886922B2 (en) 2016-09-07 2024-01-30 Pure Storage, Inc. Scheduling input/output operations for a storage system
US10671439B1 (en) 2016-09-07 2020-06-02 Pure Storage, Inc. Workload planning with quality-of-service (‘QOS’) integration
US10908966B1 (en) 2016-09-07 2021-02-02 Pure Storage, Inc. Adapting target service times in a storage system
US10146585B2 (en) 2016-09-07 2018-12-04 Pure Storage, Inc. Ensuring the fair utilization of system resources using workload based, time-independent scheduling
US11119923B2 (en) * 2017-02-23 2021-09-14 Advanced Micro Devices, Inc. Locality-aware and sharing-aware cache coherence for collections of processors
KR102443106B1 (ko) 2017-06-23 2022-09-14 후아웨이 테크놀러지 컴퍼니 리미티드 메모리 액세스 기술 및 컴퓨터 시스템
CN111066007B (zh) * 2017-07-07 2023-10-31 美光科技公司 对受到管理的nand的rpmb改进
KR101870916B1 (ko) * 2017-11-15 2018-07-19 (주)디 넷 차량 내 잔류승객 감지 및 경보 장치
US20190303777A1 (en) 2018-03-30 2019-10-03 Provino Technologies, Inc. Protocol level control for system on a chip (soc) agent reset and power management
EP3776231B1 (en) * 2018-03-30 2023-05-03 Google LLC Procedures for implementing source based routing within an interconnect fabric on a system on chip
FR3082029B1 (fr) * 2018-06-05 2020-07-10 Thales Controleur de partage de ressources d'une plate-forme informatique et procede associe de partage des ressources
US10732897B2 (en) 2018-07-03 2020-08-04 Western Digital Technologies, Inc. Quality of service based arbitrations optimized for enterprise solid state drives
CN109446125B (zh) * 2018-10-09 2024-04-02 武汉正维电子技术有限公司 Ddr读写仲裁器及方法
US11543262B2 (en) 2018-12-05 2023-01-03 Toyota Motor North America, Inc. Data analytics for smart vehicle fueling
US20210279192A1 (en) * 2020-03-06 2021-09-09 Infineon Technologies Ag Distribution of interconnect bandwidth among master agents
EP3926452A1 (en) * 2020-06-19 2021-12-22 NXP USA, Inc. Norflash sharing
US11720404B2 (en) * 2020-07-16 2023-08-08 Samsung Electronics Co., Ltd. Systems and methods for arbitrating access to a shared resource
US11579805B2 (en) * 2020-11-18 2023-02-14 Samsung Electronics Co., Ltd. Method and system for processing commands in storage devices to improve quality of service
US11467988B1 (en) 2021-04-14 2022-10-11 Apple Inc. Memory fetch granule
US20240143519A1 (en) * 2022-10-28 2024-05-02 Nxp B.V. Bandwidth allocation

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404553A (en) * 1991-01-09 1995-04-04 Mitsubishi Denki Kabushiki Kaisha Microprocessor and data flow microprocessor having vector operation function
JPH10507023A (ja) 1994-10-06 1998-07-07 ヴァーク・インコーポレイテッド 共用メモリシステム
KR0183748B1 (ko) 1995-10-30 1999-05-15 김광호 씨디-롬 구동 시스템의 고속 메모리 제어회로 및 그 방법
US6385678B2 (en) * 1996-09-19 2002-05-07 Trimedia Technologies, Inc. Method and apparatus for bus arbitration with weighted bandwidth allocation
US6209066B1 (en) * 1998-06-30 2001-03-27 Sun Microsystems, Inc. Method and apparatus for memory allocation in a multi-threaded virtual machine
US6195724B1 (en) 1998-11-16 2001-02-27 Infineon Technologies Ag Methods and apparatus for prioritization of access to external devices
CN1181438C (zh) 2001-01-18 2004-12-22 深圳市中兴集成电路设计有限责任公司 异步时钟域设备对共享存储装置访问的控制方法
US6961803B1 (en) 2001-08-08 2005-11-01 Pasternak Solutions Llc Sliced crossbar architecture with no inter-slice communication
US7177275B2 (en) * 2002-07-26 2007-02-13 Kenneth Stanwood Scheduling method and system for communication systems that offer multiple classes of service
US7594089B2 (en) 2003-08-28 2009-09-22 Mips Technologies, Inc. Smart memory based synchronization controller for a multi-threaded multiprocessor SoC
JP5094050B2 (ja) 2005-07-14 2012-12-12 キヤノン株式会社 メモリ制御装置、メモリ制御方法および組み込みシステム
KR100784385B1 (ko) 2005-08-10 2007-12-11 삼성전자주식회사 공유 자원에 대한 접근 요청을 중재하는 시스템 및 방법
US7489690B2 (en) * 2005-08-12 2009-02-10 Cellco Partnership Integrated packet latency aware QoS scheduling algorithm using proportional fairness and weighted fair queuing for wireless integrated multimedia packet services
CN1329809C (zh) 2005-10-25 2007-08-01 威盛电子股份有限公司 磁盘阵列的控制器及其工作方法
US7802040B2 (en) 2005-12-22 2010-09-21 Arm Limited Arbitration method reordering transactions to ensure quality of service specified by each transaction
US7356671B1 (en) 2006-07-27 2008-04-08 Vbridge Microsystem, Inc. SoC architecture for voice and video over data network applications
US7899994B2 (en) 2006-08-14 2011-03-01 Intel Corporation Providing quality of service (QoS) for cache architectures using priority information
KR20090065504A (ko) 2006-12-25 2009-06-22 파나소닉 주식회사 메모리 제어 장치, 메모리 장치 및 메모리 제어 방법
CN101277175B (zh) * 2007-03-30 2012-02-29 国际商业机器公司 改进会话启动协议服务器性能的方法和装置
WO2009014706A1 (en) 2007-07-23 2009-01-29 Rod Brittner Quality of service and streaming attributes for a data storage device
US8095932B2 (en) 2007-08-14 2012-01-10 Intel Corporation Providing quality of service via thread priority in a hyper-threaded microprocessor
CN101187908A (zh) 2007-09-27 2008-05-28 上海大学 单芯片多处理器共享数据存储空间的访问方法
JP2009193107A (ja) 2008-02-12 2009-08-27 Panasonic Corp メモリアクセス装置
US9542341B2 (en) * 2008-12-19 2017-01-10 St-Ericsson Sa Resolving contention between data bursts
CN101989241B (zh) * 2009-08-07 2012-08-08 无锡江南计算技术研究所 读-修改-写处理系统及方法
US8755394B2 (en) * 2010-05-06 2014-06-17 Ikanos Communications, Inc. Gateway device for performing communication with various devices in home networks and wide area networks
US8612648B1 (en) 2010-07-19 2013-12-17 Xilinx, Inc. Method and apparatus for implementing quality of service in a data bus interface
US8904115B2 (en) * 2010-09-28 2014-12-02 Texas Instruments Incorporated Cache with multiple access pipelines
US8607022B2 (en) 2010-12-17 2013-12-10 Apple Inc. Processing quality-of-service (QoS) information of memory transactions
US9098203B1 (en) * 2011-03-01 2015-08-04 Marvell Israel (M.I.S.L) Ltd. Multi-input memory command prioritization
KR101855399B1 (ko) 2011-03-24 2018-05-09 삼성전자주식회사 데이터 트래픽을 개선한 ＳｏＣ 및 이의 동작 방법
US20130054896A1 (en) * 2011-08-25 2013-02-28 STMicroelectronica Inc. System memory controller having a cache
KR101861768B1 (ko) 2011-09-16 2018-05-28 삼성전자주식회사 시스템 온칩, 이를 포함하는 전자 시스템, 및 그 동작 방법
CN102609312B (zh) 2012-01-10 2015-08-19 中国科学技术大学苏州研究院 基于公平性考虑的短作业优先内存请求调度方法
KR101949382B1 (ko) 2012-04-04 2019-02-18 삼성전자주식회사 서비스 품질의 향상을 위한 시스템 온 칩 및 시스템 온 칩의 제어 방법
CN103377154B (zh) 2012-04-25 2016-04-13 无锡江南计算技术研究所 存储器的访存控制装置及方法、处理器及北桥芯片
US9213656B2 (en) 2012-10-24 2015-12-15 Texas Instruments Incorporated Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
US9535832B2 (en) * 2013-04-30 2017-01-03 Mediatek Singapore Pte. Ltd. Multi-hierarchy interconnect system and method for cache system
US9330024B1 (en) * 2014-10-09 2016-05-03 Freescale Semiconductor, Inc. Processing device and method thereof
US9519442B2 (en) * 2014-10-27 2016-12-13 Aeroflex Colorado Springs Inc. Method for concurrent system management and error detection and correction requests in integrated circuits through location aware avoidance logic

Also Published As

Publication number Publication date
US20170017412A1 (en) 2017-01-19
EP3311288B1 (en) 2022-06-29
JP2018521419A (ja) 2018-08-02
CN107835989B (zh) 2020-12-01
EP3311288A4 (en) 2018-06-06
US10353747B2 (en) 2019-07-16
WO2017008607A1 (en) 2017-01-19
CN107835989A (zh) 2018-03-23
EP3311288A1 (en) 2018-04-25

Similar Documents

Publication Publication Date Title
JP6755935B2 (ja) 共有メモリコントローラおよびそれを使用する方法
EP2580669B1 (en) Multithread application-aware memory scheduling scheme for multi-core processors
KR100440657B1 (ko) 가중된대역폭할당에의한버스중재방법및장치
US8645639B2 (en) Hierarchical memory arbitration technique for disparate sources
JP2009508247A (ja) バス調停に関する方法及びシステム
JP4034969B2 (ja) 共通メモリのメモリ管理システム
US8060679B2 (en) Information processing apparatus and access control method capable of high-speed data access
JP5498505B2 (ja) データバースト間の競合の解決
KR100296718B1 (ko) 다중프로세서 시스템에서 가변폭 버스를 동시에 액세스하기 위한 방법 및 시스템
JP2005517228A (ja) スケジューリングの順序付けられたステージの基準を使用してリクエストをスケジューリングする方法及び装置
US7617344B2 (en) Methods and apparatus for controlling access to resources in an information processing system
US8180998B1 (en) System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations
US20070239888A1 (en) Controlling transmission of data
CN109002408B (zh) 总线仲裁方法和系统
US20120137078A1 (en) Multiple Critical Word Bypassing in a Memory Controller
JP6201591B2 (ja) 情報処理装置および情報処理装置の制御方法
US8918786B2 (en) Generating simulated stall signals based on access speed model or history of requests independent of actual processing or handling of conflicting requests
JP2005293427A (ja) データ転送処理装置及びデータ転送処理方法
JP5058116B2 (ja) ストリーミングｉｄメソッドによるｄｍａｃ発行メカニズム
KR100973419B1 (ko) 버스 중재 방법 및 장치
Kim et al. Efficient GPU multitasking with latency minimization and cache boosting
JP4214521B2 (ja) 情報処理システム及びマルチプロセッサ・システム
JPH05241958A (ja) 仮想記憶制御方式

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180215

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180215

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20180511

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20180511

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20181207

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190131

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190219

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190514

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20191105

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200124

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200804

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200826

R150 Certificate of patent or registration of utility model

Ref document number: 6755935

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250