JP6745106B2 - Gateway device and sensor network system - Google Patents

Description

The present disclosure relates to a sensor network system, and further to a gateway device for collecting data from a plurality of sensor nodes in a sensor network.

In recent years, a sensor network technology in which a large number of wireless terminals with sensors are scattered to collect and utilize various information in the real world is becoming a reality. In a sensor network, a gateway device (also called “control node”) for collecting data from a large number of wireless terminals with sensors (also called “sensor node”) and transmitting the collected data to another network such as the Internet. Is provided. The gateway device (control node) may be provided hierarchically.

When a control node fails, particularly when a higher control node that bundles lower control nodes fails, a large number of sensor nodes under its control lose their communication paths. Therefore, ensuring the availability of the control node is an important issue.

A failover system is widely adopted for general servers to ensure availability. Specifically, a server cluster is configured by a plurality of servers, and when a certain server fails, execution of applications and services is switched to another server that configures the cluster. On the other hand, in a sensor network, it is difficult to use a failover system such as that used by a server because it cannot secure as many resources as a server (mass storage device, broadband communication, power supply, etc.).

Japanese Patent Laying-Open No. 2009-260778 (Patent Document 1) discloses an example in which a gateway is configured with two masters and slaves to enable failover (see FIGS. 5 to 7 and related paragraphs). ). Specifically, in order to identify the master gateway and the slave gateway, different IDs (Identification) and different IP (Internet Protocol) addresses are given to the master and the slave. The sensor node switches the ID of the data transmission destination from the master to the slave when the data transmission to the master fails. The host computer connected to the master and slave gateways via the host network issues a data collection command to the corresponding gateway (master or slave) for each sensor node. The master gateway and the slave gateway exchange measurement data held by each other via a LAN (Local Area Network) or a host computer at regular intervals, in case one gateway stops due to a failure or the like. ..

JP, 2009-260778, A

One of the problems in the technique of the above-mentioned document is that the communication amount at the time of exchanging data (memory synchronization) between the master gateway and the slave gateway becomes considerably large.

One of the other problems is that the master gateway periodically saves the received data in the memory and synchronizes the memory between the master and slave gateways. This means that the data normally received by the master will be lost. For example, when performing digital filter processing that requires past data multiple times, according to the technique described in the above document, the data saved in the memory at the time of an abnormality is ignored and acquired after failover. The digital filtering process is restarted from the processed data.

Further, in the case of a protocol that returns ACK (Acknowledge) when a packet is normally received, such as ZigBee (registered trademark) in this document, it is possible to detect a packet reception failure by a timeout of ACK reception. Based on this, the sensor device can perform processing for switching the transmission destination gateway from the master to the slave. However, in the case of a protocol that does not return ACK for the purpose of low power consumption operation, even if an abnormality occurs, the sensor node or the repeater cannot switch the master and slave.

The present invention has been made in consideration of the above problems, and one of the objects thereof is to perform data synchronization between a master and a slave in a gateway device for a sensor network capable of failover. It is to suppress the amount of communication. Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

In one aspect, the present invention is a gateway device that performs wireless communication with a plurality of sensor nodes, and includes a first controller and a second controller. The first controller includes a first memory, receives measurement data from each sensor node, and stores the received measurement data in the first memory. The second controller includes a second memory, simultaneously receives the measurement data received by the first controller, and stores the received measurement data in the second memory. The first and second controllers perform data synchronization only in some areas of the memory spaces of the first memory and the second memory that contain different storage data.

According to the above configuration, since the measurement data from each sensor node is simultaneously received by the first controller and the second controller, it is not usually necessary to perform data synchronization between memories for the measurement data from the sensor node. .. Therefore, the amount of communication between the first and second controllers when performing data synchronization can be significantly reduced.

Preferably, when performing data synchronization, the first controller calculates an error detection code for each area when the memory space of the first memory is divided into a plurality of areas. The second controller calculates an error detection code for each corresponding area of the second memory when performing data synchronization. When performing data synchronization, the first controller transmits only the data in the areas having different error detection codes to the second controller.

According to the above configuration, the difference between the memories is minimized by the simultaneous reception of the data, and when the data synchronization is performed, the error detection codes are first compared, and only the data in the area where the error detection codes are different is transferred. The amount of communication between the first and second controllers can be significantly reduced.

Preferably, the gateway device further includes a wired bus connecting the first controller and the second controller. Data synchronization between the first memory and the second memory is performed via this wired bus.

Preferably, the gateway device further includes an upper communication unit that establishes a communication path between one of the first controller and the second controller and the upper network by switching the communication path. The high-order side communication unit establishes a communication path between the first controller and the high-order side network when the first controller has not failed. The upper-level communication unit establishes a communication path between the second controller and the higher-level network when the first controller is out of order. For example, in the case of Ethernet (registered trademark), this is realized by swapping the IP address between both controllers.

According to the above configuration, it is not necessary to separately perform communication between the upper network and the first controller and communication between the upper network and the second controller, so that failover between the controllers can be performed. It is not necessary to run the special program of (1) on the host computer.

Preferably, the first controller periodically sends a heartbeat to the second controller. The second controller commands the first controller to switch the communication path to the higher-level network from the first controller to the second controller when the heartbeats are not regularly received.

Preferably, the first controller communicates with the upper network according to an application program running on the operating system. When the operating system detects that the application program is frozen or the system is abnormal in the first controller, the operating system switches the communication path to the upper network from the first controller to the second controller. Command the controller 2

By monitoring the heartbeat, the program freeze, or the system abnormality as described above, the failover from the first controller to the second controller can be executed.

Preferably, each of the first memory and the second memory has a first data area for storing measurement data from each sensor node and a calculation result based on the measurement data, and a host computer via a host network. A second data area for storing data received from the. The frequency of synchronization between the first data area of the first memory and the first data area of the second memory depends on the second data area of the first memory and the second data area of the second memory. It differs from the frequency of synchronization with the data area.

By performing data synchronization at different frequencies for each data area as described above, it is possible to further reduce the amount of communication when performing data synchronization between memories.

In another aspect, the present invention is a sensor network system including a plurality of sensor nodes, each of which wirelessly transmits measurement data, and a gateway device. The gateway device includes a first controller and a second controller. The first controller includes a first memory, receives measurement data from each sensor node, and stores the received measurement data in the first memory. The second controller includes a second memory, simultaneously receives the measurement data received by the first controller, and stores the received measurement data in the second memory. The first and second controllers perform data synchronization only in some areas of the memory spaces of the first memory and the second memory that contain different storage data.

Therefore, according to the present invention, in the gateway device for the sensor network capable of failover, it is possible to suppress the communication amount when data synchronization is performed between the master and the slave.

It is a block diagram showing a schematic structure of a wireless sensor network system. It is a block diagram which shows the more detailed structure of the gateway apparatus of FIG. 6 is a flowchart showing a procedure until data transmitted from a sensor device is received by a host computer 41 via a gateway device. 6 is a flowchart showing a procedure until data from the host computer 41 is stored in the memory of the gateway device. It is a flow chart which shows an example of the procedure which performs the synchronous processing between the 1st and 2nd control units. 9 is a flowchart showing an example of a failover procedure. 7 is a flowchart showing a procedure until data transmitted from the host computer 41 is stored in the memory of the second controller after failover. 7 is a flowchart showing a procedure until data transmitted from the host computer 41 is stored in the memory of the second controller after failover when address switching of the host communication unit fails. 9 is a flowchart showing a procedure after the failover until data transmitted from the sensor device is received by the host computer 41 via the gateway device. It is a flowchart which shows the other example of a procedure of failover. It is a block diagram which shows the structure of the gateway by 2nd Embodiment. It is a figure for demonstrating the synchronizing method between memories in the gateway apparatus of 3rd Embodiment.

In this specification, the “gateway device” is assumed to have not only the function of relaying the measurement data from the sensor node to the higher level network, but also the function of storing and calculating the measurement data.

Hereinafter, embodiments will be described in detail with reference to the drawings. Note that the same or corresponding portions will be denoted by the same reference symbols and description thereof will not be repeated.

<First Embodiment>
[Configuration of sensor network]
FIG. 1 is a block diagram showing a schematic configuration of a wireless sensor network system. A wireless sensor network system (also referred to as a sensor network system in this specification) 1 includes a large number of sensor devices 10 and gateway devices 20. The sensor device 10 is also called a sensor node, and the gateway device 20 is also called a control node.

Each sensor device 10 has a built-in sensor element for detecting a physical quantity of the surroundings. Each sensor device 10 is configured as a wireless communication terminal for performing a filtering process, an A/D conversion process, and the like on a detection value of a built-in sensor element and transmitting the measurement data obtained by these processes. For communication 11 between each sensor device 10 and the gateway device 20, a communication protocol using the ZigBee (registered trademark) or Sub-GHz band is used.

Each sensor device 10 may have a relay routing function for transmitting measurement data from another sensor device 10 to the gateway device 20. Further, each sensor device 10 may have an ad hoc function for directly communicating with each other. Further, the plurality of sensor devices 10 configuring the sensor network may configure a tree type network, or may configure a mesh type network.

The gateway device 20 receives the measurement data transmitted from each of the plurality of sensor devices 10, and transmits the received measurement data to a host computer (personal computer, server, etc.) 41 via a host network 40 such as the Internet. .. Furthermore, the gateway device 20 receives control commands, setting information, and the like from the host computer 41 via the host network 40. A wired LAN (Local Area Network), WiFi (registered trademark), Bluetooth (registered trademark), or the like is used for communication 31 between the gateway device 20 and the upper network 40.

The gateway device 20 may be configured not only to simply relay the measurement data, but also to perform a calculation based on the measurement data and send the calculation result to the host computer 41. For example, the gateway device 20 performs digital filter processing of measurement data sent from a single sensor device 10 at a plurality of times, or performs complex arithmetic processing of a plurality of measurement data sent from a plurality of sensor devices 10. To go. The gateway device 20 may be configured to transmit the measurement data obtained by performing these calculations to the host computer 41.

As will be described in detail below, the gateway device 20 includes a plurality of control units in order to enhance availability, and has a configuration capable of performing failover between the control units.

[Detailed configuration of gateway device and normal operation]
FIG. 2 is a block diagram showing a more detailed configuration of the gateway device of FIG. Referring to FIG. 2, gateway device 20 includes two or more control units. In the example of FIG. 2, the gateway device 20 includes two control units 21A and 21B, and each control unit 21A and 21B has the same configuration. The first control unit 21A is also called a master unit 21A, and the second control unit 21B is also called a slave unit.

Specifically, the first control unit 21A includes a communication unit 22A for communicating with each sensor device 10 on the lower side (sensor side), a CPU (Central Processing Unit) 24A, a memory 25A, and an upper side network 40. It includes a communication unit 26A for communicating with and a power source 27A. The power supply 27A supplies a drive voltage to each of the constituent elements 22A, 24A, 25A, 26A of the first control unit 21A. Similarly, the second control unit 21B includes a lower side (sensor side) communication section 22B, a CPU 24B, a memory 25B, an upper side communication section 26B, and a power supply 27B. The communication unit 26A is connected to the network 40 via the communication path 31, and the communication unit 26B is connected to the network 40 via the communication path 32.

In this specification, the CPU 24A and the memory 25A of the master unit 21A may be collectively referred to as a first controller 23A. The CPU 24B and the memory 25B of the slave unit 21B may be collectively referred to as a second controller 23B. Further, it may be considered that the lower-side communication unit 22A of the master unit 21A and the lower-side communication unit 22B of the slave unit 21B are combined to form one lower-side communication unit 22, and the upper-side communication unit 26A of the master unit 21A and the slave unit It may be considered that the upper side communication unit 26B of the unit 21B is integrated to form one upper side communication unit 26.

Basically, each sensor device 10 communicates with the master unit 21A, and the host computer 41 communicates with the master unit 21A. In other words, the controller 23A (CPU 24A) provided in the master unit 21A stores the measurement data received via the communication unit 22A in the memory 25A, and the measurement data or the calculation result based on the measurement data is transmitted via the communication unit 26A. And transmits it to the host computer 41.

On the other hand, the controller 23B (CPU 24B) provided in the slave unit 21B should not be able to directly receive the measurement data transmitted from each sensor device 10. However, in the case of the present embodiment, the measurement data transmitted from each sensor device 10 is a wireless signal, and the measurement data transmitted to the communication unit 22A of the master unit 21A is transmitted to the slave unit. The communication section 22B of 21B intercepts (simultaneously receives). It is necessary to slightly change the communication protocol of the lower network to enable the interception. The measurement data intercepted by the communication unit 22B is stored in the memory 25B by the CPU 24B of the slave unit 21B. Further, the CPU 24B performs the same calculation as the CPU 24A based on the received measurement data, and stores the calculation result in the memory 25B.

As described above, the master unit 21A and the slave unit 21B simultaneously receive the transmission data from each sensor device 10, thereby eliminating the need for replication of the measurement data and the operation data based on the measurement data. Even when the secret communication using the common key or the public encryption key is performed, the measurement data can be simultaneously received by sharing the key data among the control units 21A and 21B.

On the other hand, the data (control command and setting information) transmitted from the host computer 41 to the communication unit 26A of the master unit 21A via the host network 40 is intercepted by the communication unit 26B of the slave unit 21B ( (Simultaneous reception) is not done. This is because, if an attempt is made to enable interception, it is necessary to change the communication protocol of the higher-level network, and the effect will also affect other communication devices connected to the higher-level network 40.

Therefore, the data received from the host computer 41 and stored in the memory 25A of the master unit 21A needs to be replicated. Normally, the communication unit 26A changes the destination of the signal received from the host computer 41 to the communication unit 26B and transfers the signal to the communication unit 26B via the network 40. The controller 23B stores the signal received by the communication unit 26B in the memory 25B. Thereby, the same state of the memory 25A and the memory 25B can be maintained.

In addition to the above-mentioned simultaneous reception and replication, a process of maintaining the same state by confirming whether the stored contents of the memory 25A and the stored contents of the memory 25B match, and performing data transfer only at the unmatched portions (hereinafter , "Synchronization process") is performed. In the case of FIG. 2, a wired bus 30 is provided between the CPU 24A and the CPU 24B for this synchronization processing. Since the amount of communication required for data synchronization is greatly reduced, it is not necessary to increase the communication capacity of the wired bus 30 significantly. Instead of the wired bus 30, data communication may be performed using a communication path 31 and a communication path 32 such as a wired LAN or a wireless LAN.

In the synchronization processing, first, the error detection code is calculated for each of the predetermined areas in each of the memory 25A and the memory 25B. As the error detection code, for example, a checksum, a Cyclic Redundancy Check (CRC), or a hash function such as MD5 can be used. Next, the error detection codes calculated for each of the above-described predetermined areas are compared, and data is copied from the memory 25A to the memory 25B for areas where the error detection codes differ. As a result, the amount of communication required for synchronization processing can be further reduced. Hereinafter, a normal operation procedure of the gateway device 20 (data reception from the sensor device, data reception from the host computer, and synchronization processing) will be specifically described with reference to a flowchart.

[Normal operation procedure of gateway device]
(1. Data reception from the sensor device)
FIG. 3 is a flowchart showing a procedure until the data transmitted from the sensor device is received by the host computer 41 via the gateway device. In FIG. 3, the operation of the first controller 23A (CPU 24A) provided in the master unit 21A and the operation of the second controller 23B (CPU 24B) provided in the slave unit 21B are shown.

With reference to FIGS. 2 and 3, first, the sensor device 10 performs a filtering process and an A/D conversion process on the measurement data detected by the built-in sensor element, and transmits the measurement data to the gateway device 20 (step S100). The measurement data from the sensor device 10 is simultaneously received by the first communication unit 22A and the second communication unit 22B, and fetched by the first controller 23A and the second controller 23B, respectively. The first controller 23A stores the received measurement data in the memory 25A (step S200), and the second controller 23B stores the received measurement data in the memory 25B (step S300).

Further, the first controller 23A may perform a predetermined calculation on the received data according to the program and store the calculation result in the memory 25A (step S205). For example, the first controller 23A performs digital filter processing on the measurement data at a plurality of time points and performs a composite operation on the measurement data from a plurality of sensors. In this case, it is desirable that the second controller 23B also perform the same calculation as the first controller 23A on the received data according to the program and store the calculation result in the memory 25B (step S305).

Next, the first controller 23A transmits the measurement data and/or the calculation result stored in the memory 25A to the upper network 40 via the communication unit 26A (step S210). The transmitted data is received by the host computer 41 via the network 40 (step S400). Since the data stored in the memory 25B of the second controller 23B is for failover, it is not transmitted to the host computer 41. In addition, the first controller 23A may collectively transmit the measurement data at a plurality of time points or the calculation results at a plurality of time points together.

(2. Receive data from host computer)
FIG. 4 is a flowchart showing a procedure until data from the host computer 41 is stored in the memory of the gateway device.

Referring to FIGS. 2 and 4, first, data (for example, setting information) is transmitted from host computer 41 to gateway device 20 (step S405). The signal from the host computer 41 is received by the communication unit 26A of the master unit 21A (step S510). The data (setting information) received by the communication unit 26A is written in the memory 25A of the first controller 23A (step S220).

Normally, the communication unit 26A changes the destination of the signal received from the host computer 41 to the communication unit 26B of the slave unit 21B and outputs it to the network 40 (step S520). That is, the communication unit 26A transfers the received signal from the host computer 41 to the communication unit 26B of the slave unit 21B via the network 40. The transferred signal (setting information) is received by the communication unit 26B of the slave unit 21B and written in the memory 25B of the second controller 23B (step S320). As a result, the memory 25A of the master unit 21A and the memory 25B of the slave unit 21B maintain the same state. In a normal case, the communication volume from the host computer 41 is smaller than the communication volume from a large number of sensor nodes 10, and therefore the communication capacity is not overwhelmed. Data may be transferred using the wired bus 30 instead of the wired LAN or the wireless LAN in the network 40.

(3. Synchronous processing)
FIG. 5 is a flowchart showing an example of a procedure for performing a synchronization process between the first and second control units. The cycle of data synchronization between the memory 25A and the memory 25B does not need to be the same as the cycle of measurement data transmission, and is usually longer than the cycle of measurement data transmission.

Referring to FIGS. 2 and 5, first, the first controller 23A calculates an error detection code for each predetermined area of the memory 25A (step S230), and the second controller 23B determines the corresponding predetermined area of the memory 25B. An error detection code is calculated for each area (step S330). The second controller 23B sends the calculation result of the error detection code to the first controller 23A.

Next, the first controller 23A collates the calculated error detection code for each of the above-mentioned predetermined areas (step S235). If the memory 25A and the memory 25B are synchronized after the procedure described with reference to FIGS. 3 and 4 is repeated a plurality of times and repeated, the stored contents of the memory 25A and the memory 25B are stored unless an error occurs. It is the same as the stored content. Therefore, in this case, the first controller 23A determines that the error detection code matches between the memory 25A and the memory 25B (there is no mismatched part), and ends the synchronization process (NO in step S240).

On the other hand, a case will be described in which the first controller 23A collates the calculated error detection codes for each of the above-described predetermined areas and detects a mismatch of the error detection codes (YES in step S240). In this case, the first controller 23A transfers the data of a part of the storage area of the memory 25A where the error detection codes do not match to the wired bus 30 (or the communication path 31, the network 40, the communication path 32). To the second controller 23B via (step S245). When the second controller 23B receives the memory data from the first controller 23A (YES in step S340), the second controller 23B writes the received data in the corresponding area of the memory 25B (step S345). This completes memory synchronization. Instead of the wired bus 30, data communication may be performed using a communication path 31 and a communication path 32 such as a wired LAN or a wireless LAN.

[Specific procedure for failover]
Next, a failover in which execution of subsequent processing is switched to the second control unit (slave unit 21B) when the first control unit (master unit) 21A is abnormal will be described. For example, when the OS (Operating System) detects a freeze of a program running on the CPU 24A of the master unit 21A, or a system problem such as the communication unit 22A, the memory 25A, the communication unit 26A, or the power supply 27A is detected. In this case, failover from the master unit 21A to the slave unit 21B is executed. Furthermore, when a hang-up of the CPU 24A is detected based on the result of heartbeat observation, failover from the master unit 21A to the slave unit 21B is performed. Hereinafter, the failover procedure will be specifically described with reference to the drawings.

FIG. 6 is a flowchart showing an example of a failover procedure. The flowchart of FIG. 6 shows the operation of the first controller 23A (CPU 24A) provided in the master unit 21A and the operation of the second controller 23B (provided in the slave unit 21B when the freeze of the application program is detected. The operation of the CPU 24B) is shown.

Referring to FIGS. 2 and 6, it is assumed that the OS (operating system) detects that the application program operating in first controller 23A (CPU 24A) is frozen (step S250). In this case, the first controller 23A requests the second controller 23B to start the gateway operation and change the address of the upper communication unit 26B (step S255). At the same time, the first controller 23A issues an address change command or a stop command to the higher-level communication unit 26A (step S260). The second controller 23B issues an address change command to the communication unit 26B in accordance with the request from the first controller 23A.

In the present embodiment, it is assumed that each of the communication units 26A and 26B has a programmable control circuit built therein. This control circuit can change the address used for communication with the upper network 40 and stop the operation thereof in accordance with commands from the corresponding controllers 23A and 23B. Specifically, when the upper communication is Ethernet, the IP addresses are swapped between the controllers (the IP addresses are exchanged). However, when the addresses of the communication units 26A and 26B cannot be swapped, or when the communication path cannot be switched (the operation of the communication unit 26A is stopped and the address of the communication unit 26B is changed), the addresses of the communication units 26A and 26B are It will be maintained as it is.

Further, the first controller 23A stops the operation as the gateway (or the operation is already stopped due to the failure occurrence) (step S265). The second controller 23B takes over the subsequent operation as a gateway according to the request from the first controller 23A (step S365).

[Communication route after failover]
FIG. 7 is a flowchart showing a procedure until the data transmitted from the host computer 41 is stored in the memory of the second controller after the failover.

In the normal state before the failover is performed, the transmission data from the host computer 41 passes through the communication paths of the communication path 31, the communication unit 26A, the communication path 31, the network 40, the communication path 32, and the communication unit 26B in order. It is received by the second controller 23B (see FIG. 4). On the other hand, referring to FIG. 2 and FIG. 7, after the failover, the data (step S405) transmitted from the host computer 41 due to the switching of the communication path is directly transmitted from the network 40 via the communication path 32 to the communication unit 26B. Is received by (step S610) and is taken in by the second controller 23B (step S320). On the contrary, the data transmitted from the second controller 23B to the host computer 41 is transmitted from the communication unit 26B to the host computer 41 via the communication path 32 and the network 40 in the reverse order.

FIG. 8 shows a procedure until the data transmitted from the host computer 41 after the failover is stored in the memory of the second controller when the address switching of the host communication unit fails (or when switching is not possible). It is a flowchart shown.

Referring to FIGS. 2 and 8, when the address switching fails, the data transmitted from the host computer 41 is received by the second controller 23B via the communication path before failover. That is, the data (for example, setting information) transmitted from the host computer 41 (step S405) is once received by the communication unit 26A via the network 40 (step S510). The communication unit 26A transfers the received data to the communication unit 26B via the network 40 (step S520). The data received by the communication unit 26B (step S610) is fetched by the second controller 23B and stored in the memory 25B (step S320). On the contrary, the data transmitted from the second controller 23B to the computer 41 is received by the host computer 41 via the communication path before failover (the same as the data transmission procedure of FIG. 8) in reverse order.

FIG. 9 is a flowchart showing a procedure until the data transmitted from the sensor device is received by the host computer 41 after the failover.

When the measurement data is transmitted from the sensor device 10 after the failover is performed (step S100), this measurement data is transmitted to the communication unit 22A of the master unit 21A and the communication unit 22B of the slave unit 21B. Is the same. However, since the master side cannot operate normally and is stopped, only the measurement data received by the communication section 22B on the slave side is taken into the second controller 23B and stored in the memory 25B (step S300). The second controller 23B may perform a predetermined calculation on the received data and store the calculation result in the memory 25B (step S305). The second controller 23B transmits the measurement data stored in the memory 25B and/or the above calculation result to the host computer 41 via the host network 40 (step S310). This transmission data is received by the host computer 41 via the network 40 (step S400). The specific data transmission procedure from the second controller 23B to the host computer 41 is as already described with reference to FIGS. 7 and 8.

[Other example of failover procedure]
FIG. 10 is a flowchart showing another example of the failover procedure. The flowchart of FIG. 10 shows the operation of the first controller 23A (CPU 24A) provided in the master unit 21A and the second controller 23B (CPU 24B) provided in the slave unit 21B when the heartbeat cannot be detected. And the operation of.

With reference to FIG. 2 and FIG. 10, the heartbeat from the first controller 23A causes the second controller 23B (CPU 24B) to malfunction due to an abnormality such as the OS running on the first controller 23A (CPU 24A) hanging up. ), it becomes impossible to receive (step S370). Here, the heartbeat is a pulse signal or packet that is periodically transmitted from the first controller 23A to the second controller 23B.

In this case, the second controller 23B issues an address change command to the upper communication unit 26B (S380). At the same time, the second controller 23B requests the first controller 23A to stop the operation as a gateway and to change or stop the address of the upper communication unit 26A (step S375). According to the above request, the first controller 23A issues an address change command or a stop command to the communication unit 26A (step S280) and stops the operation as a gateway (step S285). However, it is uncertain whether the first controller 23A actually operates according to the above request. On the other hand, the second controller 23B starts the operation as a gateway (step S385).

As described with reference to FIGS. 7 and 8, if the IP addresses of the communication units 26A and 26B are swapped or the communication path is switched (the operation of the communication unit 26A is stopped and the address of the communication unit 26B is changed), the The second controller 23B directly communicates with the host computer 41 via the communication path 32 and the network 40. In the case of failure, the transmission data from the host computer 41 is received by the second controller 23B via the communication path 31, the communication unit 26A, the communication path 32, and the communication path of the communication unit 26B in order. The data output from the second controller 23B to the host computer 41 is received by the host computer 41 via the above communication path in reverse order.

[effect]
As described above, the gateway device according to the first embodiment includes the plurality of controllers 23A and 23B. The controllers 23A and 23B include memories 25A and 25B, respectively. The controllers 23A and 23B are configured to simultaneously receive the measurement data from the sensor device 10. The controllers 23A and 23B store the received data in the memories 25A and 25B.

On the other hand, the data from the host computer 41 is received by the controller 23A used as a master, stored in the memory 25A, and also received by the controller 23B by replication. In this case, the data stored in the memory 25A and the memory 25B similarly change according to the instruction from the host computer and the operation of the CPU based on the instruction. Therefore, the contents of the memories 25A and 25B basically have the same contents. Most of the communication in the sensor network is communication of measurement data from each sensor node to the gateway device. Since this measurement data is already stored in both the memory 25A and the memory 25B, communication associated with replication is performed. The quantity is small. Since these basically keep the same contents, the amount of communication required for data synchronization can be significantly reduced.

Furthermore, in the case of this embodiment, there is no need to change the operation of the host computer before and after failover.

Unlike the method of this embodiment, when the measurement data is transmitted from each sensor node only to the controller 23A used as a master and the measurement data is transferred from the master controller 23A to the slave controller 23B, the master controller 23A and the slave controller 23B The communication traffic between and becomes excessive.

Furthermore, in the gateway device of this embodiment, an error detection code (checksum, CRC, MD5, etc.) is used to confirm whether the memories are synchronized between the controllers 23A and 23B. The error detection code is transmitted and received between the two controllers 23A and 23B to verify the match or mismatch of the memory data. As a result of this verification, the memory data is transmitted and received only in the memory area in which the mismatch of the error detection code is found, whereby the synchronization of the memory data is realized. As a result, the communication traffic between the controllers 23A and 23B can be reduced. Unlike the method of this embodiment, when the memory data of both controllers 23A and 23B are directly collated, the communication traffic between both controllers 23A and 23B becomes excessive.

<Second Embodiment>
In the first embodiment, as shown in FIG. 2, the gateway is configured by providing two control units having the same hardware configuration. By making the hardware configuration of the control unit common, the manufacturing cost can be suppressed, and the number of control units can be easily increased.

In the second embodiment, in order to reduce the number of parts in the gateway device 20 of FIG. 2, each of the lower side communication units 22A and 22B, the upper side communication units 26A and 26B, and the power sources 27A and 27B is made common. is there. Hereinafter, a detailed description will be given with reference to the drawings.

FIG. 11 is a block diagram showing the configuration of the gateway according to the second embodiment. Referring to FIG. 11, gateway device 20 includes a lower communication unit 22, a first controller 23A, a second controller 23B, an upper communication unit 26, and a power supply 27. As described with reference to FIG. 2, the first controller 23A includes the CPU 24A and the memory 25A, and the second controller 23B includes the CPU 24B and the memory 25B. The power supply 27 supplies a drive voltage to each component of the gateway device 20.

The communication unit 22 on the lower side receives the measurement data transmitted from each sensor device 10. The measurement data received by the communication unit 22 is basically taken in by the first controller 23A, but can also be received by the second controller 23B.

The upper communication unit 26 receives the control command, the setting information, and the like transmitted from the upper computer 41 via the upper network 40. The reception data of the communication unit 26 is received by the first controller 23A and can also be received by the second controller 23B. The first controller 23A transmits the measurement data or the calculation result based on the measurement data to the host computer 41 via the host network 40. Upon failover, the upper communication unit 26 switches the upper communication path from the first controller 23A to the second controller. In this configuration, the CPU 24A may perform writing in parallel to the memory 25A and the memory 25B. The power supply of the CPU 24B can be stopped and the low power consumption can be reduced, but in that case, the hard beat signal is not exchanged. When the CPU 24A detects an abnormality, the CPU 24B is activated to perform the same switching process as in the first embodiment.

As a modification of the above, only one of the lower side communication units 22A and 22B and the upper side communication units 26A and 26B of FIG. 2 can be shared and configured as one component.

<Third Embodiment>
In the third embodiment, a case will be described in which the communication amount of the communication line used for synchronization between the memories 25A and 25B in the first and second embodiments is considerably limited. For example, the case where a sufficient band cannot be obtained when a wireless LAN line is used is applicable. In this case, it is necessary to further reduce the data communication amount at the time of data synchronization between the memories.

FIG. 12 is a diagram for explaining a synchronization method between memories in the gateway device according to the third embodiment.

2 and 12, the memory space of the memory 25A of the first controller 23A includes a system area 50A, a data area 51A for storing setting information, and another data area 52A for storing measurement data and the like. It is assumed to be divided into. The system area 50A stores an OS (operating system) and application programs. The data area 51A stores the setting information transmitted from the host computer 41. The data area 52A stores measurement data from each sensor device 10 and a calculation result based on the measurement data. The memory space of the memory 25B of the second controller 23B is similarly divided into a system area 50B, a data area 51B, and a data area 52B. It should be noted that the division of the memory area in FIG. 12 is an example, and may be divided into smaller pieces.

Here, in the gateway device of the third embodiment, the synchronization processing is performed at different frequencies for each area. The system areas 50A and 50B in which data is hardly changed are synchronized only at the initial startup. The data areas 51A and 51B are synchronized only when data is received from the host computer 41. The data areas 52A and 52B are regularly synchronized. However, for the data areas 52A and 52B, only the error detection code is transferred, and the data is hardly actually transmitted.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

10 sensor device, 20 gateway device, 21A 1st control unit (master unit), 21B 2nd control unit (slave unit), 22, 22A, 22B lower side communication part, 23A 1st controller (master controller), 23B 2nd controller (slave controller), 24A, 24B CPU, 25A, 25B memory, 26, 26A, 26B upper side communication unit, 27, 27A, 27B power supply, 30 wired bus, 40 upper side network, 41 upper computer, 50A, 50B system area, 51A, 51B, 52A, 52B data area.

Claims (9)

A gateway device that performs wireless communication with a plurality of sensor nodes,
A first lower side communication unit and a first memory are included, the measurement data from each of the sensor nodes is received by the first lower side communication unit, and the received measurement data is stored in the first memory. A first controller,
A second lower communication unit and a second memory different from the first lower communication unit and the first memory, and the measurement data received by the first controller is the second lower communication unit; A second controller for simultaneously receiving the measurement data and storing the received measurement data in the second memory;
A higher-order side communication unit capable of establishing a communication path between one of the first controller and the second controller and a higher-order side network by switching the communication path,
The gateway device, wherein the first and second controllers perform data synchronization only in a part of the memory spaces of the first memory and the second memory that include stored data different from each other. A gateway device that performs wireless communication with a plurality of sensor nodes,
A lower side communication unit that receives measurement data from each of the sensor nodes,
A first controller that includes a first memory and stores the measurement data received by the lower-level communication unit in the first memory;
A second controller that includes a second memory different from the first memory, and that stores the measurement data received by the lower-level communication unit in the second memory;
A higher-order side communication unit capable of establishing a communication path between one of the first controller and the second controller and a higher-order side network by switching the communication path,
The one controller that has established the communication path stores the data from the higher-order computer received via the higher-order communication unit in its own memory, and the other controller that has not established the communication path is Store a copy of the data from the host computer in its own memory,
If the one of the first and second controllers, where the storage contents of the first memory and the stored contents of said second memory to verify if it matches, there is different stored data by error to the one of the first memory and the memory space of the second memory, perform data synchronization only a part of the area including the different stored data, the gateway device. The first controller calculates an error detection code for each of the areas when the memory space of the first memory is divided into a plurality of areas when performing the data synchronization,
The second controller calculates the error detection code for each corresponding area of the second memory when performing the data synchronization,
The gateway device according to claim 1, wherein the first controller transmits only data in areas having different error detection codes to the second controller when performing the data synchronization. Further comprising a wired bus connecting the first controller and the second controller,
The gateway device according to claim 3, wherein data synchronization between the first memory and the second memory is performed via the wired bus. When the first controller has not failed, the higher-level communication unit establishes a communication path between the first controller and the higher-level network,
The upper communication unit, when said first controller is faulty, establishes a communication path between said second controller and the upper network, according to claim 1, 3, and 4 The gateway device according to any one of claims. The upper communication unit,
A first upper side communication unit for communicatively connecting the first controller and the upper side network;
A second upper side communication unit for communicatively connecting the second controller and the upper side network,
The first controller periodically sends a heartbeat to the second controller,
When the second controller does not regularly receive the heartbeat, the second controller sets a communication path to the upper network from the first upper communication unit to the second upper communication unit. Command the first controller to switch,
When the switching of the communication path is successful, the second controller directly receives the data from the upper network by the second upper communication unit,
When the switching of the communication path fails, the second controller receives the data from the upper network by the second upper communication unit via the first upper communication unit. The gateway device according to claim 5. The first controller communicates with the upper network according to an application program operating on an operating system,
When the operating system detects that the application program is frozen or a system abnormality in the first controller is detected, the operating system sets a communication path from the first controller to the second controller via the communication path to the upper network. The gateway device according to claim 5 or 6, which instructs the second controller to switch to the controller. Each of the first memory and the second memory is
A first data area for storing measurement data from each of the sensor nodes and a calculation result based on the measurement data;
A second data area for storing data received from a host computer via the host network,
The frequency of performing synchronization between the first data area of the first memory and the first data area of the second memory depends on the frequency of the second data area of the first memory and the frequency of the second data area of the first memory. The gateway device according to any one of claims 5 to 7, which is different from a frequency of performing synchronization with the second data area of the second memory. A plurality of sensor nodes, each of which wirelessly transmits measurement data,
A sensor network system comprising: the gateway device according to any one of claims 1 and 3 .

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