JP6716985B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device using a semiconductor material such as silicon carbide (SiC) and a method for manufacturing the semiconductor device.

Silicon carbide (SiC) has a high dielectric breakdown electric field, and has recently attracted attention as a semiconductor most suitable for a low loss power device. Since SiC can form a SiO ₂ film on a substrate by thermal oxidation, development of a SiC power MOSFET (SiC-MOSFET) using the SiO ₂ film is under way.

The SiC-MOSFET interface in which the insulating film is formed on the SiC substrate by thermal oxidation has a high density of interface states (Dit), which causes a decrease in channel mobility. In recent years, a process capable of forming a MOS interface with reduced Dit has been developed by oxidation in an N ₂ O gas atmosphere or a NO gas atmosphere.

By using an oxide film using N ₂ O/NO gas, the interface state density can be set to 2×10 ¹² cm ^-2 ·eV ^-1 or less and high channel mobility can be realized, and it can be used as a gate insulating film of a SiC-MOSFET. It has been considered to be a good quality structure.

For example, as a wiring forming method on a substrate of a semiconductor device, a technique of forming a material of aluminum (Al) on titanium (Ti) as a base (see, for example, Patent Document 1 below), an alloy for a metal wiring layer such as a pad A technique having a layer (for example, refer to Patent Document 2 below), a technique of providing a barrier metal layer for suppressing diffusion of aluminum between a source electrode and an interlayer insulating film and between a gate pad and a gate electrode ( For example, the following Patent Document 3) is disclosed.

JP, 7-176615, A JP, 2003-309124, A JP2012-129503A

When the SiC-MOSFET is put to practical use in the background art described above, securing the reliability of the SiC-MOSFET is an issue. As a result of verifying the reliability test of the SiC-MOSFET, it was found that there is a problem in the threshold value variation with a negative bias. The contents will be described below.

In driving the SiC-MOSFET, a high voltage of both positive voltage and negative voltage must be applied to the gate electrode during driving. Further, since it operates at high temperature, it is necessary to guarantee operation at 200°C. Therefore, it is necessary to guarantee the operation when the electric field strength applied to the gate insulating film is plus or minus 2 MV/cm to 4 MV/cm and the temperature is 200°C. In this case, it has been observed that the threshold voltage (Vth) of the MOS fluctuates greatly under certain conditions.

FIG. 2 is a sectional view of a conventional SiC-MOSFET. On the high-concentration n ⁺ -type SiC substrate 1, a low-concentration n ⁻ -type drift layer 2 doped with nitrogen of 5×10 ¹⁵ /cm ³ is deposited to a thickness of 10 μm. Next, a low concentration p ⁻ type layer 3 is formed by ion implantation.

Next, on the surface (main surface) of the n ⁺ type SiC substrate 1 on the n ⁻ type drift layer 2 side, a low concentration p ⁻ type layer 4 doped with aluminum of 5×10 ¹⁵ /cm ³ was formed to a thickness of 0.5 μm. Deposit to a thickness. The p ⁻ type layer 4 has a lower concentration than the p ⁻ type layer 3. Then, a high-concentration n ⁺ -type layer 6 is selectively formed on the p ⁻ -type layer 4 by phosphorus (P) ion implantation, and a high-concentration n ⁺ -type layer 6 is formed on the side of the n ⁺ -type layer 6 on the p ⁻ -type layer 3. The p ⁺ type layer 5 is formed by aluminum ion implantation. Thereafter, activation annealing of the entire n ⁺ type SiC substrate 1 in the above manufacturing process is performed at 1600° C. in an argon atmosphere.

After that, the gate insulating film 8 is formed to 70 nm in an N ₂ O atmosphere. After that, the gate electrode 9 is formed, and the interlayer film 10 is formed so as to cover the gate electrode 9. Further, a silicide layer 11 is formed to form an ohmic electrode. Then, an aluminum (Al) layer 12 of a source wiring metal is formed to a thickness of 5 μm to form a polyimide film as a protective film 14 as a source electrode, the polyimide is cured at 380° C., and then a back electrode 13 is formed as a drain electrode. To complete the device.

The SiC-MOSFET manufactured in this manner was subjected to a gate voltage of +3 MV/cm and a voltage of -3 MV/cm at a high temperature of 200° C. for 10 minutes, and then the fluctuation of the threshold voltage was measured. As a result, the threshold shift amount was ±0.1 V or less in the positive application, but a large negative shift of the threshold voltage was observed in the negative application.

This indicates that by applying a negative bias to the gate electrode in a high temperature atmosphere, positive fixed charges were generated in the vicinity of the SiO ₂ /SiC interface or in SiO ₂ .

The phenomenon that the threshold voltage shifts to the negative side indicates that holes, which are positive charges, are generated at the SiO ₂ /SiC interface. In silicon (Si)-based Si-MOSFETs and Si-IGBT devices, there are few reports that positive charges are generated when a negative bias is applied.

In addition, although a threshold shift phenomenon (slow trap phenomenon) has been reported in Si-PMOS with a negative bias, the threshold fluctuation range is 1000 hours after the gate voltage is -3 MV/cm and 150°C. The fluctuation range is 0.1V. On the other hand, in the case of the SiC-MOSFET, the gate voltage fluctuates by -7 V or more under the conditions of -3 MV/cm and 150°C, which is significantly different from that of the Si-MOS.

The interface state density of SiO ₂ /Si is 1.0×10 ¹¹ cm ⁻² ·eV ⁻¹ or less, while the SiO ₂ /SiC interface state density is 1.0×10 ¹² cm ⁻² ·eV. ⁻¹ or more, indicating that many hole traps are present at the SiO ₂ /SiC interface. Although much research has been done on the reduction of the interface state density, there is no report that the interface state density is the same as that of Si/SiO ₂ .

The high SiO ₂ /SiC interface state density is a problem peculiar to the SiO ₂ /SiC interface. Is it caused by the difference in the amount of defects, the amount of strain, the band structure, etc. of the SiO ₂ /SiC interface? Not clear at this time.

FIG. 3 is a sectional view showing another conventional MOSFET. Next, in order to investigate the cause of the threshold shift, a lateral MOSFET in which the interlayer film 10 and the Al layer 12 are not in direct contact with each other was prepared as shown in FIG. 3, and the threshold fluctuation was measured.

In this lateral MOSFET, 5×10 ¹⁵ /cm ³ of nitrogen-doped low-concentration n ⁻ -type drift layer 2 is deposited to a thickness of 10 μm on high-concentration n ⁺ -type SiC substrate 1. Next, a low concentration p ⁻ type layer 3 is formed by ion implantation. Then, a low concentration p ⁻ -type layer 4 doped with aluminum of 5×10 ¹⁵ /cm ³ is deposited to a thickness of 0.5 μm on the surface (main surface) of n ⁺ -type SiC substrate 1. The p ⁻ type layer 4 has a lower concentration than the p ⁻ type layer 3. Then, a low concentration n ⁻ type layer 7 is formed by implanting nitrogen ions.

Then, the high-concentration n ⁺ -type layer 6 is formed by phosphorus ion implantation, and the high-concentration p ⁺ -type layer 5 is formed by aluminum ion implantation. Then, activation annealing is performed at 1600° C. in an argon atmosphere. After that, the gate insulating film 8 is formed to 70 nm in an N ₂ O atmosphere. Then, the gate electrode 9 and the interlayer film 10 are formed. Further, since the ohmic electrode is formed, the silicide layer 11 is formed with a thickness of 1.0 μm.

Thereafter, aluminum (Al) as a wiring metal is deposited to a thickness of 5 μm to form a lateral MOSFET having a structure in which the source electrode Al layer (12a) and the drain electrode Al layer (12b) are not in contact with the interlayer film 10 shown in FIG. .. Reference numeral 13 is a back surface electrode.

After applying a gate voltage of −3 MV/cm for 10 minutes at a high temperature of 200° C. to the above lateral MOSFET, the threshold voltage fluctuation was ±0.1V. From this result, it is shown that the lateral MOSFET in which the gate electrode 9 is not in contact with the Al layers 12a and 12b (source electrode, drain electrode) via the interlayer film 10 does not have threshold variation when negatively biased.

In this way, in the structure in which the Al layers 12a and 12b for wiring are not in contact with the interlayer film 10, the threshold voltage does not change, so that the threshold voltage fluctuations are large. ) Elemental analysis of the structure was performed by thermal desorption spectroscopy. In this analysis result, 3×10 ¹⁴ /cm ² or more of hydrogen was detected at a temperature of 200° C. or more. Hydrogen generation in Al and from the interface of SiO/Al can be presumed to be a reaction between Al and water.

A large amount of hydrogen ions are taken into the SiO ₂ /SiC interface at the time of forming an oxide film at a high temperature of 800° C. or higher, or by an annealing treatment at a high temperature of 800° C. or higher. The (Si-H) bond and the carbon-hydrogen (C-H) bond are not changed by the low temperature heat treatment at 400°C or lower.

However, hydrogen atoms and hydrogen ions generated from Al metal deposited at a low temperature (400° C. or lower) are not fixed. A hydrogen atom, the hydrogen ions generated from Al at high temperatures gate application state moves to SiO ₂ / SiC interface, Si-H bonds of SiO ₂ / SiC interface, C-H bonds becomes dangling bonds of Si + C +, positive charge Is considered to occur.

The diffusion coefficient of hydrogen in the oxide film at 200° C. is 1.0×10 ⁻⁸ [cm ² /s], and the diffusion length after 10 minutes is 24.5 μm, which easily moves in the oxide film. Then, it reaches the gate insulating film and causes threshold variation.

The vertical MOSFET in which the source electrode Al layer 12 and the interlayer film 10 are not in contact with each other can be produced, but cannot be practically used because the cell size of the MOS is large.

In view of the above problems, it is an object of the present invention to provide a semiconductor device and a method of manufacturing a semiconductor device that can suppress the amount of threshold voltage fluctuation during negative gate bias/plus gate bias and have stable electrical characteristics.

In order to solve the above-mentioned problems and to achieve the object of the present invention, a semiconductor device according to the present invention comprises a silicon carbide substrate, a drain region of the first conductivity type on the silicon carbide substrate, and a well of the second conductivity type. A semiconductor device comprising: a region, a first-conductivity-type source region, and a gate electrode on the silicon carbide substrate via a gate insulating film, and a source electrode in contact with the gate electrode via an interlayer film. The source electrode has a three-layer structure of titanium (Ti) layer /titanium-aluminum (Ti—Al) alloy layer /aluminum (Al) layer , and the titanium ( Ti ) layer has a thickness of 10 nm or more. The thickness of the titanium-aluminum ( Ti-Al ) alloy layer is 5 nm or more and 100 nm or less, and the content of aluminum in titanium and aluminum of the titanium - aluminum ( Ti-Al ) alloy layer is 25 atom% to 86 atom %. Is characterized in that.

In the semiconductor device according to the present invention, in the above invention, the silicon carbide substrate is n-type, an n-type drift layer on the silicon carbide substrate, and a p-type well layer provided in the n-type drift layer. An n-type source region provided in the p-type well layer, a gate insulating film formed on the p-type well layer, a gate electrode formed on the gate insulating film, and the n-type source A source electrode electrically connected to the region and a drain electrode provided on the surface of the silicon carbide substrate opposite to the surface on which the drift layer is formed are provided.

A semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, it has a semiconductor device structure of MOSFET.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the Ti—Al alloy layer is any one of TiAl ₆ , TiAl ₃ , TiAl, and Ti ₃ Al.

In the method for manufacturing a semiconductor device according to the present invention, a first conductivity type drain region, a second conductivity type well region, and a first conductivity type source region are formed on a silicon carbide substrate, and the silicon carbide substrate is formed. In a method of manufacturing a semiconductor device, wherein a gate electrode is formed on a substrate via a gate insulating film, and a source electrode is formed in contact with the gate electrode via an interlayer film, the source electrode is a titanium (Ti) layer / A titanium-aluminum (Ti-Al) alloy layer /aluminum (Al) layer is formed in this order by a sputtering method, and after the source electrode is formed, the silicon carbide substrate is annealed at 300°C to 500°C to form the source electrode. Is characterized in that, after the heat treatment after the formation of the source electrode, a titanium ( Ti ) layer having a film thickness of 10 nm or more is formed as a base of the titanium-aluminum ( Ti-Al ) alloy layer.

Further, in the method for manufacturing a semiconductor device according to the present invention, in the above invention, the sputtering of the Ti—Al alloy layer of the source electrode is performed at a sputtering pressure of 0.1 Pa to 0.8 Pa and a temperature of the silicon carbide substrate of 25. The sputtering is performed at a temperature of not less than 350° C. and not more than 350° C., and the sputtering material is characterized in that the content of aluminum in titanium and aluminum is 25 at% to 86 at %.

Further, a method of manufacturing a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the source electrode is manufactured by exposing the Ti, the Ti—Al alloy, and the Al in the same chamber without exposing to the atmosphere. To do.

Further, in the method for manufacturing a semiconductor device according to the present invention, in the above invention, the source electrode is a Ti-Al alloy layer newly formed on a base of the Ti-Al alloy layer by heat treatment after the source electrode is formed. Is 10 nm or less in thickness.

Further, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the sputtering material is any one of TiAl ₆ , TiAl ₃ , TiAl, and Ti ₃ Al.

According to the above-mentioned invention, the source electrode is formed with a three-layer structure of titanium (Ti)/Ti-Al (titanium-aluminum) alloy layer/aluminum (Al). For example, Ti/Ti-Al alloy layer/Al is formed into a source electrode by continuously forming a film having a thickness of 0.1 μm/50 nm/5.0 μm by sputtering. As the sputtering conditions, magnetron sputtering in which the temperature of the silicon carbide substrate is 25° C. and the argon pressure is 0.3 Pa is used. Thereby, by forming a Ti-Al alloy layer in advance as a second layer, a new Ti-Al alloy layer is formed at the interface between the second Ti-Al alloy layer and the first Ti layer by annealing at 380° C., for example. No Ti-Al crystal grains are generated. Then, by the Ti layer below the Ti-Al alloy layer, hydrogen atoms/hydrogen ions in Al are absorbed by the Ti layer, hydrogen is prevented from diffusing into the gate insulating film, and the SiC-MOSFET having a stable threshold voltage is obtained. Can be formed. As a result, in a small vertical semiconductor element in which a current flows from the front surface side to the back surface side of the semiconductor substrate, it is possible to suppress threshold voltage fluctuations and stabilize the electrical characteristics of the semiconductor device.

According to the present invention, it is possible to provide a semiconductor device capable of suppressing the amount of threshold voltage fluctuation and having stable electrical characteristics.

1 is a sectional view of a vertical SiC-MOSFET according to a first embodiment of the present invention. FIG. 2 is a sectional view of a conventional SiC-MOSFET. FIG. 3 is a sectional view of another conventional SiC-MOSFET.

Embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. In the present specification and the accompanying drawings, in a layer or region prefixed with n or p, it means that electrons or holes are majority carriers. Further, + and − added to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which they are not added, respectively. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted. In the present specification, in the notation of the Miller index, “−” means a bar attached to the index immediately after it, and “−” is added before the index to represent a negative index.

(Embodiment 1)
1 is a sectional view of a vertical SiC-MOSFET according to a first embodiment of the present invention. A method of manufacturing this SiC-MOSFET will be described. First, a low-concentration n ⁻ -type drift layer 2 having a nitrogen concentration of 5×10 ¹⁵ /cm ³ and having a thickness of 10 μm is formed on a high-concentration n ⁺ -type SiC substrate (which will be a drain region of the first conductivity type) 1. accumulate.

Next, a low concentration p ⁻ type layer 3 is formed by ion implantation. Next, on the surface (main surface) of the n ⁺ type SiC substrate 1 (n ⁻ type drift layer 2), a low concentration p ⁻ type layer 4 doped with 5×10 ¹⁵ /cm ³ of aluminum (Al) is formed. Deposit to a thickness of 0.5 μm. The p ⁻ type layer 4 has a lower concentration than the p ⁻ type layer 3, and the p ⁻ type layer 3 and the p ⁻ type layer 4 are second conductivity type well regions. After that, a low concentration n ⁻ type layer 7 is formed by nitrogen ion implantation.

Next, a high concentration n ⁺ type layer (first conductivity type source region) 6 is formed by phosphorus ion implantation, and a high concentration p ⁺ type layer 5 is formed by aluminum (Al) ion implantation. After that, the entire n ⁺ type SiC substrate 1 is subjected to activation annealing at 1600° C. in an argon atmosphere.

After that, the gate insulating film 8 is formed on the p ⁻ -type layer 4, the n ⁺ -type layer 6, and the n ⁻ -type layer 7 in the N ₂ O atmosphere to have a thickness of 70 nm. After that, the gate electrode 9 is formed on the gate insulating film 8, and the interlayer film 10 is formed so as to cover the gate electrode 9. Further, a silicide layer 11 having a predetermined thickness is formed to form an ohmic electrode.

Then, a three-layer structure of titanium (Ti) layer 15/(titanium-aluminum) Ti-Al alloy layer 16/aluminum (Al) layer 12 is formed as a source electrode. At this time, the Ti layer 15/Ti-Al alloy layer 16/Al layer 12 is continuously formed by sputtering to have respective film thicknesses of 0.1 μm/50 nm/5.0 μm. As the sputtering conditions, magnetron sputtering in which the temperature of the n ⁺ type substrate 1 is 25° C. and the argon pressure is 0.3 Pa can be used.

The thickness of the Ti—Al alloy layer 16 is preferably 5 nm or more and 100 nm or less, and when the thickness is less than 5 nm, it is difficult to uniformly form the Ti—Al alloy layer 16 in the wafer surface, and when it is 100 nm or more, the Ti—Al alloy layer 16 is formed. The resistance of the device will increase and affect the device characteristics.

Composition of the target to the composition and use of TiAl alloy layer _{16, TiAl 6, TiAl 3, TiAl} , Ti 3 Al are preferred, TiAl alloy for suppressing the interaction of Ti and Al after annealing layer 16 In order to keep the formation of Al, an Al content of 25 at% to 86 at% is required. Specifically, commercially available sputtering targets include targets containing 40 atomic%, 50 atomic%, 64 atomic%, 67 atomic%, 67 atomic%, and 70 atomic% of Al. A target containing% Al was used. The reason for using these intermetallic compounds is that such a composition exists as an intermetallic compound and therefore has a higher effect of suppressing mutual diffusion than other compositions.

The Al content is calculated by the calculation method of Al atom number/(Ti atom number+Al atom number)*100.

Further, the source electrode composed of these three layers is formed in the same chamber without being exposed to the atmosphere in order to prevent the formation of an inadequate oxide film or the like at the interface. Further, the Ti—Al alloy layer 16 is preferably formed by a sputtering method in order to secure its purity and uniformity.

The temperature of the n ⁺ type SiC substrate 1 at the time of sputtering is set to 25° C. or higher, which does not require a cooling mechanism, and a temperature of 350° C. or higher is not preferable because the manufacturing cost of the semiconductor device increases. When the sputtering pressure is low, the sputtering rate is slow, and when it is high, the in-plane distribution is deteriorated, so 0.1 Pa to 0.8 Pa is preferable.

After that, the Al layer 12, the Ti—Al alloy layer 16 and the Ti layer 15 are etched to form a source electrode having a three-layer structure. The source electrode thus formed has a structure in which the Al layer 12 is in contact with the gate electrode 9/interlayer film 10 via the Ti layer 15/Ti-Al alloy layer 16. After that, a polyimide film which is the protective film 14 is formed and annealed at 380° C. to form a back surface electrode 13 as a drain electrode on the back surface of the n ⁺ type SiC substrate 1 to complete a vertical SiC-MOSFET.

In the case of a structure of only Ti/Al in which the Ti-Al alloy layer 16 is not formed, a TiAl alloy layer is formed at the interface by polyimide curing or annealing, and this TiAl alloy layer penetrates the underlying Ti. , The hydrogen shielding effect had been lost.

On the other hand, in the case where the Ti—Al alloy layer 16 is formed in advance as the second layer as in the first embodiment, the annealing is performed at 380° C. and the Ti—Al alloy layer 16 in the second layer is No new TiAl crystal grains are generated at the interface of the Ti layer 15 of the first layer. Then, the Ti layer 15 under the Ti-Al alloy layer 16 absorbs hydrogen atoms/hydrogen ions in the Al layer 12 into the Ti layer 15, and hydrogen is prevented from diffusing into the gate insulating film 8. It was possible to form a stable gate insulating film 8.

The temperature of polyimide curing or annealing is preferably 500° C. or lower, and above this temperature, the polymer constituting the polyimide is decomposed. Further, since imidization does not proceed at 300° C. or lower, it cannot serve as a protective film.

By using the semiconductor device having the three-layer structure source electrode described above, the threshold voltage fluctuation width after 1000 hours at a gate voltage of -3 MV/cm and a heating temperature of 200° C. can be suppressed to 0.1 V or less. It was The Ti layer 15 is a hard material, and cracks occur when the thickness is 1.0 μm or more. The thickness of the Ti layer 15 is 10 nm or more and 1.0 μm or less.

The thickness of the Ti layer 15 after annealing is set to 10 nm or more because of the hydrogen (H) absorption effect of Ti. An experiment was conducted on the storage effect of the Ti layer 15. In the experiment, when hydrogen was injected at 400° C. into the Ti layer 15 having a film thickness of 100 nm, 6×10 ¹⁷ /cm ² of H ₂ was occluded, so that a film thickness of 10 nm was 1×10 ¹⁵ /cm ² or more. Can store hydrogen.

(Embodiment 2)
As the second embodiment, a sample was prepared in which the annealing temperature of polyimide, which was 380° C. in the first embodiment, was raised to 400° C. When the source electrode is only two layers of the Ti layer 15 and the Al layer 12, the grain size (film thickness) of the newly formed TiAl alloy is 30 nm or more and less than 100 nm, whereas in the second embodiment. When the source electrode had a three-layer structure of Ti layer 15/Ti-Al alloy layer 16/Al layer 12, the thickness of the newly formed Ti-Al alloy layer was 10 nm or less.

As described above, even when the annealing temperature is 400° C. in the second embodiment, the Ti layer 15 as the base of the source electrode remains about 90 nm, so that good device characteristics can be obtained.

In the above, the present invention is not limited to the above-described embodiments, but can be variously modified without departing from the spirit of the present invention. For example, the present invention is similarly applicable when the p-type and the n-type are exchanged, or when the silicon carbide substrate and the epitaxial layer grown on the main surface of the silicon carbide substrate have different conductivity types.

As described above, the semiconductor device according to the present invention is useful for, for example, a power semiconductor element such as a power device or a power semiconductor element used for industrial motor control or engine control. In particular, it can be applied to a small vertical semiconductor element in which a current is passed from the front surface side to the back surface side of a semiconductor substrate.

1 SiC substrate 2 n ⁻ type drift layer 3 p ⁻ layer 4 p ⁻ layer (well layer)
5 p ⁺ layer 6 n ⁺ layer (source region)
7 n ⁻ Layer 8 Gate Insulating Film 9 Gate Electrode 10 Interlayer Film 11 Silicide Layer 12 Al Layer 13 Backside Electrode 14 Protective Film 15 Ti Layer 16 Ti—Al Alloy Layer 17 TiN Layer 18 Ti Film

Claims (9)

A silicon carbide substrate,
A drain region of the first conductivity type, a well region of the second conductivity type, and a source region of the first conductivity type on the silicon carbide substrate, and a gate electrode on the silicon carbide substrate via a gate insulating film; In a semiconductor device comprising: a source electrode in contact with the gate electrode via an interlayer film,
The source electrode has a three-layer structure of titanium (Ti) layer /titanium-aluminum (Ti—Al) alloy layer /aluminum (Al) layer , and the titanium ( Ti ) layer has a thickness of 10 nm or more. The film thickness of the titanium-aluminum ( Ti-Al ) alloy layer is 5 nm or more and 100 nm or less, and the content of aluminum in titanium and aluminum of the titanium - aluminum ( Ti-Al ) alloy layer is 25 atom% to 86 atom %. There is a semiconductor device. The silicon carbide substrate is n-type, and an n-type drift layer, a p-type well layer provided in the n-type drift layer, and an n-type source region provided in the p-type well layer are provided on the silicon carbide substrate. A gate insulating film formed on the p-type well layer, a gate electrode formed on the gate insulating film, a source electrode electrically connected to the n-type source region, and the silicon carbide. The semiconductor device according to claim 1, further comprising a drain electrode provided on a surface of the substrate opposite to a surface on which the drift layer is formed. 3. The semiconductor device according to claim 1, which has a semiconductor device structure of MOSFET. The semiconductor device according to claim 1, wherein the titanium-aluminum ( Ti-Al ) alloy layer is any one of TiAl ₆ , TiAl ₃ , TiAl, and Ti ₃ Al. Forming a first conductivity type drain region, a second conductivity type well region, and a first conductivity type source region on the silicon carbide substrate;
A method for manufacturing a semiconductor device, comprising forming a gate electrode on the silicon carbide substrate via a gate insulating film, and further forming a source electrode in contact with the gate electrode via an interlayer film,
The source electrode is formed by a sputtering method in the order of titanium (Ti) layer /titanium-aluminum (Ti-Al) alloy layer /aluminum (Al) layer ,
After forming the source electrode, the silicon carbide substrate is annealed at 300° C. to 500° C., and the source electrode is a base of the titanium-aluminum ( Ti—Al ) alloy layer after the heat treatment after forming the source electrode. A method of manufacturing a semiconductor device, wherein a titanium ( Ti ) layer having a film thickness of 10 nm or more is formed on the substrate. The sputtering of the titanium-aluminum ( Ti-Al ) alloy layer of the source electrode is
The sputtering pressure is 0.1 Pa to 0.8 Pa, the temperature of the silicon carbide substrate is 25° C. or higher and 350° C. or lower,
The method for manufacturing a semiconductor device according to claim 5, wherein the sputter material has a content of aluminum in titanium and aluminum of 25 at% to 86 at %. The sputter _{material, TiAl 6, TiAl 3, TiAl} , a method of manufacturing a semiconductor device according to claim 6, characterized in that any one of Ti ₃ Al. The source electrode is manufactured by exposing the titanium ( Ti ) layer , the titanium-aluminum ( Ti-Al ) alloy layer , and the aluminum ( Al ) layer in the same chamber without exposing to the atmosphere. 7. The method for manufacturing a semiconductor device according to any one of items 7 to 7 . In the source electrode, a film thickness of a titanium-aluminum ( Ti-Al ) alloy layer newly formed on a base of the titanium-aluminum ( Ti-Al ) alloy layer by heat treatment after forming the source electrode is 10 nm or less. the method of manufacturing a semiconductor device according to any one of claims 5-8, characterized in that.

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