JP6709266B2 - ニューラルネットワークにおける処理 - Google Patents
ニューラルネットワークにおける処理 Download PDFInfo
- Publication number
- JP6709266B2 JP6709266B2 JP2018197162A JP2018197162A JP6709266B2 JP 6709266 B2 JP6709266 B2 JP 6709266B2 JP 2018197162 A JP2018197162 A JP 2018197162A JP 2018197162 A JP2018197162 A JP 2018197162A JP 6709266 B2 JP6709266 B2 JP 6709266B2
- Authority
- JP
- Japan
- Prior art keywords
- value
- execution unit
- instructions
- result
- sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/582—Pseudo-random number generators
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30018—Bit or string instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/045—Combinations of networks
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/061—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using biological neurons, e.g. biological neurons connected to an integrated circuit
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
- G06N3/082—Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- General Health & Medical Sciences (AREA)
- Evolutionary Computation (AREA)
- Data Mining & Analysis (AREA)
- Computational Linguistics (AREA)
- Artificial Intelligence (AREA)
- Neurology (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1717306.3 | 2017-10-20 | ||
| GB1717306.3A GB2568230B (en) | 2017-10-20 | 2017-10-20 | Processing in neural networks |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019079524A JP2019079524A (ja) | 2019-05-23 |
| JP2019079524A5 JP2019079524A5 (enExample) | 2020-05-28 |
| JP6709266B2 true JP6709266B2 (ja) | 2020-06-10 |
Family
ID=60481809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018197162A Active JP6709266B2 (ja) | 2017-10-20 | 2018-10-19 | ニューラルネットワークにおける処理 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US11900109B2 (enExample) |
| EP (1) | EP3474193B1 (enExample) |
| JP (1) | JP6709266B2 (enExample) |
| KR (1) | KR102197539B1 (enExample) |
| CN (1) | CN109697506B (enExample) |
| CA (1) | CA3021426C (enExample) |
| GB (1) | GB2568230B (enExample) |
| TW (1) | TWI719348B (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102683757B1 (ko) * | 2018-02-20 | 2024-07-10 | 삼성전자주식회사 | 심층 신경망의 학습을 수행시키는 방법 및 그에 대한 장치 |
| KR102694572B1 (ko) * | 2018-02-20 | 2024-08-13 | 삼성전자주식회사 | 완전 연결 네트워크의 데이터 입력 및 출력을 제어하는 방법 및 장치 |
| KR102780709B1 (ko) * | 2023-03-31 | 2025-03-12 | 한국과학기술원 | 부호형 비트 슬라이스 생성기 및 그 방법과, 부호형 비트 슬라이스 연산기와, 이들을 적용한 인공지능 신경망 가속장치 |
Family Cites Families (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU641418B2 (en) * | 1989-09-20 | 1993-09-23 | Fujitsu Limited | A parallel data processing system for processing and transmitting data concurrently |
| JPH11500547A (ja) * | 1994-12-01 | 1999-01-12 | インテル・コーポレーション | 乗算を有するマイクロプロセッサ |
| US6473522B1 (en) * | 2000-03-14 | 2002-10-29 | Intel Corporation | Estimating text color and segmentation of images |
| JP3621695B2 (ja) | 2002-07-29 | 2005-02-16 | 株式会社東芝 | 半導体装置及び素子形成用基板 |
| US20040230626A1 (en) * | 2003-05-12 | 2004-11-18 | International Business Machines Corporation | Computer system method for a one cycle implementation of test under mask instructions |
| US7961873B2 (en) * | 2004-03-03 | 2011-06-14 | King Fahd University Of Petroleum And Minerals | Password protocols using XZ-elliptic curve cryptography |
| US7502763B2 (en) * | 2005-07-29 | 2009-03-10 | The Florida International University Board Of Trustees | Artificial neural network design and evaluation tool |
| US9529592B2 (en) * | 2007-12-27 | 2016-12-27 | Intel Corporation | Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation |
| US9477467B2 (en) * | 2013-03-30 | 2016-10-25 | Intel Corporation | Processors, methods, and systems to implement partial register accesses with masked full register accesses |
| US9417845B2 (en) * | 2013-10-02 | 2016-08-16 | Qualcomm Incorporated | Method and apparatus for producing programmable probability distribution function of pseudo-random numbers |
| CN104751227B (zh) * | 2013-12-31 | 2018-03-06 | 科大讯飞股份有限公司 | 用于语音识别的深度神经网络的构建方法及系统 |
| CN106030513A (zh) * | 2014-03-27 | 2016-10-12 | 英特尔公司 | 用于采用到被屏蔽结果元素的传播将连续源元素存储到未屏蔽结果元素的处理器、方法、系统和指令 |
| EP3123300A1 (en) | 2014-03-28 | 2017-02-01 | Intel Corporation | Processors, methods, systems, and instructions to store source elements to corresponding unmasked result elements with propagation to masked result elements |
| US20160026912A1 (en) * | 2014-07-22 | 2016-01-28 | Intel Corporation | Weight-shifting mechanism for convolutional neural networks |
| US10133570B2 (en) * | 2014-09-19 | 2018-11-20 | Intel Corporation | Processors, methods, systems, and instructions to select and consolidate active data elements in a register under mask into a least significant portion of result, and to indicate a number of data elements consolidated |
| EP3035205A1 (en) * | 2014-12-19 | 2016-06-22 | Intel Corporation | Reconfigurable functional unit and method for artificial neural networks |
| US10373054B2 (en) * | 2015-04-19 | 2019-08-06 | International Business Machines Corporation | Annealed dropout training of neural networks |
| US10192162B2 (en) * | 2015-05-21 | 2019-01-29 | Google Llc | Vector computation unit in a neural network processor |
| CN106528047B (zh) * | 2015-10-08 | 2019-04-09 | 上海兆芯集成电路有限公司 | 一种处理器、神经网络单元及其运作方法 |
| JP2017097585A (ja) * | 2015-11-24 | 2017-06-01 | 株式会社リコー | 学習装置、プログラム及び学習方法 |
| CN106127301B (zh) * | 2016-01-16 | 2019-01-11 | 上海大学 | 一种随机神经网络硬件实现装置 |
| CN106796668B (zh) * | 2016-03-16 | 2019-06-14 | 香港应用科技研究院有限公司 | 用于人工神经网络中比特深度减少的方法和系统 |
| US10360496B2 (en) * | 2016-04-01 | 2019-07-23 | Intel Corporation | Apparatus and method for a digital neuromorphic processor |
| US10891538B2 (en) * | 2016-08-11 | 2021-01-12 | Nvidia Corporation | Sparse convolutional neural network accelerator |
| US11068781B2 (en) * | 2016-10-07 | 2021-07-20 | Nvidia Corporation | Temporal ensembling for semi-supervised learning |
| US10528321B2 (en) * | 2016-12-07 | 2020-01-07 | Microsoft Technology Licensing, Llc | Block floating point for neural network implementations |
| CA3051990C (en) * | 2017-02-23 | 2021-03-23 | Cerebras Systems Inc. | Accelerated deep learning |
| US10776697B2 (en) * | 2017-04-18 | 2020-09-15 | Huawei Technologies Co., Ltd. | System and method for training a neural network |
-
2017
- 2017-10-20 GB GB1717306.3A patent/GB2568230B/en active Active
-
2018
- 2018-02-01 US US15/886,331 patent/US11900109B2/en active Active
- 2018-10-12 EP EP18200108.1A patent/EP3474193B1/en active Active
- 2018-10-16 CN CN201811206575.3A patent/CN109697506B/zh active Active
- 2018-10-19 KR KR1020180125335A patent/KR102197539B1/ko active Active
- 2018-10-19 JP JP2018197162A patent/JP6709266B2/ja active Active
- 2018-10-19 TW TW107136964A patent/TWI719348B/zh active
- 2018-10-19 CA CA3021426A patent/CA3021426C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TWI719348B (zh) | 2021-02-21 |
| CA3021426A1 (en) | 2019-04-20 |
| GB2568230A (en) | 2019-05-15 |
| KR20190044549A (ko) | 2019-04-30 |
| CA3021426C (en) | 2023-08-01 |
| JP2019079524A (ja) | 2019-05-23 |
| US11900109B2 (en) | 2024-02-13 |
| CN109697506A (zh) | 2019-04-30 |
| GB201717306D0 (en) | 2017-12-06 |
| TW201931107A (zh) | 2019-08-01 |
| GB2568230B (en) | 2020-06-03 |
| CN109697506B (zh) | 2023-07-14 |
| EP3474193A1 (en) | 2019-04-24 |
| US20190121639A1 (en) | 2019-04-25 |
| KR102197539B1 (ko) | 2020-12-31 |
| EP3474193B1 (en) | 2025-09-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11169778B2 (en) | Converting floating point numbers to reduce the precision | |
| JP6744375B2 (ja) | ニューラルネットワークにおけるランダム性の生成 | |
| US11294635B2 (en) | Pseudo-random number generator | |
| US11449309B2 (en) | Hardware module for converting numbers | |
| JP6709266B2 (ja) | ニューラルネットワークにおける処理 | |
| WO2018024093A1 (zh) | 一种能支持不同位宽运算数据的运算单元、方法及装置 | |
| GB2582145A (en) | Execution unit in Processor | |
| JP2019079524A5 (enExample) | ||
| US10503691B2 (en) | Associative computer providing semi-parallel architecture | |
| US11630667B2 (en) | Dedicated vector sub-processor system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20190218 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20200121 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200204 |
|
| A524 | Written submission of copy of amendment under article 19 pct |
Free format text: JAPANESE INTERMEDIATE CODE: A524 Effective date: 20200417 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20200428 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20200522 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6709266 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |