JP6706305B2 - Analog signal generator - Google Patents

Description

The present invention relates to an analog signal generator, and more particularly to mitigation of glitch noise.

Outputs a desired DC signal through a D/A converter to a type of DC signal generator that is an analog signal generator, and also corrects errors due to the nonlinearity of the D/A converter and aging, and the resolution of the DAC. In order to control the DC voltage with high accuracy as described above, there is a configuration in which a part of the output signal is fed back through an A/D converter.

FIG. 3 is a block diagram showing an example of a conventional DC signal generator. In FIG. 3, the D/A converter 3 has a resolution of 13 bits and the output value can be set with a resolution of 24 bits.

The error calculation circuit 1 calculates the error between the set value and the feedback value, and outputs the calculation result to the DAC code generation unit 2. The DAC code generation unit 2 generates a DAC code with a bit number of 13 bits according to the bit resolution of a D/A converter (hereinafter also referred to as a DAC) 3 in the subsequent stage based on the calculation result of the calculation circuit 1 to generate the D/A. Output to the converter 3.

The D/A converter 3 converts and outputs a predetermined analog signal according to the input DAC code. The converted output signal of the D/A converter 3 is output to the outside via a low-pass filter (hereinafter also referred to as LPF) 4 and is also output to the error calculation circuit 1 via an A/D converter (hereinafter also referred to as ADC) 5. Be returned to.

Specifically, the error calculation circuit 1 outputs the 24-bit correction value Din to the DAC code generation unit 2. The DAC code generation unit 2 generates a 13-bit DAC code that matches the DAC setting resolution, based on the 24-bit correction value Din input from the error calculation circuit 1 in the previous stage.

Then, the 24-bit correction value Din is divided into upper 13 bits (Din[23:11]) and lower 11 bits (Din[10:0]), and the upper 13 bits (Din[23:11]) are used as a DAC code. Give it to the next stage.

At this time, 1 is added to Din[23:11] at the frequency of Din[10:0]/2 ¹¹ . This causes the DAC code to increase or decrease with an amplitude of 1 digit.

The DAC output value increases or decreases in the amplitude of 1LSB, by averaging the LPF4 of the subsequent DAC3, generate an intermediate level in 2 ¹¹ steps between 1LSB of the DAC output, the precision of a DC voltage higher than the resolution of DAC3 Occur.

FIG. 4 is an example diagram of a DAC code in the circuit of FIG. 3, in which the left column shows decimal numbers and the right column shows binary numbers. The DAC code repeats the transition with an amplitude of one digit to produce an intermediate value level.

FIG. 5 is an example of an output waveform of the DAC 3, in which 1 LSB of the DAC output is divided into 2 steps (1 bit) to generate an intermediate value, and (A) shows an example of a normal state, and (B) ) Indicates an example of an abnormal state. FIG. 5A shows the DAC output waveform and the LPF output waveform when 5.5 mV is set, and FIG. 5B shows the DAC output waveform and the LPF output waveform when 7.5 mV is set. For simplicity, the DAC output is 1LSB=1 mV.

As shown in FIG. 5B, the DAC output repeats the transition of "00111"/"01000". As described above, many bits change at the same time, so that glitch noise is generated in the output waveform of the DAC 3.

JP-A-7-74639

Patent Document 1 describes high-speed, high-precision interpolation using an interpolation method that combines a DAC code generation unit, a D/A converter, and a low-pass filter in a form that does not include feedback control via an A/D converter. An invention relating to a digital to analog converter is disclosed.

When generating a DC voltage with higher accuracy including feedback control via the A/D converter, an error occurs with respect to the set value when the waveform including such glitch noise is averaged, and the output value linear It may cause deterioration of sex. Although the example of 7.5 mV is shown in FIG. 5, the same problem may occur in the transition in the thick frame shown in the DAC code example diagram of FIG.

The present invention solves such a problem, and an object thereof is to achieve a high-precision analog signal generator capable of reducing an error due to the effect of a glitch on an analog output due to a digital code change and obtaining good linearity. To provide.

In order to achieve such a subject, the invention according to claim 1 of the present invention,
An error calculation circuit that calculates the error between the set value and the feedback value,
A DAC code having a number of bits corresponding to a predetermined bit resolution is generated based on the calculation result of this error calculation circuit, and upper bits are extracted from this DAC code to obtain a DAC code of system A and a DAC code of system A. A DAC code of system B in which the lower 1 bit is added and a DAC code generation unit for generating and outputting a predetermined constant a;
An adder for adding the DAC code of the system B generated and output from the DAC code generator and a predetermined constant a;
A first D/A converter for converting the output of the adder into an analog signal;
A subtractor for subtracting a predetermined constant a from the DAC code of system A generated and output from the DAC code generator,
A second D/A converter for converting the output of the subtractor into an analog signal;
An adder circuit for adding the outputs of the first D/A converter and the second D/A converter,
A low-pass filter connected to this adder circuit output terminal,
An A/D converter that converts the analog output of the adder input through the low-pass filter into a digital signal and inputs the digital signal as the feedback value into the error calculation circuit;
And
The DAC code generator in accordance with an increase of the DAC code, the DAC code of the system A, which is an analog signal generator apparatus characterized by increasing alternately DAC code of the system B.

The invention according to claim 2 is
The analog signal generator according to claim 1,
The DAC code generation unit adds or subtracts the same value to and from the DAC code of the system A and the DAC code of the system B by detecting the DAC code in which a plurality of bits change simultaneously, and avoids repeated change of a plurality of bits. It is characterized by

The invention according to claim 3 is
The analog signal generator according to claim 1,
The analog signal is a DC signal.

The invention according to claim 4 is
The analog signal generator according to claim 1,
The D/A converter is a general-purpose D/A converter.

According to the present invention, it is possible to realize a high-accuracy analog signal generator that can reduce the error due to the effect of a glitch on an analog output due to a change in a digital code and can obtain good linearity with a relatively inexpensive and easy configuration. ..

It is a block diagram which shows one Example of this invention. It is a DAC code example figure in the circuit of FIG. It is a block diagram which shows an example of the conventional DC signal generator. It is a DAC code example figure in the circuit of FIG. It is an output waveform example figure of DAC3.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and the same parts as those in FIG. 3 are designated by the same reference numerals. In FIG. 1, the error calculation circuit 1 outputs a 24-bit [23:0] correction value Din to the DAC code generation unit 2. The DAC code generation unit 2 is provided with a DAC code generation unit 21, an upper 12-bit extraction unit 22, a lower 1-bit addition unit 23, and a code detection unit 24. The DAC code generator 21 generates a 13-bit DAC code. The upper 12-bit extraction unit 22 extracts the upper 12 bits [12:1] from the 13-bit DAC code and outputs 12 bits [11:0]. The lower 1-bit addition unit 23 adds the lowest 1 bit of the 13-bit DAC code to the upper 12-bits [12:1] extracted from the 13-bit DAC code to obtain 12-bit [11:0]. Output. The code detection unit 24 monitors the 13-bit DAC code generated and output from the DAC code generation unit 21 and, when detecting a code in which a glitch is likely to occur, sets a predetermined constant a corresponding to the code to “0” or “4”. Is output.

The output of the high-order 12-bit extraction unit 22 is input to the A terminal of the subtractor 7, the output of the low-order 1-bit addition unit 23 is input to the A terminal of the adder 6, and the constant output of the code detection unit 24 is the adder 6. It is input to the B terminal and also to the B terminal of the subtractor 7.

The output data of the adder 6 is input to the first DAC 3a and converted into an analog signal (for example, a DC signal), and then input to one input terminal of the adder circuit 8.

The output data of the subtracter 7 is input to the second DAC 3b and converted into an analog signal (for example, a signal that increases or decreases with an amplitude of 1 digit), and then is input to the other input terminal of the adder circuit 8. As the DACs 3a and 3b, those having an output resolution of, for example, 12 bits are used, and these outputs are added by an adder circuit 8 to be used as 13 bits.

When the resolutions and full-scale values of the DACs 3a and 3b are the same, the following mathematical formulas hold. As the DACs 3a and 3b, D/A converters that are not designed and manufactured as high-precision electronic components for measuring instruments or the like but are commercially available as general-purpose electronic components can be used.

DAC ₁ (m)+DAC ₂ (n)=DAC ₁ (m+a)+DAC ₂ (n−a)
DAC ₁ (m)... Output value of DAC 3a
DAC ₂ (n)... Output value of DAC 3b

Focusing on the output values of the DACs 3a and 3b, there is no change even if the constant a is added to the input value of the DAC 3a and the constant a is subtracted from the input value of the DAC 3b. In the embodiment circuit shown in FIG. 1, the above equation is realized by providing the adder 6 for adding the constant a at the input stage of the DAC 3a and the subtractor 7 for subtracting the constant a at the input stage of the DAC 3b. ..

FIG. 2 is a diagram showing an example of the input code of the DAC in the circuit of FIG. 1, showing the lower 5 bits of 12-bit input. In FIG. 2, “DAC code” is a 13-bit output of the DAC code generator 21, which is expressed in decimal, and “Offset:0” means that the output a of the code detector 24 is “0”. , "Offset: 4" represents the case where the output a of the code detector 24 is "4". The list on the left shows the inputs of the DACs 3a and 3b at the output a=0, and the list on the right shows the inputs of the DACs 3a and 3b at the output a=4.

In the DAC code generation unit 2, the lower 1 bit addition unit 23 outputs the value obtained by adding the lower 1 bit to the upper 12 bits of the 13 bits of the DAC code to the DAC 3a via the adder 6 and extracted by the higher 12 bit extraction unit 22. The higher 12 bits are output to the DAC 3b via the subtractor 7. As a result, the outputs of the DACs 3a and 3b alternately increase as the DAC code increases.

A portion surrounded by a thick frame in FIG. 2 is a code in which a glitch is likely to occur because a large number of bits change at the same time due to a 1-digit DAC code transition. In the right column where the offset is set to 4 (a=4), the area of DAC code 7 or less is an area that cannot be less than or equal to the lower limit of the set value of DAC 3b. Since it is over the upper limit of the set value, it becomes an impossible area.

When the DAC code generation unit 2 detects a DAC code in which 4 bits or more are simultaneously changed and a glitch is likely to occur, the code detection unit 24 outputs a constant a=4, and the outputs of the DACs 3a and 3b are right in FIG. It becomes like the column.

When the code is used in the state where the constant a=4 is output and a code that easily causes a glitch or a code that cannot be input is detected, the code detection unit 24 outputs the constant a=0 and the DAC 3a is output. The output of 3b is as in the left column of FIG. 2 and returns to the original state.

Specifically, the following operation is performed according to the value of the 13-bit DAC code.
a) (lower 3 bits=7) & (4th bit=1)→constant a=4
b) (Lower 3 bits = 7) & (4th bit = 0)
Or (4th bit and above are all 0)
Or (4th bit or more are all 1) → → → → → Constant a=0
c) Hold constants other than the above

With such a configuration, the DAC code is changed so that “00111”→“01100”⇔“01011” can be obtained by avoiding repeated transitions of 4 bits or more such as “00111”⇔“01000”. It is possible to prevent glitches from occurring at an arbitrary value in the case of a 1-digit transition, and it is possible to obtain an output having good linearity.

Then, a high-precision output can be obtained using a general-purpose D/A converter without using an expensive high-resolution D/A converter.

Further, since the countermeasure against glitch noise in the analog section is unnecessary, the configuration of the low pass filter 4 can be simplified.

As described above, according to the present invention, it is possible to reduce the error due to the effect of the glitch on the analog output due to the change in the digital code, and it is possible to realize a high-resolution analog signal generator capable of obtaining good linearity, and to perform DC measurement. It is suitable as a power source and a DC signal generator.

1 Error Calculation Circuit 2 DAC Code Generator 21 DAC Code Generator 22 Upper 12-bit Extractor 23 Lower 1-bit Adder 24 Code Detector 3a, 3b D/A Converter (DAC)
4 Low pass filter (LPF)
5 A/D converter (ADC)
6 adder 7 subtractor 8 adder circuit

Claims (4)

An error calculation circuit that calculates the error between the set value and the feedback value,
A DAC code having a number of bits corresponding to a predetermined bit resolution is generated based on the calculation result of this error calculation circuit, and upper bits are extracted from this DAC code to obtain a DAC code of system A and a DAC code of system A. A DAC code of system B in which the lower 1 bit is added and a DAC code generation unit for generating and outputting a predetermined constant a;
An adder for adding the DAC code of the system B generated and output from the DAC code generator and a predetermined constant a;
A first D/A converter for converting the output of the adder into an analog signal;
A subtractor for subtracting a predetermined constant a from the DAC code of system A generated and output from the DAC code generator,
A second D/A converter for converting the output of the subtractor into an analog signal;
An adder circuit for adding the outputs of the first D/A converter and the second D/A converter,
A low-pass filter connected to this adder circuit output terminal,
An A/D converter that converts the analog output of the adder input through the low-pass filter into a digital signal and inputs the digital signal as the feedback value into the error calculation circuit;
And
The DAC code generator, the following increase of the DAC code, the DAC code of the system A, the analog signal generator apparatus characterized by increasing alternately DAC code of the system B. The DAC code generation unit adds or subtracts the same value to and from the DAC code of the system A and the DAC code of the system B by detecting the DAC code in which a plurality of bits change simultaneously, and avoids repeated change of a plurality of bits. The analog signal generator according to claim 1, wherein The analog signal generator according to claim 1, wherein the analog signal is a DC signal. The analog signal generator according to claim 1, wherein the D/A converter is a general-purpose D/A converter.

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