JP6698649B2 - Semiconductor device - Google Patents

Description

  The present invention relates to, for example, a transistor and a semiconductor device. Alternatively, the present invention relates to a method for manufacturing a transistor and a semiconductor device, for example. Alternatively, the present invention relates to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a processor, and an electronic device. Alternatively, the present invention relates to a manufacturing method of a display device, a liquid crystal display device, a light emitting device, a storage device, and an electronic device. Alternatively, the present invention relates to a display device, a liquid crystal display device, a light-emitting device, a storage device, and a method for driving an electronic device.

  Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

  Note that in this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.

  Transistors made of silicon are widely used in various integrated circuits (ICs) such as CPUs and memories that constitute electronic devices. 2. Description of the Related Art As electronic devices have become higher in performance, smaller in size, and lighter in weight, integrated circuits have been highly integrated and transistors have been miniaturized. In accordance with this, the process rule for manufacturing a transistor has been reduced to 45 nm, 32 nm, and 22 nm year by year.

  As described above, the miniaturization of transistors has caused a problem called a short channel effect. The short channel effect is deterioration of electrical characteristics which is manifested with miniaturization of a transistor (reduction of channel length (L)), and is caused by the effect of an electric field of a drain electrode reaching a source electrode. is there. Specific examples of the short channel effect include a decrease in threshold voltage, an increase in subthreshold swing value, and an increase in leakage current.

  One of the measures against the short channel effect is a nanowire transistor (see Patent Document 1). A nanowire transistor is a transistor in which an extremely thin cylindrical silicon having a diameter of several nm to several tens nm is used for an active layer. The gate has a structure that surrounds silicon so as to intersect with the extending direction of silicon, and the gate electrode that surrounds the entire circumference can prevent the electric field of the drain electrode from affecting the source electrode.

JP, 2011-111127, A

  However, the leakage current of a nanowire transistor using silicon when it is non-conductive is about several μA/μm, and it is required to further reduce the leakage current at a gate voltage of 0V.

  Therefore, it is an object of one embodiment of the present invention to provide a transistor having resistance to a short channel effect. Another object is to provide a transistor having normally-off electrical characteristics. Another object is to provide a transistor with low leakage current when not conducting. Another object is to provide a transistor with a small subthreshold swing value. Another object is to provide a transistor having stable electric characteristics in a microstructure with a short channel length.

  Another object is to provide a semiconductor device including the transistor. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module. Another object is to provide a novel semiconductor device. Another object is to provide a new module. Another object is to provide a new electronic device.

  Note that the description of these problems does not prevent the existence of other problems. Note that one embodiment of the present invention does not need to solve all of these problems. It should be noted that problems other than these are obvious from the description of the specification, drawings, claims, etc., and other problems can be extracted from the description of the specification, drawings, claims, etc. Is.

  One embodiment of the present invention includes a first conductor provided in a ring shape, an oxide semiconductor having a region extending through the inside of the ring of the first conductor, a first conductor, and an oxide semiconductor. A first insulator provided between the first conductor, a first conductor, a second insulator provided between the first insulator, and an inner side of the ring of the first conductor. And a second conductor provided therein, the second conductor being a semiconductor device provided in the second insulator.

  Further, according to one embodiment of the present invention, in the above invention, a third conductor and a fourth conductor which are in contact with the oxide semiconductor and are sandwiched with the first conductor are provided. The distance between the third conductor and the fourth conductor is 2 nm or more and 30 nm or less, which is a semiconductor device.

  Further, according to one embodiment of the present invention, in the above invention, the oxide semiconductor has a substantially circular cross-sectional shape in a plane substantially perpendicular to the extending direction.

  Further, according to one embodiment of the present invention, in the above invention, the oxide semiconductor has a cross-sectional shape in a plane substantially perpendicular to the extending direction which is a substantially polygonal shape.

  Further, according to one embodiment of the present invention, in the above invention, the semiconductor device is provided over a substrate, and an upper surface of the substrate is substantially parallel to an extension direction of the oxide semiconductor. ..

  Further, according to one embodiment of the present invention, in the above invention, the semiconductor device is provided over a substrate, and an upper surface of the substrate is substantially perpendicular to an extension direction of the oxide semiconductor. ..

  Further, according to one embodiment of the present invention, in the above invention, the first insulator is at least one of indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf) and zinc. A semiconductor device having the above.

  Further, according to one embodiment of the present invention, a first conductor provided over the substrate in a first direction, a first insulator provided over the first conductor, and a first insulator A second insulator having an opening provided on the second insulator and an opening formed in the second insulator and extending in a second direction substantially perpendicular to the first direction. A second conductor provided, a second insulator, a third insulator provided on the second conductor, a fourth insulator provided on the third insulator, A third conductor and a fourth conductor provided on the third insulator with the fourth insulator interposed therebetween, and a fourth insulator, a third conductor, and a fourth conductor. The oxide semiconductor provided in contact with the upper surface of the oxide semiconductor and extending in the second direction, the upper surface and the side surface of the oxide semiconductor, and the side surface of the third conductor with the fifth insulator interposed therebetween. The fifth insulator is provided so as to face the sixth conductor, and the top surface and the side surface of the oxide semiconductor are in contact with the side surface of the fourth conductor, and the fifth insulator is interposed therebetween. And a sixth conductor provided to face the fifth conductor, and provided on the fifth conductor and the sixth conductor, and an opening is provided between the fifth conductor and the sixth conductor. And a fifth insulator provided in contact with the upper surface of the oxide semiconductor, the fifth conductor and the side surface of the sixth conductor, the fifth insulator provided in contact with the side surface of the sixth insulator, No. 5, which has a seventh insulator provided in contact with the upper surface of the insulator, and a seventh conductor provided in contact with the upper surface of the seventh insulator, and is substantially perpendicular to the first direction. The fourth insulator and the fifth insulator are provided so as to surround the oxide semiconductor, and the third insulator and the seventh insulator are the fourth insulator and the oxide. It is provided so as to surround the semiconductor and the fifth insulator, and the first conductor and the seventh conductor are provided so as to surround the first to third insulators and the seventh insulator. And a semiconductor device.

  Further, according to one embodiment of the present invention, in the above invention, the fourth insulator and the fifth insulator are indium and an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). And a semiconductor device containing at least one or more of zinc.

  Further, according to one embodiment of the present invention, in the above invention, the oxide semiconductor contains indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), zinc, and oxygen. A characteristic semiconductor device.

  A transistor having resistance to a short channel effect can be provided. Alternatively, a transistor having normally-off electrical characteristics can be provided. Alternatively, it is possible to provide a transistor with a small leak current when it is not conducting. Alternatively, a transistor with a small subthreshold swing value can be provided. Alternatively, a transistor having stable electric characteristics in a microstructure with a short channel length can be provided.

  Alternatively, a semiconductor device including the transistor can be provided. Alternatively, a module including the semiconductor device can be provided. Alternatively, an electronic device including the semiconductor device or the module can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a new module can be provided. Alternatively, a new electronic device can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally apparent from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the description of the specification, drawings, claims, etc. Is.

3A and 3B are a top view and a cross-sectional view illustrating a transistor of one embodiment of the present invention. 7A and 7B are cross-sectional views illustrating a transistor of one embodiment of the present invention. 7A and 7B are cross-sectional views illustrating a transistor of one embodiment of the present invention. 7A and 7B are cross-sectional views illustrating a transistor of one embodiment of the present invention. 6A to 6C are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention. 6A to 6C are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention. 6A to 6C are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention. FIG. 7 is a band diagram of a transistor according to one embodiment of the present invention. The schematic diagram which shows the model of the transistor used for numerical calculation. The figure showing the potential calculated by numerical calculation. 6A to 6C each illustrate a structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD, and a selected area electron diffraction pattern of the CAAC-OS. A cross-sectional TEM image of the CAAC-OS, a planar TEM image, and an image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 6 is a diagram showing a change in a crystal part of an In—Ga—Zn oxide by electron irradiation. FIG. 11 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. 6A and 6B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. 16A and 16B are graphs and circuit diagrams each illustrating one embodiment of the present invention. 6A and 6B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. 6A and 6B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. FIG. 13 is a block diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 11 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 16 is a perspective view illustrating an electronic device according to one embodiment of the present invention. FIG. 3 is a schematic diagram showing a model of a transistor used in this example. The graph which shows the calculation result of a present Example.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details thereof can be variously modified. The present invention should not be construed as being limited to the description of the embodiments below. In describing the structure of the invention with reference to the drawings, the same reference numerals are used in different drawings. In addition, when referring to the same thing, the hatch pattern may be the same, and there is a case where no reference numeral is given in particular.

  The structures described in the following embodiments can be applied to, combined with, or replaced with the other structures described in the embodiments as appropriate to form one embodiment of the present invention.

  Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity.

  Note that in this specification, the notation “film” and the notation “layer” can be interchanged with each other.

  Further, the voltage often indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Therefore, the voltage can be restated as the potential. Generally, the potential (voltage) is relative and is determined by the relative magnitude from the reference potential. Therefore, even if it is described as "ground potential" or the like, the potential is not always 0V. For example, the lowest potential in the circuit may be the “ground potential”. Alternatively, an intermediate potential in the circuit may be the “ground potential”. In that case, a positive potential and a negative potential are defined with reference to the potential.

  Note that the ordinal numbers given as the first and second are used for convenience and do not indicate the order of steps or the order of stacking. Therefore, for example, “first” can be replaced with “second” or “third” as appropriate. In addition, the ordinal numbers described in this specification and the like may be different from the ordinal numbers used to specify one embodiment of the present invention.

  Note that even when the term “semiconductor” is used, it may have characteristics as an “insulator” if the conductivity is sufficiently low, for example. In addition, the boundary between “semiconductor” and “insulator” is ambiguous and may not be strictly distinguished. Therefore, the “semiconductor” described in this specification can be called the “insulator” in some cases. Similarly, the “insulator” in this specification can be referred to as a “semiconductor” in some cases.

  Further, even when described as “semiconductor”, for example, when the conductivity is sufficiently high, it may have characteristics as a “conductor”. In addition, the boundary between “semiconductor” and “conductor” is ambiguous, and in some cases cannot be strictly distinguished. Therefore, the “semiconductor” described in this specification can be referred to as a “conductor” in some cases. Similarly, the “conductor” described in this specification can be referred to as a “semiconductor” in some cases.

  Note that the impurities of the semiconductor refer to, for example, components other than the main constituents of the semiconductor. For example, an element whose concentration is less than 0.1 atomic% is an impurity. Due to the inclusion of impurities, for example, DOS (Density of State) may be formed in the semiconductor, carrier mobility may be reduced, and crystallinity may be reduced. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 14 element, a Group 15 element, and a transition metal other than the main component. In particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by the mixture of impurities such as hydrogen. When the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include a Group 1 element other than oxygen and hydrogen, a Group 2 element, a Group 13 element, and a Group 15 element.

  Note that the channel length is, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor in which a current flows) and a gate electrode overlap with each other, or a region where a channel is formed, in a top view of the transistor. In, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be set to one value. Therefore, in this specification, the channel length is any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

  The channel width is, for example, a region where a semiconductor (or a portion of a semiconductor in which a current flows when a transistor is in an on state) and a gate electrode overlap with each other, or a region where a channel is formed, a source and a drain face each other. It means the length of the part. Note that in one transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of one transistor may not be set to one value. Therefore, in this specification, the channel width is any one of the values, the maximum value, the minimum value, or the average value in the region where the channel is formed.

  Note that depending on the structure of the transistor, a channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and a channel width shown in a top view of the transistor (hereinafter, an apparent channel width). May be different from. For example, in a transistor having a three-dimensional structure, the effective channel width becomes larger than the apparent channel width shown in the top view of the transistor, and the effect thereof may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of channel regions formed on the side surface and the bottom surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

  In the present specification, “parallel” means a state in which two straight lines are arranged at an angle of −10° or more and 10° or less. Therefore, a case of -5° or more and 5° or less is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30° or more and 30° or less. Further, “vertical” means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

  In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system.

(Embodiment 1)
In this embodiment, a structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

<Transistor configuration>
The structure of a transistor is described below as an example of the semiconductor device of one embodiment of the present invention.

  The structure of the transistor 10 will be described with reference to FIGS. FIG. 1A is a top view of the transistor 10. 1B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 1A, and FIG. 1C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. Note that a region shown by a dashed-dotted line A1-A2 shows a structure in the channel length direction of the transistor 10, and a region shown by a dashed-dotted line A3-A4 shows a structure in a direction perpendicular to the dashed-dotted line A1-A2. .. Note that the channel length direction of a transistor means a direction in which carriers move between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode). Further, in FIGS. 1A and 1B, some structures such as the insulator 112 are omitted in order to avoid complexity of the drawings.

  The transistor 10 includes a conductor 114 provided in a ring shape, a semiconductor 106b having a region extending through the inside of the ring of the conductor 114, an insulator 106a provided between the conductor 114 and the semiconductor 106b, and a conductive material. The insulator 112 is provided between the body 114 and the insulator 106a, and the conductor 102 is provided inside the ring of the conductor 114. Here, the conductor 102 is provided in the insulator 112. Further, a conductor 108a and a conductor 108b which are in contact with the semiconductor 106b and face each other with the conductor 114 interposed therebetween are provided.

  Here, the insulator 106a and the insulator 112 can also be referred to as an insulating film or an insulating layer. Further, the conductor 102, the conductor 108a, the conductor 108b, and the conductor 114 can be referred to as a conductive film or a conductive layer. The semiconductor 106b can also be referred to as a semiconductor film or a semiconductor layer.

  Although details will be described later, when the insulator 106a is used alone, a substance that can function as a conductor, a semiconductor, or an insulator may be used in some cases. However, when a transistor is formed in contact with the semiconductor 106b, electrons flow in the vicinity of the interface between the semiconductor 106b and the insulator 106a, and the insulator 106a has a region which does not function as a channel of the transistor. Therefore, in this specification and the like, the insulator 106a is not described as a conductor or a semiconductor but is described as an insulator.

  In the transistor 10, the semiconductor 106b functions as an active layer, the conductor 114 functions as a gate electrode, the insulator 112 functions as a gate insulating film, and the conductors 108a and 108b function as a source electrode or a drain electrode. ..

  As shown in FIG. 1B, the semiconductor 106b is provided so as to extend at least in a portion passing inside the ring of the conductor 114, and has a string shape, a rod shape, a column shape, or the like, for example. Further, as shown in FIG. 1C, it is preferable that the cross section of the cross section of the semiconductor 106b substantially perpendicular to the extending direction be substantially circular. The width of the semiconductor 106b in FIG. 1C (which can also be referred to as a diameter if the semiconductor 106b is circular) is about several nm to several tens nm, for example, 1 nm to 50 nm, preferably 2 nm to 30 nm. Good. Note that in this specification and the like, the term “approximately circular” includes not only a perfect circle but also a circle deviating from a perfect circle such as an ellipse.

  As described above, the semiconductor 106b is a long and thin wire-shaped structure having a width of several nm to several tens of nm and can be called a nanowire. In addition, as shown in FIGS. 1A to 1C, the insulator 106a, the conductor 108a, the conductor 108b, the insulator 112, the conductor 102, and the conductor 114 are long and thin wire-shaped structures. , And these can also be called nanowires. Further, since the transistor 10 is a transistor using nanowires, it can be called a nanowire transistor.

  As illustrated in FIG. 1B, the insulator 106a is provided in contact with the semiconductor 106b in at least part of a region where the semiconductor 106b and the conductor 114 overlap with each other. In addition, as illustrated in FIG. 1C, the insulator 106a is provided concentrically in contact with the semiconductor 106b in a cross section which is substantially perpendicular to the extension direction (A1-A2 direction) of the semiconductor 106b.

  As shown in FIG. 1B, the conductors 108a and 108b are preferably provided so that their side surfaces are in contact with the insulator 106a and face each other. Although not shown, the conductor 108a and the conductor 108b are preferably provided so as to enclose the semiconductor 106b in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b.

  In addition, as illustrated in FIG. 1B, the channel length L of the transistor 10 is the distance between the conductor 108a and the conductor 108b. The distance between the conductor 108a and the conductor 108b, that is, the channel length L of the transistor 10 may be several nm to several tens nm, for example, preferably 2 nm or more and 30 nm or less.

  Further, as shown in FIG. 1B, it is preferable that side surface end portions of the conductors 108a and 108b have tapered shapes. Specifically, the inclination angle θ of the side surface end portions of the conductors 108a and 108b is 30° or more and less than 90°, preferably 45° or more and less than 80°, and more preferably 45° or more and less than 60°. In this manner, by forming the side surface end portions of the conductors 108a and 108b into tapered shapes, the distance between the conductors 108a and 108b can be further shortened and the channel length L of the transistor 10 can be shortened. You can

  As shown in FIGS. 1B and 1C, the conductor 114 is provided in a ring shape so as to surround at least part of the semiconductor 106b, the insulator 106a, and the conductor 102. In this specification and the like, the term “ring” includes not only a ring shape but also a polygonal shape. Alternatively, the conductor 114 may surround at least part of the semiconductor 106b, the insulator 106a, and the conductor 102. For example, the conductor 114 may have a structure including a closed circuit structure. Here, the conductor 114 is formed so as to overlap with at least part of a region between the conductor 108a and the conductor 108b of the semiconductor 106b (also referred to as a channel formation region of the semiconductor 106b). preferable.

  The insulator 112 is preferably formed so as to fill a space between the insulator 106a and the conductor 114. In addition, it is preferable that the semiconductor 112 b, the conductor 102, and the conductor 114 be insulated by the insulator 112. Therefore, the insulator 112 may be formed by combining a plurality of insulators. For example, the insulator 112 may be a combination of an insulator formed between the insulator 106a and the conductor 102 and an insulator formed between the conductor 102 and the conductor 114.

  The conductor 102 is provided through the inside of the ring of the conductor 114, and is formed between the insulator 106 a and the conductor 114 with the insulator 112 interposed therebetween. In addition, as illustrated in FIG. 1C, in a cross section which is substantially perpendicular to the extension direction (A1-A2 direction) of the semiconductor 106b, the width of the conductor 102 may be approximately equal to the width of the semiconductor 106b, for example. However, the width of the conductor 102 is not limited to this and can be set as appropriate. In addition, in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b, the shape of the conductor 102 may be a shape having a concentric arc with the semiconductor 106b. However, the shape of the conductor 102 is not limited to this, and can be set as appropriate.

  Although the transistor 10 is provided over the substrate, the transistor 10 may be formed so that the extension direction (A1-A2 direction) of the semiconductor 106b is substantially parallel to the upper surface of the substrate. Further, the transistor 10 may be formed so that the extension direction (A1-A2 direction) of the semiconductor 106b is substantially perpendicular to the upper surface of the substrate.

<Semiconductor>
Hereinafter, a detailed configuration of the semiconductor 106b will be described.

  In this item, the detailed structure of the insulator 106a as well as the semiconductor 106b will be described.

  The semiconductor 106b is, for example, an oxide semiconductor containing indium. The semiconductor 106b has a high carrier mobility (electron mobility) when it contains indium, for example. Further, the semiconductor 106b preferably contains the element M. The element M preferably represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf. However, in some cases, a combination of the above-mentioned elements may be used as the element M. The element M is, for example, an element having a high binding energy with oxygen. For example, it is an element having a binding energy with oxygen higher than that of indium. Alternatively, the element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example. Further, the semiconductor 106b preferably contains zinc. The oxide semiconductor may be easily crystallized if it contains zinc.

  However, the semiconductor 106b is not limited to an oxide semiconductor containing indium. The semiconductor 106b may be, for example, an oxide semiconductor containing zinc, an oxide semiconductor containing gallium, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, which does not contain indium, such as zinc tin oxide or gallium tin oxide.

  For example, the insulator 106a is an oxide semiconductor including one or more elements other than oxygen included in the semiconductor 106b. Since the insulator 106a is composed of one or more elements other than oxygen which form the semiconductor 106b, or two or more elements, a defect level is unlikely to be formed at the interface between the insulator 106a and the semiconductor 106b.

  The insulator 106a and the semiconductor 106b preferably contain at least indium. Note that when the insulator 106a is an In-M-Zn oxide, In is less than 50 atomic%, M is higher than 50 atomic%, more preferably 25 atomic% when In and M are 100 atomic%. And M is higher than 75 atomic %. In the case where the semiconductor 106b is an In-M-Zn oxide, In is higher than 25 atomic% and M is less than 75 atomic%, more preferably In is higher than 34 atomic% when the sum of In and M is 100 atomic%. It is high and M is less than 66 atomic %. However, in some cases, the insulator 106a may not contain indium. For example, the insulator 106a may be gallium oxide. Note that the number of atoms of each element included in the insulator 106a and the semiconductor 106b does not have to be a simple integer ratio.

  For example, when a film is formed by a sputtering method, In:M:Zn=1:2:4 and In:M:Zn=1 as typical examples of the atomic ratio of the metal elements of the target used for the insulator 106a. :3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4. :3, In:M:Zn=1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4:6, In:M:Zn=1:6:3. , In:M:Zn=1:6:4, In:M:Zn=1:6:5, In:M:Zn=1:6:6, In:M:Zn=1:6:7, In :M:Zn=1:6:8 and In:M:Zn=1:6:9.

  In addition, for example, when a film is formed by a sputtering method, as a typical example of the atomic ratio of the metal element of the target used for the semiconductor 106b, In:M:Zn=1:1:1 and In:M:Zn= 1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In: There are M:Zn=3:1:2, In:M:Zn=4:2:4.1 and the like. In particular, when the atomic ratio In:Ga:Zn=4:2:4.1 is used as the sputtering target, the atomic ratio of the semiconductor 106b to be formed is In:Ga:Zn=4:2:3. It may be in the vicinity.

  For the semiconductor 106b, for example, an oxide with a wide energy gap is used. The energy gap of the semiconductor 106b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less. Here, the energy gap of the insulator 106a is larger than the energy gap of the semiconductor 106b.

  For the semiconductor 106b, an oxide having an electron affinity higher than that of the insulator 106a is used. For example, as the semiconductor 106b, an oxide having an electron affinity higher than that of the insulator 106a by 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, and more preferably 0.15 eV to 0.4 eV is used. .. The electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band. In other words, the energy level at the lower end of the conduction band of the insulator 106a is closer to the vacuum level than the energy level at the lower end of the conduction band of the semiconductor 106b.

  At this time, when a gate voltage is applied, a channel is formed in the semiconductor 106b having a high electron affinity among the insulator 106a and the semiconductor 106b. Note that when a high gate voltage is applied, current may flow even in the vicinity of the interface between the insulator 106a and the semiconductor 106b.

  As described above, the insulator 106a is made of a substance that can function as a conductor, a semiconductor, or an insulator when used alone. However, when a transistor is formed by stacking with the semiconductor 106b, electrons flow near the interface between the semiconductor 106b or the semiconductor 106b and the insulator 106a, and the insulator 106a has a region which does not function as a channel of the transistor. Therefore, in this specification and the like, the insulator 106a is not described as a semiconductor but is described as an insulator. Note that the insulator 106a is referred to as an insulator because it has a function similar to that of an insulator in function of a transistor as compared with the semiconductor 106b, and thus a substance which can be used for the semiconductor 106b is used as the insulator 106a. In some cases.

  Here, a mixed region of the insulator 106a and the semiconductor 106b may be provided between the insulator 106a and the semiconductor 106b. The mixed region has a low defect level density. Therefore, in the vicinity of the interface between the insulator 106a and the semiconductor 106b, a band diagram in which energy continuously changes (also referred to as continuous junction) is obtained (see FIG. 8). Note that the interface between the insulator 106a and the semiconductor 106b may not be clearly discriminated in some cases.

  At this time, the electrons mainly move in the semiconductor 106b, not in the insulator 106a. As described above, by lowering the density of defect states at the interface between the insulator 106a and the semiconductor 106b, electron movement in the semiconductor 106b is less likely to be hindered, and the on-state current of the transistor can be increased. ..

The insulator 106a and the semiconductor 106b described in this embodiment, particularly the semiconductor 106b are oxide semiconductors with low impurity concentration and low density of defect states (low oxygen deficiency), and have high purity intrinsic or substantially high purity. It can be called an intrinsic oxide semiconductor. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources and thus can have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor rarely has negative threshold voltage (is rarely normally on). Further, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states and thus has a low density of trap states in some cases. Further, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has an extremely small off-state current, has a channel width W of 1×10 ⁶ μm, and has a channel length L of 10 μm, even if it is an element. When the voltage between the drain electrodes (drain voltage) is in the range of 1 V to 10 V, it is possible to obtain the characteristic that the off current is less than the measurement limit of the semiconductor parameter analyzer, that is, 1×10 ⁻¹³ A or less.

  Therefore, a transistor in which a channel region is formed in the above-described highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor can be a highly reliable transistor with less variation in electric characteristics. Note that the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear and may behave like fixed charge. Therefore, electric characteristics of a transistor in which a channel region is formed in an oxide semiconductor with a high trap level density might be unstable. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, and the like.

Hydrogen contained in the insulator 106a and the semiconductor 106b reacts with oxygen bonded to a metal atom to be water, and also forms oxygen vacancies in a lattice from which oxygen is released (or a portion from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons that are carriers may be generated. Further, part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. In particular, hydrogen trapped in oxygen vacancies may form a shallow donor level with respect to the semiconductor band structure. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable that the insulator 106a and the semiconductor 106b have hydrogen as low as possible. Specifically, in the insulator 106 a and the semiconductor 106 b, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 2×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, 5×10 ¹⁸ atoms/cm ³ or less, preferably 1×10 ¹⁸ atoms/cm ³ or less, more preferably 5×10 ¹⁷ atoms/cm ³ or less. cm ³ or less, and more preferably 1×10 ¹⁶ atoms/cm ³ or less.

If silicon or carbon, which is one of Group 14 elements, is included in the insulator 106a and the semiconductor 106b, oxygen vacancies increase in the insulator 106a and the semiconductor 106b, so that the insulator 106a and the semiconductor 106b become n-type. Therefore, the concentration of silicon or carbon in the insulator 106a and the semiconductor 106b and the concentration of silicon or carbon near the interface between the insulator 106a and the semiconductor 106b (the concentration obtained by SIMS analysis) are 2×10 ¹⁸ atoms/cm ³ Hereafter, it is preferably 2×10 ¹⁷ atoms/cm ³ or less.

In the insulator 106a and the semiconductor 106b, the concentration of an alkali metal or an alkaline earth metal obtained by SIMS analysis is 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less. Alkali metal and alkaline earth metal may generate carriers when combined with an oxide semiconductor, which might increase off-state current of the transistor. Therefore, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the insulator 106a and the semiconductor 106b.

When nitrogen is contained in the insulator 106a and the semiconductor 106b, electrons that are carriers are generated, carrier density is increased, and n-type is easily generated. As a result, a transistor including an oxide semiconductor film containing nitrogen is likely to have normally-on characteristics. Therefore, in the semiconductor 106b, nitrogen is preferably reduced as much as possible. For example, the nitrogen concentration obtained by SIMS analysis is preferably 5×10 ¹⁸ atoms/cm ³ or less.

  Further, a low resistance region may be formed in the vicinity of an interface in contact with the conductor 108a such as the semiconductor 106b or the conductor 108b. The low resistance region is mainly formed by oxygen being extracted to the conductor 108a or the conductor 108b in contact with the semiconductor 106b, or the conductive material contained in the conductor 108a or the conductor 108b is bonded to an element in the semiconductor 106b. It is formed. By forming such a low resistance region, the contact resistance between the conductor 108a or the conductor 108b and the semiconductor 106b can be reduced, so that the on-state current of the transistor 10 can be increased.

  Note that the above-described two-layer structure of the insulator 106a and the semiconductor 106b is an example. For example, a single-layer structure in which the insulator 106a is not provided may be used, or an n-layer structure (n is an integer of 3 or more) that further includes any of the insulators, semiconductors, or conductors illustrated as the insulator 106a or the semiconductor 106b. I don't care.

  Note that the structure of the oxide semiconductor will be described in detail in embodiments to be described later.

<Calculation of channel potential>
Here, a result of performing numerical calculation on a model of a transistor including an oxide semiconductor film and evaluating a height of a potential barrier in a channel portion is described.

FIG. 9 shows a schematic diagram of the model of the transistor used for the numerical calculation. As shown in FIG. 9, in the model used for the numerical calculation, the semiconductor film is formed between the source electrode and the drain electrode, the gate insulating film is formed on the source electrode, the semiconductor film, and the drain electrode, and the gate insulating film is formed. A gate electrode is formed on the. In FIG. 9, ε _S is the dielectric constant of the semiconductor film, ε _OX is the dielectric constant of the gate insulating film, t _S is the thickness of the semiconductor film, and t _OX is the thickness of the gate insulating film. In the numerical calculation, the relative permittivity of ε _S was 15, the relative permittivity of ε _OX was 4.1, and the permittivity in vacuum was 8.854187817×10 ⁻¹² F/m. Further, t _S was set to 15 nm and t _OX was set to 10 nm. Further, the distance (channel length) between the source electrode and the drain electrode is L.

  For the transistor shown in FIG. 9, Gauss's law is applied to the minute sections x to x+dx in the semiconductor film to be the channel portion, which are shown by hatching in the figure. Here, the transistor including an oxide semiconductor film is an n-channel storage transistor and is represented by the following formula (1).

Here, φ(x) is the potential (surface potential) at the position x, φ(x+dx) is the potential (surface potential) at the position x+dx, V _G is the gate voltage, V _FB is the flat band voltage, and e is the elementary charge, N _C is the effective density of states, k _B is the Boltzmann constant, and T is the absolute temperature. In the numerical calculation, V _G =0V, V _FB =0.4V, N _C =5.00×10 ¹⁸ pieces/cm ³ , and T=300K.

  Further, assuming an n-channel inversion type transistor as a comparison target, the transistor is expressed by the following equation (2).

Here, N _A is the acceptor density, and was set to N _A =1.00×10 ⁸ pieces/cm ^{3 in} the numerical calculation.

  The Poisson's equation is obtained by modifying the above equations (1) and (2). The Poisson equation was numerically calculated and the potential of the channel part was analyzed. Numerical calculations were performed for models of L=1 μm, 300 nm, 100 nm, 60 nm, 30 nm, and 10 nm in each of the storage type equation (1) and the inversion type equation (2). The numerical calculation was performed according to the Gauss-Seidel method.

  10A and 10B show the results of numerical calculation of the potential of the storage-type channel portion and the potential of the inversion-type channel portion. 10A and 10B, the horizontal axis represents x [nm] and the vertical axis represents −eφ(x) [eV]. 10C and 10D are graphs in which the horizontal axis x in FIGS. 10A and 10B is normalized by L.

  Comparing FIGS. 10(A) and 10(C) with FIGS. 10(B) and 10(D), the potentials are approximately the same in the models of L=1 μm, 300 nm, and 100 nm. On the other hand, in the models of L=60 nm, 30 nm, and 10 nm, the potential of the accumulation type model is larger than the potential of the inversion type model, and the tendency becomes more remarkable as L becomes shorter.

As described above, in a transistor having a short channel length of less than L=100 nm, a storage-type transistor including an oxide semiconductor film has a higher barrier barrier at V _G =0 V than an inversion-type transistor such as silicon. Was done. Therefore, in the storage transistor including an oxide semiconductor film, the threshold voltage can be higher than 0 V even in a structure with a short channel length of less than L=100 nm. That is, it can be said that a storage transistor including an oxide semiconductor film has higher resistance to a short channel effect than an inversion transistor such as silicon.

  Further, as shown in the above embodiment mode, the impurity concentration in the OS film is reduced to a high-purity intrinsic or substantially high-purity intrinsic, whereby the carrier density can be further reduced; thus, a shorter channel effect can be obtained. Can be more resistant to.

  Further, as shown in this embodiment, by forming a transistor having a structure in which an oxide semiconductor film is surrounded by a gate electrode, a transistor having resistance to a short channel effect can be formed. For example, it is presumed that good off-current characteristics can be obtained even when the channel length is about 2 nm to 30 nm.

<insulator, conductor>
Hereinafter, each component of the transistor 10 other than the semiconductor will be described in detail.

  It is preferable that the conductor 102 at least partly overlap with each other in a region between the conductor 108a and the conductor 108b of the semiconductor 106b. The conductor 102 functions as a back gate of the transistor 10. By providing such a conductor 102, the threshold voltage of the transistor 10 can be controlled. By controlling the threshold voltage, the transistor 10 is prevented from becoming conductive when the voltage applied to the gate (the conductor 114) of the transistor 10 is low, for example, when the applied voltage is 0 V or lower. be able to. That is, it becomes easier to shift the electrical characteristics of the transistor 10 in the normally-off direction.

  As the conductor 102, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, A conductor containing one or more kinds of tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen. Etc. may be used.

  The insulator 112 functions as a gate insulating film with respect to the conductor 114 and the conductor 102 in the transistor 10. The insulator 112 is preferably an insulator having excess oxygen. For example, the insulator 112 includes, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The body may be used as a single layer or as a stack. For example, as the insulator 112, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide is used. Tantalum may be used. Preferably, silicon oxide or silicon oxynitride is used.

  By providing the insulator 112 containing excess oxygen, oxygen can be supplied from the insulator 112 to the insulator 106a and the semiconductor 106b. With the oxygen, oxygen vacancies which are defects in the insulator 106a and the semiconductor 106b can be reduced. Accordingly, the defect level density of the insulator 106a and the semiconductor 106b can be reduced.

  Note that in this specification and the like, excess oxygen refers to oxygen contained in excess of the stoichiometric composition, for example. Alternatively, excess oxygen means oxygen released from a film or a layer containing the excess oxygen by heating, for example. Excess oxygen can move inside a film or layer, for example. Excessive oxygen may move between atoms in the film or layer, or may move in a blunt manner while replacing oxygen forming the film or layer.

The insulator 112 having excess oxygen has a desorption amount of oxygen molecules within a surface temperature range of 100° C. or higher and 700° C. or lower or 100° C. or higher and 500° C. or lower in thermal desorption spectroscopy analysis (TDS analysis). Is 1.0×10 ¹⁴ molecule/cm ² or more and 1.0×10 ¹⁶ molecule/cm ² or less, and more preferably 1.0×10 ¹⁵ molecule/cm ² or more and 5.0×10 ¹⁵ molecule/cm ² or less. Becomes

  A method for measuring the amount of released molecules using TDS analysis will be described below by taking the amount of released oxygen as an example.

  The total amount of released gas in TDS analysis of the measurement sample is proportional to the integral value of the ionic strength of the released gas. Then, by comparing with the standard sample, the total amount of released gas can be calculated.

For example, from the TDS analysis result of a silicon substrate containing hydrogen having a predetermined density, which is a standard sample, and the TDS analysis result of a measurement sample, the amount of released oxygen molecules (N _O2 ) of the measurement sample should be calculated by the following formula. You can Here, it is assumed that all the gases detected by TDS analysis with a mass-to-charge ratio of 32 are derived from oxygen molecules. The mass to charge ratio of CH ₃ OH is 32, but is not considered here as it is unlikely to be present. Oxygen molecules containing oxygen atoms having a mass number of 17 and oxygen atoms having a mass number of 18, which are isotopes of oxygen atoms, are not considered because their abundance ratios in nature are extremely small.

N _O2 =N _H2 /S _H2 ×S _O2 ×α

_NH2 is a value obtained by converting the hydrogen molecules desorbed from the standard sample into densities. S _H2 is an integrated value of ion intensity when the standard sample is subjected to TDS analysis. Here, the reference value of the standard sample is N _H2 /S _H2 . S _O2 is an integrated value of ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ionic strength in TDS analysis. For details of the above equation, reference is made to JP-A-6-275697. The amount of released oxygen is measured by using a thermal desorption spectroscopy apparatus EMD-WA1000S/W manufactured by Electronic Science Co., Ltd. and using a silicon substrate containing a certain amount of hydrogen atoms as a standard sample.

  Further, in TDS analysis, part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Since the above-mentioned α includes the ionization rate of oxygen molecules, it is possible to estimate the release amount of oxygen atoms by evaluating the release amount of oxygen molecules.

Note that N _O2 is the amount of released oxygen molecules. The release amount when converted into oxygen atoms is twice the release amount of oxygen molecules.

Alternatively, the insulator that releases oxygen by heat treatment may contain a peroxide radical. Specifically, it means that the spin density due to the peroxide radical is 5×10 ¹⁷ spins/cm ³ or more. Note that an insulator containing a peroxide radical may have an asymmetric signal with ag value of around 2.01 by an electron spin resonance method (ESR).

  Further, the insulator 112 may have a function of preventing diffusion of impurities from the outside of the insulator 112.

  The conductor 108a and the conductor 108b each function as either a source electrode or a drain electrode of the transistor 10.

  As the conductor 108a and the conductor 108b, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, A conductor containing one or more kinds of silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen. Etc. may be used.

  The conductor 114 functions as a gate electrode of the transistor 10. As the conductor 114, a conductor that can be used as the conductor 102 may be used.

  Here, as shown in FIG. 1C, a gate electric field can be applied from the entire periphery of the semiconductor 106b by having a structure in which the conductor 114 surrounds the semiconductor 106b in a cross section perpendicular to the channel length direction. As a result, it is possible to reduce the occurrence of leakage current during non-conduction due to the DIBL (Drain Induced Barrier Lowering) effect.

  The DIBL effect is an effect caused by application of a drain voltage, and an energy barrier at a junction between a source and a semiconductor is reduced, so that a subthreshold characteristic is deteriorated. As the width of the depletion layer in the drain side region widens, the voltage drop in the source side region increases. In particular, when the channel length is short as in the transistor described in this embodiment, a more remarkable effect appears, which is sometimes called a single-channel effect.

  On the other hand, in the transistor 10 described in this embodiment, the expansion of the depletion layer on the drain side can be suppressed by applying the gate electric field from the entire periphery of the semiconductor 106b. As a result, the transistor 10 can reduce leakage current when it is not conducting, reduce the subthreshold swing value, and have normally-off electrical characteristics.

  Further, as described above, the oxide semiconductor used for the semiconductor 106b is a storage type and the threshold voltage can be easily made higher than 0 V even in a structure with a short channel length.

  Further, the transistor 10 described in this embodiment is provided with the conductor 102 which functions as a back gate, so that the threshold voltage can be easily controlled.

  With the above structure, a transistor having resistance to a short channel effect can be provided. Alternatively, a transistor having normally-off electrical characteristics can be provided. Alternatively, it is possible to provide a transistor with a small leak current when it is not conducting. Alternatively, a transistor having a small subthreshold swing value can be provided. Alternatively, a transistor having stable electric characteristics in a microstructure with a short channel length can be provided.

<Transistor modification>
Hereinafter, modified examples of the transistor 10 will be described with reference to FIGS. Note that FIGS. 2A to 2F and FIGS. 3A and 3B are cross-sectional views in the channel length direction of the transistor and the channel width of the transistor, as in FIGS. It becomes a sectional view in the direction.

  In the transistor 10 described above, the cross-sectional shape of the cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b is substantially circular, but the semiconductor device described in this embodiment is not limited to this. For example, the cross-sectional shape in a cross section substantially perpendicular to the extension direction (A1-A2 direction) of the semiconductor 106b may be a substantially polygonal shape. Note that in this specification and the like, the term “substantially polygonal shape” includes not only a strict polygonal shape such as a triangle and a quadrangle, but also a polygonal shape with rounded corners.

  For example, in the transistor 10a illustrated in FIGS. 2A and 2B, the cross-sectional shape in a cross section which is substantially perpendicular to the extension direction (A1-A2 direction) of the semiconductor 106b is a square shape with rounded corners. Different from the transistor 10. The shapes of the insulator 106a, the insulator 112, and the conductor 114 in the same cross section correspond to the cross sectional shape of the semiconductor 106b.

  In addition, for example, in the transistor 10b illustrated in FIGS. 2C and 2D, a cross-sectional shape in a cross section which is substantially perpendicular to the extension direction (A1-A2 direction) of the semiconductor 106b is a triangle with rounded corners. Is different from the transistor 10. The shapes of the insulator 106a, the insulator 112, and the conductor 114 in the same cross section correspond to the cross sectional shape of the semiconductor 106b.

  Further, in the transistor 10a and the transistor 10b, an example in which the cross-sectional shape of a cross section substantially perpendicular to the extending direction of the semiconductor 106b (A1-A2 direction) is close to a regular polygon is shown; however, the semiconductor device described in this embodiment. Is not limited to this. For example, as in a transistor 10c illustrated in FIGS. 2E and 2F, a cross-sectional shape in a cross section which is substantially perpendicular to the extension direction (A1-A2 direction) of the semiconductor 106b is a hexagonal shape with rounded corners. The shape may be different from the regular hexagon. The shapes of the insulator 106a, the insulator 112, and the conductor 114 in the same cross section correspond to the cross sectional shape of the semiconductor 106b.

  Alternatively, as in the transistor 10d illustrated in FIGS. 3A and 3B, the conductor 102 may be provided outside the conductor 114.

  Further, as in the transistor 10e illustrated in FIG. 3C, a plurality of nanowires including the semiconductor 106b, the insulator 106a, the insulator 112, and the conductor 102 are arranged so that the semiconductor 106b extends in parallel. Alternatively, a single conductor 114 may surround each nanowire. With such a configuration, a small on-current can be sufficiently increased with one nanowire.

  Further, an example in which the transistor 50 is provided so that the extension direction of the nanowire is substantially parallel to the upper surface of the substrate will be described with reference to FIGS. FIG. 4A is a top view of the transistor 50. 4B is a cross-sectional view taken along dashed-dotted line B1-B2 in FIG. 4A, and FIG. 4C is a cross-sectional view taken along dashed-dotted line B3-B4 in FIG. 4A. Note that a region indicated by a dashed-dotted line B1-B2 shows a structure in the channel length direction of the transistor 50, and a region indicated by a dashed-dotted line B3-B4 shows a structure in a direction perpendicular to the dashed-dotted line B1-B2. .. In addition, in FIG. 4A, some structures such as the insulator 162 are omitted in order to avoid complexity of the drawing.

  The transistor 50 has an insulator 151 provided over the substrate 150. Further, an insulator 157 having an opening provided over the insulator 151 is included. Further, a conductor 164a which extends in the B3-B4 direction is provided in the opening. Further, an insulator 162a provided over the conductor 164a is included. Further, an insulator 162b having an opening provided over the insulator 162a is provided. Further, the conductor 152 which extends in the B1-B2 direction is provided in the opening formed in the insulator 162b. Further, the insulator 162b and the insulator 162c provided over the conductor 152 are included. Further, an insulator 156a provided over the insulator 162c is included. Further, a conductor 158c and a conductor 158d which are provided with the insulator 156a interposed therebetween are provided over the insulator 162c. Further, a semiconductor 156b provided in contact with the top surfaces of the insulator 156a, the conductor 158c, and the conductor 158d and extending in the B1-B2 direction is provided. Further, a conductor 158a is provided which is in contact with the top surface and the side surface of the semiconductor 156b and the side surface of the conductor 158c so as to face the conductor 158b with the insulator 156c interposed therebetween. Further, a conductor 158b is provided which is in contact with the top surface and the side surface of the semiconductor 156b and the side surface of the conductor 158d so as to face the conductor 158a with the insulator 156c interposed therebetween. Further, an insulator 167 which is provided over the conductors 158a and 158b and has an opening between the conductors 158a and 158b is provided. Further, an insulator 156c provided in contact with the top surface of the semiconductor 156b, the side surfaces of the conductor 158a and the conductor 158b, and the side surface of the insulator 167 is provided. Further, an insulator 162d provided in contact with the top surface of the insulator 156c is included. Further, a conductor 164b provided in contact with the top surface of the insulator 162d is included.

  In the cross section in the B3-B4 direction, the insulator 156a and the insulator 156c are provided so as to surround the semiconductor 156b, and the side ends of the insulator 156a and the insulator 156c are substantially aligned with each other. In a cross section in the B3-B4 direction, the insulator 162c and the insulator 162d are provided so as to surround the insulator 156a, the semiconductor 156b, and the insulator 156c, and side end portions of the insulator 162c and the insulator 162d are substantially uniform. I am doing it. In the cross section in the B3-B4 direction, the conductors 164a and 164b are provided so as to surround the insulators 162a to 162d.

  The transistor 50 is provided corresponding to the transistor 10. The semiconductor 156b corresponds to the semiconductor 106b, and a semiconductor that can be used as the above-described semiconductor 106b may be used. The insulator 156a and the insulator 156c correspond to the insulator 106a, and an insulator or a semiconductor which can be used as the above-described insulator 106a may be used. The insulators 162a to 162d correspond to the insulator 112, and any insulator that can be used as the above-described insulator 112 may be used. The conductor 152 corresponds to the conductor 102, and a conductor that can be used as the above-described conductor 102 may be used. The conductors 164a and 164b correspond to the conductor 114, and a conductor that can be used as the above-described conductor 114 may be used.

As a modification of the transistor 50, a transistor 50a is shown in FIGS. FIG. 4(D) corresponds to FIG. 4(B), and FIG. 4(E) corresponds to FIG. 4(C). The transistor 50a differs from the transistor 50 in that the inclination angle θ ₁ of the side surface end portion of the conductor 158a (or the conductor 158b) and the inclination angle θ ₂ of the side surface end portion of the insulator 167 do not match. Here, the inclination angle θ ₁ of the side surface end portions of the conductor 158a and the conductor 158b is preferably 30° or more and less than 90°, preferably 45° or more and less than 80°, more preferably 45° or more and less than 60°. .. Further, the inclination angle θ ₂ of the side surface end portion of the insulator 167 is preferably larger than the inclination angle θ ₁ . In this manner, by making the side surface end portions of the conductors 158a and 158b tapered, the distance between the conductors 158a and 158b can be further shortened and the channel length L of the transistor 50a can be shortened. You can

  In addition, as illustrated in FIG. 4D, the semiconductor 156b may have a region between the conductors 158a and 158b that has a smaller thickness than a region where the conductors 158a and 158b overlap with each other. This is formed by removing part of the upper surface of the semiconductor 156b when forming the conductors 158a and 158b. A low resistance region may be formed on the upper surface of the semiconductor 156b when a conductor to be the conductor 158a and the conductor 158b is formed. As described above, by removing the region located between the conductors 158a and 158b on the upper surface of the semiconductor 156b, formation of a channel in the low resistance region on the upper surface of the semiconductor 156b can be prevented. Further, in the following drawings, even when the thin film region is not shown in an enlarged view or the like, a similar thin film region may be formed.

<Method for manufacturing transistor>
Hereinafter, a method for manufacturing the transistor 50 will be described with reference to FIGS.

  First, the substrate 150 is prepared. As the substrate 150, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a single semiconductor substrate made of silicon, germanium, or the like, or a semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like. Further, there is a semiconductor substrate having an insulating region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, a substrate including a metal nitride, a substrate including a metal oxide, or the like can be given. Furthermore, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like. Alternatively, a substrate provided with an element may be used. The elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.

  Alternatively, as the substrate 150, a flexible substrate that can withstand heat treatment at the time of manufacturing a transistor may be used. Note that as a method for providing a transistor over a flexible substrate, there is also a method in which the transistor is formed over a non-flexible substrate, the transistor is separated, and the transistor is transferred to the substrate 150 which is a flexible substrate. In that case, a peeling layer may be provided between the non-flexible substrate and the transistor. Note that as the substrate 150, a fiber-woven sheet, film, foil, or the like may be used. Further, the substrate 150 may have elasticity. Further, the substrate 150 may have a property of returning to its original shape when bending or pulling is stopped. Alternatively, it may have a property of not returning to the original shape. The thickness of the substrate 150 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. When the substrate 150 is thin, the weight of the semiconductor device can be reduced. Further, by thinning the substrate 150, the substrate 150 may have elasticity even when glass or the like is used, or may have a property of returning to an original shape when bending or pulling is stopped. Therefore, a shock or the like applied to the semiconductor device over the substrate 150 by dropping or the like can be mitigated. That is, a durable semiconductor device can be provided.

As the substrate 150 that is a flexible substrate, for example, a metal, an alloy, a resin, glass, or a fiber thereof can be used. It is preferable that the substrate 150, which is a flexible substrate, has a lower linear expansion coefficient because deformation due to the environment is suppressed. As the substrate 150 which is a flexible substrate, for example, a material having a linear expansion coefficient of 1×10 ⁻³ /K or less, 5×10 ⁻⁵ /K or less, or 1×10 ⁻⁵ /K or less may be used. Good. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic and the like. In particular, aramid has a low linear expansion coefficient, and thus is suitable as the substrate 150 which is a flexible substrate.

  Next, the insulator 151 is formed. The insulator 151 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, or a pulsed laser deposition (PLD) method. It can be performed using a deposition (ALD: Atomic Layer Deposition) method or the like.

  As the insulator 151, an insulator having a function of blocking hydrogen or water is used. Hydrogen and water in the insulator provided in the vicinity of the insulator 156a and the semiconductor 156b are one of the factors that generate carriers in the insulator 156a and the semiconductor 156b. This may reduce the reliability of the transistor 50. In particular, when a substrate provided with a silicon-based semiconductor element such as a switch element is used as the substrate 150, hydrogen is used to terminate the dangling bond of the semiconductor element and the hydrogen may diffuse to the transistor 50. On the other hand, by providing the insulator 151 having a function of blocking hydrogen or water, diffusion of hydrogen or water from the lower layer of the transistor 10 can be suppressed and the reliability of the transistor 50 can be improved.

  Further, the insulator 151 preferably has a function of blocking oxygen. Since the insulator 151 blocks oxygen which diffuses from the insulator 162c and the insulator 162d, oxygen can be effectively supplied from the insulator 162c and the insulator 162d to the insulator 156a and the semiconductor 156b.

  As the insulator 151, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like can be used. When these are used as the insulator 151, they can function as an insulating film having an effect of blocking diffusion of oxygen, hydrogen, or water. Further, as the insulator 151, for example, silicon nitride, silicon nitride oxide, or the like can be used. By using these as the insulator 151, they can function as an insulating film having an effect of blocking diffusion of hydrogen and water.

  Next, an insulator to be the insulator 157 is formed. As the insulator, an insulator that can be used as the above-described insulator 112 may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, a resist or the like is formed over the insulator and processed using the resist or the like to form the insulator 157 having an opening.

  The resist is removed after the object is processed by etching or the like. Plasma treatment and/or wet etching is used to remove the resist. Plasma ashing is suitable for the plasma treatment. If the resist or the like is insufficiently removed, the resist left behind by hydrofluoric acid or/and ozone water having a concentration of 0.001 volume% or more and 1 volume% or less may be removed.

  Next, a conductor to be the conductor 164a is formed. As the conductor to be the conductor 164a, the above-described conductor can be used. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, the conductor is polished until the insulator 157 is exposed, so that the conductor 164a is formed (see FIGS. 5A and 5B). The polishing can be performed by CMP processing or the like.

  Next, an insulator 162e to be the insulator 162a in a later step is formed. As the insulator 162e, an insulator that can be used as the above-described insulator 112 may be used. The insulator 162e can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, an insulator to be the insulator 162b is formed in a later step. As the insulator, an insulator that can be used as the above-described insulator 112 may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, a resist or the like is formed over the insulator and processed using the resist or the like, so that the insulator 162f having an opening is formed.

  Next, a conductor to be the conductor 152 is formed. As the conductor serving as the conductor 152, a conductor that can be used as the above conductor 102 may be used. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, the conductor is polished until the insulator 162f is exposed, so that the conductor 152 is formed (see FIGS. 5C and 5D). The polishing can be performed by CMP processing or the like.

  Next, an insulator 162g to be the insulator 162c in a later step is formed. As the insulator 162g, an insulator that can be used as the above-described insulator 112 may be used. The insulator 162g can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, the film formation may be performed while heating the substrate in order to reduce water or hydrogen contained in the insulator 162g.

  Next, heat treatment is preferably performed. By performing the heat treatment, water or hydrogen contained in the insulator 162g or the like can be further reduced. In some cases, the insulator 162g can have excess oxygen. The heat treatment may be performed at 250 °C to 650 °C inclusive, preferably 450 °C to 600 °C inclusive, and more preferably 520 °C to 570 °C inclusive. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an inert gas atmosphere and then in an atmosphere containing an oxidizing gas in an amount of 10 ppm or more, 1% or more, or 10% or more in order to supplement desorbed oxygen. For the heat treatment, an RTA device using lamp heating can be used. The heat treatment by the RTA device requires a shorter time than that in the furnace, and is effective for improving productivity.

  Next, an insulator to be the insulator 156a is formed in a later step and processed with a resist or the like to form the insulator 156d (see FIGS. 5E and 5F). As the insulator 156d, an insulator, a semiconductor, or the like that can be used as the insulator 106a described above may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, a conductor to be the conductor 158c and the conductor 158d is formed in a later step, and the conductor is polished until the insulator 156d is exposed to form the conductor 158e and the conductor 158f (FIG. 5). (See (G) and (H)). The polishing can be performed by CMP processing or the like. As the conductors 158e and 158f, conductors that can be used as the conductors 108a and 108b described above may be used. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, a semiconductor to be the semiconductor 156b is formed. As the semiconductor, a semiconductor that can be used as the above-described semiconductor 106b may be used. The semiconductor film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, heat treatment is preferably performed. By performing the heat treatment, water or hydrogen in the semiconductor to be the semiconductor 156b, the insulator 156d, or the insulator 162g can be further reduced. In some cases, the insulator 162g can have excess oxygen. The heat treatment may be performed at 250 °C to 650 °C inclusive, preferably 450 °C to 600 °C inclusive, and more preferably 520 °C to 570 °C inclusive. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an inert gas atmosphere and then in an atmosphere containing an oxidizing gas in an amount of 10 ppm or more, 1% or more, or 10% or more in order to supplement desorbed oxygen. By the heat treatment, crystallinity of a semiconductor to be the insulator 156d and the semiconductor 156b can be increased, impurities such as hydrogen and water can be removed, and the like. For the heat treatment, an RTA device using lamp heating can be used. The heat treatment by the RTA device requires a shorter time than that in the furnace, and is effective for improving productivity.

  Next, a resist or the like is formed over the semiconductor, and processing is performed using the resist or the like to form the semiconductor 156b. Then, a resist or the like is formed over the conductor 158e and the conductor 158f, and processing is performed using the resist or the like to form the conductor 158c and the conductor 158d (see FIGS. 6A and 6B).

  Further, heat treatment is preferably performed after the semiconductor 156b is formed. By performing the heat treatment, water or hydrogen in the semiconductor 156b, the insulator 156d, or the insulator 162g can be further reduced. In some cases, the insulator 162g can have excess oxygen. The heat treatment may be performed at 250 °C to 650 °C inclusive, preferably 450 °C to 600 °C inclusive, and more preferably 520 °C to 570 °C inclusive. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an inert gas atmosphere and then in an atmosphere containing an oxidizing gas in an amount of 10 ppm or more, 1% or more, or 10% or more in order to supplement desorbed oxygen. By the heat treatment, crystallinity of the insulator 156d and the semiconductor 156b can be increased, impurities such as hydrogen and water can be removed, and the like. For the heat treatment, an RTA device using lamp heating can be used. The heat treatment by the RTA device requires a shorter time than that in the furnace, and is effective for improving productivity.

  Further, high density plasma treatment or the like may be performed. High-density plasma may be generated using microwaves. In the high density plasma treatment, for example, an oxidizing gas such as oxygen or nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a rare gas such as He, Ar, Kr, or Xe may be used. A bias may be applied to the substrate in the high density plasma treatment. As a result, oxygen ions in the plasma can be drawn to the substrate side. The high-density plasma treatment may be performed while heating the substrate. For example, when high-density plasma treatment is performed instead of the heat treatment, the same effect can be obtained at a temperature lower than the temperature of the heat treatment. The high-density plasma treatment may be performed before the insulator 156d is formed, after the opening of the insulator 167 described later is formed, or after the insulator 156f described later is formed.

  Next, a conductor to be the conductor 158a and the conductor 158b is formed. A resist or the like is formed on the conductor and processed using the resist or the like to form the conductor in an island shape. As the conductor, a conductor that can be used as the conductor 108a and the conductor 108b described above may be used. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, an insulator to be the insulator 167 is formed. As the insulator, an insulator that can be used as the above-described insulator 112 may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, a resist or the like is formed over the insulator and processed using the resist or the like to form the insulator 167, the conductor 158a, and the conductor 158b (see FIGS. 6C and 6D).

  Next, an insulator 156e to be the insulator 156c in a later step is formed (see FIGS. 6E and 6F). As the insulator 156e, an insulator, a semiconductor, or the like that can be used as the insulator 106a described above may be used. The insulator 156e can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, a resist or the like is formed over the insulator 156e and processed using the resist or the like to form the insulator 156f and the insulator 156a (see FIGS. 7A and 7B). Here, the side surfaces of the insulator 156f and the insulator 156a in the B3-B4 direction are formed to substantially coincide with each other.

  Next, an insulator to be the insulator 162d is formed in a later step. As the insulator, an insulator, a semiconductor, or the like that can be used as the insulator 112 described above may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, a resist or the like is formed over the insulator and processed using the resist or the like to form the insulator 162a, the insulator 162b, the insulator 162c, and the insulator 162h (see FIGS. 7C and 7D). ..). Here, the side surfaces of the insulator 162a, the insulator 162b, the insulator 162c, and the insulator 162h in the B3-B4 direction are formed to be substantially aligned with each other.

  Next, a conductor to be the conductor 164b is formed. As the conductor, a conductor that can be used as the above-described conductor 114 may be used. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, the conductor 164b, the insulator 162d, and the insulator 156c are formed by polishing from above the conductor until the insulator 167 is exposed (see FIGS. 7E and 7F). The conductor 164b and the insulator 162d have a function as a gate electrode and a gate insulator of the transistor 50, respectively. The conductor 164b and the insulator 162d can be formed in a self-aligned manner by the method described above.

  Further, an insulator functioning as a protective insulating film may be formed. As the insulator, an insulator that can be used as the above-described insulator 151 may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, by forming a film of an insulator by a sputtering method in an atmosphere containing oxygen, oxygen can be added to the surfaces of the insulator 162d and the insulator 167 at the same time as the film formation.

  Next, heat treatment is preferably performed. By heat treatment, oxygen added to the insulator 162c, the insulator 162d, and the insulator 167 can be diffused and supplied to the insulator 156a, the semiconductor 156b, and the insulator 156c.

  Through the above steps, the transistor of one embodiment of the present invention can be manufactured.

  As described above, the structure and the method described in this embodiment can be combined with any of the structures and methods described in other embodiments as appropriate.

(Embodiment 2)
In this embodiment, details of the oxide semiconductor included in the semiconductor device of one embodiment of the present invention will be described below.

<Structure of oxide semiconductor>
The structure of the oxide semiconductor will be described below.

  Oxide semiconductors are classified into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystal oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide). : Amorphous-like oxide semiconductor) and an amorphous oxide semiconductor.

  From another viewpoint, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. As the crystalline oxide semiconductor, a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS, or the like can be given.

  Amorphous structure is generally isotropic and does not have a heterogeneous structure, metastable state in which the arrangement of atoms is not fixed, bond angle is flexible, short-range order but long-range order It is said that it does not have

  That is, a stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (eg, has a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. On the other hand, the a-like OS is not isotropic but has an unstable structure including a void (also referred to as a void). The a-like OS is physically similar to an amorphous oxide semiconductor in that it is unstable.

<CAAC-OS>
First, the CAAC-OS will be described.

  The CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when the CAAC-OS including InGaZnO ₄ crystals classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) is obtained as illustrated in FIG. Shows a peak near 31°. Since this peak is assigned to the (009) plane of the InGaZnO ₄ crystal, in the CAAC-OS, the crystal has c-axis orientation and the c-axis has a surface which forms a film of CAAC-OS (formation target). It is also confirmed that it is oriented in a direction substantially perpendicular to the upper surface). In addition to the peak near 2θ of 31°, a peak may appear near 2θ of 36°. The peak near 2θ of 36° is due to the crystal structure classified into the space group Fd-3m. Therefore, CAAC-OS preferably does not show the peak.

On the other hand, when a structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to the formation surface, a peak appears at 2θ of around 56°. This peak is assigned to the (110) plane of the InGaZnO ₄ crystal. Then, even if 2θ is fixed near 56° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), it is clear as shown in FIG. No peak appears. On the other hand, when a single crystal InGaZnO ₄ was scanned at φ with 2θ fixed at around 56°, six peaks attributed to a crystal plane equivalent to the (110) plane were observed as shown in FIG. 11C. To be done. Therefore, from the structural analysis using XRD, it can be confirmed that the CAAC-OS has irregular a-axis and b-axis orientations.

Next, the CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including InGaZnO ₄ crystals in parallel to a surface on which the CAAC-OS is formed, a diffraction pattern (restricted area) as shown in FIG. Electron diffraction pattern) may appear. This diffraction pattern includes spots due to the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction also shows that the pellets included in the CAAC-OS have c-axis orientation and the c-axis faces a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 11E shows a diffraction pattern when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface. From FIG. 11E, a ring-shaped diffraction pattern is confirmed. Therefore, it is found that the a-axis and the b-axis of the pellet included in the CAAC-OS do not have orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 11E is considered to be derived from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. The second ring in FIG. 11E is considered to be derived from the (110) plane and the like.

  Further, when a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of the CAAC-OS is observed with a transmission electron microscope (TEM), a plurality of pellets are confirmed. You can On the other hand, even in a high-resolution TEM image, a boundary between pellets, that is, a grain boundary (also referred to as a grain boundary) may not be clearly confirmed in some cases. Therefore, it can be said that in the CAAC-OS, electron mobility is less likely to be reduced due to crystal grain boundaries.

  FIG. 12A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface. A spherical aberration correction (Spherical Aberration Corrector) function was used for the observation of the high-resolution TEM image. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

  From FIG. 12A, a pellet which is a region where metal atoms are arranged in layers can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be called a nanocrystal (nc). Further, the CAAC-OS can be referred to as an oxide semiconductor having CANC (C-Axis Aligned nanocrystals). The pellet reflects unevenness on the surface where the CAAC-OS film is formed or on the upper surface, and is parallel to the surface where the CAAC-OS is formed and the upper surface.

Further, FIGS. 12B and 12C show Cs-corrected high-resolution TEM images of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. FIGS. 12D and 12E are images obtained by performing image processing on FIGS. 12B and 12C, respectively. The method of image processing will be described below. First, an FFT image is acquired by performing a fast Fourier transform (FFT: Fast Fourier Transform) processing of FIG. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Then, the masked FFT image is subjected to inverse fast Fourier transform (IFFT) processing to obtain an image-processed image. The image thus obtained is called an FFT filtered image. The FFT filtered image is an image obtained by extracting the periodic component from the Cs-corrected high resolution TEM image, and shows a lattice arrangement.

  In FIG. 12D, a broken line indicates a portion where the lattice arrangement is disturbed. The area surrounded by the broken line is one pellet. And the part shown by the broken line is the connecting portion between the pellets. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. The shape of the pellet is not limited to the regular hexagonal shape, and is often a non-regular hexagonal shape.

  In FIG. 12E, a dotted line indicates a portion where the orientation of the lattice array is changed between a region where the lattice arrangement is uniform and another region where the lattice arrangement is uniform. It is indicated by a broken line. Even in the vicinity of the dotted line, no clear grain boundary can be confirmed. By connecting the lattice points around the dotted line to the surrounding lattice points, a distorted hexagon, pentagon, and/or heptagon can be formed. That is, it is understood that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate strain due to a non-dense atomic arrangement in the ab plane direction, a change in the bond distance between atoms due to substitution with a metal element, or the like. Conceivable.

  As described above, the CAAC-OS has a c-axis orientation and has a strained crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction. Therefore, the CAAC-OS can also be referred to as a CAA crystal (c-axis-aligned ab-plane-anchored crystal).

  CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be lowered due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies).

  Note that the impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon which has a stronger bonding force with oxygen than a metal element forming the oxide semiconductor deprives the oxide semiconductor of oxygen, which disturbs the atomic arrangement of the oxide semiconductor and reduces crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have a large atomic radius (or molecular radius), which disturbs the atomic arrangement of the oxide semiconductor and causes deterioration of crystallinity.

  When the oxide semiconductor has impurities or defects, the characteristics of the oxide semiconductor may be changed by light, heat, or the like. For example, an impurity contained in the oxide semiconductor may serve as a carrier trap or a carrier generation source. For example, oxygen vacancies in the oxide semiconductor might serve as carrier traps or serve as carrier generation sources by capturing hydrogen.

The CAAC-OS containing few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8×10 ¹¹ pieces/cm ³ , preferably less than 1×10 ¹¹ pieces/cm ³ , more preferably less than 1×10 ¹⁰ pieces/cm ³ , and 1×10 ⁻⁹ pieces/cm 3. An oxide semiconductor having a carrier density of ³ or more can be used. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<nc-OS>
Next, the nc-OS will be described.

  A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by the out-of-plane method, no peak showing orientation is observed. That is, the crystal of nc-OS has no orientation.

In addition, for example, when an nc-OS including a crystal of InGaZnO ₄ is thinned and an electron beam having a probe diameter of 50 nm is made incident on a region having a thickness of 34 nm in parallel with a formation surface, FIG. A ring-shaped diffraction pattern (nano-beam electron diffraction pattern) as shown is observed. Further, FIG. 13B shows a diffraction pattern (nano-beam electron diffraction pattern) when an electron beam having a probe diameter of 1 nm is incident on the same sample. From FIG. 13B, a plurality of spots are observed in the ring-shaped region. Therefore, in the nc-OS, ordering is not confirmed when an electron beam having a probe diameter of 50 nm is incident, but ordering is confirmed when an electron beam having a probe diameter of 1 nm is incident.

  When an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagon is observed as shown in FIG. There are cases where Therefore, it is understood that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. In addition, since the crystals are oriented in various directions, there are regions where a regular electron diffraction pattern is not observed.

  FIG. 13D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed in a direction substantially parallel to the formation surface. In the high-resolution TEM image, the nc-OS has a region where crystal parts can be confirmed, such as a portion indicated by an auxiliary line, and a region where clear crystal parts cannot be confirmed. The crystal part included in the nc-OS has a size of 1 nm to 10 nm, in particular, a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal portion is greater than 10 nm and less than or equal to 100 nm is referred to as a microcrystalline oxide semiconductor. In the high resolution TEM image of the nc-OS, for example, the crystal grain boundaries may not be clearly confirmed in some cases. Note that nanocrystals may have the same origin as pellets in CAAC-OS. Therefore, the crystal part of nc-OS may be called a pellet below.

  As described above, the nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly, a region of 1 nm to 3 nm). Moreover, in the nc-OS, no regularity is found in the crystal orientation between different pellets. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.

  Since the crystal orientations between pellets (nanocrystals) do not have regularity, nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

  The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than the a-like OS and the amorphous oxide semiconductor. However, in the nc-OS, no regularity is found in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<a-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor.

FIG. 14 shows a high-resolution cross-sectional TEM image of a-like OS. Here, FIG. 14A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 14B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁻ ) at 4.3×10 ⁸ e ⁻ /nm ² . From FIGS. 14A and 14B, it can be seen that a striped bright region extending in the vertical direction is observed in the a-like OS from the start of electron irradiation. Further, it is found that the shape of the bright region changes after the electron irradiation. The bright region is presumed to be a void or a low density region.

  The a-like OS has an unstable structure because it has a void. Hereinafter, since the a-like OS has a more unstable structure than the CAAC-OS and the nc-OS, a structure change due to electron irradiation is shown.

  As samples, a-like OS, nc-OS, and CAAC-OS are prepared. All the samples are In-Ga-Zn oxides.

  First, a high-resolution cross-sectional TEM image of each sample is acquired. From the high-resolution cross-sectional TEM image, each sample has a crystal part.

Note that a unit cell of a crystal of InGaZnO ₄ has a structure in which three In—O layers and six Ga—Zn—O layers are stacked, and a total of nine layers are layered in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from the crystal structure analysis. Therefore, in the following description, the portion where the lattice fringe spacing is 0.28 nm or more and 0.30 nm or less is regarded as the InGaZnO ₄ crystal part. The lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 15 is an example in which the average size of the crystal parts (22 to 30 points) of each sample was investigated. The length of the above-mentioned lattice stripes is the size of the crystal part. From FIG. 15, it is found that in the a-like OS, the crystal part becomes larger according to the cumulative irradiation amount of electrons related to the acquisition of the TEM image and the like. From FIG. 15, the crystal part (also referred to as an initial nucleus), which had a size of about 1.2 nm in the initial observation by TEM, had a cumulative irradiation dose of electrons (e ⁻ ) of 4.2×10 ⁸ e ⁻ /nm. ^In No. ² , it can be seen that the growth has reached about 1.9 nm. On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2×10 ⁸ e ⁻ /nm ^2. I understand. From FIG. 15, it is found that the sizes of the crystal parts of the nc-OS and the CAAC-OS are about 1.3 nm and about 1.8 nm, respectively, regardless of the cumulative dose of electrons. For electron beam irradiation and TEM observation, Hitachi transmission electron microscope H-9000NAR was used. The electron beam irradiation conditions were such that the acceleration voltage was 300 kV, the current density was 6.7×10 ⁵ e ⁻ /(nm ² ·s), and the diameter of the irradiation region was 230 nm.

  As described above, in the a-like OS, the crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, almost no crystal part growth due to electron irradiation is observed. That is, it is found that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

  Further, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal having the same composition. The density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of a single crystal having the same composition. It is difficult to form an oxide semiconductor having a single crystal density of less than 78%.

For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g/cm ³ . Therefore, for example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of a-like OS is 5.0 g/cm ³ or more and less than 5.9 g/cm ^3. .. Further, for example, in an oxide semiconductor that satisfies In:Ga:Zn=1:1:1 [atomic ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g/cm ³ or more and 6.3 g/cm ³ or more. It is less than cm ³ .

  When single crystals having the same composition do not exist, the density corresponding to the single crystal having a desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. The density corresponding to a single crystal having a desired composition may be estimated by using a weighted average with respect to a ratio of combining single crystals having different compositions. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

  As described above, oxide semiconductors have various structures and have various characteristics. Note that the oxide semiconductor may be, for example, a stacked film including two or more kinds of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

  As described above, the structure and the method described in this embodiment can be combined with any of the structures and methods described in other embodiments as appropriate.

(Embodiment 3)
In this embodiment, an example of a circuit of a semiconductor device including a transistor or the like according to one embodiment of the present invention will be described.
<Circuit>
Hereinafter, an example of a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention will be described.

<CMOS inverter>
The circuit diagram in FIG. 16A illustrates a so-called CMOS inverter in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.

  In the semiconductor device illustrated in FIG. 16A, a p-channel transistor is formed using a semiconductor substrate and an n-channel transistor is formed thereover, whereby the area occupied by the element can be reduced. That is, the degree of integration of the semiconductor device can be increased. Further, since the process can be simplified as compared with the case where the n-channel transistor and the p-channel transistor are manufactured using the same semiconductor substrate, the productivity of the semiconductor device can be increased. In addition, the yield of semiconductor devices can be increased. In addition, in the p-channel transistor, complicated processes such as LDD (Lightly Doped Drain) region, shallow trench structure, and strain design may be omitted in some cases. Therefore, the productivity and the yield of the n-channel transistor can be increased in some cases as compared with the case where the n-channel transistor is manufactured using a semiconductor substrate.

<CMOS analog switch>
The circuit diagram in FIG. 16B illustrates a structure in which the sources and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, it can function as a so-called CMOS analog switch.

<Memory device 1>
FIG. 17 illustrates an example of a semiconductor device (memory device) including the transistor according to one embodiment of the present invention, which can retain stored data even when power is not supplied and has no limitation on the number of times of writing.

  The semiconductor device illustrated in FIG. 17A includes a transistor 3200 including a first semiconductor, a transistor 3300 including a second semiconductor, and a capacitor 3400. Note that as the transistor 3300, a transistor similar to the above-described transistor 2100 can be used.

  The transistor 3300 is preferably a transistor with low off-state current. For the transistor 3300, for example, a transistor including an oxide semiconductor can be used. Since the off-state current of the transistor 3300 is small, stored data can be stored in a specific node of the semiconductor device for a long time. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely reduced; thus, a semiconductor device with low power consumption can be obtained.

  In FIG. 17A, the first wiring 3001 is electrically connected to the source of the transistor 3200, and the second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of a source and a drain of the transistor 3300, and the fourth wiring 3004 is electrically connected to a gate of the transistor 3300. The gate of the transistor 3200 and the other of the source and the drain of the transistor 3300 are electrically connected to one of the electrodes of the capacitor 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor 3400. Has been done.

  The semiconductor device illustrated in FIG. 17A has a characteristic of holding the potential of the gate of the transistor 3200, and thus can write, hold, and read data, as described below.

  Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is applied to the node FG which is electrically connected to the gate of the transistor 3200 and one of the electrodes of the capacitor 3400. That is, predetermined charge is applied to the gate of the transistor 3200 (writing). Here, it is assumed that either one of the charges that gives two different potential levels (hereinafter referred to as Low level charge and High level charge) is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off, so that the transistor 3300 is turned off, so that electric charge is held in the node FG (holding).

  Since the off-state current of the transistor 3300 is small, the charge of the node FG is held for a long time.

Next, reading of information will be described. When a suitable potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 causes the charges held in the node FG to be applied. It takes a potential according to the amount. This is because when the transistor 3200 is an n-channel type, the apparent threshold voltage V _{th_H} in the case where the gate of the transistor 3200 is _supplied with High level charge is as follows. This is because the threshold voltage becomes lower than the apparent threshold voltage V _{th_L} . Here, the apparent threshold voltage refers to a potential of the fifth wiring 3005, which is necessary for bringing the transistor 3200 into a “conductive state”. Therefore, by _setting the potential of the fifth wiring 3005 to the potential V ₀ between V _{th_H} and V _{th_L} , the charge applied to the node FG can be determined. For example, in writing, when high-level charge is applied to the node FG and the potential of the fifth wiring 3005 becomes V ₀ (>V _{th_H} ), the transistor 3200 is turned on. On the other hand, in the case where low-level charge is applied to the node FG, the transistor 3200 remains in a “non-conduction state” even when the potential of the fifth wiring 3005 becomes V ₀ (<V _{th_L} ). Therefore, the information held in the node FG can be read by determining the potential of the second wiring 3002.

Note that when the memory cells are arranged in an array, the information of a desired memory cell must be read at the time of reading. For example, in a memory cell in which data is not read, a potential such that the transistor 3200 is in a “non-conducting state” regardless of charge applied to the node FG, that is, a potential lower than V _{th_H} is applied to the fifth wiring 3005. Therefore, only the information of a desired memory cell may be read. _{Alternatively} , in the memory cell in which data is not read, a potential such that the transistor 3200 is in a “conductive state” regardless of the charge applied to the node FG, that is, a potential higher than V _{th_L} is applied to the fifth wiring 3005. Therefore, only the information of the desired memory cell can be read.

  Although an example in which two types of charges are held in the node FG has been described above, the semiconductor device of the present invention is not limited to this. For example, the structure may be such that three or more kinds of charges can be held in the node FG of the semiconductor device. With such a structure, the semiconductor device can be multivalued and the storage capacity can be increased.

<Memory device 2>
The semiconductor device illustrated in FIG. 17B is different from the semiconductor device illustrated in FIG. 17A in that it does not include the transistor 3200. In this case also, information writing and data holding operations can be performed by operations similar to those of the semiconductor device illustrated in FIG.

  Reading of information in the semiconductor device in FIG. 17B is described. When the transistor 3300 is turned on, the third wiring 3003 which is in a floating state and the capacitor 3400 are turned on, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 has a different value depending on the potential of one of the electrodes of the capacitor 3400 (or the charge accumulated in the capacitor 3400).

  For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before charge is redistributed is When VB0 is set, the potential of the third wiring 3003 after the charge is redistributed is (CB×VB0+CV)/(CB+C). Therefore, assuming that one of the electrodes of the capacitor 3400 has two potentials V1 and V0 (V1>V0) as states of the memory cell, the third wiring 3003 in the case where the potential V1 is held is retained. It can be seen that the potential (=(CB×VB0+CV1)/(CB+C)) is higher than the potential of the third wiring 3003 (=(CB×VB0+CV0)/(CB+C)) when the potential V0 is held. ..

  Information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

  In this case, a transistor to which the first semiconductor is applied is used for a driver circuit for driving the memory cell, and a transistor to which the second semiconductor is applied is stacked as the transistor 3300 on the driver circuit. do it.

  By applying a transistor including an oxide semiconductor and having a small off-state current, the semiconductor device described above can retain stored data for a long time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely reduced, so that a semiconductor device with low power consumption can be realized. Further, even when power is not supplied (however, it is preferable that the potential is fixed), the stored content can be held for a long time.

  In addition, the semiconductor device does not require high voltage for writing data, and thus deterioration of elements is less likely to occur. For example, unlike the conventional nonvolatile memory, neither injection of electrons into the floating gate nor extraction of electrons from the floating gate is performed, so that the problem of deterioration of the insulator does not occur. That is, the semiconductor device according to one embodiment of the present invention is a semiconductor device in which there is no limitation on the number of rewritable times, which is a problem in the conventional nonvolatile memory, and the reliability is dramatically improved. Further, since data is written depending on whether the transistor is on or off, high speed operation is possible.

<Memory device 3>
A modified example of the semiconductor device (memory device) illustrated in FIG. 17A will be described with reference to a circuit diagram in FIG. 18.

  The semiconductor device illustrated in FIG. 18 includes transistors 4100 to 4400, a capacitor 4500, and a capacitor 4600. Here, the transistor 4100 can be a transistor similar to the above-described transistor 3200, and the transistors 4200 to 4400 can be similar to the above-described transistor 3300. Although not shown in FIG. 18, the semiconductor device illustrated in FIG. 18 is provided in a matrix. In the semiconductor device illustrated in FIG. 18, writing and reading of a data voltage can be controlled in accordance with a signal or a potential applied to the wiring 4001, the wiring 4003, and the wirings 4005 to 4009.

  One of a source and a drain of the transistor 4100 is connected to the wiring 4003. The other of the source and the drain of the transistor 4100 is connected to the wiring 4001. Note that although the conductivity type of the transistor 4100 is a p-channel type in FIG. 18, it may be an n-channel type.

  The semiconductor device shown in FIG. 18 has two data holding units. For example, the first data holding portion holds electric charge between one of the source and the drain of the transistor 4400, the one electrode of the capacitor 4600, and the one of the source and the drain of the transistor 4200, which are connected to the node FG1. In addition, the second data holding portion is provided between the gate of the transistor 4100 connected to the node FG2, the other of the source and the drain of the transistor 4200, the one of the source and the drain of the transistor 4300, and the one electrode of the capacitor 4500. Holds an electric charge.

  The other of the source and the drain of the transistor 4300 is connected to the wiring 4003. The other of the source and the drain of the transistor 4400 is connected to the wiring 4001. The gate of the transistor 4400 is connected to the wiring 4005. The gate of the transistor 4200 is connected to the wiring 4006. The gate of the transistor 4300 is connected to the wiring 4007. The other electrode of the capacitor 4600 is connected to the wiring 4008. The other electrode of the capacitor 4500 is connected to the wiring 4009.

  The transistors 4200 to 4400 have a function as a switch which controls writing of a data voltage and retention of electric charge. Note that as the transistors 4200 to 4400, it is preferable to use transistors in which a current (off-state current) flowing between a source and a drain in a non-conduction state is low. A transistor having a small off-state current is preferably a transistor including an oxide semiconductor in a channel formation region (OS transistor). The OS transistor has advantages that it has low off-state current, can be stacked with a transistor including silicon, and the like. Although the conductivity type of the transistors 4200 to 14 is shown as an n-channel type in FIG. 18, it may be a p-channel type.

  The transistors 4200 and 4300 and the transistor 4400 are preferably provided in different layers even if they are transistors including an oxide semiconductor. That is, as illustrated in FIG. 18, the semiconductor device illustrated in FIG. 18 includes a first layer 4021 including a transistor 4100, a second layer 4022 including a transistor 4200 and a transistor 4300, and a third layer including a transistor 4400. 4023 and are preferably comprised. By stacking layers each including a transistor, the circuit area can be reduced and the semiconductor device can be downsized.

  Next, an operation of writing information to the semiconductor device shown in FIG. 18 will be described.

First, a write operation of a data voltage to a data holding portion connected to the node FG1 (hereinafter referred to as write operation 1) will be described. Note that in the following, the data voltage written in the data holding portion connected to the node FG1 is V _D1 and the threshold voltage of the transistor 4100 is V th.

In the writing operation 1, the wiring 4003 is set to V _D1 , the wiring 4001 is set to the ground potential, and then the wiring 4003 is brought into an electrically floating state. Further, the wirings 4005 and 4006 are set to a high level. In addition, the wirings 4007 to 4009 are set to a low level. Then, the potential of the node FG2 which is in an electrically floating state is increased and a current flows through the transistor 4100. When the current flows, the potential of the wiring 4001 rises. Further, the transistors 4400 and 4200 are turned on. Therefore, as the potential of the wiring 4001 is increased, the potentials of the nodes FG1 and FG2 are increased. When the potential of the node FG2 rises and the voltage (Vgs) between the gate and the source of the transistor 4100 reaches the threshold voltage Vth of the transistor 4100, the current flowing through the transistor 4100 decreases. Therefore, the wiring 4001, the node FG1, increase in the potential of FG2 is _stopped, the constant drops from _{V D1} by Vth _"V D1 -Vth".

That is, V _D1 given to the wiring 4003 is given to the wiring 4001 as the current flows through the transistor 4100, and the potentials of the nodes FG1 and FG2 rise. When the potential of the node FG2 becomes “V _D1 −Vth” due to the increase in potential, Vgs of the transistor 4100 becomes Vth, and the current stops.

Next, a data voltage writing operation to the data holding portion connected to the node FG2 (hereinafter referred to as writing operation 2) will be described. The data voltage written in the data holding unit connected to the node FG2 will be described as V _D2 .

In the writing operation 2, the wiring 4001 is set to V _D2 , the wiring 4003 is set to the ground potential, and then the wiring 4003 is brought into an electrically floating state. In addition, the wiring 4007 is set to a high level. Further, the wirings 4005, 4006, 4008, and 4009 are set to low level. The transistor 4300 is turned on and the wiring 4003 is set at a low level. Therefore, the potential of the node FG2 also drops to low level, and current flows through the transistor 4100. When the current flows, the potential of the wiring 4003 rises. Further, the transistor 4300 is turned on. Therefore, the potential of the node FG2 rises as the potential of the wiring 4003 rises. When the potential of the node FG2 rises and Vgs of the transistor 4100 reaches Vth of the transistor 4100, the current flowing through the transistor 4100 decreases. For this reason, stops the rise of the potential of the wiring _4003, FG2, becomes constant at dropped from _{V D2} only Vth _"V D2 -Vth".

That is, V _D2 given to the wiring 4001 is given to the wiring 4003 as the current flows through the transistor 4100, and the potential of the node FG2 is increased. When the potential of the node FG2 becomes “V _D2 −Vth” due to the increase in potential, Vgs of the transistor 4100 becomes Vth, and the current stops. At this time, the potential of the node FG1 is non-conducting in both the transistors 4200 and 4400, and “V _D1 −Vth” written in the writing operation 1 is held.

  In the semiconductor device illustrated in FIG. 18, after writing a data voltage in a plurality of data holding portions, the wiring 4009 is set at a high level and the potentials of the nodes FG1 and FG2 are increased. Then, each transistor is brought into a non-conducting state to eliminate the movement of charges and hold the written data voltage.

By the operation of writing the data voltage to the nodes FG1 and FG2 described above, the data voltage can be held in the plurality of data holding units. The potentials to be written are described as "V _D1 -Vth" and "V _D2- Vth" as examples, but these are data voltages corresponding to multi-valued data. Therefore, when 4-bit data is held in each data holding unit, 16-valued “V _D1 −Vth” or “V _D2 −Vth” can be obtained.

  Next, an operation of reading information from the semiconductor device illustrated in FIG. 18 is described.

  First, a read operation of a data voltage to the data holding portion connected to the node FG2 (hereinafter, referred to as read operation 1) will be described.

In the read operation 1, the wiring 4003, which is in an electrically floating state after precharging, is discharged. The wirings 4005 to 4008 are set to low level. Further, the potential of the node FG2 which is in an electrically floating state is “V _D2 −Vth” with the wiring 4009 at a low level. When the potential of the node FG2 decreases, current flows through the transistor 4100. When the current flows, the potential of the wiring 4003 which is in an electrically floating state is lowered. As the potential of the wiring 4003 decreases, Vgs of the transistor 4100 decreases. When Vgs of the transistor 4100 becomes Vth of the transistor 4100, the current flowing through the transistor 4100 becomes smaller. That is, the potential of the wiring 4003 becomes “V _D2 ”, which is a value larger than the potential “V _D2 −Vth” of the node FG2 by Vth. The potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG2. The read analog voltage data voltage is subjected to A/D conversion to obtain data in the data holding unit connected to the node FG2.

That is, the wiring 4003 after precharge is brought into a floating state and the potential of the wiring 4009 is switched from a high level to a low level, whereby a current flows through the transistor 4100. When the current flows, the potential of the wiring 4003 which is in a floating state is lowered to “V _D2 ”. In the transistor 4100, Vgs between the node FG2 and “V _D2 −Vth” becomes Vth, so that the current stops. Then, “V _D2 ”written in the writing operation 2 is read to the wiring 4003.

When the data in the data holding unit connected to the node FG2 is acquired, the transistor 4300 is turned on and “V _D2 −Vth” of the node FG2 is discharged.

  Next, the charge held in the node FG1 is distributed to the node FG2, and the data voltage of the data holding portion connected to the node FG1 is transferred to the data holding portion connected to the node FG2. Here, the wirings 4001 and 4003 are set to a low level. The wiring 4006 is set to a high level. In addition, the wiring 4005 and the wirings 4007 to 4009 are set to a low level. When the transistor 4200 is turned on, the charge of the node FG1 is distributed to the node FG2.

Here, the electric potential after the charge is distributed decreases from the written electric potential “V _D1 −Vth”. Therefore, it is preferable that the capacitance value of the capacitor 4600 be larger than that of the capacitor 4500. Alternatively, the potential “V _D1 −Vth” written to the node FG1 is preferably higher than the potential “V _D2 −Vth” representing the same data. As described above, by changing the ratio of the capacitance values and increasing the potential to be written in advance, it is possible to suppress the decrease in the potential after the charge is distributed. The fluctuation of the potential due to the charge distribution will be described later.

  Next, a read operation of the data voltage to the data holding unit connected to the node FG1 (hereinafter referred to as a read operation 2) will be described.

In the read operation 2, the wiring 4003, which is in an electrically floating state after precharging, is discharged. The wirings 4005 to 4008 are set to low level. Further, the wiring 4009 is set to a high level at the time of precharge and then set to a low level. By setting the wiring 4009 to a low level, the potential of the node FG2 which is in an electrically floating state is set to “V _D1 −Vth”. When the potential of the node FG2 decreases, current flows through the transistor 4100. When the current flows, the potential of the wiring 4003 which is in an electrically floating state is lowered. As the potential of the wiring 4003 decreases, Vgs of the transistor 4100 decreases. When Vgs of the transistor 4100 becomes Vth of the transistor 4100, the current flowing through the transistor 4100 becomes smaller. That is, the potential of the wiring 4003 becomes “V _D1 ”, which is a value larger than the potential “V _D1 −Vth” of the node FG2 by Vth. The potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG1. The read analog value data voltage is subjected to A/D conversion to obtain data in the data holding unit connected to the node FG1. The above is the operation of reading the data voltage to the data holding unit connected to the node FG1.

That is, the wiring 4003 after precharge is brought into a floating state and the potential of the wiring 4009 is switched from a high level to a low level, whereby a current flows through the transistor 4100. With the current flowing, the potential of the wiring 4003 which is in a floating state is lowered and becomes “V _D1 ”. In the transistor 4100, Vgs between the node FG2 and “V _D1 −Vth” becomes Vth, so that the current stops. Then, “V _D1 ”written in the writing operation 1 is read to the wiring 4003.

  By the data voltage read operation from the nodes FG1 and FG2 described above, the data voltage can be read from the plurality of data holding units. For example, by storing 4-bit (16-valued) data in each of the node FG1 and the node FG2, 8-bit (256-valued) data can be held in total. Although the structure including the first layer 4021 to the third layer 4023 is shown in FIG. 18, by further forming layers, the storage capacity can be increased without increasing the area of the semiconductor device. ..

Note that the potential to be read can be read as a voltage higher than the written data voltage by Vth. Therefore, the Vth of “V _D1 −Vth” or “V _D2 −Vth” written in the writing operation can be canceled and read. As a result, the storage capacity per memory cell can be improved, and the read data can be made closer to the correct data, so that the reliability of the data can be made excellent.

<Memory device 4>
The semiconductor device illustrated in FIG. 17C is different from the semiconductor device illustrated in FIG. 17A in that it includes a transistor 3500 and a sixth wiring 3006. In this case also, information writing and data holding operations can be performed by operations similar to those of the semiconductor device illustrated in FIG. As the transistor 3500, a transistor similar to the above transistor 3200 may be used.

  The sixth wiring 3006 is electrically connected to the gate of the transistor 3500, one of a source and a drain of the transistor 3500 is electrically connected to a drain of the transistor 3200, and the other of the source and the drain of the transistor 3500 is a third wiring. It is electrically connected to the wiring 3003.

  The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 4)
In this embodiment, an example of a circuit structure to which the OS transistor described in any of the above embodiments can be applied will be described with reference to FIGS.

A circuit diagram of the inverter is shown in FIG. The inverter 800 outputs a signal obtained by inverting the logic of the input terminal IN to the output terminal OUT. The inverter 800 has a plurality of OS transistors. The signal S _BG is a signal that can switch the electrical characteristics of the OS transistor.

  FIG. 19B is a circuit diagram which is an example of the inverter 800. The inverter 800 has an OS transistor 810 and an OS transistor 820. Since the inverter 800 can be manufactured using an n-channel transistor, it can be manufactured at lower cost as compared with a case where an inverter (CMOS inverter) is manufactured using a CMOS (Complementary Metal Oxide Semiconductor).

  Note that the inverter 800 having an OS transistor can also be provided over the CMOS including a Si transistor. Since the inverter 800 can be arranged so as to overlap the circuit configuration of the CMOS, it is possible to suppress an increase in circuit area due to the addition of the inverter 800.

  The OS transistors 810 and 820 each have a first gate that functions as a front gate, a second gate that functions as a back gate, a first terminal that functions as one of a source and a drain, and a second terminal that functions as the other of the source and the drain. Have.

The first gate of the OS transistor 810 is connected to the second terminal. The second gate of the OS transistor 810 is connected to the wiring which supplies the signal S _BG . The first terminal of the OS transistor 810 is connected to a wiring which supplies the voltage VDD. The second terminal of the OS transistor 810 is connected to the output terminal OUT.

  The first gate of the OS transistor 820 is connected to the input terminal IN. The second gate of the OS transistor 820 is connected to the input terminal IN. The first terminal of the OS transistor 820 is connected to the output terminal OUT. The second terminal of the OS transistor 820 is connected to a wiring which supplies the voltage VSS.

FIG. 19C is a timing chart for explaining the operation of the inverter 800. The timing chart in FIG. 19C shows a signal waveform of the input terminal IN, a signal waveform of the output terminal OUT, a signal waveform of the signal S _BG , and changes in the threshold voltage of the OS transistor 810 (FET 810).

The threshold voltage of the OS transistor 810 can be controlled by applying the signal S _{BG to} the second gate of the OS transistor 810.

Signal _{S BG} has a voltage _{V BG_B} for voltage _{V BG_A} for causing negative shift of the threshold voltage, the threshold voltage is positive shift. By applying the voltage V _{BG_A} to the second gate, the OS transistor 810 can be negatively shifted to the threshold voltage V _{TH_A} . _Further, by applying the voltage V _{BG_B} to the second gate, the OS transistor 810 can be positively shifted to the threshold voltage V _{TH_B} .

  In order to visualize the above description, FIG. 20A shows a Vg-Id curve which is one of electric characteristics of a transistor.

The electrical characteristics of the OS transistor 810 described above can be shifted to the curve represented by the dashed line 840 in FIG. 20A by increasing the voltage of the second gate like the voltage V _{BG_A} . The electrical characteristics of the OS transistor 810 described above can be shifted to the curve represented by the solid line 841 in FIG. 20A by reducing the voltage of the second gate like the voltage V _{BG_B} . As illustrated in FIG. 20A, the OS transistor 810 can shift the signal S _BG to the voltage V _{BG_A} or the voltage V _{BG_B} so that the threshold voltage is shifted to the plus side or the minus side.

By positively shifting the threshold voltage to the threshold voltage V _{TH_B} , the OS transistor 810 can be in a state in which current hardly flows. This state is visualized and shown in FIG. As illustrated in FIG. 20B, the current I _B flowing in the OS transistor 810 can be extremely small. Therefore, when the signal applied to the input terminal IN is at high level and the OS transistor 820 is in the on state (ON), the voltage of the output terminal OUT can be sharply decreased.

  As illustrated in FIG. 20B, the current flowing through the OS transistor 810 can be made difficult to flow. Therefore, the signal waveform 831 of the output terminal in the timing chart in FIG. You can Since a penetrating current flowing between the wiring which supplies the voltage VDD and the wiring which supplies the voltage VSS can be reduced, operation with low power consumption can be performed.

_Further , by negatively shifting the threshold voltage to the threshold voltage V _{TH_A} , the OS transistor 810 can be in a state in which current easily flows. This state is visualized and shown in FIG. As shown in FIG. 20 (C), it can be larger than at least the current I _B of the current I _A flowing at this time. Therefore, when the signal applied to the input terminal IN is low level and the OS transistor 820 is in the off state (OFF), the voltage of the output terminal OUT can be sharply increased.

  As illustrated in FIG. 20C, the current flowing in the OS transistor 810 can be easily made to flow, so that the signal waveform 832 of the output terminal in the timing chart in FIG. You can

Note that the threshold voltage of the OS transistor 810 is preferably controlled by the signal S _BG before the state of the OS transistor 820 is switched, that is, before the time T1 or T2. For example, as illustrated in FIG. _19C , the threshold voltage of the OS transistor 810 is switched from the threshold voltage V _{TH_A} to the threshold voltage V _{TH_B} before time T1 when the signal applied to the input terminal IN is switched to the high level. Is preferred. As illustrated in FIG. _19C , the threshold voltage of the OS transistor 810 is switched from the threshold voltage V _{TH_B} to the threshold voltage V _{TH_A} before time T2 when the signal applied to the input terminal IN is switched to the low level. Is preferred.

Note that the timing chart in FIG. _19C shows the structure in which the signal S _BG is switched in accordance with the signal _supplied to the input terminal IN, but another structure may be used. For example, the voltage for controlling the threshold voltage may be held in the second gate of the OS transistor 810 in a floating state. FIG. 21A illustrates an example of a circuit structure which can realize the structure.

In FIG. 21A, an OS transistor 850 is provided in addition to the circuit structure illustrated in FIG. The first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. The second terminal of the OS transistor 850 is connected to a wiring which _{supplies the} voltage V _{BG_B} (or the voltage V _{BG_A} ). The first gate of the OS transistor 850 is connected to a wiring for providing signal _{S F.} The second gate of the OS transistor 850 is connected to a wiring which _{supplies the} voltage V _{BG_B} (or the voltage V _{BG_A} ).

  The operation of FIG. 21A will be described with reference to the timing chart of FIG.

The voltage for controlling the threshold voltage of the OS transistor 810 is applied to the second gate of the OS transistor 810 before time T3 when the signal applied to the input terminal IN is switched to the high level. The signal S _{F is set} to a high level to turn on the OS transistor 850, and the voltage V _{BG_B} for controlling the threshold voltage is applied to the node N _BG .

After the node N _BG becomes the voltage V _{BG — B} , the OS transistor 850 is turned off. OS transistor 850, an off-state current is extremely small, by continuing to the OFF state, it is possible to hold the voltage _{V BG_B} obtained by temporarily held in the node _{N BG.} Therefore, the number of operations of applying the voltage V _{BG_B} to the second gate of the OS transistor 850 is reduced, so that power consumption required for rewriting the voltage V _{BG_B} can be reduced.

  In the circuit configurations of FIGS. 19B and 21A, the configuration in which the voltage applied to the second gate of the OS transistor 810 is externally controlled is shown, but another configuration may be adopted. For example, the voltage for controlling the threshold voltage may be generated based on the signal applied to the input terminal IN and applied to the second gate of the OS transistor 810. FIG. 22A shows an example of a circuit structure which can realize the structure.

  22A, a CMOS inverter 860 is provided between the input terminal IN and the second gate of the OS transistor 810 in the circuit configuration illustrated in FIG. 19B. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal of the CMOS inverter 860 is connected to the second gate of the OS transistor 810.

  The operation in FIG. 22A will be described with reference to the timing chart in FIG. The timing chart of FIG. 22B shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the output waveform IN_B of the CMOS inverter 860, and the threshold voltage of the OS transistor 810 (FET 810).

  The output waveform IN_B, which is a signal obtained by inverting the logic of the signal supplied to the input terminal IN, can be used as a signal for controlling the threshold voltage of the OS transistor 810. Therefore, the threshold voltage of the OS transistor 810 can be controlled as described with reference to FIGS. For example, at time T4 in FIG. 22B, the signal supplied to the input terminal IN is at a high level and the OS transistor 820 is on. At this time, the output waveform IN_B becomes low level. Therefore, the OS transistor 810 can be in a state in which a current hardly flows, and the voltage of the output terminal OUT can be sharply decreased.

  At time T5 in FIG. 22B, the signal supplied to the input terminal IN is at a low level and the OS transistor 820 is off. At this time, the output waveform IN_B becomes high level. Therefore, the OS transistor 810 can be in a state in which a current easily flows, and the voltage of the output terminal OUT can be sharply increased.

  As described above, in the configuration of this embodiment, the back gate voltage in the inverter having the OS transistor is switched according to the logic of the signal at the input terminal IN. With this structure, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the OS transistor with a signal applied to the input terminal IN, the voltage of the output terminal OUT can be changed sharply. Further, it is possible to reduce the through current between the wirings that supplies the power supply voltage. Therefore, low power consumption can be achieved.

(Embodiment 5)
In this embodiment, an example of a CPU including a transistor according to one embodiment of the present invention and a semiconductor device such as the above memory device will be described.

<CPU configuration>
FIG. 23 is a block diagram showing a configuration of an example of a CPU partially including the above transistor.

  The CPU shown in FIG. 23 includes an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198 on a substrate 1190. , A rewritable ROM 1199, and a ROM interface 1189. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in another chip. Of course, the CPU shown in FIG. 23 is merely an example in which the configuration is simplified and shown, and an actual CPU has various configurations depending on its application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG. 23 may be one core, a plurality of the cores may be included, and each core may operate in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit or the data bus can be set to 8 bits, 16 bits, 32 bits, 64 bits, or the like.

  The instruction input to the CPU via the bus interface 1198 is input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

  The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instruction. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. Further, the interrupt controller 1194 determines and processes an interrupt request from an external input/output device or a peripheral circuit based on its priority or mask state during execution of the program of the CPU. The register controller 1197 generates the address of the register 1196 and reads or writes the register 1196 according to the state of the CPU.

  The timing controller 1195 also generates signals that control the timing of the operations of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1 and supplies the internal clock signal CLK2 to the above various circuits.

  In the CPU illustrated in FIG. 23, the register 1196 is provided with a memory cell. As the memory cell of the register 1196, the above transistor, the memory device, or the like can be used.

  In the CPU shown in FIG. 23, the register controller 1197 selects a holding operation in the register 1196 according to an instruction from the ALU 1191. That is, in the memory cell included in the register 1196, it is selected whether the data is held by the flip-flop or the capacitor. When data holding by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When data retention in the capacitor is selected, data is rewritten in the capacitor and supply of power supply voltage to the memory cell in the register 1196 can be stopped.

  FIG. 24 is an example of a circuit diagram of a memory element 1200 that can be used as the register 1196. The storage element 1200 includes a circuit 1201 in which stored data is volatilized by power interruption, a circuit 1202 in which stored data is not volatilized by power interruption, a switch 1203, a switch 1204, a logic element 1206, a capacitor element 1207, and a selection function. And a circuit 1220 included therein. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include another element such as a diode, a resistance element, or an inductor as needed.

  Here, the above memory device can be used for the circuit 1202. When the supply of power supply voltage to the memory element 1200 is stopped, GND (0 V) or a potential at which the transistor 1209 is turned off is continuously input to the gate of the transistor 1209 in the circuit 1202. For example, the gate of the transistor 1209 is grounded via a load such as a resistor.

  The switch 1203 is formed using a transistor 1213 of one conductivity type (for example, an n-channel type), and the switch 1204 is formed using a transistor 1214 of a conductivity type (for example, a p-channel type) opposite to the one conductivity type. Here is an example. Here, the first terminal of the switch 1203 corresponds to one of the source and the drain of the transistor 1213, the second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and the switch 1203 is the gate of the transistor 1213. The control signal RD input to the terminal selects conduction or non-conduction between the first terminal and the second terminal (that is, the conduction or non-conduction state of the transistor 1213). The first terminal of the switch 1204 corresponds to one of the source and the drain of the transistor 1214, the second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and the switch 1204 is input to the gate of the transistor 1214. The control signal RD that selects the conduction or non-conduction between the first terminal and the second terminal (that is, the conduction or non-conduction state of the transistor 1214).

  One of a source and a drain of the transistor 1209 is electrically connected to one of a pair of electrodes of the capacitor 1208 and a gate of the transistor 1210. Here, the connection portion is the node M2. One of a source and a drain of the transistor 1210 is electrically connected to a wiring capable of supplying a low power supply potential (eg, a GND line), and the other is a first terminal of the switch 1203 (a source and a drain of the transistor 1213). On the other hand). A second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to a first terminal of the switch 1204 (one of the source and the drain of the transistor 1214). The second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a wiring which can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), the first terminal of the switch 1204 (one of the source and the drain of the transistor 1214), the input terminal of the logic element 1206, and the capacitor 1207. One of the pair of electrodes is electrically connected. Here, the connection portion is the node M1. The other of the pair of electrodes of the capacitor 1207 can have a structure in which a constant potential is input. For example, a low power supply potential (GND or the like) or a high power supply potential (VDD or the like) can be input. The other of the pair of electrodes of the capacitor 1207 is electrically connected to a wiring which can supply a low power supply potential (eg, a GND line). The other of the pair of electrodes of the capacitor 1208 can have a structure in which a constant potential is input. For example, a low power supply potential (GND or the like) or a high power supply potential (VDD or the like) can be input. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a wiring that can supply a low power supply potential (eg, a GND line).

  Note that the capacitor 1207 and the capacitor 1208 can be omitted by positively utilizing parasitic capacitance of a transistor or a wiring.

  The control signal WE is input to the gate of the transistor 1209. The switch 1203 and the switch 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE, and the first terminal and the second terminal of one switch are selected. When the terminals of the other switch are in the conductive state, the first terminal and the second terminal of the other switch are in the non-conductive state.

  A signal corresponding to the data held in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. In the example shown in FIG. 24, the signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. The signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) becomes an inverted signal whose logical value is inverted by the logic element 1206 and is input to the circuit 1201 through the circuit 1220. ..

  Note that FIG. 24 illustrates an example in which the signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220. Not limited to. The signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without being inverted in logical value. For example, in the case where there is a node in the circuit 1201 in which a signal in which a logic value of a signal input from an input terminal is inverted is held, the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) The output signal can be input to the node.

  In FIG. 24, among the transistors used for the memory element 1200, transistors other than the transistor 1209 can be transistors in which a channel is formed in a film formed using a semiconductor other than an oxide semiconductor or the substrate 1190. For example, a transistor in which a channel is formed in a silicon film or a silicon substrate can be used. Alternatively, all the transistors used in the memory element 1200 can be transistors whose channels are formed using an oxide semiconductor. Alternatively, the memory element 1200 may include a transistor whose channel is formed using an oxide semiconductor, in addition to the transistor 1209, and the remaining transistors have a channel formed in a layer formed using a semiconductor other than an oxide semiconductor or in the substrate 1190. It can also be a transistor that is closed.

  A flip-flop circuit can be used for the circuit 1201 in FIG. As the logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.

  In the semiconductor device according to one embodiment of the present invention, the data stored in the circuit 1201 can be held by the capacitor 1208 provided in the circuit 1202 while the power supply voltage is not supplied to the memory element 1200.

  Further, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is extremely low. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor is significantly lower than the off-state current of a transistor whose channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held in the capacitor 1208 can be kept for a long time even when the power supply voltage is not supplied to the memory element 1200. In this way, the memory element 1200 can retain the memory content (data) even while the supply of the power supply voltage is stopped.

  In addition, since the memory element is characterized in that a precharge operation is performed by providing the switch 1203 and the switch 1204, the time until the circuit 1201 holds the original data again after the supply of power supply voltage is restarted is shortened. be able to.

  In the circuit 1202, the signal held by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after the supply of the power supply voltage to the memory element 1200 is restarted, the signal held by the capacitor 1208 is converted into the state (conducting state or non-conducting state) of the transistor 1210 and read from the circuit 1202. You can Therefore, the original signal can be accurately read even if the potential corresponding to the signal held in the capacitor 1208 slightly changes.

  By using such a memory element 1200 for a memory device such as a register or a cache memory included in a processor, data loss in the memory device due to supply of power supply voltage can be prevented. Moreover, after the supply of the power supply voltage is restarted, the state before the power supply is stopped can be restored in a short time. Therefore, the power supply can be stopped for a short time in the entire processor or one or a plurality of logic circuits included in the processor, so that power consumption can be suppressed.

  Although the storage element 1200 has been described as an example using the CPU, the storage element 1200 is also applicable to an LSI such as a DSP (Digital Signal Processor), a custom LSI, a PLD (Programmable Logic Device), or an RF (Radio Frequency) device. .

  The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 6)
In this embodiment, electronic devices each including a transistor or the like according to one embodiment of the present invention will be described.

<Electronic equipment>
A semiconductor device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display capable of reproducing a recording medium such as a DVD: Digital Versatile Disc) and displaying the image. Can be used for a device having a. In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a video camera, a camera such as a digital still camera, or goggles. Type display (head mounted display), navigation system, sound reproduction device (car audio, digital audio player, etc.), copier, facsimile, printer, printer complex machine, automatic teller machine (ATM), vending machine, etc. Be done. Specific examples of these electronic devices are shown in FIGS.

  25A shows a portable game machine, which includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like. Note that although the portable game machine illustrated in FIG. 25A includes two display portions 903 and 904, the number of display portions included in the portable game machine is not limited to this.

  25B shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like. The first display portion 913 is provided in the first housing 911, and the second display portion 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connecting portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. is there. The image on the first display unit 913 may be switched according to the angle between the first housing 911 and the second housing 912 in the connection unit 915. Further, a display device in which a function as a position input device is added to at least one of the first display unit 913 and the second display unit 914 may be used. The function as the position input device can be added by providing a touch panel on the display device. Alternatively, the function as the position input device can be added by providing a photoelectric conversion element also called a photosensor in a pixel portion of the display device.

  25C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

  FIG. 25D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, a freezer compartment door 933, and the like.

  FIG. 25E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connecting portion 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by the connecting portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. is there. The image on the display portion 943 may be switched according to the angle between the first housing 941 and the second housing 942 in the connection portion 946.

  FIG. 25F is an automobile, which includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.

  Note that one embodiment of the present invention is described in this embodiment. However, one embodiment of the present invention is not limited to these. In other words, various modes of the invention are described in this embodiment mode and the like; therefore, one mode of the present invention is not limited to a specific mode. For example, as one embodiment of the present invention, an example in which the channel formation region, the source/drain region, and the like of the transistor include an oxide semiconductor is described; however, one embodiment of the present invention is not limited to this. Depending on the case or conditions, the various transistors, the channel formation region of the transistor, the source/drain region of the transistor, or the like in one embodiment of the present invention may include various semiconductors. Depending on circumstances or conditions, various transistors, channel formation regions of transistors, source/drain regions of transistors, and the like in one embodiment of the present invention include, for example, silicon, germanium, silicon germanium, silicon carbide, gallium. At least one of arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be included. Alternatively, for example, in some cases or in some cases, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source/drain region of the transistor, or the like do not include an oxide semiconductor. Good.

  In this example, device simulation was performed on the transistor of one embodiment of the present invention, and the electrical characteristics of the transistor were confirmed.

  In this example, a model 11 is created corresponding to the transistor 10 shown in the above embodiment, and device simulation is performed on the model 11. 26A and 26B are cross-sectional views of the model 11. FIG. 26A corresponds to FIG. 1B described in the above embodiment and is a cross-sectional view of the model 11 in the channel length direction. Further, FIG. 26B corresponds to FIG. 1C described in the above embodiment and is a cross-sectional view of the model 11 which is perpendicular to the channel length direction.

  However, unlike the transistor 10, as illustrated in FIG. 26A, a low resistance region 106c and a low resistance region 106d are provided at both ends in the channel length direction of the semiconductor 106b, and further outside the low resistance region 106c. The conductor 108a is provided, and the conductor 108b is provided outside the low resistance region 106d. As shown in FIG. 26B, the insulator 112 is continuously provided inside and outside the conductor 114, and a portion provided inside the conductor 114 is the conductor 114 and the conductor. It functions as a gate insulating film for 102.

Here, the insulator 106a is assumed to be IGZO (134), and the semiconductor 106b is assumed to be IGZO (111). Further, the low resistance region 106c and the low resistance region 106d are assumed to have a donor density of 1.0×10 ¹⁹ /cm ³ by adding a donor to the semiconductor.

  For the calculation, a device simulator ATLAS3D manufactured by Silvaco was used. As main calculation conditions, the channel length L (width of the conductor 114 shown in FIG. 26) is 30 nm, the radius of the semiconductor 106b is 10 nm, the film thickness of the insulator 106a is 5 nm, and the film thickness of the conductor 114 is The thickness of the conductor 102 was set to 10 nm and the thickness of the conductor 102 was set to 2 nm. In the insulator 112, the film thickness between the insulator 106a and the conductor 114 is 12 nm, the film thickness between the insulator 106a and the conductor 102 is 5 nm, and the film thickness outside the conductor 114 is 10 nm. did. Further, Table 1 below shows detailed parameters used in the calculation. In Table 1, the conduction band density of states (Nc) indicates the density of states at the bottom of the conduction band, and the valence band density of states (Nc) indicates the density of states at the top of the valence band.

  Like the transistor 10, the model 11 includes a semiconductor 106b, an insulator 106a, an insulator 112, a conductor 102, a conductor 114, a conductor 108a, and a conductor 108b. Here, the semiconductor 106b functions as an active layer, the insulator 112 functions as a gate insulating film for the conductors 104 and 102, the conductor 114 functions as a gate electrode, and the conductor 102 functions as a back gate electrode. However, the conductor 108a functions as a source electrode, and the conductor 108b functions as a drain electrode.

  FIG. 27 shows Id-Vg characteristics (drain current-gate voltage characteristics) obtained by performing device simulation. In FIG. 27, the horizontal axis represents the gate voltage Vg [V] and the vertical axis represents the drain current Id [A]. The calculation of the Id-Vg characteristics was performed when the back gate voltage Vbg was set to -3V and when Vbg was set to 0V. In each case, the drain voltage is set to 0.1V and the gate voltage is swept from -3.0V to 3.0V.

  As shown in FIG. 27, when the back gate voltage is not applied (Vbg=0V), the transistor is in a conductive state at Vg=0V, but when Vbg=-3V, at Vg=0V. The transistor is off. As described above, it was shown that the normally-off type Id-Vg characteristics can be obtained by applying the back gate voltage.

  In this manner, by providing the conductor 114 having a function as a gate electrode so as to surround the semiconductor 106b and the conductor 102 functioning as a back gate, normally-off even in a transistor having a short channel length. It can give electrical characteristics.

10 transistor 10a transistor 10b transistor 10c transistor 10d transistor 10e transistor 11 model 14 transistor 50 transistor 50a transistor 102 conductor 104 conductor 106a insulator 106b semiconductor 106c low resistance region 106d low resistance region 108a conductor 108b conductor 112 insulator 114 conductivity Body 150 Substrate 151 Insulator 152 Conductor 156a Insulator 156b Semiconductor 156c Insulator 156d Insulator 156e Insulator 156f Insulator 157 Insulator 158a Conductor 158b Conductor 158c Conductor 158d Conductor 158e Conductor 158f Conductor 162 Insulator 162a Insulator 162b Insulator 162c Insulator 162d Insulator 162e Insulator 162f Insulator 162g Insulator 162h Insulator 164a Conductor 164b Conductor 167 Insulator 800 Inverter 810 OS transistor 820 OS transistor 831 Signal waveform 832 Signal waveform 840 Dashed line 841 Solid line 850 OS transistor 860 CMOS inverter 901 Housing 902 Housing 903 Display 904 Display 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Housing 912 Housing 913 Display 914 Display 915 Connection 916 Operation key 921 Housing 922 Display unit 923 Keyboard 924 Pointing device 931 Housing 932 Refrigerating room door 933 Freezing room door 941 Housing 942 Housing 943 Display unit 944 Operation keys 945 Lens 946 Connection unit 951 Body 952 Wheel 953 Dashboard 954 Light 1189 ROM interface 1190 Board 1191 ALU
1192 ALU controller 1193 Instruction decoder 1194 Interrupt controller 1195 Timing controller 1196 Register 1197 Register controller 1198 Bus interface 1199 ROM
1200 storage element 1201 circuit 1202 circuit 1203 switch 1204 switch 1206 logic element 1207 capacitance element 1208 capacitance element 1209 transistor 1210 transistor 1213 transistor 1214 transistor 1220 circuit 2100 transistor 2200 transistor 3001 wiring 3002 wiring 3003 wiring 3004 wiring 3005 wiring 3006 wiring 3200 transistor 3300 transistor 3400 Capacitance element 3500 Transistor 4001 Wiring 4003 Wiring 4005 Wiring 4006 Wiring 4007 Wiring 4008 Wiring 4009 Wiring 4021 Layer 4022 Layer 4023 Layer 4100 Transistor 4200 Transistor 4300 Transistor 4400 Transistor 4500 Capacitive element 4600 Capacitive element

Claims (10)

A first conductor provided in a ring,
An oxide semiconductor having a region extending through the inside of the ring of the first conductor;
A first insulator provided between the first conductor and the oxide semiconductor;
A second insulator provided between the first conductor and the first insulator;
A second conductor provided through the inside of the ring of the first conductor,
A semiconductor device in which the second conductor is provided in the second insulator. In claim 1,
A third conductor and a fourth conductor which are in contact with the oxide semiconductor and are sandwiched by the first conductor; and
The distance between the said 3rd conductor and the said 4th conductor is 2 nm or more and 30 nm or less, The semiconductor device characterized by the above-mentioned. In claim 1 or claim 2,
A cross-sectional shape of a plane substantially perpendicular to the extending direction of the oxide semiconductor is a substantially circular shape. In claim 1 or claim 2,
A cross-sectional shape of a plane substantially perpendicular to the extending direction of the oxide semiconductor is a substantially polygonal shape. In claim 1 or claim 2,
The semiconductor device is provided on a substrate,
The upper surface of the substrate is substantially parallel to the extension direction of the oxide semiconductor. In claim 1 or claim 2,
The semiconductor device is provided on a substrate,
The semiconductor device, wherein the upper surface of the substrate is substantially perpendicular to the extending direction of the oxide semiconductor. In claim 1 or claim 2,
The semiconductor device, wherein the first insulator contains at least one of indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf) and zinc. A first conductor extending on the substrate in a first direction;
A first insulator provided on the first conductor;
A second insulator provided on the first insulator and having an opening;
A second conductor provided in the opening formed in the second insulator so as to extend in a second direction that is substantially perpendicular to the first direction, the second insulator, and the second insulator. A third insulator provided on the second conductor,
A fourth insulator provided on the third insulator,
A third conductor and a fourth conductor provided on the third insulator with the fourth insulator interposed therebetween;
An oxide semiconductor provided in contact with the upper surfaces of the fourth insulator, the third conductor, and the fourth conductor and extending in the second direction,
A fifth conductor provided in contact with an upper surface and a side surface of the oxide semiconductor and a side surface of the third conductor and facing the sixth conductor with a fifth insulator interposed therebetween; ,
The sixth conductor provided in contact with the upper surface and the side surface of the oxide semiconductor and the side surface of the fourth conductor, and facing the fifth conductor with a fifth insulator interposed therebetween. When,
A sixth insulator provided on the fifth conductor and the sixth conductor and having an opening between the fifth conductor and the sixth conductor;
An upper surface of the oxide semiconductor, side surfaces of the fifth conductor and the sixth conductor, and a fifth insulator provided in contact with a side surface of the sixth insulator;
A seventh insulator provided in contact with the upper surface of the fifth insulator,
A seventh conductor provided in contact with the upper surface of the seventh insulator,
In a cross section of a plane substantially perpendicular to the first direction,
The fourth insulator and the fifth insulator are provided so as to surround the oxide semiconductor,
The third insulator and the seventh insulator are provided so as to surround the fourth insulator, the oxide semiconductor, and the fifth insulator,
The semiconductor device, wherein the first conductor and the seventh conductor are provided so as to surround the first to third insulators and the seventh insulator. In claim 8,
The fourth insulator and the fifth insulator include at least one or more of indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf) and zinc. Semiconductor device. In any one of claim 1, claim 2, claim 8 and claim 9,
The semiconductor device, wherein the oxide semiconductor contains indium, elements M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), zinc, and oxygen.

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