JP6686938B2 - Drive circuit and inkjet recording device - Google Patents

Description

  The present invention relates to a drive circuit and an inkjet recording device.

  2. Description of the Related Art Conventionally, there is an ink jet recording apparatus that ejects ink from a nozzle to form an image or a structure on a medium. In an ink jet recording apparatus, an appropriate amount of ink is ejected at a desired speed by applying a pressure change to the ink in an ink flow path communicating with each nozzle.

  As one of methods of applying pressure to ink, there is a technique of deforming the wall surface of the pressure chamber in the ink flow path by applying a predetermined drive waveform voltage to an actuator such as a piezoelectric element. Since the actuator deforms at high speed and with high accuracy with respect to the applied voltage, it is possible to precisely control the ejection timing and the ejection amount.

  2. Description of the Related Art In recent years, the number of nozzles and actuators corresponding thereto has been increasing according to the demand for higher speed and higher accuracy of inkjet recording apparatuses. If a large number of nozzles are provided with actuators, which are capacitive loads, and drive voltages are applied simultaneously to these actuators depending on whether or not ink is ejected, a large amount of current will flow at a time and instantaneous consumption will occur. There is a problem that the electric power becomes large, the output voltage is lowered beyond the capacity of the power supply, and the waveform of the driving voltage actually applied is blunted. On the other hand, there is known a technique for suppressing an instantaneous increase in current value and power consumption by shifting the phase of the ink ejection cycle from a plurality of nozzles (Patent Document 1).

JP-A-6-127034

  However, it is known that when a drive circuit in which the phases of the ink discharge cycles from a plurality of nozzles are shifted is used, a slight shift occurs in the ink landing position in the inkjet recording apparatus according to the phase shift. Therefore, depending on the intended use of the inkjet recording apparatus, such as formation of a high-quality image or a structure that requires highly accurate alignment, it may be desired to secure a sufficient power supply capacity and prevent such a phase shift. . As described above, preparing a drive circuit having a separate circuit configuration depending on whether or not there is a phase shift in the ink ejection cycle has a problem that it takes time and cost.

  An object of the present invention is to provide a drive circuit and an ink jet recording apparatus that can be easily set depending on whether or not there is a phase shift in the ink ejection cycle.

In order to achieve the above object, the invention according to claim 1 is
A drive circuit for outputting an operation signal for driving each of the predetermined number of loads for ejecting ink from a predetermined number of two or more nozzles,
An output circuit that generates and outputs an operation signal for each of the predetermined number of loads,
A delay circuit for delaying the output timing of the predetermined number of operation signals to a plurality of different timings;
A delay setting element that switches the setting related to the presence or absence of the delay operation in the delay circuit by being irreversibly invalidated;
A setting circuit for transmitting a setting signal for disabling the delay setting element,
It is characterized by having.

The invention described in claim 2 is the drive circuit according to claim 1,
The setting circuit has an input end for inputting an input signal from the outside, and disables the delay setting element according to a predetermined input signal from the input end.

Further, the invention according to claim 3 is the drive circuit according to claim 1 or 2,
The setting circuit is formed to be able to detect whether or not the delay setting element is invalid by inputting a predetermined inspection signal.

Further, the invention according to claim 4 is the drive circuit according to claim 1 or 2,
It is characterized by having a detection circuit for detecting whether or not the delay setting element is invalid.

According to a fifth aspect of the present invention, in the drive circuit according to the fourth aspect,
The detection circuit is provided with a notification operation unit that performs a predetermined notification operation according to at least one of whether the delay setting element is invalid when a predetermined inspection signal is input. There is.

The invention according to claim 6 is the drive circuit according to any one of claims 1 to 5, wherein
The output circuit, a drive waveform input unit for acquiring a plurality of drive waveform data in time series,
A waveform selection unit that selects any one of the plurality of acquired drive waveform data according to ink ejection data;
An operation signal generation unit that converts the selected waveform into an analog signal corresponding to each of the waveforms and outputs the operation signal as an operation signal,
Equipped with
The delay circuit delays the input timing of the drive waveform data acquired by the drive waveform input unit, thereby delaying the output timing of the operation signal output from the operation signal generation unit.

The invention according to claim 7 is the drive circuit according to any one of claims 1 to 6, wherein:
The delay setting element is a separation element that does not perform the delay operation by separating a part of the delay circuit by being cut off, and the delay setting element is delayed according to the setting signal input to the setting circuit. It is characterized by cutting the setting element.

The invention according to claim 8 is the drive circuit according to claim 7,
The delay circuit is an RC circuit,
The isolation element is characterized by separating the capacitor from the RC circuit by cutting.

The invention according to claim 9 is the drive circuit according to any one of claims 1 to 8, wherein
The predetermined number of loads each belong to one of a plurality of blocks,
The delay circuit is characterized in that the output timings of the plurality of blocks are different from each other.

Further, the invention according to claim 10 is
The drive circuit according to any one of claims 1 to 9,
A recording unit having a plurality of loads driven by receiving the operation signals respectively output from the drive circuits, and a plurality of nozzles ejecting ink by the operation of the loads,
An ink jet recording apparatus comprising:

  According to the present invention, there is an effect that the drive circuit of the inkjet head can be easily set in accordance with whether or not there is a phase shift in the ink ejection cycle.

FIG. 3 is a block diagram showing a functional configuration of the inkjet recording apparatus according to the embodiment of the present invention. It is a figure explaining the structure regarding the signal generation in a drive pulse generation part. It is a figure which shows the output waveform of three types of drive signals and a corresponding drive voltage signal. The correspondence table of pixel data and a drive waveform pattern is shown. It is a figure which shows the drive voltage waveform pattern output to the piezoelectric element of a 1st operation part from a buffer amplifier according to a nozzle group selection signal and pixel data. It is a figure which shows the output timing of the drive voltage signal at the time of the discharge operation which the 1st drive pulse generation part-the 4th drive pulse generation part output. It is a figure which shows the circuit structure of a 1st delay part and a 2nd delay part. It is a figure which shows the structure at the time of connecting the structure which detects the presence or absence of a fuse cut to the external terminal of a delay part. It is a figure which shows the modification of the circuit structure of a delay part. It is a figure which shows the modification of the 1st delay part. It is a figure which shows the other modification of the 1st delay part.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the functional configuration of the inkjet recording apparatus 1.
The inkjet recording device 1 includes a main body 2 and an inkjet head 3. Here, only one inkjet head 3 is shown, but when the inkjet recording apparatus 1 is a color printer that ejects a plurality of ink colors, the inkjet head 3 uses the plurality of ink colors (for example, It is provided corresponding to each of four colors (yellow, magenta, cyan, and black). Further, a plurality of inkjet heads 3 for ejecting ink of the same color may be provided to further increase the number of nozzles. The main body 2 and the inkjet head 3 are connected by, for example, an FPC (Flexible Printed Circuit).

  The main body 2 includes a CPU 21 (Central Processing Unit), an input / output interface 22, a memory 23, a control circuit 24, a drive signal generation circuit 25, a unit control unit 26, and the like.

  The CPU 21 performs arithmetic processing and various control processing relating to image recording operation in the inkjet recording apparatus 1.

  The input / output interface 22 receives commands related to image recording, settings and image data to be recorded from an external device, and outputs statuses and abnormality occurrence information related to the image recording operation from the CPU 21 to the external device. Interface. A network card (LAN card) or the like is used as the input / output interface 22.

  The memory 23 stores image data to be recorded, which is acquired from an external device, and pixel data, which is generated from the image data and determines an ink ejection state from each nozzle. The pixel data is output from the memory 23 to the drive pulse generator 33 of the inkjet head 3 and used to generate a drive voltage signal (drive pulse, operation signal) according to whether or not ink is ejected from each nozzle.

  The control circuit 24 supplies various control signals to the drive pulse generator 33 of the inkjet head 3. The control signal includes a signal for controlling whether or not an operation such as transfer of pixel data or supply of a driving voltage and the operation timing are performed.

  The drive signal generation circuit 25 supplies a drive signal representing the waveform of the drive voltage signal generated by the inkjet head 3 to the drive pulse generation unit 33 of the inkjet head 3. Here, the drive signal generation circuit 25 can output three kinds of drive signals (drive signal PLSTIM0 used when ink is not ejected, drive signal PLSTIM1 used when ink is not operated, drive signal PLSTIM2 used when ink is ejected). , Are stored as digital data in a memory (not shown). For example, SRAM is used as the memory.

  The unit controller 26 controls the overall operation of the inkjet recording apparatus 1.

  The inkjet head 3 includes a nozzle array 31, an ejection operation unit 32, a drive pulse generation unit 33 (output circuit), a delay unit 34 (delay circuit), and the like.

  The nozzle row 31 has a predetermined number of 2 or more, which is 1024 nozzles, arranged in an appropriate pattern. The nozzle row 31 is divided into four nozzle rows of a first nozzle row 31a, a second nozzle row 31b, a third nozzle row 31c, and a fourth nozzle row 31d, each of which has 256 nozzles. The ejection operation unit 32 performs a first operation unit 32a, a second operation unit 32b, a third operation unit 32c, and a fourth operation unit 32a that perform operations related to ink ejection from each of the 256 nozzles in these four nozzle rows 31a to 31d. The operation portion 32d is formed separately (belonging to any one of the plurality of blocks). In the ink jet recording apparatus 1 of the present embodiment, for simplification, 1024 nozzles are one-dimensionally arranged, divided into three groups, and each group is driven by three cycles in which ink is ejected sequentially at different timings. .

  The ejection operation unit 32 ejects ink for each channel (ink flow path) that communicates with each nozzle and supplies ink, or a pressure change for vibrating a liquid surface (meniscus) without ejecting ink. It has an actuator (load) that imparts to ink. Here, as the actuator, a piezoelectric element such as PZT (lead zirconate titanate) is used, and the piezoelectric element is arranged between the channels as a partition wall of the channels arranged one-dimensionally. When a predetermined voltage is applied to the actuator via the electrode films provided on both side surfaces of the actuator (that is, the inner surface of the channel), the actuator is bent and deformed, and pressure is applied to the ink inside. It should be noted that dummy channels are provided at both ends of the 1024 channels which are one-dimensionally arranged so as to influence the channels at the both ends, and a deforming operation is performed without supplying or ejecting ink. . Although the shear mode (shear mode) is used for the deformation of the actuator here, the deformation in other modes such as the bend mode may be used.

  The first nozzle row 31a and the first operating portion 32a, the second nozzle row 31b and the second operating portion 32b, the third nozzle row 31c and the third operating portion 32c, and the fourth nozzle row 31d and the fourth operating portion 32d, Each is configured as one head chip. Alternatively, all of them may be configured as one head chip (recording unit).

  The drive pulse generation unit 33 sets each actuator of the ejection operation unit 32 to an appropriate timing according to the presence or absence of ink ejection from each nozzle and the density gradation at the time of ejection, which is determined based on the image data input from the main body unit 2. , And generates and outputs a drive voltage signal (drive pulse) for changing the amplitude and the period. The drive pulse generation unit 33 outputs a drive voltage signal to each of the first operation unit 32a to the fourth operation unit 32d, a first drive pulse generation unit 33a, a second drive pulse generation unit 33b, and a third drive pulse generation. The unit 33c and the fourth drive pulse generator 33d are provided with four IC chips. These four IC chips are arranged in series with respect to the transmission path of the pixel data output from the memory 23. That is, the pixel data is input / output from the memory 23 to the fourth drive pulse generation unit 33d, and then sequentially transmitted to the third drive pulse generation unit 33c, the second drive pulse generation unit 33b, and the first drive pulse generation unit 33a. . The pixel data may be output from the first drive pulse generation unit 33a and returned to the main body unit 2, or may be terminated by the terminating device (terminator). Here, each pixel data is represented by a 3-bit value (SI0 to SI2).

The delay unit 34 delays the drive signal input from the drive signal generation circuit 25. The delay unit 34 sets the ink ejection timing from each of the nozzle rows 31a to 31d, that is, the output timing of the drive voltage signal output from the drive pulse generation unit 33, between the operation units 32a to 32d (plural blocks) that are output destinations. In order to make them different from each other (shifted to a plurality of different timings), different delay amounts are given to the drive signals. The delay unit 34 includes a first delay unit 34a corresponding to the first drive pulse generation unit 33a, a second delay unit 34b corresponding to the second drive pulse generation unit 33b, and a third delay corresponding to the third drive pulse generation unit 33c. It is divided into parts 34c. Then, the first delay unit 34a, the second delay unit 34b, and the third delay unit 34c generate different delay amounts. Here, a delay unit is not provided for the fourth drive pulse generation unit 33d, and the fourth drive pulse generation unit 33d generates the drive voltage signal according to the input timing signal and waveform pattern. Alternatively, a delay unit corresponding to the fourth drive pulse generation unit 33d may be provided, and the delay amount of this delay unit is different from the delay amounts of the first delay unit 34a to the third delay unit 34c.
The drive pulse generation unit 33 and the delay unit 34 are collectively arranged and formed on the semiconductor substrate or the like as the drive circuit 30 according to the embodiment of the present invention.

  FIG. 2 is a diagram illustrating a configuration related to signal generation in the drive pulse generation unit 33. Here, the fourth drive pulse generation unit 33d will be described, but the first drive pulse generation unit 33a to the third drive pulse generation unit 33c are the same except that the data input source, output destination, and nozzle to be operated are different. .

The fourth drive pulse generation unit 33d includes a shift register 331, a latch circuit 332, a waveform selection unit 333 (gray scale controller, drive waveform input unit), and a buffer amplifier 334 (operation signal generation unit).
Note that, here, the wirings that connect the shift register 331, the latch circuit 332, the waveform selection unit 333, and the buffer amplifier 334 to each other, and the output terminal that outputs the drive voltage signal from the buffer amplifier 334 to the fourth operation unit 32d are partially Only the picture is drawn.

  The shift register 331 is a FIFO type memory that stores 3-bit data for 256 channels (ink channels). The shift register 331 stores the pixel values (SI0 to SI2) of the 3-bit pixel data SI input in parallel from the memory 23 while transferring them in synchronization with the transfer clock signal DCLK. 256 pieces of pixel data SI are stored in the order of being input to the shift register 331, respectively, and then further output to the third drive pulse generation unit 33c as each pixel value (SO0 to SO2) of the output pixel data SO. In the third drive pulse generator 33c, these output pixel data SO are input as pixel data SI. The 256 pieces of 3-bit data stored in the shift register 331 are collectively output in parallel to the latch circuit 332 at a predetermined timing.

  The latch circuit 332 holds the 3-bit data of 256 channels output from the shift register 331 until the timing designated by the latch signal LAT, and outputs the data to the waveform selection unit 333. The latch signal LAT is input in synchronization with the four IC chips (latch circuit 332) of the drive pulse generator 33.

  The waveform selection unit 333 selects a drive signal in a drive waveform pattern corresponding to a grayscale (gray scale; 8 grayscales) indicated by 3-bit pixel data (ink ejection data) input from the latch circuit 332. Output the selection signal of each to the buffer amplifier 334. The waveform selection unit 333 includes a counter 333a and an output pattern register 333b. The synchronization clock signal GSCLK, the reset signal RST, and the nozzle group selection signal STB-n [0: 2] are input to the waveform selection unit 333 from the control circuit 24. Further, the above-mentioned three types of drive signals PLSTIM0 to PLSTIM2 (a plurality of drive waveform data) are input from the drive signal generation circuit 25 to the waveform selection unit 333, and are acquired in time series.

  FIG. 3A shows output waveforms of three types of drive signals. The drive signal PLSTIM0 used when ink is not ejected (non-ejection) is maintained at a low level during the period of one count of the gray scale count GSC. The drive signal PLSTIM2 used when ink is ejected is at a high level for a predetermined period of the one grayscale count GSC period. The drive signal PLSTIM1 used during non-operation is at the high level for a predetermined period after the drive signal PLSTIM2 returns from the high level to the low level in the period of one count of the gray scale count GSC.

  The nozzle group selection signal STB-n is a signal that determines from which set of nozzles the 1024 nozzles divided into three sets can eject ink. As described above, when one channel is contracted by the displacement of the partition to eject ink, the channel on the side opposite to the one channel with respect to the partition expands and ink is not ejected. Three-cycle driving is performed in which channels (nozzles) for dividing and sequentially ejecting ink are switched. Therefore, any one of STB-1, STB-2, and STB-3 can be set to the high level, and the rest can be set to the low level. When STB-1 is at a high level, ink can be ejected only from the first set of nozzles, and when STB-2 is at a high level, ink can be ejected only from the second set of nozzles, When STB-3 is at high level, ink can be ejected only from the nozzles of the third set. In each channel, STB-n expands during a low level period to allow ink to flow into the channel, and then STB-n contracts during a high level period to push out the inflowing ink to eject the ink from the nozzle.

  The counter 333a counts and outputs the gray scale counts GSC (0 to 7) one by one according to the synchronous clock signal GSCLK and outputs the gray scale count GSC (0 to 7).

  The output pattern register 333b stores a conversion table that defines the relationship between the 3-bit pixel data SI and the nozzle group selection signal STB-n, and the drive waveform pattern data for driving the piezoelectric element of the first operation unit 32a. Has been done. The waveform selection unit 333 selects drive waveform pattern data that is data indicating an array of eight drive waveforms (drive signals) that are sequentially output according to the input pixel data SI and the nozzle group selection signal STB-n. , A signal corresponding to the type of drive waveform for each gray scale count GSC is output to the buffer amplifier 334 as a selection signal.

  FIG. 4 shows a correspondence table between pixel data SI and drive waveform patterns.

  The drive waveform pattern is defined for each of the 3-bit 8-gradation pixel data SI ((0,0,0) to (1,1,1)). The drive waveform pattern data is data representing an array of eight drive signals that are determined corresponding to the respective values 0 to 7 of the gray scale count GSC, and three types of values 0 to 2 are set. . The values 0 to 2 correspond to the drive signals PLSTIM0, PLSTIM1, and PLSTIM2, respectively. For example, the input pixel data SI (1,0,1) is driven by (0,2,2,2,2,1,1,1) when the nozzle group selection signal STB-n is at high level. Corresponding to the waveform pattern data, according to this, the drive signal PLSTIM0 is selected once, PLSTIM2 is selected four times, and PLSTIM1 is selected three times in succession for each period of the value of each gray scale count GSC. As described above, the selection signal is generated and output to the buffer amplifier 334. When the nozzle group selection signal STB-n is low level, (0, 1, 1, 1, 1, 1, 1, 1, 1) is selected as the drive waveform pattern data regardless of the input pixel data SI. To be done.

  The drive waveform pattern data of (0, 1, 1, 1, 1, 1, 1, 1, 1) is always selected for the output terminal out-D for the dummy channel.

  The buffer amplifier 334 generates a drive voltage signal (converts into an analog signal) at a voltage necessary for the operation of each piezoelectric element of the first operation unit 32a based on the selection signal input from the waveform selection unit 333, It outputs to the output terminal out-N (N = 1 to 256, D) to each piezoelectric element of the 1st operation part 32a. Positive voltage VH1 and voltage VH2 are supplied to the buffer amplifier 334. The voltage VH1 is a voltage value corresponding to the deformation operation of the piezoelectric element when not operating, and the deformation of the piezoelectric element can vibrate the liquid surface (meniscus) without ejecting ink from the nozzle openings. The voltage VH2 is larger than the voltage VH1 and has a voltage value corresponding to the deformation operation of the piezoelectric element during ink ejection.

  As shown in FIG. 3B, as the drive voltage signal, the voltage VH1 is output while the drive signal PLSTIM1 input as the selection signal from the waveform selection unit 333 is at the high level, and the drive voltage signal is selected from the waveform selection unit 333. The voltage VH2 is output while the drive signal PLSTIM2 input as a signal is at a high level. Here, the ground voltage GND is output while the drive signals PLSTIM1, PLSTIM2, and PLSTIM0 are at a low level.

  FIG. 5 is a diagram showing a drive voltage waveform pattern output from the buffer amplifier 334 to the piezoelectric element of the first operation unit 32a according to the nozzle group selection signal STB-n and the pixel data SI.

  With the selection signals corresponding to the eight drive signals input according to the drive waveform pattern selected by the waveform selection unit 333, the buffer amplifier 334 outputs eight drive voltages per pixel data for the piezoelectric element that operates each nozzle. The signal is output in a cycle corresponding to the interval of the synchronous clock signal GSCLK. Then, ink is ejected from each nozzle and the liquid surface (meniscus) is vibrated in accordance with the deformation operation of the piezoelectric element driven by the drive voltage signal.

  When the gray scale count GSC is counted up to 7 and eight driving voltage signals are supplied to the nozzles of the set selected by the nozzle group selection signal STB-1, the gray scale count GSC is reset by the reset signal RST. When the nozzle group selection signal STB-1 is changed to low level and STB-2 is changed to high level, eight driving voltage signals are supplied to the changed selected nozzles. To be done. Similarly, at the time of the next reset, the high level is changed from the nozzle group selection signals STB-2 to STB-3 and the eight drive voltage signals are supplied, whereby ink can be ejected from all the nozzles.

  As described above, each nozzle ejects ink according to the drive voltage signal of the piezoelectric element generated by the drive pulse generator 33 and supplied to each piezoelectric element of the ejection operation unit 32. At this time, the timing of the drive signal input from the drive signal generation circuit 25 varies according to the delay amount of the delay unit 34, and therefore the deformation timing of the piezoelectric element between the first operation unit 32a to the fourth operation unit 32d. Shifts according to the delay amount.

  FIG. 6 is a diagram showing the output timing of the drive voltage signal during the ejection operation output from the first drive pulse generation unit 33a to the fourth drive pulse generation unit 33d.

  In contrast to the drive voltage signal for the ejection operation output from the fourth drive pulse generation unit 33d having no delay unit, the drive voltage signal for the ejection operation output from the third drive pulse generation unit 33c has a delay time Td3. There is a rise to the voltage VH2 and a fall to the ground voltage with a delay of. Similarly, the drive voltage signal for the ejection operation output from the second drive pulse generation unit 33b and the drive voltage signal for the ejection operation output from the first drive pulse generation unit 33a are respectively generated by the fourth drive pulse generation operation. Rise and fall occur after a delay time Td2, Td1 with respect to the drive voltage signal output from the portion 33d during the ejection operation. This delay amount is the same for the drive voltage signal when not operating.

  Since the piezoelectric element is a capacitive load, a current related to charging / discharging is generated at the time of rising and falling of these drive voltage signals where the applied voltage changes, and power is consumed. If this timing overlaps for all piezoelectric elements, the power consumption (instantaneous power consumption) consumed at one time becomes extremely large, and depending on the capacity of the power supply, the supply voltage drops and the voltage required for the piezoelectric elements. Is not applied or it takes time to be applied.

  On the other hand, although the initial cost and power consumption increase, it is possible to drive all the piezoelectric elements with certainty by connecting to a power source having a sufficient capacity. On the other hand, by using the delay unit 34, the timing at which this current flows is divided into four, and the maximum value of the instantaneous power consumption decreases, so there is no need to increase the power supply capacity or power consumption. However, in this case, a slight deviation of the ink ejection timing occurs due to the deviation of the driving timing of the piezoelectric element, which may deteriorate the image quality.

  In the inkjet recording apparatus 1 of the present embodiment, whether or not to use the delay unit 34 can be initially set and shipped according to the application by the user.

FIG. 7 is a diagram showing a circuit configuration of the first delay unit 34a and the second delay unit 34b.
Since the circuit configuration of the third delay unit 34c is the same as the circuit configuration of the first delay unit 34a and the second delay unit 34b, the description thereof will be omitted.

  The first delay unit 34a includes resistance elements 341a and 343a, a capacitor 342a, a buffer 344a, a fuse 345a (delay setting element, separation element), diodes 346a and 347a, and the like. The drive signal input from the drive signal generation circuit 25 is output to the first drive pulse generation unit 33a via a signal path connected to the buffer 344a via the resistance elements 341a and 343a. The second delay unit 34b includes resistance elements 341b and 343b, a capacitor 342b, a buffer 344b, a fuse 345b, diodes 346b and 347b, and the like. The drive signal input from the drive signal generation circuit 25 is output to the second drive pulse generation unit 33b via a signal path connected to the buffer 344b via the resistance elements 341b and 343b. Hereinafter, only the first delay unit 34a will be described.

  One end of the capacitor 342a is connected to the other end of the fuse 345a connected to this signal path, and the other end is grounded. When the fuse 345a is in the conductive state, an RC circuit is formed by the capacitor 342a and the resistance elements 341a and 343a in the signal path, and the drive signal output is input with the drive signal input from the drive signal generation circuit 25. A delay amount occurs depending on the resistance value and the capacitance with respect to the timing. In the first delay unit 34a, the second delay unit 34b, and the third delay unit 34c, at least one of the resistance value of the resistance element and the capacitance of the capacitor is set to be different from each other, and thus the delay amount is made different.

  A diode 346a is provided in parallel with the capacitor 342a and the fuse 345a. The cathode of the diode 346a is connected to the signal path, and the anode is grounded. Therefore, a drive signal which is normally a positive voltage of 0 or more does not flow through this diode 346a. Further, the diode 347a has an anode connected between the capacitor 342a and the fuse 345a, and a cathode connected to an external connection external terminal (an input end for inputting an input signal from the outside). During normal operations such as image recording of the inkjet head 3, the external terminal is open and no current flows through the diode 347a. Schottky barrier diodes are used here as the diodes 346a and 347a. Note that, here, the external terminal is also provided with a connection end of a wiring for frame grounding.

  When the fuse 345a is blown, the capacitor 342a is substantially isolated from the signal path. As a result, the drive signal input from the drive signal generation circuit 25 is output to the first drive pulse generation unit 33a without delay.

  A negative voltage fuse disconnection signal may be input to the external terminal. When the fuse cut signal is input, a current flows from the ground plane connected to the anodes of the capacitor 342a and the diode 346a through the diode 346a, the fuse 345a, and the diode 347a until the fuse 345a is cut. . The resistance value of the cutting path 340a (setting circuit) is low, and by setting an appropriate voltage as the fuse cutting signal (setting signal), the amount of current flowing exceeds the reference current of the fuse 345a and the fuse 345a is cut. At this time, the fuse 345b of the second delay unit 34b and the fuse of the third delay unit 34c are also blown almost at the same time via the cutting circuit 340b of the second delay unit 34b. That is, the presence / absence of the delay operation by the delay unit 34 is switched according to the presence / absence of disconnection of the fuse 345a and the like (presence / absence of irreversible invalidation).

In addition, an inspection signal for detecting whether or not the fuse 345a is cut may be input to the cut path 340a of the fuse 345a from an external terminal.
FIG. 8 is a diagram showing a configuration in which a configuration for detecting whether or not the fuse 345a is cut is connected to the external terminal of the delay unit 34.

  When the fuse 345a is not cut off by connecting the resistor element 501 and the LED 502 (Light Emitting Diode) in series to the external terminal and applying a negative voltage to the cathode side of the LED 502, the diode 346a and the fuse 345a are connected from the ground plane. A current flows to the external terminal through the 345a and the diode 347a, and the LED 502 emits light. When the fuse 345a is cut off, the LED 502 emits light for a short time until the charge corresponding to the negative voltage applied to the capacitor 342a is accumulated, and then turns off immediately. Whether or not the fuse 345a is blown can be determined by visually detecting the light emission of the LED 502 or by detecting with a detection unit such as a photodiode. Note that the fuses 345a and 345b and the fuses of the third delay unit 34c are normally blown together. However, if any one of them is not blown, the LED 502 continues to emit light, so the amount of light emission (luminance) is reduced. Accordingly, the number of uncut lines may be detected.

Alternatively, the delay unit 34 may have a configuration (detection circuit) for detecting whether or not the fuse 345a (and the fuse of the fuse 345b and the third delay unit 34c) is cut.
FIG. 9 is a diagram showing a modification of the circuit configuration of the delay unit 34.

  The switching element 503 is connected to the external terminal. One of the switching elements 503 is directly connected to the diode 347a of the first delay section 34a, and the other is connected to the diode 347a via the LED 502 (notification operation section) and the resistance element 501 shown in FIG. The user switches the switching element 503 manually or through switching control by the main body 2 to switch between cutting and detection of the fuse 345a, inputting an appropriate signal, and at the time of detection, whether or not the LED 502 emits light. (Predetermined notification operation) can be detected.

FIG. 10 is a diagram showing a modification of the first delay unit 34a.
In the modified example of FIG. 10A, the anode side of the diode 346a is directly connected to the external terminal without being grounded. In this case, by applying a positive voltage to the external terminal and applying a negative voltage to the external terminal to which the cathode of the other diode 347a is connected, a high voltage is applied to the fuse 345a with a large margin. A current can be passed to blow the fuse 345a. Further, by making the absolute values of the positive voltage and the negative voltage applied to the external terminal equal, a large voltage is not applied to the signal circuit portion.

  In the modification of FIG. 10B, a functional element 349a provided in parallel with the resistance element 341a is provided instead of the fuse 345a that disconnects the signal path and the capacitor 342a. One ends of the functional element 349a and the resistance element 341a are grounded via the capacitor 342a, and the other ends are connected to the cathode of the diode 346a. A node between the one end and the capacitor 342a is connected to the anode of the diode 347a, and the cathode is connected to the external terminal.

  Here, a varistor is drawn as an example, and the functional element 349a is a high resistance (insulator) normally, but it is an element that can be short-circuited by applying a predetermined high voltage. In the case of high resistance, the resistance element 341a and the capacitor 342a work as a normal delay circuit, and by short-circuiting, the resistance element 341a is bypassed so that the delay time can be ignored.

FIG. 11 is a diagram showing another modification of the first delay unit 34a.
In this modification, the functional element 349a in the modification shown in FIG. 10B is replaced with the fuse 345a.
In this case, in the state where the fuse 345a is not cut, the resistance element 341a in the signal path is bypassed by the fuse 345a. As a result, the drive signal input from the drive signal generation circuit 25 is output to the first drive pulse generation unit 33a without delay. On the other hand, when a fuse cut signal of a negative voltage is input to the external terminal and the fuse 345a is cut, the resistance element 341a functions, and the resistance element 341a and the capacitor 342a work as a delay circuit. As described above, the delay operation does not occur at the initial stage (when the delay setting element is valid), and the fuse 345a is cut (the delay setting element is invalid), so that the delay operation is changed to the state where the delay operation occurs. It is also possible to use a circuit that makes the delay operation effective.

As described above, the drive circuit 30 included in the inkjet recording apparatus 1 according to the present embodiment has a predetermined number of piezoelectric elements (ejection operation section 32) for ejecting ink from a predetermined number of nozzles (nozzle row 31) of 2 or more. ), A drive circuit 30 for outputting a drive voltage signal for driving each of the), a drive pulse generator 33 for generating and outputting a drive voltage signal for a predetermined number of piezoelectric elements, and A delay unit 34 that performs a delay operation that shifts the output timing to a plurality of different timings, and a delay setting such as a fuse 345a and a functional element 349a that switch settings related to the presence or absence of the delay operation in the delay unit 34 by being irreversibly disabled. An element and a disconnect path 340a for transmitting a setting signal for disabling the delay setting element.
In this way, once the delay setting element is switched via the disconnecting path 340a, it is possible to perform the setting to invalidate the operation of the delay unit 34, and thereafter, without supplying power like the switching element. The setting can be maintained and used by the user. Therefore, it is possible to easily perform the setting corresponding to the presence / absence of the phase deviation of the ink ejection cycle, without burdening the setting inspection or the user's use and suppressing the increase in cost.

  Further, the cutting path 340a has an external terminal for inputting an input signal from the outside, and invalidates the delay setting element according to a predetermined setting signal input from the external terminal. As described above, if the setting signal is input once from the dedicated external terminal, all the delay setting elements of the delay unit 34 can be invalidated together, so that the setting process is very easy.

  Further, the disconnection path 340a is formed so as to be able to detect whether the delay setting element (fuse 345a) is invalid (disconnected state) by inputting a predetermined inspection signal. That is, since it is possible to easily inspect whether or not the invalid setting has been made by using the invalid setting circuit as it is, it is possible to easily increase the circuit forming time without increasing the time and effort required for the inspection. It is possible to check whether it is in the invalid state.

  The drive circuit 30 also has a detection circuit for detecting whether the delay setting element is invalid. That is, since it is possible to determine whether or not the delay setting element is invalid by supplying an appropriate current without separately preparing a device for detection, it is possible to disable the delay setting element or to perform a subsequent inspection. The labor can be further reduced.

  In addition, the detection circuit is provided with an LED 502 that performs a predetermined notification operation according to at least one of whether the delay setting element is invalid when a predetermined inspection signal is input. That is, in the circuit as shown in FIG. 9, it is possible to determine whether or not the delay setting element is invalid by supplying an appropriate current without separately preparing a detection device. It is possible to further reduce the trouble such as invalidation and subsequent inspection.

  In addition, the drive pulse generation unit 33 acquires the plurality of drive signals in time series according to the ink ejection data, and the waveform selection unit 333 that selects one of the acquired drive signals in time series. A buffer amplifier 334 for converting the selected drive signal into an analog signal corresponding to the waveform of the drive signal and outputting the analog drive signal as a drive voltage signal. The delay unit 34 includes a buffer amplifier 334 for converting the drive signal acquired by the buffer amplifier 334. By delaying the input timing, the output timing of the drive voltage signal output from the buffer amplifier 334 is delayed. In this way, by generating an appropriate time lag at the transmission stage of a digital signal, especially a binary signal, and shifting the output timing of the final drive voltage signal, it is possible to avoid complication of delay-related processing and high accuracy. An appropriate delay amount can be obtained with a simple circuit.

  Further, the delay setting element is a separation element such as a fuse 345a that does not perform a delay operation by separating a part of the delay unit 34 by being cut, and it corresponds to the setting signal input to the cutting path 340a. Disconnect the delay setting element. As described above, an element that can be cut by a high current or a high voltage is well known and is easy to process, so that it is possible to stably and safely perform the invalidation processing of the delay operation.

  The delay unit 34 is an RC circuit having a resistance element 341a and a capacitor 342a, and disconnects the fuse 345a to separate the capacitor 342a from the RC circuit. Since such a simple circuit can cause a delay and invalidate the delay, the delay operation and the configuration and operation related to the invalidation can be prevented from increasing in cost and labor, and the setting as a whole can be suppressed. The cost and labor for switching can be reduced more than ever before.

Further, the predetermined number of piezoelectric elements belong to one of the first operating unit 32a to the fourth operating unit 32d, and the delay unit 34 drives the drive voltage signal between the first operating unit 32a to the fourth operating unit 32d. The output timings of are different from each other.
In this way, the output timing of the drive voltage signal can be performed for each operation unit without making the output timing of the piezoelectric element different, so that the instantaneous power consumption can be reduced within a necessary range by a simple configuration. It is possible to easily invalidate the delay operation.

In addition, the inkjet recording apparatus 1 of the present embodiment includes the drive circuit 30 described above, a plurality of piezoelectric elements that are driven by receiving drive voltage signals that are respectively output from the drive circuit 30, and ink is generated by the operation of the piezoelectric elements. A head chip having a plurality of nozzles for ejecting.
With such an inkjet recording apparatus 1, it is possible to easily set which of power consumption and image quality should be prioritized according to the intended use of the inkjet recording apparatus 1, in particular, the business use, and the setting is made to the user after the setting. It does not take time and labor for maintenance. Further, it is possible to reduce the cost of providing the configuration related to the setting. That is, the setting can be easily performed in accordance with whether or not there is a phase shift in the ink ejection cycle.

The present invention is not limited to the above embodiment, and various modifications can be made.
For example, in the above-described embodiment, an inkjet head provided with a channel that is driven for 3 cycles has been described as an example, but channels for ejecting ink and dummy channels for not ejecting ink are alternately provided, and all the channels are provided. It may be an inkjet head in which independent driving is performed to simultaneously eject ink from the channels.

  Further, in the above-described embodiment, the fuse is used for description, but other one having a function of similarly switching the presence / absence of delay of the delay unit 34 due to an irreversible change, for example, an IC protector may be used.

  Further, in the above embodiment, the presence / absence of the delay operation of the first delay unit 34a to the third delay unit 34c is collectively set, but the circuit configuration may be set individually, or , It may be possible to change to a two-stage setting.

  Further, in the above-mentioned embodiment, the piezoelectric element such as PZT is used as the capacitive load, but other electrostrictive element may be used. Further, even in the case of a drive circuit using a resistive load, if the power consumption is reduced due to the deviation of the output timing, the power consumption and the image quality based on the user's application are reduced as in the present invention. Switching settings can be set according to the degree of priority.

  Further, in the above-described embodiment, the configuration in which the presence or absence of the blow of the fuse 345a is notified by the LED 502 has been shown, but other light emitting elements may be used, or a device that outputs a sound such as a beep or simply outputs. The current value may be displayed by a numerical value or a pointer operation. Further, not only when not disconnected, but also when not disconnected, it may be provided with a notification operation unit that performs different operations.

  Further, in the above embodiment, the RC circuit is used to cause the delay, but other circuits, LC circuits, etc. may be used. Further, the delay is not limited to being generated before the input to the drive pulse generation unit 33, and may be performed within the drive pulse generation unit 33 (the waveform selection unit 333 or the buffer amplifier 334).

Further, in the above embodiment, three types of drive signals are used, but the present invention is not limited to these. Further, the drive signal is not limited to a simple rectangular wave signal, and the technology according to the present invention can be applied to a signal other than a rectangular wave signal.
In addition, the specific details such as the configuration, the circuit arrangement, and the operation procedure shown in the above-described embodiment can be appropriately changed without departing from the spirit of the present invention.

1 Inkjet recording device 2 Main body 3 Inkjet head 21 CPU
22 input / output interface 23 memory 24 control circuit 25 drive signal generation circuit 26 unit control section 30 drive circuit 31 nozzle row 31a first nozzle row 31b second nozzle row 31c third nozzle row 31d fourth nozzle row 32 ejection operation section 32a 1 operation part 32b 2nd operation part 32c 3rd operation part 32d 4th operation part 33 drive pulse generation part 33a 1st drive pulse generation part 33b 2nd drive pulse generation part 33c 3rd drive pulse generation part 33d 4th drive pulse generation Unit 331 shift register 332 latch circuit 333 waveform selection unit 333a counter 333b output pattern register 334 buffer amplifier 34 delay unit 34a first delay unit 34b second delay unit 34c third delay unit 340a, 340b disconnection paths 341a, 343a, 341b, 343b resistance Child 342a, 342b capacitors 344a, 344b buffers 345a, 345b fuses 346a, 347a, 346b, 347b diode 349a functional element 501 resistance element 502 LED
503 switching elements PLSTIM0 to PLSTIM2 drive signal SI pixel data STB-1 to STB-3 nozzle group selection signal

Claims (10)

A drive circuit for outputting an operation signal for driving each of the predetermined number of loads for ejecting ink from a predetermined number of two or more nozzles,
An output circuit that generates and outputs an operation signal for each of the predetermined number of loads,
A delay circuit for delaying the output timing of the predetermined number of operation signals to a plurality of different timings;
A delay setting element that switches the setting related to the presence or absence of the delay operation in the delay circuit by being irreversibly invalidated;
A setting circuit for transmitting a setting signal for disabling the delay setting element,
A drive circuit comprising:   2. The setting circuit has an input end portion for inputting an input signal from the outside, and disables the delay setting element according to a predetermined input signal from the input end portion. Drive circuit.   3. The drive circuit according to claim 1, wherein the setting circuit is formed so as to be able to detect whether or not the delay setting element is invalid by inputting a predetermined inspection signal.   3. The drive circuit according to claim 1, further comprising a detection circuit for detecting whether or not the delay setting element is invalid.   The detection circuit is provided with a notification operation unit that performs a predetermined notification operation according to at least one of whether the delay setting element is invalid when a predetermined inspection signal is input. The drive circuit according to claim 4. The output circuit, a drive waveform input unit for acquiring a plurality of drive waveform data in time series,
A waveform selection unit that selects any one of the plurality of acquired drive waveform data according to ink ejection data;
An operation signal generation unit that converts the selected waveform into an analog signal corresponding to each of the waveforms and outputs the operation signal as an operation signal,
Equipped with
The delay circuit delays the input timing of the drive waveform data acquired by the drive waveform input section, thereby delaying the output timing of the operation signal output from the operation signal generation section. Item 6. The drive circuit according to any one of items 1 to 5.   The delay setting element is a separation element that does not perform the delay operation by disconnecting a part of the delay circuit by being cut off, and the delay setting element is delayed according to the setting signal input to the setting circuit. 7. The drive circuit according to claim 1, wherein the setting element is cut off. The delay circuit is an RC circuit,
8. The driving circuit according to claim 7, wherein the separation element separates the capacitor from the RC circuit by being cut. The predetermined number of loads each belong to one of a plurality of blocks,
9. The drive circuit according to claim 1, wherein the delay circuit makes the output timings different from each other among the plurality of blocks. The drive circuit according to any one of claims 1 to 9,
A recording unit having a plurality of loads driven by receiving the operation signals respectively output from the drive circuits, and a plurality of nozzles ejecting ink by the operation of the loads,
An inkjet recording apparatus comprising:

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