JP6680503B2 - ESD protection circuit - Google Patents

Description

  The present invention relates to an ESD protection circuit for preventing malfunction of an integrated circuit or destruction of a circuit element due to electrostatic discharge (ESD: Electro-Static Discharge), and for example, an ESD protection applied to an integrated circuit requiring high bandwidth characteristics. Regarding the circuit.

  Generally, a circuit element such as a transistor or a capacitor forming an integrated circuit (IC: Integrated Circuit) formed on a semiconductor substrate has a withstand voltage of about several V to several tens of V. On the other hand, the voltage instantaneously applied by ESD may be several hundreds V or more. Therefore, in order to prevent malfunction of the integrated circuit and dielectric breakdown of the circuit element, an ESD protection circuit is generally required.

A conventional ESD protection circuit is disclosed in Non-Patent Document 1, for example.
FIG. 15 is a diagram showing a configuration of a conventional ESD protection circuit.
The ESD protection circuit 91 shown in FIG. 15 is, for example, a circuit for protecting the grounded-emitter amplifier circuit 92 including a transistor Q1 and resistors R1 and R2 as an internal circuit.

  For example, in FIG. 15, when a large positive (+) voltage is applied to the input terminal PIN by ESD, the ESD protection circuit 91 causes the amplifier circuit to flow a current to the power supply terminal VCC through the diode Da. Protect 92. On the other hand, when a large negative (-) voltage is applied to the input terminal PIN by ESD, the ESD protection circuit 91 protects the amplifier circuit 92 by supplying a current to the power supply terminal VEE via the diode Db. .

JP, 2007-174440, A

Behzad Razavi, Translated by Tadahiro Kuroda, “Design and Application of Analog CMOS Integrated Circuits”, 9th edition, pp. 806-807.

  By the way, an amplifier circuit for processing a high-speed signal represented by a receiving amplifier used in an optical communication system or a wireless communication system which exceeds 10 Gbit / s is required to have a wide band characteristic.

  However, as shown in FIG. 15, when the ESD protection circuit 91 including the diodes Da and Db is connected to the input terminal PIN of the amplifier circuit 92, the band of the amplifier circuit 92 is rate-limited by the capacitive load of the two diodes Da and Db. Will be done.

  Therefore, when the conventional ESD protection circuit is connected to the amplifier circuit that processes high-speed signals as described above, there is a problem that the signal pass band of the amplifier circuit is lowered and it is difficult to widen the band of the amplifier.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an ESD protection circuit with a small capacitive load.

An ESD protection circuit according to the present invention includes an amplifier circuit including an NPN bipolar transistor having a base electrode connected to an external terminal, an anode connected to an emitter electrode of the bipolar transistor, and a cathode having a higher potential than the emitter electrode. A first diode connected to a first fixed potential and connected in reverse bias between the first fixed potential and the emitter electrode; and a second diode whose anode has a lower potential than the base electrode of the bipolar transistor. A second diode connected to a fixed potential, a cathode connected to the base electrode, and a second diode connected in reverse bias between the base electrode and the second fixed potential; The bipolar transistor is connected between the collector electrode of the bipolar transistor and the first fixed potential. A first load, and a second load connected between the emitter electrode of the bipolar transistor and the second fixed potential, amplifying a signal input from the external terminal to output from the collector electrode of the bipolar transistor. It is a circuit for taking out .

  In the above description, as an example, the constituent elements in the drawings corresponding to the constituent elements of the invention are represented by reference numerals in parentheses.

  According to the present invention, the first diode as one of the diodes for ESD protection is not directly connected to the external terminal of the amplifier circuit, but is connected to the external terminal via the PN junction of the bipolar transistor forming the amplifier circuit. Therefore, an ESD protection circuit with a small capacitive load can be realized.

FIG. 1 is a diagram showing a configuration of an integrated circuit including an ESD protection circuit according to the first embodiment. FIG. 2 is a diagram for explaining the operation of the ESD protection circuit according to the first embodiment. FIG. 3 is a diagram showing a gain frequency characteristic of the grounded-emitter amplifier circuit to which the ESD protection circuit according to the first embodiment is connected. FIG. 4 is a diagram showing another configuration of the integrated circuit including the ESD protection circuit according to the first embodiment. FIG. 5 is a diagram showing a configuration of an integrated circuit including the ESD protection circuit according to the second embodiment. FIG. 6 is a diagram for explaining the operation of the ESD protection circuit according to the second embodiment. FIG. 7 is a diagram showing a configuration of an integrated circuit including the ESD protection circuit according to the third embodiment. FIG. 8 is a diagram showing a configuration of an integrated circuit including the ESD protection circuit according to the fourth embodiment. FIG. 9 is a diagram showing the configuration of an integrated circuit including the ESD protection circuit according to the fifth embodiment. FIG. 10 is a diagram showing the configuration of an integrated circuit including the ESD protection circuit according to the sixth embodiment. FIG. 11 is a diagram for explaining the operation of the ESD protection circuit according to the sixth embodiment. FIG. 12 is a diagram showing the configuration of an integrated circuit including the ESD protection circuit according to the seventh embodiment. FIG. 13 is a diagram for explaining the operation of the ESD protection circuit according to the seventh embodiment. FIG. 14 is a diagram showing another configuration of the integrated circuit including the ESD protection circuit according to the seventh embodiment. FIG. 15 is a diagram showing a configuration of a conventional ESD protection circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<< Embodiment 1 >>
FIG. 1 is a diagram showing a configuration of an integrated circuit including an ESD protection circuit according to the first embodiment.
The integrated circuit 101 shown in FIG. 1 is, for example, a circuit forming a part of a receiving amplifier mounted in a receiving device such as an optical communication system or a wireless communication system.

  Here, the receiving amplifier is, for example, in a receiving device of an optical communication system, a current signal obtained by photo-current converting an optical signal sent from a transmission line (optical fiber) by a photodiode (PD) is used as a circuit in a subsequent stage. (For example, an analog-digital converter and a digital signal processor) linearly amplifying to a voltage amplitude at which the signal can be operated.

  The integrated circuit 101 is formed on one semiconductor substrate by, for example, a known HBT (Heterojunction Bipolar Transistor) manufacturing process. Specifically, the integrated circuit 101 has a plurality of external terminals, an amplifier circuit 21 as an internal circuit, and an ESD protection circuit 11. In FIG. 1, as an example of the external terminals included in the integrated circuit 101, power supply terminals VCC and VEE and an input terminal PIN are typically shown.

  The power supply terminals VCC and VEE are terminals for externally supplying power for driving the internal circuit (amplifier circuit 21).

The power supply terminal VCC is supplied with the voltage VCC as the first fixed potential, and the power supply terminal VEE is supplied with the voltage VEE as the second fixed potential. Here, VCC> VEE.
Hereinafter, inside the integrated circuit 101, a signal line connected to the power supply terminal VCC is referred to as a power supply line VCC, and a signal line connected to the power supply terminal VEE is referred to as a power supply line VEE.

  The input terminal PIN is a terminal to which a signal to be amplified is supplied.

The amplifier circuit 21 constitutes, for example, a first-stage amplifier circuit in the reception amplifier.
Specifically, the amplifier circuit 21 is a grounded-emitter amplifier circuit, and includes an NPN-type bipolar transistor (hereinafter simply referred to as “transistor”) Q1 as a transistor for amplification, a resistor R1 as a load of the transistor Q1, R2 and.

  The base electrode of the transistor Q1 is connected to the input terminal PIN. The resistor R1 is connected between the collector electrode of the transistor Q1 and the power supply line VCC. The resistor R2 is connected between the emitter electrode of the transistor Q1 and the power supply line VEE.

  According to the amplifier circuit 21, the signal input to the input terminal PIN is amplified and output from the collector electrode of the transistor Q1.

  The ESD protection circuit 11 is a circuit for preventing malfunction of the amplifier circuit 21 due to ESD and destruction of circuit elements due to ESD. The ESD protection circuit 11 is composed of diodes D1 and D2 for ESD protection and a transistor Q1 that constitutes the amplifier circuit 21.

  The diode D1 is connected between the emitter electrode of the transistor Q1 and the power supply line VCC. Specifically, the anode of the diode D1 is connected to the emitter electrode of the transistor Q1 and the cathode of the diode D1 is connected to the power supply line VCC.

  That is, the direction of the PN junction of the diode D1 is made the same as the direction of the PN junction inside the transistor Q1. Specifically, the PN junction inside the transistor Q1 and the PN junction of the diode D1 are connected in series so as to be in the forward direction with respect to the current path from the input terminal PIN to the power supply line VCC. More specifically, in order from the input terminal PIN, the base electrode (P electrode) of the transistor Q1, the emitter electrode (N electrode) of the transistor Q1, the anode (P electrode) of the diode D1, and the cathode (N electrode) of the diode D1. The diode D1 is arranged between the emitter electrode of the transistor Q1 and the power supply line VCC so that a current path reaching the power supply line VCC is formed.

  The diode D2 is connected between the base electrode of the transistor Q1 and the power supply line VEE. Specifically, the anode of the diode D2 is connected to the power supply line VEE, and the cathode of the diode D2 is connected to the base electrode of the transistor Q1.

FIG. 2 is a diagram for explaining the operation of the ESD protection circuit 11 according to the first embodiment.
For example, when a negative (-) large voltage (<< VEE) is applied to the input terminal PIN, as indicated by reference numeral 201, from the power supply terminal VEE to the input terminal PIN via the diode D2. When the current flows in, the internal circuit (amplifier circuit 21) is protected.

  On the other hand, when a positive (+) large voltage (>> VCC) is applied to the input terminal PIN, a PN junction between the input terminal PIN and the base-emitter of the transistor Q1 is applied, as indicated by reference numeral 202. The current flows into the power supply terminal VCC via the diode D1 and the diode D1 to protect the internal circuit (amplifier circuit 21).

  FIG. 3 is a diagram showing a gain frequency characteristic of the grounded-emitter amplifier circuit 21 to which the ESD protection circuit 11 according to the first embodiment is connected.

  In the figure, the vertical axis represents the gain, and the horizontal axis represents the frequency. Further, in FIG. 1, reference numeral 301 is a simulation result of the frequency characteristic of the gain of the amplifier circuit 21 to which the ESD protection circuit 11 according to the first embodiment is connected, and reference numeral 302 is the conventional result shown in FIG. It is a simulation result of the frequency characteristic of the gain of the amplifier circuit 92 to which the ESD protection circuit 91 is connected.

  As understood from FIG. 3, the amplification circuit 21 to which the ESD protection circuit 11 according to the first embodiment is connected has a wider band than the amplification circuit 92 to which the conventional ESD protection circuit 91 is connected. The reason for this is as follows.

  The ESD protection circuit 11 according to the first embodiment does not directly connect the ESD protection diode D1 for releasing charges from the input terminal PIN to the power supply terminal VCC side, but configures the amplification circuit 21. Since the transistor Q1 is connected to the input terminal PIN through the PN junction between the base and the emitter of the transistor Q1, the capacitive load added to the input terminal PIN is smaller than that of the conventional ESD protection circuit 91. As a result, the amplification circuit 21 has a wider band than the conventional amplification circuit 92.

  Since the diode D1 is connected to the emitter electrode of the transistor Q1, the capacitive load added to the emitter electrode of the transistor Q1 increases, but the amplifier circuit 21 is supplied from the input terminal PIN to the base electrode of the transistor Q1. Since this is a circuit that amplifies the signal and extracts it from the collector electrode of the transistor Q1, even if the capacitive load of the emitter electrode of the transistor Q1 increases, the band of the amplifier circuit 21 is not adversely affected.

  As described above, according to the ESD protection circuit of the present invention, one ESD protection diode is not directly connected to the external terminal of the amplifier circuit, but is connected to the external terminal of the bipolar transistor forming the amplifier circuit. By connecting to another electrode of the bipolar transistor that forms a PN junction between the external terminal of the amplifier circuit and the external terminal of the amplifier circuit by connecting the ESD protection circuit as compared with the conventional ESD protection circuit. The capacity load can be reduced.

  Specifically, as in the ESD protection circuit 11 shown in FIG. 1, an ESD protection diode D1 is provided via a PN junction between the base and emitter of a transistor Q1 that constitutes an amplification circuit 21 that is an ESD protection target. By connecting to the input terminal PIN, the capacitive load on the input stage of the amplifier circuit 21 can be reduced as compared with the conventional case. As a result, the band of the amplifier circuit 21 can be widened.

  In the above embodiment, the case where the ESD protection circuit 11 is applied to the grounded-emitter amplifier circuit including NPN-type bipolar transistors has been described as an example. However, the present invention is not limited to this, and the common-emitter type PNP-type bipolar transistor is used. The same can be applied to the amplifier circuit of. The details will be described below with reference to the drawings.

FIG. 4 is a diagram showing another configuration of the integrated circuit including the ESD protection circuit according to the first embodiment.
The integrated circuit 101A shown in the figure has a grounded-emitter amplifier circuit 21A using a PNP-type bipolar transistor Q1A instead of the grounded-emitter amplifier circuit 21 using an NPN-type bipolar transistor Q1. An ESD protection circuit 11A is provided instead of the protection circuit 11.

In the ESD protection circuit 11A, the diode D2A is connected between the base electrode of the transistor Q1A and the power supply line VCC. Specifically, the anode of the diode D1 is connected to the base electrode of the transistor Q1A , and the cathode of the diode D1 is connected to the power supply line VCC.

  In the ESD protection circuit 11A, the diode D1A is connected between the emitter electrode of the transistor Q1A and the power supply line VEE. Specifically, the anode of the diode D1A is connected to the power supply line VEE, and the cathode of the diode D1A is connected to the emitter electrode of the transistor Q1A.

  According to the ESD protection circuit 11A shown in FIG. 4, similar to the ESD protection circuit 11 shown in FIG. 1, it is possible to reduce the capacitive load on the input terminal PIN of the amplifier circuit including NPN bipolar transistors. It becomes possible to widen the band of the amplifier circuit as compared with the above.

<< Embodiment 2 >>
FIG. 5 is a diagram showing a configuration of an integrated circuit including the ESD protection circuit according to the second embodiment.
The ESD protection circuit 12 shown in the figure differs from the ESD protection circuit 11 according to the first embodiment in that a diode D3 for ESD protection is further provided, while in other respects the ESD protection circuit according to the first embodiment is different. It is similar to the protection circuit 11.

  In the integrated circuit 102 including the ESD protection circuit 12 according to the second embodiment, the same components as those of the integrated circuit 101 including the ESD protection circuit 11 according to the first embodiment are designated by the same reference numerals, Detailed description thereof will be omitted.

  As shown in FIG. 5, the ESD protection circuit 12 is connected between the input terminal PIN and the power supply line VCC in addition to the ESD protection diodes D1 and D2 and the transistor Q1 that constitutes the amplifier circuit 21. A diode D3 for ESD protection is provided.

  The anode of the diode D3 is connected to the input terminal PIN, and the cathode of the diode D3 is connected to the power supply line VCC.

FIG. 6 is a diagram for explaining the operation of the ESD protection circuit 12 according to the second embodiment.
For example, when a negative (−) large voltage (<< VEE) is applied to the input terminal PIN, a current is generated through the path indicated by reference numeral 201, as in the ESD protection circuit 11 according to the first embodiment. By flowing, the internal circuit (amplifier circuit 21) is protected.

On the other hand, when a positive (+) large voltage (>> VCC) is applied to the input terminal PIN, a current flows through the path indicated by reference numeral 202, as in the ESD protection circuit 11 according to the first embodiment. In addition to flowing, a current flows from the input terminal PIN to the power supply terminal VCC via the diode D3 as indicated by reference numeral 203.
In this way, when a large positive voltage is applied to the input terminal PIN, a current flows through the path indicated by reference numeral 202 and the path indicated by reference numeral 203, so that the internal circuit (amplifier circuit 21) is protected.

  As described above, according to the ESD protection circuit 12 according to the second embodiment, since the ESD protection diode D3 is further connected between the input terminal PIN and the power supply line VCC, a large positive voltage is applied to the input terminal PIN. The ESD resistance when applied can be further increased. This ESD protection circuit is particularly effective when the ESD allowable current required for the PN junction between the base and emitter of the transistor Q1 cannot flow.

  In the ESD protection circuit 12 according to the second embodiment, the addition of the diode D3 increases the capacitive load on the input terminal PIN as compared with the ESD protection circuit 11 according to the first embodiment. However, as described above, since the ESD protection circuit 12 has a structure in which the ESD allowable current is secured by the two current paths 202 and 203, the added diode D3 is larger than the diode Da in the conventional ESD protection circuit 91. The current capacity may be small.

  That is, in the ESD protection circuit 12, the size of the diode D3 (the area of the PN junction) can be made smaller than that of the diode Da in the conventional ESD protection circuit 91. Therefore, the capacitive load added to the input terminal PIN is The size is smaller than that of the ESD protection circuit 91, and the band of the amplifier circuit 21 can be widened as compared with the conventional one.

<< Embodiment 3 >>
FIG. 7 is a diagram showing a configuration of an integrated circuit including the ESD protection circuit according to the third embodiment.
The ESD protection circuit 13 shown in the figure is different from the ESD protection circuit 11 according to the first embodiment in that the amplifier circuit to be ESD protected is a collector-grounded amplifier circuit.

  In the integrated circuit 103 including the ESD protection circuit 13 according to the third embodiment, the same components as those of the integrated circuit 101 including the ESD protection circuit 11 according to the first embodiment are designated by the same reference numerals, Detailed description thereof will be omitted.

  As shown in FIG. 7, the amplifier circuit 22 is a collector-grounded amplifier circuit (emitter follower circuit). Specifically, the amplifier circuit 22 includes a transistor Q1 as an amplifying transistor, a resistor R1 and a current source I0 as a load of the transistor Q1.

  The base electrode of the transistor Q1 is connected to the input terminal PIN. The resistor R1 is connected between the collector electrode of the transistor Q1 and the power supply line VCC. The current source IO is connected between the emitter electrode of the transistor Q1 and the power supply line VEE.

According to the amplifier circuit 22 described above, the signal input to the input terminal PIN is amplified and output from the emitter electrode of the transistor Q1.

  The ESD protection circuit 13 is composed of diodes D1 and D2 for ESD protection and a transistor Q1 that constitutes the amplifier circuit 22.

  The diode D1 is connected between the collector electrode of the transistor Q1 and the power supply line VCC. Specifically, the anode of the diode D1 is connected to the collector electrode of the transistor Q1, and the cathode of the diode D1 is connected to the power supply line VCC. The connection destination of the diode D2 is the same as that of the ESD protection circuit 11.

  In the integrated circuit 103, for example, when a negative (−) large voltage (<< VEE) is applied to the input terminal PIN, a current flows from the power supply terminal VEE to the input terminal PIN via the diode D2. Thus, the internal circuit (amplifier circuit 22) is protected.

  On the other hand, when a positive (+) large voltage (>> VCC) is applied to the input terminal PIN, the power terminal is supplied from the input terminal PIN via the base-collector PN junction of the transistor Q1 and the diode D1. The internal circuit (amplifier circuit 22) is protected by the current flowing into VCC.

  As described above, according to the ESD protection circuit 13 according to the third embodiment, the ESD protection diode D1 is input via the PN junction between the base and collector of the transistor Q1 that constitutes the amplification circuit 22 that is the ESD protection target. Since it is connected to the terminal PIN, like the ESD protection circuit 11 according to the first embodiment, it is possible to reduce the capacitive load on the input terminal PIN of the amplifier circuit 22 by connecting the ESD protection circuit 13, and the amplifier circuit. A wide band of 22 is possible.

  Since the diode D1 is connected to the collector electrode of the transistor Q1, the capacitance load applied to the collector electrode of the transistor Q1 increases, but the amplifier circuit 22 is supplied from the input terminal PIN to the base electrode of the transistor Q1. Since this is an emitter follower circuit that amplifies a signal and extracts it from the emitter electrode of the transistor Q1, even if the capacitive load on the collector electrode side of the transistor Q1 increases, the band of the amplifier circuit 22 is not adversely affected.

<< Embodiment 4 >>
FIG. 8 is a diagram showing a configuration of an integrated circuit including the ESD protection circuit according to the fourth embodiment.
This is different from the ESD protection circuit 11 according to the first embodiment in that the amplifier circuit to be protected by the ESD protection circuit 14 shown in the figure is a grounded base amplifier circuit.

  In the integrated circuit 104 including the ESD protection circuit 14 according to the fourth embodiment, the same components as those of the integrated circuit 101 including the ESD protection circuit 11 according to the first embodiment are designated by the same reference numerals, Detailed description thereof will be omitted.

  As shown in FIG. 8, the amplifier circuit 23 is a grounded base amplifier circuit. Specifically, the amplifier circuit 23 includes a transistor Q1 as an amplifying transistor, and a resistor R1 and an NPN-type transistor Q2 as a load of the transistor Q1.

  The emitter electrode of the transistor Q1 is connected to the input terminal PIN. The bias voltage Vb1 is supplied to the base electrode of the transistor Q1. The emitter electrode of the transistor Q2 is connected to the power supply line VEE, and the collector electrode of the transistor Q2 is connected to the emitter electrode of the transistor Q1 and the input terminal PIN. The bias voltage Vb2 is supplied to the base electrode of the transistor Q2. Here, for example, Vb2 <Vb1. The resistor R1 is connected between the collector electrode of the transistor Q1 and the power supply line VCC.

  According to the amplifier circuit 23, the signal input to the input terminal PIN is amplified and output from the collector electrode of the transistor Q1.

  The ESD protection circuit 14 is composed of diodes D1 and D2 for ESD protection and a transistor Q1 that constitutes the amplifier circuit 23.

  The diode D1 is connected between the base electrode of the transistor Q1 and the power supply line VEE. Specifically, the anode of the diode D1 is connected to the power supply line VEE, and the cathode of the diode D1 is connected to the base electrode of the transistor Q1.

  The diode D2 is connected between the emitter electrode of the transistor Q1 and the power supply line VCC. Specifically, the anode of the diode D2 is connected to the emitter electrode of the transistor Q1 and the input terminal PIN, and the cathode of the diode D2 is connected to the power supply line VCC.

  In the integrated circuit 104, for example, when a positive (+) large voltage (>> VCC) is applied to the input terminal PIN, a current flows from the input terminal PIN to the power supply terminal VCC via the diode D2. , The internal circuit (amplifier circuit 23) is protected.

  On the other hand, when a large negative (-) voltage (<< VEE) is applied to the input terminal PIN, the power supply terminal VEE passes through the diode D1 and the base-emitter PN junction of the transistor Q1. The current flows into the input terminal PIN, so that the internal circuit (amplifier circuit 23) is protected.

  As described above, according to the ESD protection circuit 14 of the fourth embodiment, the ESD protection diode D1 is input via the PN junction between the base and the emitter of the transistor Q1 that constitutes the amplification circuit 23 that is the ESD protection target. Since it is connected to the terminal PIN, similar to the ESD protection circuit 11 according to the first embodiment, it is possible to reduce the capacitive load on the input terminal PIN of the amplifier circuit 23 by connecting the ESD protection circuit, and the amplifier circuit 23. It becomes possible to widen the band.

  Since the diode D1 is connected to the base electrode of the transistor Q1, the capacitive load added to the base electrode of the transistor Q1 increases, but the amplifier circuit 23 is supplied from the input terminal PIN to the emitter electrode of the transistor Q1. Since it is a circuit that amplifies the signal and extracts it from the collector electrode of the transistor Q1, even if the capacitive load on the base electrode side of the transistor Q1 increases, the band of the amplifier circuit 23 is not adversely affected.

<< Fifth Embodiment >>
FIG. 9 is a diagram showing the configuration of an integrated circuit including the ESD protection circuit according to the fifth embodiment.
The ESD protection circuit 15 shown in the figure is different from the ESD protection circuit 14 according to the fourth embodiment in that the diode D1 for ESD protection is connected to the base electrode of the transistor Q2, while the other points are implemented. This is similar to the ESD protection circuit according to mode 4.

  In the integrated circuit 105 including the ESD protection circuit 15 according to the fifth embodiment, the same components as those of the integrated circuit 104 including the ESD protection circuit 14 according to the fourth embodiment are designated by the same reference numerals, Detailed description thereof will be omitted.

  The ESD protection circuit 15 is composed of diodes D1 and D2 for ESD protection and a transistor Q2 that constitutes the amplifier circuit 23.

  As shown in FIG. 9, the diode D1 is connected between the base electrode of the transistor Q2 and the power supply line VEE. Specifically, the anode of the diode D1 is connected to the power supply line VEE, and the cathode of the diode D1 is connected to the base electrode of the transistor Q2. The connection destination of the diode D2 is the same as that of the ESD protection circuit 14 according to the fourth embodiment.

  In the integrated circuit 105, for example, when a positive (+) large voltage (>> VCC) is applied to the input terminal PIN, a current flows from the input terminal PIN to the power supply terminal VCC via the diode D2. , The internal circuit (amplifier circuit 23) is protected.

  On the other hand, when a large negative (-) voltage (<< VEE) is applied to the input terminal PIN, the power supply terminal VEE passes through the diode D1 and the PN junction between the base and collector of the transistor Q2. The current flows into the input terminal PIN, so that the internal circuit (amplifier circuit 23) is protected.

  As described above, according to the ESD protection circuit 15 according to the fifth embodiment, the ESD protection diode D1 is input via the PN junction between the base and collector of the transistor Q2 that constitutes the amplification circuit 23 that is the ESD protection target. Since it is connected to the terminal PIN, similar to the ESD protection circuit 14 according to the first embodiment, it is possible to reduce the capacitive load on the input terminal PIN of the amplification circuit 23 by connecting the ESD protection circuit, and the amplification circuit 23. Can be made wider.

<< Sixth Embodiment >>
FIG. 10 is a diagram showing the configuration of an integrated circuit including the ESD protection circuit according to the sixth embodiment.
The ESD protection circuit 16 shown in the figure differs from the ESD protection circuit 11 according to the first embodiment in that the amplification protection target amplification circuit is an amplification circuit including a transistor for DC bias adjustment of an amplification transistor. .

  In the integrated circuit 106 including the ESD protection circuit 16 according to the sixth embodiment, the same components as those of the integrated circuit 101 including the ESD protection circuit 11 according to the first embodiment are designated by the same reference numerals, Detailed description thereof will be omitted.

  As shown in FIG. 10, the amplifier circuit 24 further includes an NPN transistor Q2 for DC bias adjustment in addition to the circuit elements of the amplifier circuit 21.

  The emitter electrode of the transistor Q2 is connected to the power supply line VEE, and the collector electrode of the transistor Q2 is connected to the base electrode of the transistor Q1 and the input terminal PIN. The bias voltage Vb2 is supplied to the base electrode of the transistor Q2.

  According to the amplifier circuit 24 described above, a current is bypassed from the transistor Q2 to the power supply line VEE in response to the input signal input to the input terminal PIN, so that the base potential of the transistor Q1 increases according to the input signal. It is possible to prevent the dynamic range from being limited (see Patent Document 1).

  The ESD protection circuit 16 is composed of diodes D1 and D2 for ESD protection and transistors Q1 and Q2 that form the amplifier circuit 24.

  The diode D1 is connected between the base electrode of the transistor Q2 and the power supply line VEE. Specifically, the anode of the diode D1 is connected to the power supply line VEE, and the cathode of the diode D1 is connected to the base electrode of the transistor Q2.

  The diode D2 is connected between the emitter electrode of the transistor Q1 and the power supply line VCC. Specifically, the anode of the diode D2 is connected to the emitter electrode of the transistor Q1, and the cathode of the diode D2 is connected to the power supply line VCC.

FIG. 11 is a diagram for explaining the operation of the ESD protection circuit according to the sixth embodiment.
In the integrated circuit 106, for example, when a negative (−) large voltage (<< VEE) is applied to the input terminal PIN, as indicated by reference numeral 301, from the power supply terminal VEE, the diode D1 and the transistor The current flows into the input terminal PIN via the PN junction between the base and collector of Q2, and the internal circuit (amplifier circuit 24) is protected.

  On the other hand, when a positive (+) large voltage (>> VCC) is applied to the input terminal PIN, a PN junction between the base and emitter of the transistor Q1 is formed from the input terminal PIN, as indicated by reference numeral 302. The internal circuit (amplifier circuit 24) is protected by the current flowing into the power supply terminal VCC via the diode D2.

  As described above, according to the ESD protection circuit 16 of the sixth embodiment, one diode D2 is connected to the base of the transistor Q1 with respect to the amplification circuit 24 including the transistor Q2 for adjusting the DC bias of the amplification transistor Q1. Since it is connected to the input terminal PIN via the PN junction between the emitters and the other diode D1 is connected to the input terminal PIN via the PN junction between the base and collector of the transistor Q2, the first embodiment is described. Similar to the ESD protection circuit 11, the capacitive load on the input terminal PIN of the amplifier circuit 24 due to the connection of the ESD protection circuit can be reduced, and the bandwidth of the amplifier circuit 24 can be widened.

<< Embodiment 7 >>
FIG. 12 is a diagram showing the configuration of an integrated circuit including the ESD protection circuit according to the seventh embodiment.
The ESD protection circuit 17 shown in the figure is different from the ESD protection circuit 11 according to the first embodiment in that it is connected to the output terminal of the amplification circuit to be ESD protected.

  Note that in FIG. 12, power supply terminals VCC and VEE and an output terminal POUT are typically shown as external terminals of the integrated circuit 107.

  The amplifier circuit 31 constitutes, for example, a final disconnection amplifier circuit in the reception amplifier. Specifically, the amplifier circuit 31 is a grounded-emitter amplifier circuit, and includes an NPN transistor Q4 as an amplifying transistor, an NPN transistor Q3 as a load of the transistor Q4, and resistors R3 and R4.

  A signal to be amplified is input to the base electrode of the transistor Q4. The emitter electrode of the transistor Q4 is connected to the power supply line VEE via the resistor R4. The collector electrode of the transistor Q4 is connected to the emitter electrode of the transistor Q3.

  The bias voltage Vb3 is supplied to the base electrode of the transistor Q3. The collector electrode of the transistor Q3 is connected to the output terminal POUT and also connected to the power supply line VCC via the resistor R3.

  According to the amplifier circuit 31, the signal input to the base electrode of the transistor Q4 is amplified and output from the collector electrode of the transistor Q3.

  The ESD protection circuit 17 is a circuit for preventing malfunction of the amplifier circuit 31 and destruction of circuit elements due to ESD. The ESD protection circuit 17 is composed of diodes D1 and D2 for ESD protection and a transistor Q3 that constitutes the amplifier circuit 31.

  The diode D1 is connected between the base electrode of the transistor Q3 and the power supply line VEE. Specifically, the anode of the diode D1 is connected to the power supply line VEE, and the cathode of the diode D1 is connected to the base electrode of the transistor Q3.

  The diode D2 is connected between the collector electrode of the transistor Q3 and the power supply line VCC. Specifically, the anode of the diode D2 is connected to the collector electrode of the transistor Q1 and the output terminal POUT, and the cathode of the diode D2 is connected to the power supply line VCC.

FIG. 13 is a diagram for explaining the operation of the ESD protection circuit 17 according to the seventh embodiment.
For example, when a negative (−) large voltage (<< VEE) is applied to the output terminal POUT, the diode D1 and the base-collector of the transistor Q3 are connected from the power supply terminal VEE as indicated by reference numeral 401. The internal circuit (amplifier circuit 31) is protected by the current flowing into the output terminal POUT via the PN junction between them.

  On the other hand, when a positive (+) large voltage (>> VCC) is applied to the output terminal POUT, as indicated by reference numeral 402, from the output terminal POUT to the power supply terminal VCC via the diode D2. The flow of current protects the internal circuit (amplifier circuit 31).

  As described above, according to the ESD protection circuit 17 according to the seventh embodiment, one ESD protection diode D1 is connected to the input terminal via the PN junction between the base and collector of the transistor Q3 that constitutes the output stage amplification circuit 31. Since it is connected to the PIN, similar to the ESD protection circuit 11 according to the first embodiment, it is possible to reduce the capacitive load of the output terminal POUT of the amplification circuit 31 due to the connection of the ESD protection circuit. Broadband can be achieved.

  Since the diode D1 is connected to the base electrode of the transistor Q3, the capacitive load added to the base electrode of the transistor Q3 increases, but the amplifier circuit 31 amplifies the signal supplied to the base electrode of the transistor Q4. Therefore, even if the capacitive load on the base electrode of the transistor Q3 increases, the band of the amplifier circuit 31 is not adversely affected.

  In the above embodiments, the case where the ESD protection circuit 17 is applied to the amplifier circuit 31 formed of the NPN type bipolar transistor has been described as an example. However, the present invention is not limited to this, and is also applicable to the amplifier circuit formed of the PNP type bipolar transistor. It can be applied similarly. The details will be described below with reference to the drawings.

  FIG. 14 is a diagram showing another configuration of the integrated circuit including the ESD protection circuit according to the seventh embodiment. In the integrated circuit 107A shown in the figure, a grounded-emitter amplifier circuit 31A using PNP-type bipolar transistors Q3A and Q4A is used in place of the grounded-emitter amplifier circuit 31 using NPN-type bipolar transistors Q3 and Q4. And has an ESD protection circuit 17A instead of the ESD protection circuit 17.

  In the ESD protection circuit 17A, the diode D1A is connected between the base electrode of the transistor Q3A and the power supply line VCC. Specifically, the anode of the diode D1A is connected to the base electrode of the transistor Q3A, and the cathode of the diode D1A is connected to the power supply line VCC.

  In the ESD protection circuit 17A, the diode D2A is connected between the collector electrode of the transistor Q3A and the power supply line VEE. Specifically, the anode of the diode D2A is connected to the power supply line VEE, and the cathode of the diode D2A is connected to the collector electrode of the transistor Q3A and the output terminal POUT.

  According to the ESD protection circuit 17A shown in FIG. 14, similarly to the ESD protection circuit 17 shown in FIG. 12, the capacitive load of the output terminal POUT of the amplifier circuit 31A composed of the PNP type bipolar transistor can be reduced. The band of the amplifier circuit can be widened as compared with the conventional one.

  Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited thereto and needless to say, various modifications can be made without departing from the gist thereof. Yes.

  For example, in the second to sixth embodiments, the case where the ESD protection circuit according to the present invention is applied to the amplifier circuit including the NPN type transistor has been described as an example, but as shown in the first and seventh embodiments. The ESD protection circuit according to the present invention can also be applied to the case where the amplifier circuit is composed of PNP type transistors.

  Specifically, in the second to sixth embodiments, for example, VCC <VEE is set, the transistors Q1 and Q2 are replaced with PNP-type bipolar transistors, and the connection directions of the diodes D1, D2, and D3 that configure each ESD protection circuit are set. By reversing the above, the capacitive load added to the input terminal PIN can be similarly reduced in the amplifier circuit including the PNP type transistor.

  Further, although cases have been described with the above embodiment as examples where the ESD protection circuit according to the present invention is applied to an amplification circuit in a reception amplifier used in an optical communication system or a wireless communication system, the present invention is not limited to this. For example, in the case of an integrated circuit in which any electrode of a bipolar transistor formed on a semiconductor substrate is connected to an external terminal, a diode for ESD protection is provided through a PN junction of the bipolar transistor in the same manner as above. By connecting the external terminals to the external terminals, the capacitive load added to the external terminals can be reduced.

  101-107, 101A, 107A ... Integrated circuits, 11-17 ... ESD protection circuits, 21-24, 31 ... Amplification circuits, Q1, Q2, Q3, Q4, Q1A, Q3A, Q4A ... Transistors, R1, R2, R3 R4 ... Resistor, D1, D2, D3, D1A, D2A ... Diode, VCC, VEE ... Power supply terminal, PIN ... Input terminal, POUT ... Output terminal.

Claims (9)

An amplifier circuit including an NPN bipolar transistor whose base electrode is connected to an external terminal;
An anode is connected to an emitter electrode of the bipolar transistor, a cathode is connected to a first fixed potential higher than the emitter electrode, and a reverse bias is connected between the first fixed potential and the emitter electrode. A first diode ,
An anode is connected to a second fixed potential that is lower than the base electrode of the bipolar transistor, a cathode is connected to the base electrode, and a reverse bias is connected between the base electrode and the second fixed potential. And a second diode that is
The amplifier circuit is
The bipolar transistor,
A first load connected between the collector electrode of the bipolar transistor and the first fixed potential;
A circuit that includes a second load connected between the emitter electrode of the bipolar transistor and the second fixed potential, amplifies a signal input from the external terminal, and extracts the signal from the collector electrode of the bipolar transistor. ESD protection circuit. An amplifier circuit including a PNP bipolar transistor whose base electrode is connected to an external terminal;
An anode is connected to a first fixed potential that is lower than the emitter electrode of the bipolar transistor, a cathode is connected to the emitter electrode, and a reverse bias is connected between the emitter electrode and the first fixed potential. A first diode ,
An anode is connected to the base electrode of the bipolar transistor, a cathode is connected to a second fixed potential higher than the base electrode, and a reverse bias is connected between the second fixed potential and the base electrode. And a second diode that is
The amplifier circuit is
The bipolar transistor,
A first load connected between the collector electrode of the bipolar transistor and the first fixed potential;
A circuit that includes a second load connected between the emitter electrode of the bipolar transistor and the second fixed potential, amplifies a signal input from the external terminal, and extracts the signal from the collector electrode of the bipolar transistor. ESD protection circuit. The ESD protection circuit according to claim 1 ,
An anode is connected to the base electrode of the bipolar transistor, a cathode is connected to the first fixed potential, and a third diode connected in reverse bias between the first fixed potential and the base electrode is further included. An ESD protection circuit having. An amplifier circuit including an NPN bipolar transistor whose base electrode is connected to an external terminal;
An anode is connected to the collector electrode of the bipolar transistor, a cathode is connected to a first fixed potential higher than the collector electrode, and a reverse bias is connected between the first fixed potential and the collector electrode. A first diode,
An anode is connected to a second fixed potential that is lower than the base electrode of the bipolar transistor, a cathode is connected to the base electrode, and a reverse bias is connected between the base electrode and the second fixed potential. And a second diode that is
The amplifier circuit is
The bipolar transistor,
A load connected between the collector electrode of the bipolar transistor and the first fixed potential,
A circuit that includes a current source connected between the emitter electrode of the bipolar transistor and the second fixed potential, amplifies a signal input from the external terminal, and extracts the signal from the emitter electrode of the bipolar transistor. Characteristic ESD protection circuit. A first bias voltage is supplied to the base electrode, an NPN type first bipolar transistor having an emitter electrode connected to an external terminal, and a second bias voltage is supplied to the base electrode, and a collector electrode is an emitter electrode of the first bipolar transistor. And an NPN-type second bipolar transistor having an emitter electrode connected to a first fixed potential lower than the base electrode supplied with the second bias voltage,
An anode is connected to the first fixed potential, a cathode is connected to the base electrode of the first bipolar transistor, and a reverse bias is connected between the base electrode of the first bipolar transistor and the first fixed potential. A first diode,
The anode is connected to the emitter electrode of the first bipolar transistor, the cathode is connected to a second fixed potential higher than the emitter electrode of the first bipolar transistor, the second fixed potential and the emitter of the first bipolar transistor. A second diode connected in reverse bias between the electrode and
The amplifier circuit is
The first bipolar transistor;
The second bipolar transistor;
A circuit that includes a load connected between the collector electrode of the first bipolar transistor and the second fixed potential, amplifies a signal input from the external terminal, and extracts the signal from the collector electrode of the first bipolar transistor. There is an ESD protection circuit. A first bias voltage is supplied to the base electrode, an NPN type first bipolar transistor having an emitter electrode connected to an external terminal, and a second bias voltage is supplied to the base electrode, and a collector electrode is an emitter electrode of the first bipolar transistor. And an NPN-type second bipolar transistor having an emitter electrode connected to a first fixed potential lower than the base electrode supplied with the second bias voltage,
An anode is connected to the first fixed potential, a cathode is connected to the base electrode of the second bipolar transistor, and a reverse bias is connected between the base electrode of the second bipolar transistor and the first fixed potential. A first diode,
The anode is connected to the emitter electrode of the first bipolar transistor, the cathode is connected to a second fixed potential higher than the emitter electrode of the first bipolar transistor, the second fixed potential and the emitter of the first bipolar transistor. A second diode connected in reverse bias between the electrode and
The amplifier circuit is
The first bipolar transistor;
The second bipolar transistor;
A circuit that includes a load connected between the collector electrode of the first bipolar transistor and the second fixed potential, amplifies a signal input from the external terminal, and extracts the signal from the collector electrode of the first bipolar transistor. There is an ESD protection circuit. An NPN first bipolar transistor having a base electrode connected to an external terminal, a bias voltage is supplied to the base electrode, a collector electrode is connected to the base electrode of the first bipolar transistor, and the base electrode supplied with the bias voltage An amplifier circuit including an NPN second bipolar transistor whose emitter electrode is connected to a first fixed potential lower than the above;
An anode is connected to the first fixed potential, a cathode is connected to the base electrode of the second bipolar transistor, and a reverse bias is connected between the base electrode of the second bipolar transistor and the first fixed potential. A first diode,
The anode is connected to the emitter electrode of the first bipolar transistor, the cathode is connected to a second fixed potential higher than the emitter electrode of the first bipolar transistor, the second fixed potential and the emitter of the first bipolar transistor. A second diode connected in reverse bias between the electrode and
The amplifier circuit is
The first bipolar transistor;
The second bipolar transistor;
A first load connected between the collector electrode of the first bipolar transistor and the second fixed potential;
A second load connected between the emitter electrode of the first bipolar transistor and the first fixed potential is amplified, and a signal input from the external terminal is amplified and taken out from the collector electrode of the first bipolar transistor. An ESD protection circuit, which is a circuit. It includes an NPN first bipolar transistor whose base electrode is connected to an external terminal, and an NPN second bipolar transistor whose base electrode is supplied with a bias voltage and whose emitter electrode is connected to the collector electrode of the first bipolar transistor. An amplifier circuit,
The anode is connected to a first fixed potential lower than the base electrode of the second bipolar transistor, the cathode is connected to the base electrode of the second bipolar transistor, the base electrode of the second bipolar transistor and the first fixed. A first diode connected in reverse bias between the potential and
The anode is connected to the collector electrode of the second bipolar transistor, the cathode is connected to a second fixed potential higher than the collector electrode of the second bipolar transistor, and the second fixed potential and the collector of the second bipolar transistor. A second diode connected in reverse bias between the electrode and
The amplifier circuit is
The first bipolar transistor;
The second bipolar transistor;
A first load connected between the collector electrode of the second bipolar transistor and the second fixed potential;
A second load connected between the emitter electrode of the first bipolar transistor and the first fixed potential is amplified, and a signal input from the external terminal is amplified and taken out from the collector electrode of the second bipolar transistor. An ESD protection circuit, which is a circuit. It includes a PNP first bipolar transistor whose base electrode is connected to an external terminal, and a PNP second bipolar transistor whose base electrode is supplied with a bias voltage and whose emitter electrode is connected to the collector electrode of the first bipolar transistor. An amplifier circuit,
The anode is connected to the base electrode of the second bipolar transistor, the cathode is connected to a first fixed potential higher than the base electrode of the second bipolar transistor, the first fixed potential and the base of the second bipolar transistor. A first diode connected in reverse bias between the electrodes,
The anode is connected to a second fixed potential lower than the collector electrode of the second bipolar transistor, the cathode is connected to the collector electrode of the second bipolar transistor, and the collector electrode of the second bipolar transistor and the second fixed A second diode connected so as to be reverse-biased with respect to the potential,
The amplifier circuit is
The first bipolar transistor;
The second bipolar transistor;
A first load connected between the collector electrode of the second bipolar transistor and the second fixed potential;
A second load connected between the emitter electrode of the first bipolar transistor and the first fixed potential is amplified, and a signal input from the external terminal is amplified and taken out from the collector electrode of the second bipolar transistor. An ESD protection circuit, which is a circuit.

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