JP6679337B2 - Charge pump - Google Patents

Description

  The present invention relates to a charge pump.

  In an IC equipped with a charge pump, its output voltage is generally determined by a reference voltage and a boosting ratio. For example, when setting the reference voltage and the boosting ratio according to a command sent from the host outside the IC, the set value instructed by the command is stored in a register inside the IC, and this is read and charged. It may be converted into an analog control signal for the pump.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2005-318787 A

  However, if an incorrect set value is stored in the register due to command misrecognition, or if the set value stored in the register changes due to disturbance noise, the output voltage of the charge pump will fall outside the normal range. However, there is a possibility that the IC may malfunction or be destroyed.

  In particular, in recent years, in-vehicle ICs have been required to comply with ISO26262 (international standard for functional safety related to electric / electronics of automobiles), and charge pumps also have reliability with fail-safe in mind. Sex design is important.

  In view of the above problems found by the inventor of the present application, the invention disclosed in this specification is a charge pump capable of keeping an output voltage within a normal range even if command misrecognition or garbled register occurs. The purpose is to provide.

  A charge pump disclosed in the present specification generates a first boosted voltage by boosting a first reference voltage according to a first set value by a first boosting ratio according to a second set value. A charge pump unit, a first boosted voltage calculation unit that receives the first set value and the second set value and calculates a first predicted voltage value corresponding to the first boosted voltage, and the first predicted voltage A configuration including a determination unit that determines whether or not the value is within a normal range, and an adjustment unit that adjusts at least one of the first set value and the second set value according to the determination result of the determination unit. (First configuration).

  The charge pump having the above-mentioned first configuration generates the second boosted voltage by boosting the second reference voltage corresponding to the third set value by the second boosting ratio corresponding to the fourth set value. A charge pump unit, a second boosted voltage calculation unit that receives the third set value and the fourth set value and calculates a second predicted voltage value corresponding to the second boosted voltage, and the first predicted voltage And a subtraction unit that calculates a differential voltage value between the second expected voltage value and the second expected voltage value, and the determination unit replaces the first expected voltage value with the differential voltage value within a normal range. It is preferable that the adjustment unit determines whether or not the adjustment unit adjusts at least one of the set values according to the determination result of the determination unit (second configuration).

  Further, in the charge pump having the second configuration, it is preferable that the first boosted voltage is a positive voltage and the second boosted voltage is a negative voltage (third configuration).

  In the charge pump having the second or third configuration, the first charge pump unit and the second charge pump unit are respectively synchronized with a flying capacitor, an output capacitor, a charge transfer transistor, and a clock signal. Then, one end of the flying capacitor may be pulse-driven and a control unit for turning on / off the charge transfer transistor may be included (fourth configuration).

  Further, in the charge pump having the above-mentioned fourth configuration, the first charge pump unit and the second charge pump unit each further include a DAC that converts a digital set value into an analog reference voltage (fifth configuration). Configuration) is recommended.

  Further, a semiconductor device disclosed in this specification includes a charge pump having any one of the first to fifth configurations, a register that stores each setting value of the charge pump, and a power supply from the charge pump. It is configured to integrate a load that receives and operates (sixth configuration).

  The semiconductor device having the sixth configuration may have a configuration (seventh configuration) in which a refresh unit that periodically rewrites each set value stored in the register is further integrated.

  Further, in the semiconductor device having the sixth or seventh configuration, the load may be a gate driver (eighth configuration) for driving a gate of an LCD [liquid crystal display] panel.

  Further, the liquid crystal display device disclosed in this specification is configured to have a semiconductor device having the above-described eighth configuration and an LCD panel driven by the semiconductor device (a ninth configuration). There is.

  Further, the vehicle disclosed in this specification is configured to have the liquid crystal display device having the ninth configuration (tenth configuration).

  According to the invention disclosed in this specification, it is possible to provide a charge pump that can keep an output voltage within a normal range even if command misrecognition or garbled register occurs.

Block diagram showing a configuration example of a liquid crystal display device Block diagram showing the first embodiment of the charge pump Circuit diagram showing one configuration example of the positive boost charge pump unit Circuit diagram showing an example of positive boost operation (first phase) Circuit diagram showing an example of positive boost operation (second phase) Circuit diagram showing one configuration example of the negative boosting charge pump unit Circuit diagram showing an example of negative boosting operation (first phase) Circuit diagram showing an example of negative boosting operation (2nd phase) Block diagram showing a second embodiment of the charge pump Block diagram showing a third embodiment of the charge pump Layout diagram near the driver's seat showing an example of in-vehicle display

<Liquid crystal display device>
FIG. 1 is a block diagram showing a configuration example of a liquid crystal display device. The liquid crystal display device 1 of this configuration example includes an LCD [liquid crystal display] driver 20 and an LCD panel 35.

  The LCD driver 20 controls the drive of the LCD panel 35 based on a video signal input from the host controller 10 (microcomputer or the like) and various commands.

  The LCD panel 35 is a video output unit using liquid crystal elements as pixels, and is driven as a load of the LCD driver 20.

<LCD driver>
Next, the LCD driver 20 will be described in detail with reference to FIG. The LCD driver 20 includes an interface 21, command register 22, timing controller 23, data latch unit 24, source DAC (D / A converter) 25, source driver 26, DC / DC converter 27, charge pump 28, gate driver 29, regulator. The semiconductor device (IC) includes the elements of a common voltage generation unit 31, a common voltage generation unit 31, a gamma voltage generation unit 32, and an abnormality detection unit 33, and these elements are integrated into one chip.

  The interface 21 exchanges data with the host controller 10, receives image data and various commands from the host controller 10, and sends the detection result of the abnormality detection unit 33 to the host controller 10. .

  The command register 22 stores various commands sent from the host controller 10 via the interface 21.

  The timing controller 23 controls various timings of the LCD driver 20 based on the command stored in the command register 22. For example, the timing controller 23 performs vertical synchronization control of the gate driver 29, horizontal synchronization control of the source driver 26, and the like.

  The data latch unit 24 latches the video data input from the host controller 10 via the interface 21 and outputs it to the source DAC 25.

  The source DAC 25 operates by being supplied with the positive power supply voltage VSP and the negative power supply voltage VSN, and D / A converts digital (m-bit) video data latched and input from the data latch unit 24 to generate an analog video signal. To do.

  The source driver 26 operates by being supplied with the positive power supply voltage VSP and the negative power supply voltage VSN, and converts the analog video signal input from the source DAC 25 into source signals S (1) to S (x). The source signals S (1) to S (x) are supplied to the liquid crystal elements of the LCD panel 35 (in the case where the LCD panel 35 is an active matrix type, the source terminals of the active elements respectively connected to the liquid crystal elements). To be done.

  DC / DC converter 27 includes a positive boost converter unit that positively boosts input voltage VDD to generate positive power supply voltage VSP, and a negative boost converter unit that negatively boosts input voltage VDD to generate negative power supply voltage VSN. It is a switching power supply circuit. The positive power supply voltage VSP and the negative power supply voltage VSN are supplied to the source DAC 25, the source driver 26, the regulator 30, the common voltage generation unit 31, the gamma voltage generation unit 32, and the like.

  The charge pump 28 drives the flying capacitor in synchronization with the clock signal input from the timing controller 23, thereby boosting a predetermined reference voltage by a predetermined boosting ratio to obtain desired positive boosted voltage VGH and negative boosted voltage. Generate VGL.

  The gate driver 29 operates by being supplied with the positive boosted voltage VGH and the negative boosted voltage VGL, and based on the vertical synchronizing signal input from the timing controller 23, the gate signals G (1) to G (y) of the LCD panel 35. ) Is generated. The gate signals G (1) to G (y) are supplied to the liquid crystal elements of the LCD panel 35 (when the LCD panel 35 is an active matrix type, the gate terminals of the active elements respectively connected to the liquid crystal elements). To be done.

  The regulator 30 generates various internal voltages by reducing the positive power supply voltage VSP and the negative power supply voltage VSN, respectively.

  The common voltage generator 31 generates the common voltage VC by stepping down the negative power supply voltage VSN, and is connected to the liquid crystal element of the LCD panel 35 (when the LCD panel 35 is an active matrix type, it is connected to each liquid crystal element). Supply to the drain terminal of the active element).

The gamma voltage generation unit 32 operates by being supplied with the positive power supply voltage VSP and the negative power supply voltage VSN, and outputs 2 ^m different gradation voltages V (0) to V (n) (where n = 2 ^m −1). It is generated and supplied to the source DAC 25. The gradation voltages V (0) to V (n) correspond to the data values “0” to “n” of the video data input to the source DAC 25 one-to-one.

  The abnormality detection unit 33 detects an abnormality in the display operation of the LCD panel 35 by monitoring the operation of the DC / DC converter 27.

<Charge pump (first embodiment)>
FIG. 2 is a block diagram showing a first embodiment (and peripheral circuits thereof) of the charge pump 28. The charge pump 28 of this embodiment includes a positive boost charge pump unit 281 and a negative boost charge pump unit 282.

  The positive boosting charge pump unit 281 boosts the positive reference voltage VGHR (> 0) corresponding to the set value D1 by the boosting ratio (× A) corresponding to the setting value D2, so that the positive boosting voltage VGH (= VGHR × A). ) Is generated.

  The negative boosting charge pump unit 282 boosts the negative reference voltage VGLR (<0) corresponding to the set value D3 by the boosting ratio (× B) corresponding to the setting value D4, thereby generating the negative boosted voltage VGL (= VGLR × B). ) Is generated.

  The set values D1 to D4 are stored in the register units 221 to 224 of the command register 22, respectively.

  Further, the semiconductor device 20 is further integrated with a refresh unit 40 that periodically rewrites the set values D1 to D4 stored in the command register 22. The refresh unit 40 includes a timer 41, a non-volatile memory 42, and a selector 43.

  The timer 41 is a counter that determines the refresh timing of the set values D1 to D4, and instructs the non-volatile memory 42 to read regular data at predetermined intervals.

  The non-volatile memory 42 stores the normal data of the set values D1 to D4 in a non-volatile manner. As the non-volatile memory 42, for example, an OTPROM [one time programmable read-only memory] integrated in the semiconductor device 20 may be used, or an EEPROM [electrically erasable programmable] externally attached to the semiconductor device 20. read-only memory] or the like may be used.

  The selector 43 sends one of the command input from the host controller 10 and the regular data read from the nonvolatile memory 42 to the command register 22. More specifically, the selector 43 selects and outputs a command input from the host controller 10 when the command register 22 is externally set, and selects and outputs regular data read from the non-volatile memory when the command register 22 is refreshed. To do.

  By providing such a refresh unit 40, when the wrong setting values D1 to D4 are stored in the command register 22 due to erroneous command recognition, or the setting values D1 to D4 stored in the command register 22 due to disturbance noise or the like. Even when is changed, the set values D1 to D4 can be rewritten into regular data by the periodic refresh operation. Therefore, the output abnormality of the charge pump 28 does not continue for a long time.

<Positive boost charge pump section>
FIG. 3 is a circuit diagram showing a configuration example of the positive boost charge pump unit 281. The positive boost charge pump unit 281 of this configuration example includes a DAC 281a, a control unit 281b, flying capacitors Cf1 to Cf3 (hereinafter simply referred to as capacitors Cf1 to Cf3), and an output capacitor Co1 (hereinafter simply referred to as capacitor Co1). And charge transfer transistors P1 to P4 (all of which are PMOSFET [P-channel type metal oxide semiconductor field effect transistors in the example of the figure, and are simply referred to as transistors P1 to P4 hereinafter), and buffers B1 to B3, It is a Dixon type charge pump including.

  The DAC 281a is connected between the application end of the positive power supply voltage VSP and the application end of the ground voltage GND, and converts the digital set value D1 into an analog positive reference voltage VGHR (where GND <VGHR <VSP).

  The control unit 281b performs pulse output to the buffers B1 to B3 (= pulse driving of the capacitors Cf1 to Cf3) and on / off control of the transistors P1 to P4 in synchronization with the clock signal CLK. The control unit 281b also has a function of performing switching control of the boosting ratio (× A) according to the set value D2. In the positive boosting charge pump 281 of this configuration example, the boosting ratio is switched to either A = 2, A = 3, or A = 4.

  The drain of the transistor P1 is connected to the application terminal of the positive reference voltage VGHR. The source of the transistor P1 is connected to the first end of the capacitor Cf1 and the drain of the transistor P2. The source of the transistor P2 is connected to the first end of the capacitor Cf2 and the drain of the transistor P3. The source of the transistor P3 is connected to the first end of the capacitor Cf3 and the drain of the transistor P4. The source of the transistor P4 is connected to the first end of the capacitor Co1 and the output end of the positive boosted voltage VGH. The second end of the capacitor Cf1 is connected to the output end of the buffer B1. The second end of the capacitor Cf2 is connected to the output end of the buffer B2. The second end of the capacitor Cf3 is connected to the output end of the buffer B3. The second end of the capacitor Co1 is connected to the ground end.

  The buffers B1 to B3 are connected between the application end of the positive reference voltage VGHR and the application end of the ground voltage GND, respectively, and are respectively connected to the second ends of the capacitors Cf1 to Cf3 according to the pulse input from the control unit 281b. Pulse the ends. That is, the second end of each of the capacitors Cf1 to Cf3 becomes either high level (= VGHR) or low level (= GND) depending on the operation phase of the positive boost charge pump unit 281.

  The positive boost charge pump unit 281 configured as described above outputs the positive boost voltage VGH higher than the positive reference voltage VGHR by alternately repeating the first phase and the second phase in synchronization with the clock signal CLK. In the following, the operation state of each phase will be specifically described by taking the case where the boosting ratio is set to the maximum value (A = 4) as an example.

  FIG. 4 is a circuit diagram (first phase) showing an example of the positive boosting operation. In the first phase, the pulse outputs of the buffers B1 to B3 are set to low level (= GND), high level (= VGHR), and low level (= GND), respectively, and the transistors P1 and P3 are turned on and the transistor P2 is turned on. And P4 are turned off.

  At this time, the charging current flows through the capacitor Cf1 from the application end of the positive reference voltage VGHR through the transistor P1. Therefore, the capacitor Cf1 is charged until the voltage across the capacitor Cf1 becomes the positive reference voltage VGHR.

  The capacitor Cf2 is charged until the voltage across the capacitor Cf2 becomes twice the positive reference voltage VGHR (= 2VGHR) in the immediately preceding second phase. Therefore, when the second end of the capacitor Cf2 is pulled up to a high level (= VGHR) due to the transition to the first phase, the first end of the capacitor Cf2 follows both ends of the capacitor Cf2 in accordance with the charge conservation law of the capacitor Cf2. The voltage is raised to a voltage (= VGHR + 2VGHR = 3VGHR) that is higher by the inter-voltage.

  At this time, charges are transferred between the capacitors Cf2 and Cf3 via the transistor P3. As a result, the capacitor Cf3 is charged until the voltage across the capacitor Cf3 becomes three times the positive reference voltage VGHR (= 3VGHR).

  Further, the capacitor Co1 is charged until the voltage across the capacitor Co1 becomes four times the positive reference voltage VGHR (= 4VGHR) in the second phase immediately before, and this is output as the positive boosted voltage VGH.

  In the first phase, both the transistors P2 and P3 are turned off, so that the current does not flow backward in the path passing through these elements.

  FIG. 5 is a circuit diagram (second phase) showing an example of the positive boosting operation. In the second phase, the pulse outputs of the buffers B1 to B3 are set to the high level (= VGHR), the low level (= GND), and the high level (= VGHR), respectively, and the transistors P1 and P3 are turned off and the transistor P2 is turned off. And P4 are turned on.

  The capacitor Cf1 is charged until the voltage across the capacitor Cf1 becomes the positive reference voltage VGHR in the immediately preceding first phase. Therefore, when the second end of the capacitor Cf1 is pulled up to a high level (= VGHR) due to the transition to the second phase, the first end of the capacitor Cf1 follows both ends of the capacitor Cf1 according to the charge conservation law. The voltage is raised to a voltage (= VGHR + VGHR = 2VGHR) higher by the amount of the inter-voltage.

  At this time, charges are transferred between the capacitors Cf1 and Cf2 via the transistor P2. As a result, the capacitor Cf2 is charged until the voltage across the capacitor Cf2 becomes twice the positive reference voltage VGHR (= 2VGHR).

  The capacitor Cf3 is charged until the voltage across the capacitor Cf3 becomes three times the positive reference voltage VGHR (= 3VGHR) in the immediately preceding first phase. Therefore, when the second end of the capacitor Cf3 is pulled up to a high level (= VGHR) due to the transition to the second phase, the first end of the capacitor Cf3 follows both ends than the second end in accordance with the charge conservation law of the capacitor Cf3. The voltage is raised to a voltage (= GHR + 3VGHR = 4VGHR) higher by the amount of the inter-voltage.

  At this time, charges are transferred between the capacitors Cf3 and Co1 via the transistor P4. As a result, the capacitor Co1 is charged until the voltage across the capacitor Co1 becomes four times (= 4VGHR) the positive reference voltage VGHR.

  In the second phase, since both the transistors P1 and P3 are turned off, the current does not flow backward in the path passing through these elements.

  Thus, in the positive boost charge pump unit 281, the positive boost voltage VGH is generated by alternately repeating the first phase and the second phase in synchronization with the clock signal CLK.

  In the above description, the case where the boosting ratio is set to the maximum value (A = 4) has been taken as an example, but basically the same is true when the boosting ratio is A = 3 or A = 2. The charge pump operation is performed.

  For example, when the boosting ratio is set to A = 3, the transistor P4 is always turned on, the buffer B3 is always set to the output high impedance state, and the charge pump operation similar to the above may be performed. According to such an operation, the voltage between both ends of the capacitor Co1 is charged up to three times (= 3VGHR) the positive reference voltage VGHR, so that a triple boosting operation can be realized.

  When the boosting ratio is set to A = 2, the transistors P3 and P4 are always turned on, the buffers B2 and B3 are always set to the output high impedance state, and the same charge pump operation as the above is performed. I'll do it. According to such an operation, charging is performed until the voltage across the capacitor Co1 becomes twice the positive reference voltage VGHR (= 2VGHR), so that the double boosting operation can be realized.

  However, the configuration and operation of the positive boost charge pump unit 281 are not limited to the above, and the positive reference voltage VGHR can be boosted by the boosting ratio (× A) to generate the positive boost voltage VGH. As long as it is possible, any configuration and operation may be adopted.

<Negative boost charge pump section>
FIG. 6 is a circuit diagram showing a configuration example of the negative boosting charge pump unit 282. The negative boosting charge pump unit 282 of this configuration example includes a DAC 282a, a control unit 282b, flying capacitors Cf4 and Cf5 (hereinafter simply referred to as capacitors Cf4 and Cf5), and an output capacitor Co2 (hereinafter simply referred to as capacitor Co2). And a charge transfer transistors P5 to P7 (all PMOSFETs in the figure, and hereinafter simply referred to as transistors P5 to P7) and buffers B4 and B5 are Dickson type charge pumps.

  The DAC 282a is connected between the application end of the ground voltage GND and the application end of the negative power supply voltage VSN, and converts the digital set value D3 into an analog negative reference voltage VGLR (where VSN <VGLR <GND).

  The control unit 282b performs pulse output to the buffers B4 and B5 (= pulse driving of the capacitors Cf4 and Cf5) and on / off control of the transistors P5 to P7 in synchronization with the clock signal CLK. The control unit 282b also has a function of performing switching control of the boosting ratio (× B) according to the set value D4. In the negative boosting charge pump 282 of this configuration example, the boosting ratio is switched to either B = 2 or B = 3.

  The source of the transistor P5 is connected to the application terminal of the negative reference voltage VGLR. The drain of the transistor P5 is connected to the first end of the capacitor Cf4 and the source of the transistor P6. The drain of the transistor P6 is connected to the first end of the capacitor Cf5 and the source of the transistor P7. The drain of the transistor P7 is connected to the first end of the capacitor Co2 and the output end of the negative boosted voltage VGL. The second end of the capacitor Cf4 is connected to the output end of the buffer B4. The second end of the capacitor Cf5 is connected to the output end of the buffer B5. The second end of the capacitor Co2 is connected to the ground end.

  The buffers B4 and B5 are connected between the application end of the ground voltage GND and the application end of the negative reference voltage VGLR, respectively, and are connected to the second ends of the capacitors Cf4 and Cf5 according to the pulse input from the control unit 282b. Pulse the ends. That is, the second ends of the capacitors Cf4 and Cf5 are either at the high level (= GND) or at the low level (= VGHR) depending on the operation phase of the negative boosting charge pump unit 282.

  The negative boosting charge pump unit 282 having the above configuration outputs the negative boosting voltage VGL lower than the negative reference voltage VGLR by alternately repeating the first phase and the second phase in synchronization with the clock signal CLK. In the following, the operating state of each phase will be specifically described.

  FIG. 7 is a circuit diagram (first phase) showing an example of the negative boosting operation. In the first phase, the pulse outputs of the buffers B4 and B5 are set to high level (= GND) and low level (= VGLR), respectively, and the transistors P5 and P7 are turned on and the transistor P6 is turned off.

  At this time, the charging current flows through the capacitor Cf4 through the transistor P5 toward the application end of the negative reference voltage VGLR. Therefore, the capacitor Cf4 is charged until the voltage across the capacitor Cf4 becomes the negative reference voltage VGLR.

  The capacitor Cf5 is charged until the voltage across the capacitor Cf5 becomes twice the negative reference voltage VGLR (= 2VGLR) in the immediately preceding second phase. Therefore, when the second end of the capacitor Cf5 is pulled down to a low level (= VGLR) by the transition to the first phase, the first end of the capacitor Cf5 follows both ends of the capacitor Cf5 according to the charge conservation law of the capacitor Cf5. The voltage is reduced to a voltage (= VGLR + 2VGLR = 3VGLR) lower by the inter-voltage.

  At this time, charges are transferred between the capacitors Cf5 and Co2 via the transistor P7. As a result, the capacitor Co2 is charged until the voltage across the capacitor Co2 becomes three times the negative reference voltage VGLR (= 3VGLR).

  In the first phase, since the transistor P6 is off, the current does not reversely flow in the path passing through the element.

  FIG. 8 is a circuit diagram (second phase) showing an example of the negative boosting operation. In the second phase, the pulse outputs of the buffers B4 and B5 are set to low level (= VGLR) and high level (= GND), respectively, and the transistors P5 and P7 are turned off and the transistor P6 is turned on.

  The capacitor Cf4 is charged until the voltage across the capacitor Cf4 becomes the negative reference voltage VGLR in the immediately preceding first phase. Therefore, when the second end of the capacitor Cf4 is pulled down to the low level (= VGLR) due to the transition to the second phase, the first end of the capacitor Cf4 follows both ends of the capacitor Cf4 in accordance with the charge conservation law of the capacitor Cf4. The voltage is lowered to a voltage (= VGLR + VGLR = 2VGLR) lower by the inter-voltage.

  At this time, charges are transferred between the capacitors Cf4 and Cf5 via the transistor P6. As a result, the capacitor Cf5 is charged until the voltage across the capacitor Cf5 becomes twice the negative reference voltage VGLR (= 2VGLR).

  Further, the capacitor Co2 is charged until the voltage across the capacitor Co2 becomes three times the negative reference voltage VGLR (= 3VGLR) in the immediately preceding first phase, and this is output as the negative boosted voltage VGL.

  In the second phase, since both the transistors P5 and P7 are turned off, the current does not flow backward in the path passing through these elements.

  As described above, in the negative boost charge pump unit 282, the negative boost voltage VGL is generated by alternately repeating the first phase and the second phase in synchronization with the clock signal CLK.

  In the above description, the case where the boosting ratio is set to the maximum value (B = 3) has been taken as an example, but basically, when the boosting ratio is B = 2, a similar charge pump operation is performed. Done.

  For example, when the boosting ratio is set to B = 2, the transistor P7 is always turned on, the buffer B5 is always set to the output high impedance state, and the charge pump operation similar to the above may be performed. According to such an operation, charging is performed until the voltage across the capacitor Co2 becomes twice the negative reference voltage VGLR (= 2VGHR), so that the double boosting operation can be realized.

  However, the configuration and operation of the negative boosting charge pump unit 282 are not limited to the above, and it is possible to boost the negative reference voltage VGLR by the boosting ratio (× B) to generate the negative boosting voltage VGL. As long as it is possible, any configuration and operation may be adopted. Alternatively, the positive reference voltage VGH may be received and inverted and boosted (x-B).

<Charge pump (second embodiment)>
FIG. 9 is a block diagram showing the second embodiment of the charge pump 28. Since the first embodiment (FIG. 2) described above has the refreshing unit 40 that periodically rewrites the set values D1 to D4 of the charge pump 28, it may occur when command misrecognition or garbled registers occur. However, the output abnormality of the charge pump 28 does not continue for a long time.

  However, with such measures, the output abnormality of the charge pump 28 occurs for a short time from when the set values D1 to D4 of the charge pump 28 become abnormal until the refresh operation thereof is performed. Therefore, for example, when the difference voltage (= VGH-VGL) between the positive boosted voltage VGH and the negative boosted voltage VGL exceeds the breakdown voltage of the gate driver 29, the gate driver 29 is destroyed at the time when the output abnormality occurs. There is also a risk of being lost.

  In view of the above, it can be said that the regular refresh operation is not sufficient for erroneous command recognition and garbled registers, and it is desirable to take further measures. Therefore, in the charge pump 28 of the present embodiment, a positive boosted voltage calculation unit 283, a negative boosted voltage calculation unit 284, and a subtraction unit 285 are provided before the positive boosting charge pump unit 281 and the negative boosting charge pump unit 282. A determination unit 286 and an adjustment unit 287 are added.

  The positive boosted voltage calculation unit 283 receives the input of the set value D1 for setting the positive reference voltage VGHR and the set value D2 for setting the boosting ratio (× A), and predicts that the positive boosted voltage VGH will be obtained. The voltage value D5 (= D1 × D2) is calculated.

  The negative boosted voltage calculation unit 284 receives the set value D3 for setting the negative reference voltage VGLR and the set value D4 for setting the boosting ratio (× B), and predicts that it corresponds to the negative boosted voltage VGL. The voltage value D6 (= D3 × D4) is calculated.

  The subtraction unit 285 calculates a difference voltage value D7 (= D5-D6) by subtracting the expected voltage value D6 from the expected voltage value D5. The differential voltage value D7 corresponds to the voltage applied to the gate driver 29 (= VGH-VGL).

  The determination unit 286 determines whether or not the differential voltage value D7 is within the normal range, and outputs the determination result to the adjustment unit 287 as the determination signal S1. For example, the determination signal S1 is set to the high level H (= logical level at the time of abnormality) when the differential voltage value D7 is higher than the predetermined upper limit value DU, and when the differential voltage value D7 is lower than the upper limit value DU. It is set to low level L (= logical level during normal operation).

  The adjustment unit 287 adjusts at least one of the set values D1 to D4 according to the determination signal S1, and outputs the adjusted set values D1a to D4a to the positive boost charge pump unit 281 and the negative boost charge pump unit 282. .

  The operation of each unit will be described below with reference to specific numerical examples. First, as an example of a normal state, the operation of each part when VGHR = + 5V, A = 3 times, VGLR = -5V, and B = 3 times will be described. Note that DU = + 32V (= withstand voltage of the gate driver 29). In this case, D5 = + 15V (= (+ 5V) × 3) and D6 = −15V (= (− 5V) × 3), so D7 = + 30V (= (+ 15V) − (− 15V)) Become. Therefore, since D7 <DU, S1 = L. At this time, the adjustment unit 287 outputs the set values D1 to D4 as they are as the adjusted set values D1a to D4a.

  Next, as an example at the time of abnormality, each part operation when VGHR = + 5V, A = 4 times, VGLR = -5V, and B = 3 times (when the boosting ratio A has changed from 3 times to 4 times) Will be explained. In this case, D5 = + 20V (= (+ 5V) × 4) and D6 = −15V (= (− 5V) × 3), so D7 = + 35V (= (+ 20V) − (− 15V)) Become. Therefore, since D7> DU, S1 = H. At this time, the adjusting unit 287 adjusts at least one of the set values D1 to D4 and then outputs the adjusted set values D1a to D4a.

  Note that, as the adjusting operation of the set values D1 to D4, for example, the place where D1 = + 5V is lowered to D1a = + 4V, and only the set value D1 (therefore, the positive reference voltage VGHR) may be clipped. . By performing such clipping processing, the adjusted positive boosted voltage VGH becomes + 16V (= (+ 4V) × 4), so that the voltage applied to the gate driver 29 is + 31V (= (+ 16V)-(-15V). ).

  Therefore, if the set values D1 to D4 become abnormal due to command misrecognition or garbled registers, it is possible to prevent breakdown of the gate driver 29 withstand voltage even while waiting for those refresh operations.

  Further, as can be seen from the above example, the adjusting operation of the set values D1 to D4 is always an operation of returning an abnormal value to a normal value (in the above example, an operation of returning the boosting ratio A from 4 times to 3 times). There is no need, and any setting value D1 to D4 may be adjusted as long as the voltage applied to the gate driver 29 does not exceed the withstand voltage. For example, with a configuration in which it is possible to arbitrarily set what kind of adjustment operation is performed for the set values D1 to D4, it is possible to perform adjustment with a high degree of freedom for each application.

  When it is necessary to finely adjust the positive boosted voltage VGH or the negative boosted voltage VGL, it can be said that it is preferable to adjust the positive reference voltage VGHR or the negative reference voltage VGLR rather than the boosting ratios A or B.

  In the above example, the determination unit 286 compares the difference voltage value D7 corresponding to the voltage applied to the gate driver 29 (= VGH-VGL) with the predetermined upper limit value DU. The abnormality determination may be performed by comparing the voltage value D7 with a predetermined lower limit value DL, or by comparing the differential voltage value D7 with both the upper limit value DU and the lower limit value DL.

<Charge pump (third embodiment)>
FIG. 10 is a block diagram showing a third embodiment of the charge pump 28. In the charge pump 28 of the present embodiment, the negative boosting charge pump unit 282, the negative boosted voltage calculating unit 284, and the subtracting unit 285 are omitted from the second embodiment (FIG. 9) described above.

  As shown in the figure, when the charge pump 28 that generates only a single boosted voltage (here, the positive boosted voltage VGH) is an application target of the present invention, in the determination unit 286, the positive boosted voltage calculation unit 283 is used. It may be determined whether or not the generated expected voltage value D5 (= D1 × D2) is within the normal range. The adjusting unit 287 may adjust at least one of the set values D1 and D2 according to the determination signal S1.

  With such a configuration, even when the charge pump 28 is a single output type, it is possible to take sufficient measures against command misrecognition and garbled registers.

  Although not shown again, the same applies to the case where the positive boost charge pump unit 281, the positive boost voltage calculation unit 283, and the subtraction unit 285 are omitted from the second embodiment (FIG. 9) described above. It is possible to understand.

<In-vehicle display>
The liquid crystal display device 1 described so far is particularly suitable for application to a vehicle-mounted display. The vehicle-mounted display is provided on the dashboard in front of the driver's seat in the vehicle, like the vehicle-mounted displays 81 to 83 shown in FIG. 11, for example.

  For example, the vehicle-mounted display 81 functions as an instrument panel (instrument panel: instrument panel mounted on a dashboard) that displays a speedometer, a tachometer, and the like. The in-vehicle display 82 displays a fuel gauge, a fuel consumption meter, a shift position, and the like. The vehicle-mounted display 83 has a navigation function for displaying current position information of the vehicle, route information to the destination, and the like, and also has a back monitor function for displaying a captured image of the rear of the vehicle.

  As described above, in recent years, in addition to the conventional car navigation device, applications such as an instrument panel that displays a liquid crystal over the entire surface and a back monitor that displays an image of the rear of the vehicle have come to be installed. Therefore, the use of in-vehicle displays is expanding. Therefore, the information displayed on the in-vehicle displays 81 to 83 is becoming more and more important to the driver, and it is required to further enhance the reliability of the in-vehicle displays 81 to 83 in order to safely drive the vehicle. To be

  In that respect, the liquid crystal display device 1 described above is designed to be reliable with fail-safe in mind, and even if some trouble occurs, it is fatal enough to hinder the safe operation of the vehicle. You don't have to fall into a situation like this.

<Other modifications>
In the above-described embodiment, the configuration in which the present invention is applied to the charge pump used as the power supply means of the vehicle-mounted display has been described as an example, but the application target of the present invention is not limited to this. It can also be widely applied to charge pumps used for other purposes.

  Further, various technical features disclosed in this specification can be variously modified in addition to the above-described embodiment without departing from the spirit of the technical creation. That is, the above-described embodiments should be considered as illustrative in all points and not restrictive, and the technical scope of the present invention is shown not by the description of the above-described embodiments but by the claims. It is to be understood that all modifications that come within the meaning and range of equivalency of the claims are to be embraced.

  INDUSTRIAL APPLICABILITY The invention disclosed in this specification can be applied to, for example, a charge pump used as a power supply unit of a vehicle-mounted display.

1 Liquid Crystal Display 10 Host Controller 20 LCD Driver 21 Interface 22 Command Registers 221 to 224 Register 23 Timing Controller 24 Data Latch 25 Source DAC
26 Source Driver 27 DC / DC Converter 28 Charge Pump 281 Positive Boost Charge Pump Section 282 Negative Boost Charge Pump Section 283 Positive Boost Voltage Calculation Section 284 Negative Boost Voltage Calculation Section 285 Subtracting Section 286 Judging Section 287 Adjusting Section 281a, 282a DAC
281b, 282b Control part Cf1-Cf5 Flying capacitor Co1, Co2 Output capacitor P1-P7 Charge transfer transistor (PMOSFET)
B1 to B5 Buffer 29 Gate driver 30 Regulator 31 Common voltage generation unit 32 Gamma voltage generation unit 33 Abnormality detection unit 35 LCD panel 40 Refresh unit 41 Timer 42 Nonvolatile memory 43 Selector 81 to 83 In-vehicle display

Claims (10)

A first charge pump unit for generating a first boosted voltage by boosting a first reference voltage according to the first set value by a first boosting ratio according to the second set value;
A first boosted voltage calculation unit that receives inputs of the first set value and the second set value and calculates a first expected voltage value corresponding to the first boosted voltage;
A determination unit that determines whether or not the first expected voltage value is within a normal range;
An adjusting unit that adjusts at least one of the first setting value and the second setting value according to the determination result of the determining unit;
A charge pump having: A first charge pump unit for generating a first boosted voltage by boosting a first reference voltage according to the first set value by a first boosting ratio according to the second set value;
A second charge pump unit for generating a second boosted voltage by boosting a second reference voltage according to the third set value by a second boosting ratio according to the fourth set value;
A first boosted voltage calculation unit that receives inputs of the first set value and the second set value and calculates a first expected voltage value corresponding to the first boosted voltage;
A second boosted voltage calculation unit that receives the third set value and the fourth set value and calculates a second expected voltage value corresponding to the second boosted voltage;
A subtraction unit that calculates a differential voltage value between the first predicted voltage value and the second predicted voltage value;
A determination unit determining whether the difference voltage value is within the normal range,
An adjusting unit that adjusts at least one of the set values according to the determination result of the determining unit,
A charge pump having:   The charge pump according to claim 2, wherein the first boosted voltage is a positive voltage and the second boosted voltage is a negative voltage. The first charge pump unit and the second charge pump unit are respectively
A flying capacitor,
An output capacitor,
A charge transfer transistor,
A control unit for pulse-driving one end of the flying capacitor in synchronization with a clock signal and for turning on / off the charge transfer transistor;
The charge pump according to claim 2 or 3, further comprising: The first charge pump unit may further seen including a first DAC for converting the first set value of the digital to the first reference voltage of the analog,
The charge pump of claim 4, wherein the second charge pump unit further includes a second DAC that converts the digital third set value into the analog second reference voltage . A charge pump according to any one of claims 1 to 5,
A register that stores each setting value of the charge pump,
A load that operates by receiving power supply from the charge pump,
A semiconductor device formed by integrating.   7. The semiconductor device according to claim 6, further comprising a refreshing unit that rewrites each setting value stored in the register at regular intervals.   8. The semiconductor device according to claim 6, wherein the load is a gate driver that drives a gate of an LCD [liquid crystal display] panel. A semiconductor device according to claim 8,
An LCD panel driven by the semiconductor device;
A liquid crystal display device comprising:   A vehicle comprising the liquid crystal display device according to claim 9.

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