JP6671816B2 - Gaming machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachislot machine.

  Conventionally, a gaming machine called a pachislot has been known. In such a gaming machine, a plurality of reels each having a plurality of symbols arranged on each surface, game medals and coins (hereinafter, referred to as “medals”) are inserted, and the start lever is operated by the player. A start switch for requesting the start of rotation of a plurality of reels, and detecting that a stop button provided for each of the plurality of reels has been pressed by a player, and rotating the corresponding reel. And a stop switch for outputting a signal for requesting the stop of the operation.

  In addition, such a gaming machine is provided corresponding to each of a plurality of reels, and a stepping motor that transmits each driving force to each reel, and a stepping motor based on signals output by a start switch and a stop switch. A reel control unit that controls the operation of the motor and rotates and stops each reel.

  With this configuration, when the gaming machine detects that the start lever has been operated, the gaming machine performs a lottery based on the random number, and the result of the lottery (hereinafter referred to as “internal winning combination”) and the operation of the stop button. The rotation of the reel is stopped on the basis of the timing at which is detected.

  In recent years, as a gaming machine of this type, a replay related to a replay has been determined as an internal winning combination after a big bonus (hereinafter, referred to as “BB”) in which a game that provides a player with a relatively large profit can be performed a predetermined number of times. There is known a game device that activates a game state (hereinafter, referred to as “high RT”) having a high probability of being played (for example, see Patent Literature 1).

  Further, in this gaming machine, when the number of medals paid out during the operation of the BB is equal to or more than a predetermined number, in addition to the above-mentioned high RT, a specific internal winning combination (hereinafter referred to as “small winning combination”) related to the payout of medals. ) Is activated (hereinafter referred to as "AT"). The state where both the high RT and the AT are operated is referred to as ART.

  According to the gaming machine, during the operation of the ART, the probability that the winning combination is lost is lower than that in the general gaming state, and the probability that the small combination is won becomes higher. be able to. For this reason, it is possible to attract the interest of the player and enhance the playability.

  In addition, in recent years, a predetermined small combination (for example, cherry) is internally won during a general game, so that a special game state (hereinafter, referred to as a chance zone) advantageous to the player with a predetermined probability is generated with a predetermined number of games. There is known a gaming machine in which a predetermined small number of games are internally won in a chance zone to add a chance zone of a predetermined number of games with a predetermined probability (for example, see Patent Document 2). According to the gaming machine, the player's interest can be maintained by appropriately extending the number of continuous games in the chance zone which is advantageous to the player.

  On the other hand, important processing of the gaming machine, such as control of the spinning reel of the gaming machine, internal winning combination processing, winning determination processing, and medal payout processing, is performed by the CPU of the main control circuit. It is executed according to a program stored in the ROM in advance.

  The internal winning combination is determined based on the random number and the internal lottery table, and the rotation of each reel is stopped based on the determined internal winning combination and the timing at which the stop operation of the reel is detected. At this time, the extracted random number value is stored in the random number value storage area of the RAM, and the internal winning combination is determined at the time of the internal lottery process based on the stored random number value.

  In addition, the sub-control circuit performs various processes such as determining and executing effect data based on various commands output from the main control board such as a start command. For this reason, the sub control circuit is also provided with a RAM, and in the RAM, various information obtained by the processing of the CPU of the main control board, for example, the above extracted random number value, game state, internal winning combination, payout number , Information for specifying the bonus carryover status, the set value, etc., various counters, flags, and the like.

  Further, a sub-device such as a scaler device for enlarging a picture displayed on the display device of the gaming machine in order to enhance the effect is connected to the sub-control circuit (for example, see Patent Documents 3 and 4). As the sub device, there are a touch sensor panel, a camera device, and the like in addition to the scaler device.

  By the way, there is a fraudulent technique for fraudulently inducing and continuing the ART for operating both the high RT and the AT. For example, an electromagnetic wave is applied to an information path connecting a main control circuit that manages the entire gaming machine and a sub-control circuit that manages a presentation surface, etc., thereby temporarily interrupting the flow of information to induce an ART.・ There is a technique called continuation electromagnetic wave ART.

  For example, when a certain number of small wins corresponding to a particular game are acquired, the ART is determined when a certain number of small wins are obtained. By irradiating an electromagnetic wave at the final game of the ART, the sub-control circuit cannot recognize the end signal. To

  Thereby, as a result, it is possible to continue until a specific small combination is drawn, so that it is possible to reliably enter and continue the ART. In addition, if the game has the game property that the ART is determined when the replay is continuously performed a predetermined number of times and the addition is determined when the replay is performed continuously beyond the predetermined number of times, an electromagnetic wave is emitted when a small role other than the replay is drawn. Then, the information flowing from the main control circuit to the sub-control circuit is temporarily interrupted so that the sub-control circuit is not made aware of the game, so that the replay can be continuously drawn.

  In order to prevent fraud, the history of the power switch BQ is detected and the history is held during the standby time until the power is turned off, and the history is confirmed after the power is restored. 2. Description of the Related Art There is known a gaming machine that can determine whether a setting has been changed by an operation or a setting has been illegally changed by a flash or the like (for example, see Patent Document 5).

JP 2009-5978 A JP-A-2004-236763 JP 2001-58021 A JP 2011-11035 A JP 2006-068241 A

  However, as described above, in recent gaming machines, various types of sub-devices are connected to a control unit such as a sub-control circuit with the diversification of effects. However, conventional gaming machines (particularly, Patent Literature 3, Patent Literature 3) In 4), efficient communication control between the sub device and the control unit has not been sufficiently considered. For this reason, there has been a problem that when communication is interrupted between the sub device and the control unit, communication cannot be efficiently restored.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a gaming machine capable of efficiently returning communication when communication is interrupted between a sub device and a control unit. And

Therefore, the gaming machine according to the present invention includes a display unit (liquid crystal display area 23) capable of displaying predetermined information, a control unit (sub CPU 71) connected to the display unit for controlling effects, and A contact input unit (a touch panel configured by a touch sensor module 781 and a touch sensor relay board 780) that is connected and transmits a signal to the control unit. The control unit is configured to transmit a contact input to the contact input unit. Regardless of the presence or absence, the presence or absence of a signal from the contact input unit to the control unit, a communication disconnection detection unit that detects a state where the signal does not exist for a predetermined time as a communication disconnection, the contact input unit, A contact input signal indicating contact information of the contact input when there is a contact input to the contact input unit; And the transmission and a operation confirmation signal for the control unit confirms as the signal, the control unit, after the communication disconnection detecting means detects the communication disconnection, receiving the signal from the touch input unit Sometimes, it is determined that communication is restarted.

  According to this, this gaming machine ends the task (inter-sub-device communication control task) when communication is interrupted between the touch panel including the touch sensor relay board 780 and the sub-CPU 71 constituting the control unit. Communication can be resumed without having to restart communication, so that communication can be efficiently resumed when there is a disconnection between the sub device and the control unit without having to start another task to resume communication. Can be.

The gaming machine, the contact input portion includes a plurality of input method, and the contact information corresponding to the input method and transmitted as the signal to the control unit, the touch input unit in the storage area corresponding to the input method of the contact information received from, and storing the contact information, even when receiving the contact information corresponding to the input method from the touch input unit, the communication resumption May be determined. According to this, the gaming machine can make full use of the functions of the touch input unit (touch panel) having a plurality of input methods, and thus can expand the range of effects.

  In the gaming machine, the contact input unit may be arranged at a predetermined position in a display area of the display unit, and may input the contact information by a capacitance method. According to this, since the touch panel occupies a part of the liquid crystal display area 23, the touch panel and the liquid crystal display area 23 can be integrally formed, the number of components constituting the gaming machine can be reduced, and the manufacturing cost can be reduced. Can be reduced.

  According to the present invention, it is possible to provide a gaming machine capable of efficiently returning communication when communication is interrupted between the sub device and the control unit.

It is an external view of a gaming machine in this embodiment. It is a figure showing a symbol display area and a winning line of the gaming machine in the present embodiment. It is a diagram showing a symbol arrangement table of the gaming machine in the present embodiment. It is a figure showing the front upper part of the game machine in this embodiment. It is a figure showing a section near a display panel unit of a game machine in this embodiment. It is a figure showing a display panel of a game machine in this embodiment. (A) is a diagram showing a left decorative panel and a left infrared sensor of the gaming machine according to the present embodiment. (B) is a diagram showing a left infrared sensor of the gaming machine according to the present embodiment. FIG. 3 is a diagram showing a configuration of a main control circuit of the gaming machine according to the present embodiment. It is a diagram showing a configuration of a sub-control circuit of the gaming machine in the present embodiment. It is a figure which shows the example of transition of the game state of the gaming machine in this Embodiment. It is a figure showing an example of an internal lottery table determination table of the gaming machine in the present embodiment. It is a figure showing an example of an internal lottery table of a game machine in this embodiment. It is a figure showing an example of the RB1 gaming state internal lottery table of the gaming machine in the present embodiment. It is a figure showing the example of the RB2 game state internal lottery table of the gaming machine in the present embodiment. It is a figure showing an example of a RT transition table of a game machine in this embodiment. It is a figure showing an example of a bonus internal winning combination determination table of a gaming machine in the present embodiment. It is a diagram showing an example of a small winning combination / replay internal winning combination determination table of the gaming machine in the present embodiment. It is a figure showing the example of the symbol combination table of the game machine in this embodiment. It is a figure showing an example of a table at the time of bonus operation of a game machine in this embodiment. It is a figure showing an example of a draw-in priority order table A of a gaming machine in the present embodiment. It is a figure showing an example of a draw-in priority order table B of a gaming machine in the present embodiment. It is a figure showing an example of a stop table of a game machine in this embodiment. It is a figure showing an example of an internal winning combination storing area of the gaming machine in the present embodiment. It is a figure showing an example of a display combination storing area of the gaming machine in the present embodiment. It is a figure showing an example of a carry-over combination storage area of the gaming machine of the present embodiment. It is a figure showing an example of a game state flag storage area of the gaming machine of the present embodiment. It is a figure showing an example of storage of design storage area A of a game machine in this embodiment. It is a figure showing an example of storage of design storage area B of a game machine in this embodiment. It is a figure showing an example of navigation mode shift lottery table A of a game machine in this embodiment. It is a figure showing an example of navigation mode shift lottery table B of a game machine in this embodiment. It is a figure showing an example of navigation mode shift lottery table C of a game machine in this embodiment. It is a figure showing an example of the navi game state shift waiting number lottery table of the gaming machine in the present embodiment. It is a figure showing an example of the navi game state 3 shift waiting number random determination table of the gaming machine in the present embodiment. It is a figure showing an example of navi game state 3 addition game number lottery table A of the gaming machine in the present embodiment. It is a figure showing an example of navi game state 3 addition game number lottery table B of the gaming machine in the present embodiment. It is a figure showing an example of navi game state 3 addition game number lottery table C of the gaming machine in the present embodiment. It is a figure showing an example of the navi game state 3 addition game number lottery table D of the gaming machine in the present embodiment. It is a figure showing an example of navigation game state 3 addition lottery mode lottery table A of the gaming machine in the present embodiment. It is a figure showing an example of navigation game state 3 addition lottery mode lottery table B of the gaming machine in the present embodiment. It is a figure showing an example of navigation game state 3 addition lottery mode lottery table C of the gaming machine in the present embodiment. It is a figure showing an example of navigation game state 3 addition lottery mode lottery table D of the gaming machine in the present embodiment. It is a figure showing the example of the navi set number lottery table of the game machine in this embodiment. It is a figure showing the example of the navi game state 3 navigation game number addition lottery table of the game machine in this embodiment. It is a figure showing the example of the navi game number special addition lottery table of the game machine in this execution form. It is a figure showing an example of a billy get challenge occurrence lottery table of the gaming machine in the present embodiment. It is a figure showing an example of a billy get challenge control counter lottery table of the gaming machine in the present embodiment. It is a figure showing an example of a billy get challenge correct answer lottery table of a game machine in this embodiment. It is a figure showing an example of a lottery table at the time of no billy challenge selection of a game machine in this embodiment. FIG. 5 is a diagram showing a flowchart of a reset interrupt process by a main CPU performed by a main control circuit in the present embodiment. FIG. 9 is a view illustrating a flowchart of bonus operation monitoring processing performed by the main control circuit according to the present embodiment. FIG. 9 is a diagram illustrating a flowchart of an internal lottery process performed by the main control circuit according to the present embodiment. FIG. 9 is a diagram illustrating a flowchart of an internal lottery process performed by the main control circuit according to the present embodiment. FIG. 5 is a diagram illustrating a flowchart of a reel stop control process performed by a main control circuit according to the present embodiment. FIG. 9 is a diagram showing a flowchart of a display combination search process performed by the main control circuit in the present embodiment. FIG. 4 is a diagram showing a flowchart of an RT control process performed by the main control circuit in the present embodiment. It is a figure showing a flow chart of the bonus end check processing performed in the main control circuit in the present embodiment. It is a figure showing a flow chart of the bonus operation check processing performed in the main control circuit in the present embodiment. FIG. 11 is a diagram showing a flowchart of an interrupt process (1.1173 ms) by the main CPU performed by the main control circuit in the present embodiment. It is a figure showing the flow chart of the effect registration processing performed by the sub control circuit in the present embodiment. It is a figure showing the flow chart of the production content decision processing performed by the sub control circuit in the present embodiment. FIG. 5 is a diagram showing a flowchart of a start command receiving process performed by the sub control circuit in the present embodiment. FIG. 5 is a diagram showing a flowchart of a start command receiving process performed by the sub control circuit in the present embodiment. FIG. 7 is a diagram illustrating a flowchart of a process during BB performed by the sub control circuit in the present embodiment. It is a figure showing the flow chart of the lottery processing in BB4 performed by the sub control circuit in this embodiment. FIG. 5 is a diagram showing a flowchart of billy get challenge processing performed by a sub control circuit in the present embodiment. It is a figure showing the flow chart of the number of games 3 for navi game state addition and lottery mode lottery processing performed by the sub control circuit in the present embodiment. FIG. 5 is a diagram illustrating a flowchart of an ART first hit processing performed by a sub control circuit according to the present embodiment. It is a figure showing a flow chart of navigation game state transition processing in standby state performed by a sub control circuit in this embodiment. It is a figure showing a flow chart of navigation game state transition processing in navigation game state 1 performed by a sub control circuit in this embodiment. It is a figure showing a flow chart of navigation game state transition processing in navigation game state 2 performed by a sub control circuit in this embodiment. It is a figure showing a flow chart of navigation game state transition processing in navigation game state 2 performed by a sub control circuit in this embodiment. It is a figure showing a flowchart of navigation game state 3 shift processing in navigation game state 2 performed by the sub control circuit in the present embodiment. It is a figure showing a flow chart of navigation game state shift processing in navigation game state 3 performed by a sub control circuit in this embodiment. FIG. 8 is a diagram illustrating a flowchart of a navigation game number addition process performed by a sub control circuit according to the present embodiment. It is a figure showing the flowchart of the billy get challenge lottery processing performed by the sub control circuit in this embodiment. FIG. 7 is a diagram showing a flowchart of billy get challenge determination processing performed by a sub control circuit in the present embodiment. It is a figure showing a flow chart of navigation game state change processing performed by a sub control circuit in this embodiment. FIG. 5 is a diagram showing a flowchart of a display command receiving process performed by the sub control circuit in the present embodiment. FIG. 11 is a diagram showing a flowchart of processing at the time of receiving a bonus end command performed by the sub control circuit in the present embodiment. It is a figure which shows the example of a change of LED brightness at the time of the display panel unit effect in this Embodiment. It is the schematic which shows the whole management system of the gaming machine in this Embodiment. It is a schematic diagram showing a menu screen of the gaming machine in the present embodiment. It is a schematic diagram showing an error information history screen of the gaming machine in the present embodiment. It is an explanatory view showing contents of information of a two-dimensional code used for a management system of a game machine in this embodiment. It is an explanatory view showing a code number, a type, and a parameter of a received command used for a gaming machine in the present embodiment. It is explanatory drawing which shows the recording image of the information of the two-dimensional code when a COM error occurs in the gaming machine in this Embodiment, (a) is when it happens accidentally during a normal game, (b) is (C) shows a case in which lever transmission has been performed when a setting change has occurred due to a goto action. FIG. 4 is an explanatory diagram showing a communication log collection ring buffer area in a sub RAM of a sub control circuit according to the present embodiment. FIG. 4 is an explanatory diagram illustrating a communication error storage area in a sub RAM of a sub control circuit according to the present embodiment. FIG. 9 is a diagram illustrating an example of notifying a liquid crystal display area of a RAM destruction in the gaming machine according to the present embodiment when the RAM is destroyed. FIG. 11 is a diagram showing a flowchart of main board communication reception interrupt processing by a sub CPU performed by a sub control circuit in the present embodiment. FIG. 4 is a diagram showing a detailed flowchart of a main board communication task performed by a sub control circuit in the present embodiment. FIG. 9 is a diagram showing a flowchart of main board communication reception data log storage processing performed by the sub control circuit in the present embodiment. FIG. 9 is a diagram showing a flowchart of main board communication reception data log temporary area saving processing performed by the sub control circuit in the present embodiment. FIG. 9 is a diagram illustrating a flowchart of main board communication error history data storage processing performed by a sub control circuit according to the present embodiment. FIG. 9 is a diagram illustrating a flowchart of an inter-command elapsed time monitoring process performed by the sub control circuit according to the present embodiment. FIG. 7 is a diagram illustrating a flowchart of a monitoring timer activation process performed by a sub control circuit according to the present embodiment. FIG. 4 is a diagram illustrating a flowchart of a monitoring timer stop process performed by a sub control circuit in the present embodiment. FIG. 9 is a diagram illustrating a flowchart of a monitoring timer operation status check process performed by a sub control circuit in the present embodiment. FIG. 5 is a diagram showing a timing chart of monitoring of two monitoring timers performed by a sub control circuit in the present embodiment. FIG. 4 is a diagram illustrating a flowchart of a COM error check process performed by a sub control circuit according to the present embodiment. FIG. 3 is a diagram showing an area image in a sub ROM of a sub control circuit according to the present embodiment. FIG. 4 is a diagram showing an area image in a sub RAM of a sub control circuit in the present embodiment. FIG. 4 is a diagram showing an image of an area in a backup RAM of a sub control circuit according to the present embodiment. FIG. 4 is a diagram showing a transmission / reception command data format between a sub control circuit and a sub device in the present embodiment. FIG. 4 is a diagram showing the contents of data transmitted and received between a sub control circuit and a sub device in the present embodiment. FIG. 5 is a diagram showing a sub-device communication data consistency check table in the present embodiment. FIG. 4 is a diagram illustrating an example of a structure of an error information history storage area in a sub RAM of a sub control circuit according to the present embodiment. FIG. 5 is a diagram illustrating an example of data contents stored in an error information history storage area in a sub RAM of a sub control circuit according to the present embodiment. FIG. 9 is a diagram illustrating an example of the content of other data stored in an error information history storage area in a sub RAM of a sub control circuit according to the present embodiment. FIG. 9 is a diagram illustrating a flowchart for describing processing when the power of a sub CPU of the sub control circuit is turned on in the present embodiment. FIG. 9 is a diagram illustrating a flowchart of a power interruption process of a sub CPU of the sub control circuit in the present embodiment. (A) is a diagram showing a flowchart of a mother task for performing various task activation requests performed by the sub CPU of the sub control circuit in the present embodiment, and (b) is a diagram showing an example of a game information providing system. is there. FIG. 9 is a diagram showing a flowchart of a unimemo management task executed by the sub CPU of the sub control circuit in the present embodiment. It is a figure showing an example of a procedure which inputs a password using a touch sensor module provided in a liquid crystal display area of a game machine in this embodiment. FIG. 9 is a diagram showing a flowchart of a unimemo management task executed by the sub CPU of the sub control circuit in the present embodiment. FIG. 9 is a diagram illustrating a flowchart of an RTC activation task performed by a sub CPU of the sub control circuit according to the present embodiment. FIG. 9 is a diagram showing a flowchart of a sub RAM management process performed by a sub CPU of the sub control circuit in the present embodiment. FIG. 114 is a diagram showing a flowchart of backup creation processing in the sub RAM management processing shown in FIG. 113. FIG. 9 is a diagram illustrating a flowchart of a communication control task between sub-devices performed by the sub-CPU of the sub-control circuit in the present embodiment. FIG. 9 is a diagram illustrating a flowchart of a sub-device serial reception interrupt process performed by a sub-CPU of the sub-control circuit in the present embodiment. FIG. 115 is a diagram showing a flowchart of a sub-device command receiving process in the inter-sub-device communication control task shown in FIG. 115. FIG. 115 is a diagram showing a flowchart of processing at the time of reception of sub-device communication in the inter-sub-device communication control task shown in FIG. 115. FIG. 118 is a view illustrating a flowchart of processing at the time of receiving a touch sensor relay command in the processing at the time of reception of the sub device communication illustrated in FIG. 118. FIG. 120 is a view illustrating a flowchart of sub-device received data determination processing in the touch sensor relay command reception processing illustrated in FIG. 119. FIG. 115 is a diagram illustrating a flowchart of a sub-device communication disconnection process in the inter-sub-device communication control task illustrated in FIG. 115. FIG. 115 is a diagram showing a flowchart of a sub-device communication return process in the inter-sub-device communication control task shown in FIG. 115. FIG. 9 is a diagram illustrating a flowchart of a touch sensor relay main task executed by the touch sensor relay board of the sub control circuit in the present embodiment. FIG. 124 is a view illustrating a flowchart of a sub-control reception process in the touch sensor relay main task illustrated in FIG. 123. FIG. 124 is a view illustrating a flowchart of a touch sensor module input process in the touch sensor relay main task illustrated in FIG. 123. FIG. 124 is a view illustrating a flowchart of sub-control transmission processing in the touch sensor relay main task illustrated in FIG. 123. FIG. 124 is a view illustrating a flowchart of an operating state determination process in the touch sensor relay main task illustrated in FIG. 123. It is a perspective view showing the appearance of a game machine in another embodiment of the present invention. It is a front view showing the appearance of a game machine in another embodiment of the present invention. It is an exploded perspective view showing a schematic configuration of a gaming machine according to another embodiment of the present invention. It is a front view showing a schematic structure of a game board of a game machine in another embodiment of the present invention. FIG. 14 is a block diagram showing a configuration of a main control circuit and a sub control circuit of a gaming machine according to another embodiment of the present invention.

[Configuration of pachislot machine]
Hereinafter, the gaming machine of the present invention will be specifically described with reference to the drawings. In the following embodiments, the gaming machine of the present invention is provided with three rotating reels that variably display symbols, and is provided to a player in addition to coins, medals, tokens, and the like. A description will be given using a gaming machine capable of playing using a gaming value such as a card, a so-called pachislot gaming machine. In the following embodiments, a pachislot gaming machine will be described as an example, but the gaming machine of the present invention is not limited thereto, and may be a pachinko machine or a slot machine. Examples of pachinko gaming machines will be described later separately.

  First, an overview of a pachislo gaming machine according to the present embodiment will be described with reference to FIG. FIG. 1 is a perspective view of a gaming machine 1 according to the present embodiment.

  As shown in FIG. 1, the gaming machine 1 includes a housing 1a that accommodates reels 3L, 3C, 3R, a main control circuit 60 (see FIG. 8) described later, and the like. The housing 1a includes a front door 1b that can be opened and closed. The gaming machine 1 further includes a lock mechanism for switching the front door 1b to a locked state or an unlocked state with the front door 1b closed. The lock mechanism is operated by inserting the door key 2 into the door key hole 1c and rotating the door key 2.

  The door key 2 is inserted into the door key hole 1c. For example, when the door key 2 is turned clockwise, the front door 1b can be opened and closed. When the door key 2 is turned counterclockwise, the main control circuit 60 and the like are electrically reset. I have. That is, the door key 2 has a reset function of electrically resetting the gaming machine 1 in addition to the operation of the lock mechanism.

  On the front of the central part of the front door 1b, symbol display areas 4L, 4C and 4R as substantially vertical planes and a liquid crystal display area 23 are formed. Three reels 3L, 3C and 3R are rotatably provided in a horizontal line inside the front of the central portion of the cabinet 1a. On the three reels 3L, 3C, 3R, a symbol row composed of a plurality of types of symbols is drawn on each outer peripheral surface.

  The symbols on each of the reels 3L, 3C, 3R are visible through the symbol display areas 4L, 4C, 4R. Further, the reels 3L, 3C, 3R are controlled by a main control circuit 60 (see FIG. 8) described later so as to rotate at a constant speed (for example, 80 rotations / minute), and are set in the symbol display areas 4L, 4C, 4R. The displayed symbols drawn on the reels 3L, 3C, 3R change with the rotation of the reels.

  Below the liquid crystal display area 23, a pedestal portion 10 having a substantially horizontal plane is formed. On the left side of the pedestal section 10, a C / P button 14 for switching between credit (Credit) / payout (Pay) of medals obtained by the player and a bet for credited medals by operating a push button. Is provided.

  The player switches the payout mode or the credit mode by operating the C / P button 14. In the credit mode, when a winning is established, medals corresponding to the number of payouts corresponding to the winning are credited.

  In the payout mode, when a prize is established, medals corresponding to the number of payouts corresponding to the prize are paid out from the medal payout opening 15 at the lower front, and the medals paid out from the medal payout outlet 15 are sent to the medal receiving unit 16. Can be stored.

  Note that winning means stopping the combination of the symbols related to the small combination on the activated line. The small combination is a combination in which medals are paid out when the small combination is established.

  In addition, by the operation of the maximum BET button 13 by the player, among the credited medals, the maximum number of medals that can be inserted at that time is inserted. By operating the maximum BET button 13, a winning line described later is activated.

  On the right side of the pedestal portion 10, a medal insertion slot 22 is provided. According to the medals inserted into the medal insertion slot 22, a winning line described later is activated.

  A selection button 24 and a decision button 25 are provided to the left of the medal insertion slot 22. The player can make an input to the menu screen or the like displayed on the liquid crystal display area 23 by using the selection button 24 and the determination button 25.

  Speakers 21L and 21R are provided on the left and right above the medal receiving portion 16. The speakers 21L and 21R output game sounds such as staging sound and notification sound according to the game situation.

  A start lever 6 is provided on the left side of the front surface of the pedestal portion 10. The start lever 6 rotates the reels 3L, 3C, 3R by a start operation of the player, and starts changing the symbols displayed in the symbol display areas 4L, 4C, 4R.

  At the center of the front of the pedestal portion 10, on the right side of the start lever 6, three stop buttons 7L for stopping the rotation of the three reels 3L, 3C, 3R respectively by the player's pressing operation (stop operation). , 7C and 7R are provided.

  Here, when the rotation of the three reels 3L, 3C, and 3R is performed, the first stop of the rotation of the reel is referred to as a first stop. The first stop is performed after the first stop, and the rotation of the two reels is performed. The second stop of the reel rotation performed when the rotation is being performed is referred to as a second stop. The second stop is performed after the second stop, and is performed last when the remaining one reel is rotated. The stop of the rotation of the reel is called a third stop.

  A stop operation for the player to make the first stop is referred to as a first stop operation. Similarly, a stop operation for making a second stop by a player is called a second stop operation, and a stop operation for making a third stop is called a third stop operation.

  A light-transmitting upper panel 101 is provided above the front door 1b, and an upper panel LED (Light Emitting Diode) 111 (another light emitter may be used instead of the LED) inside the upper panel 101. Is provided. The upper panel LED 101 emits light in accordance with the effect contents to be described later.

  The liquid crystal display area 23 is arranged on the front side of the reels 3L, 3C, 3R when viewed from the front side, displays an image, and is drawn on the reels 3L, 3C, 3R in the symbol display areas 4L, 4C, 4R. This is for transparently displaying the symbol. Note that the transmittance in the symbol display areas 4L, 4C, and 4R can be changed.

  The liquid crystal display area 23 displays the number of stored (credited) medals, and displays the number of paid out medals when winning is achieved. In addition, the liquid crystal display area 23 displays a frame image having a predetermined shape so as to surround the symbol display areas 4L, 4C, and 4R, and a predetermined image according to the effect content described later.

  A lower panel 102 is provided below the liquid crystal display area 23 and above the pedestal portion 10, and inside the lower panel 102, an LED 102 for the lower panel (another light emitter may be used instead of the LED). Is provided. The lower panel 102 emits light in accordance with the effect contents described later.

  A light transmissive waist panel 103 is provided below the pedestal portion 10, and a waist panel LED 103 (other light emitters may be used instead of the LEDs) is provided inside the light transmissive waist panel 103. The waist panel LED 103 emits light in accordance with the effect content to be described later.

  One symbol is displayed in each of the upper, middle, and lower rows in each of the vertically long rectangular symbol display areas 4L, 4C, and 4R, and each of the symbol display areas 4L, 4C, and 4R has a corresponding peripheral surface of the reel. Three of the arranged symbols are displayed. That is, the symbol display areas 4L, 4C, and 4R have a function as a so-called display window.

  Next, the winning line will be described with reference to FIG. The symbol display areas 4L, 4C, and 4R have five winning lines (the center line 8c, the bottom line 8d, and the cross line) connecting any of the upper, middle, and lower rows in the above-described symbol display areas 4L, 4C, and 4R. An up line 8a, a cross down line 8e, and an RB special line 8f) are provided.

  When the rotation of the reels 3L, 3C, and 3R is stopped, the gaming machine 1 determines whether a winning combination has been established or not based on the combination of symbols displayed on the activated pay line. Hereinafter, activated pay lines are referred to as activated lines, and activated pay lines are referred to as inactive lines.

  As shown in FIG. 2, the center line 8c is a line connecting the left / middle region D, the middle / middle region E, and the right / middle region F, respectively. The bottom line 8d is a line connecting the left / lower region G, the middle / lower region H, and the right / lower region I, respectively.

  The cross-up line 8a is a line connecting the left / lower region G, the middle / middle region E, and the right / upper region C, respectively. The cross-down line 8e is a line connecting the left / upper area A, the middle / middle area E, and the right / lower area I, respectively. The RB middle special line 8f is a line connecting the left / middle region D, the middle / lower region H, and the right / upper region C, respectively.

  In the present embodiment, in the BB gaming state (RB gaming state), only the special line 8f during RB becomes an active line by inserting two medals. On the other hand, in a game state other than the BB game state (RB game state), four pay lines of the center line 8c, the bottom line 8d, the cross-up line 8a, and the cross-down line 8e become effective lines by inserting three medals. Become.

  Note that the BB1 gaming state to the BB4 gaming state may be collectively referred to as a BB gaming state. The RB1 game state and the RB2 game state may be collectively referred to as an RB game state.

  Next, with reference to the symbol arrangement table shown in FIG. 3, the symbol rows arranged on the reels 3L, 3C, 3R will be described. FIG. 3 is a diagram showing an arrangement of symbols drawn on the outer peripheral surface on reels 3L, 3C, 3R of gaming machine 1 in the present embodiment.

  On the outer peripheral surfaces of the reels 3L, 3C, 3R, a symbol row in which 21 symbols of a plurality of types are arranged is drawn. Specifically, a pattern row composed of 7 red patterns, 1 Don pattern, 2 Don patterns, BAR pattern, wave pattern, 1 Bell pattern, 2 Bell patterns, 1 Cherry pattern, 2 Cherry patterns, and 2 replay patterns is drawn. ing.

  The symbol arrangement table is stored in the main ROM 32 of the main control circuit 60 described later. As shown in FIG. 3, the symbol arrangement table includes 1/21 rotation of the reels 3L, 3C, 3R in order to associate the rotation positions of the reels 3L, 3C, 3R with the symbols drawn on the outer peripheral surface of the reel. The symbol positions from "0" to "20" sequentially given for each are defined.

  Next, an upper portion of the gaming machine will be described with reference to FIGS. FIG. 4 is a view showing the upper front part of the gaming machine 1. FIG. 5 is a view showing a cross section near the display panel unit 110 of the gaming machine 1. FIG. 6 is a view showing the display panels 110Pa to 110Pd of the gaming machine 1. FIG. 7A is a diagram illustrating the left decorative panel 121L and the left infrared sensor 120L of the gaming machine 1, and FIG. 7B is a diagram illustrating the left infrared sensor 120L of the gaming machine 1.

  As shown in FIG. 4, a rectangular touch sensor module 781 is provided at the lower right of the liquid crystal display area 23. The liquid crystal display area 23 and the touch sensor module 781 constitute a touch panel.

  A predetermined command input or the like can be performed by a player touching a predetermined position displayed on the touch panel with, for example, a fingertip. The dimensions of the touch sensor module 781 and the positions provided are not limited to this embodiment, but may be any position such as one of the upper, lower, left, and right sides of the liquid crystal display area 23 and the position of almost the entire liquid crystal display area 23. It is.

  The touch sensor module 781 is, for example, a capacitance type device that can perform position input by touching a fingertip, a stylus, or the like, and can detect operations such as touch, flick, and pinch.

  A display panel unit 110 is provided in the upper center of the liquid crystal display area 23, and a left selection panel 151L and a right selection panel 151R are provided on the left and right sides of the display panel unit 110.

  A left decorative panel 121L and a right decorative panel 121R are provided on the upper left and right sides of the display panel unit 110. A CCD camera 121C described later is provided between the left decorative panel 121L and the right decorative panel 121R.

  As shown in FIG. 5, the display panel unit 110 includes four display panels 110Pa, 110Pb, 110Pc, and 110Pd having high light transmittance and excellent light guide (in the case where the display panels 110Pa to 110Pd are collectively referred to as a display panel 110P). And four LEDs 111, 112, 113, and 114.

  The display panels 110Pa to 110Pd are installed in a state where they are overlapped with a gap therebetween. A symbol is drawn on each of the display panels 110Pa to 110Pd, and the LED 111 to 114 provided individually emits light so that the symbol can be visually recognized by a player.

  Also, as shown in FIG. 6, a character pattern is drawn on each of the display panels 110Pa to 110Pd. Specifically, as shown in FIGS. 6A to 6D, the characters are drawn larger on the display panels 110Pa to 110Pd provided closer to the player as viewed from the player.

  Then, the symbols drawn on each of the display panels 110Pa to 110Pd can be more clearly recognized by the player as the brightness of the LED corresponding to the display panel 110P increases. The control of the brightness of the LEDs 111 to 114 is performed by a sub CPU 71 in a sub control circuit 70 described later.

  For example, the sub CPU 71 sets the LED 114 corresponding to the display panel 110Pc, the LED 113 corresponding to the display panel 110Pb, the LED 112 corresponding to the display panel 110Pb, and the LED 111 corresponding to the display panel 110Pa in order from the LED 114 corresponding to the display panel 110Pd provided on the back side as viewed from the player. By increasing the luminance (that is, causing the LED to emit light), the character appears to the player to approach the character.

  Note that the control of the LEDs 111 to 114 includes, from the LED 111 corresponding to the display panel 110Pa provided on the near side as viewed from the player, to the LED 112 corresponding to the display panel 110Pb, the LED 113 corresponding to the display panel 110Pc, and the display panel 110Pd. By increasing the luminance in the order of the corresponding LEDs 114, the player can also be shown to be moving away from the character.

  Thus, when changing the brightness | luminance of LED111-114 in order, it is preferable not to make it difficult to see a symbol repeatedly. For example, when increasing the luminance of the LED 112 after increasing the luminance of the LED 111, the luminance of a certain LED is increased, such as decreasing the luminance of the LED 111. Is preferably reduced.

  Further, regarding the symbol, the character may be drawn smaller as the display panel 110P provided closer to the player as viewed from the player, and may be drawn larger as the display panel 110P at the back. Further, a liquid crystal display device is provided further behind the display panel unit (or the display portion of the liquid crystal display device 5 is enlarged) so that a player can see an image displayed by the liquid crystal display device through the display panels 110Pa to 110Pd. It may be.

  As shown in FIG. 7A, a left infrared sensor 120L is provided behind the left decorative panel 121L. Although not shown, a right infrared sensor 120R is provided at the back of the right decorative panel 121R. Hereinafter, the description of the left decorative panel 121L and the left infrared sensor 120L is the same for the right decorative panel 121R and the right infrared sensor 120R.

  The infrared sensors 120L and 120R are so-called reflection-type infrared sensors, and can detect whether an object (for example, a player's hand) exists or approaches in the direction of outputting the infrared beam.

  As shown in FIG. 7B, the left infrared sensor 120L outputs an infrared beam in the direction of the arrow AR and receives the reflected infrared beam, whereby a player's hand or the like approaches the left selection panel 151L. Detect that Similarly, the right infrared sensor 120R detects whether the player's hand or the like has approached the vicinity of the right selection panel 151R.

  The infrared sensors 120L and 120R do not always operate, but operate when a billy get challenge effect described later is executed.

  Further, in the present embodiment, the reflection type infrared sensor is employed, but other sensors capable of detecting that a player's hand or the like approaches the vicinity of the left selection panel 151L and the right selection panel 151R may be employed. It may be. Further, the left selection panel 151L and the right selection panel 151R may be so-called touch sensors.

[Circuit configuration of gaming machine]
Next, referring to FIG. 8, the circuit configuration of gaming machine 1 including main control circuit 60, sub-control circuit 70 as a control unit, peripheral devices electrically connected to main control circuit 60 or sub-control circuit 70, and the like. Will be described. FIG. 8 is a diagram showing a circuit configuration of the gaming machine 1. As shown in FIG.

  The main control circuit 60 controls the progress of a series of games, such as determining an internal winning combination and controlling reel rotation. The main control circuit 60 has a microcomputer 30 disposed on a circuit board as a main component, and is further provided with a circuit for sampling random numbers. The microcomputer 30 includes a main CPU 31, a main ROM 32, and a main RAM 33.

  The main CPU 31 is connected to a clock pulse generation circuit 34, a frequency divider 35, a random number generator 36, and a sampling circuit 37.

  The main CPU 31 determines an internal winning combination based on a random number value and an internal lottery table described later, and stops the rotation of the reels 3L, 3C, and 3R based on the internal winning combination and a timing at which a stop operation is detected. Let it.

  Further, the main CPU 31 determines whether or not a combination has been established based on a combination of symbols displayed in the symbol display areas 4L, 4C, 4R when the rotation of the reels 3L, 3C, 3R is stopped. When the player has been established, the player is provided with a profit such as paying out a medal according to the established role.

  The clock pulse generation circuit 34 and the frequency divider 35 generate a reference clock pulse. The random number generator 36 generates a random number in a range from “0” to “65535”. The sampling circuit 37 extracts (samples) one random number value from the random numbers generated by the random number generator 36.

  In the gaming machine 1, the extracted random number value is stored in a random value storage area of the main RAM 33 described later. Then, an internal winning combination is determined in an internal lottery process, which will be described later, based on the random number value stored in the random value storage area of the main RAM 33 for each game.

  As a means for random number sampling, random number sampling may be performed in the microcomputer 30, that is, on the operation program of the main CPU 31. In that case, the random number generator 36 and the sampling circuit 37 can be omitted, or can be left as a backup for the random number sampling operation.

  The main ROM 32 of the microcomputer 30 stores programs relating to the processing of the main CPU 31, various tables, and the like.

  Various information obtained by the processing of the main CPU 31 is set in the main RAM 33. For example, information for specifying the extracted random number value, game state, internal winning combination, number of payouts, bonus carryover status, set value, etc., various counters and flags are set. Part of this information is transmitted to the sub-control circuit 70 by the aforementioned command.

  Main peripheral devices whose operation is controlled by a control signal from the microcomputer 30 include a hopper 40, stepping motors 49L, 49C, and 49R. Transmission and reception of signals between these actuators and the main CPU 31 are performed via the I / O port 38.

  The output section of the microcomputer 30 is connected to circuits for receiving the control signal output from the main CPU 31 and controlling the operations of the above-described peripheral devices and the like. Each circuit includes a motor drive circuit 39 and a hopper drive circuit 41.

  The hopper drive circuit 41 controls the drive of the hopper 40. Thereby, the payout of the medals stored in the hopper 40 is performed.

  The motor drive circuit 39 controls the drive of the stepping motors 49L, 49C, 49R. Thereby, rotation and stop of the reels 3L, 3C, 3R are performed.

  Further, the input unit of the microcomputer 30 is connected to each switch and each circuit for generating an input signal which triggers the output of a control signal to each circuit and each peripheral device described above. The switches and circuits include a start switch 6S, stop switches 7LS, 7CS, 7RS, a maximum BET switch 13S, a C / P switch 14S, a setting key SW20S, a medal sensor 22S, a reel position detection circuit 50, and a payout completion signal circuit 51. There is. Note that the stop switches 7LS, 7CS, 7RS are collectively referred to as a stop switch 7S.

  The start switch 6S detects a player's start operation on the start lever 6, and outputs a start signal for instructing start of the game to the microcomputer 30.

  The stop switches 7LS, 7CS, 7RS detect the player's stop operation on the stop buttons 7L, 7C, 7R, respectively, and stop the rotation of the reels 3L, 3C, 3R corresponding to the detected stop buttons 7L, 7C, 7R. A commanded stop signal is output to the microcomputer 30.

  The maximum BET switch 13S detects a player's insertion operation (press operation) on the maximum BET button 13 and outputs a signal for instructing insertion of medals from credited medals to the microcomputer 30.

  The C / P switch 14S detects a player's switching operation on the C / P button 14 and outputs a signal for switching between the credit mode and the payout mode to the microcomputer 30. When the mode is switched from the credit mode to the payout mode, a signal for instructing payout of medals credited to the gaming machine 1 is output to the microcomputer 30.

  The medal sensor 22S detects a medal inserted into the medal insertion slot 22 by a player's insertion operation, and outputs a signal indicating that a medal has been inserted to the microcomputer 30.

  The reel position detection circuit 50 detects a pulse signal from the reel rotation sensor and generates a signal for detecting the position of the symbol on each of the reels 3L, 3C, 3R.

  The payout completion signal circuit 51 determines that the payout of medals has been completed when the number of medals detected by the medal detection unit 40S (that is, the number of medals paid out from the hopper 40) reaches the specified number. Generate a signal to indicate.

  The sub-control circuit 70 performs various processes such as determination and execution of effect data based on various commands output from the main control circuit 60, such as a start command described later. The sub control circuit 70 does not input commands, information, and the like to the main control circuit 60, and one-way communication from the main control circuit 60 to the sub control circuit 70 is performed.

  The main peripheral devices and the like whose operations are controlled by the control signal from the sub-control circuit 70 include a liquid crystal display device 5 as a display unit for displaying an image on the liquid crystal display area 23, speakers 21L and 21R, LEDs 101 to 103, and a display. The panel unit 110 includes LEDs 111 to 114 and infrared sensors 120L and 120R.

  The sub-control circuit 70 determines an image to be displayed on the liquid crystal display device 5 based on the determined effect data and displays the image, determines and outputs light emission patterns of the various LEDs 101 to 103 and 111 to 114, and infrared sensors 120L and 120R. For example, it determines the production timing and effect sound to be output from the speakers 21L and 21R, and controls the output and the like such as the determination of the operation timing.

  The configuration of the sub-control circuit 70 in the present embodiment will be described later in detail.

  In the gaming machine 1, when a signal to start a game is output from the start switch 6S by the operation of the start lever 6 by the player on condition that a medal is inserted, a control signal is output to the motor drive circuit 39, and the stepping motor is output. The rotation of the reels 3L, 3C, 3R is started by drive control of the 49L, 49C, 49R (for example, excitation of each phase).

  At this time, the number of pulses output to the stepping motors 49L, 49C, 49R is counted, and the counted value is set in a predetermined area of the main RAM 33 as a pulse counter.

  In the gaming machine 1, when the pulse of "16" is output, the reels 3L, 3C, and 3R move by one symbol. The number of symbols moved is counted, and the counted value is set in a predetermined area of the main RAM 33 as a symbol counter. That is, each time the pulse counter counts “16” pulses, the symbol counter is updated by “1”.

  The symbol at the symbol position indicated by the symbol counter value (see FIG. 3) corresponds to the symbol located on the center line 8c. For example, when the symbol counter of the left reel 3L is "0", the bell at the symbol position "0" in the symbol arrangement table shown in FIG. 3 is located on the center line 8c.

  A reel index is obtained from the reels 3L, 3C, and 3R for each rotation, and is output to the main CPU 31 via the reel position detection circuit 50. By the output of the reel index, the pulse counter and the symbol counter set in the main RAM 33 are cleared to "0".

  In this way, the symbol position within the range of one rotation is specified for each of the reels 3L, 3C, and 3R. The distance that each symbol moves by one symbol by the rotation of the reel is called one frame. That is, moving the symbol by one frame corresponds to updating the symbol counter by “1”.

  A symbol arrangement table is stored in the main ROM 32 in order to associate the rotational positions of the reels 3L, 3C, 3R with the symbols drawn on the outer peripheral surface of the reel. The symbol arrangement table includes code numbers from “00” to “20” which are sequentially assigned at fixed rotation pitches of the reels 3L, 3C, and 3R based on the position at which the reel index is output. , And a symbol code for identifying the type of symbol provided corresponding to each code number.

  When a start signal is output from the start switch 6S, a random number value is extracted by the random number generator 36 and the sampling circuit 37. In the gaming machine 1, when the random value is extracted, it is stored in the random value storage area of the main RAM 33. Then, the internal winning combination is determined based on the random number value stored in the random value storage area.

  After the reels 3L, 3C, and 3R reach the constant speed rotation, when a stop signal is output from the stop switches 7LS, 7CS, and 7RS by a stop operation, based on the output stop signal and the determined internal winning combination, A control signal for stopping and controlling the reels 3L, 3C, 3R is output to the motor drive circuit 39. The motor drive circuit 39 controls the drive of the stepping motors 49L, 49C, 49R, and stops the rotation of the reels 3L, 3C, 3R.

  The gaming machine 1 stops the rotation of the reel 3 by pulling in the symbols related to the establishment of the internal winning combination by the maximum number of sliding frames, that is, by four frames, from the time when the stop operation is performed. Specifically, after the stop operation is detected by the stop switches 7LS, 7CS, and 7RS, the gaming machine 1 determines whether or not a symbol related to the establishment of the internal winning combination exists within four frames, When there is a symbol related to the establishment of the internal winning combination within four frames, the number of sliding frames is determined so that the symbol is stopped and displayed on the activated line, and the corresponding reel is stopped.

  In the case where a plurality of winning combinations are determined as the internal winning combinations, if there are a plurality of symbols related to the establishment of the internal winning combinations within four frames, the gaming machine 1 relates to the internal winning combinations having higher priority. The number of sliding frames is determined so that the symbols are stopped and displayed on the activated line.

  Basically, the first priority (highest priority) is a combination of symbols related to replay, and the second priority is a combination of symbols related to small wins. Next, the third priority is a combination of symbols related to the bonus.

  Further, when the stop operation is detected by the stop switches 7LS, 7CS, 7RS, the symbol position corresponding to the symbol counter of the relevant reel 3, that is, the symbol position at which the rotation of the reel 3 is stopped is set to the "stop start position". The symbol position obtained by adding the determined number of sliding frames (numerical range “0” to “4”) to the stop start position, that is, the symbol position at which the rotation of the reel 3 is stopped is referred to as “scheduled stop position”. The number of sliding frames is the rotation amount of the reel 3 from the time when the stop operation is detected by the stop switches 7LS, 7CS, 7RS to the time when the rotation of the corresponding reel 3 is stopped. 4 ".

  When the rotation of all the reels 3L, 3C, 3R is stopped, a process of searching for a display combination, that is, a process of determining whether a combination has been achieved or not has been performed based on the combination of symbols displayed on the activated line. The search for the display combination is performed based on a symbol combination table described later stored in the main ROM 32. In this symbol combination table, a combination of symbols related to a display combination and a corresponding payout are set.

  When it is determined that the combination of the symbols related to the winning is displayed by the search for the display combination, a control signal is output to the hopper drive circuit 41, and the hopper 40 is driven to pay out medals.

  At this time, the medal detection unit 40S counts the number of medals paid out from the hopper 40, and when the counted value reaches the designated number, a signal indicating completion of medal payout is output by the payout completion signal circuit 51. . As a result, a control signal is output to the hopper drive circuit 41, and the drive of the hopper 40 is stopped.

  When it is determined by the C / P switch 14S that the mode has been switched to the credit mode, if it is determined that the combination of the symbols related to the winning has been displayed, the payout number corresponding to the combination of the symbols related to the winning is stored in the main RAM 33. Add to credit counter.

  Further, the number of paid out medals is transmitted to the sub control circuit 70, and based on this, the liquid crystal display area 23 displays the number of paid out medals and the updated number of credits. Here, there is a case where the payout of medals or credits, which is performed when a combination of symbols related to winning is displayed, is simply referred to as “payout”.

  Next, a circuit configuration of the sub control circuit 70 will be described with reference to FIG. FIG. 9 is a diagram showing a circuit configuration of the sub-control circuit 70 of the gaming machine 1.

  The sub-control circuit 70 performs control for performing an effect related to a game using video, sound, light, and the like. The sub-control circuit 70 determines effect data based on various commands transmitted from the main control circuit 60 and input information from the selection switch 24S and the decision switch 25S, and performs various effect processes.

  The sub control circuit 70 includes a sub CPU 71 as processing means, a sub ROM 72 functioning as processing information storage means, a DRAM 73-1 (also referred to as “sub RAM 73-1”) functioning as control information storage means, an SRAM 73-2, a GPU 74, It has a VRAM 75, an A / D converter 78 and an amplifier 79.

  In addition, a touch sensor relay board 780 is connected to the sub CPU 71 via the serial communication relay board 76, and a touch sensor module 781 is connected to the touch sensor relay board 780.

  As shown in FIG. 4, the touch sensor module 781 is provided at a lower right position of the liquid crystal display area 23 of the gaming machine, and allows a player to perform a predetermined input with a fingertip or the like. The liquid crystal display area 23, the touch sensor module 781, and the touch sensor relay board 780 form a touch panel device.

  The touch sensor relay board 780 is one of sub-devices that can be connected to the sub CPU, and includes a touch sensor control LSI having a built-in ROM and RAM (not shown). The ROM functions as processing information storage means in which processing information is stored, and the RAM functions as control information storage means capable of reading and writing control information.

  The sub-control circuit 70 and the serial communication relay board 76 are connected by a UART, and data is transmitted and received between them. The UART is also connected between the serial communication relay board 76 and the touch sensor control LSI of the touch sensor relay board 780, and data is transmitted and received between them.

  Note that, in FIG. 9, the connection between the sub CPU 71 and the touch sensor relay board 780 and the connection between the serial communication relay board 76 and the touch sensor relay board 780 are shown as being connected by one line. However, the control line and the data line are constituted by separate lines, and their input and output lines are constituted by separate lines. The TxD terminal and the RxD terminal of the data line are mutually connected between devices to which the data line is connected.

  As shown by a two-dot chain line in FIG. 9, a scaler control board 77 and a camera relay board 790 may be connected to the serial communication relay board 76 in addition to the touch sensor relay board 780. In this case, the liquid crystal display device 5 is connected to the scaler control board 77, and the camera module 791 is connected to the camera relay board 790. When the scaler control board 77 is not connected, the liquid crystal display device 5 is connected to the sub CPU 71 via the GPU 74.

  In these plurality of sub-devices, the UART is connected between the scaler control board 77 and the touch sensor relay board 780 and between the touch sensor relay board 780 and the camera relay board 790 to perform serial transmission / reception communication. Will be.

  The selection switch 24S detects a player's operation on the selection button 24, and moves, for example, a display (for example, an icon) indicating which of the items to be selected displayed on the menu screen or the like is in a selected state. Is output to the sub CPU 71.

  The decision switch 25S detects a player's operation on the decision button 25, and outputs, for example, a signal indicating that the player has selected an item in a selected state to the sub CPU 71. That is, the player can select an item by pressing the select button 24 on the menu screen or the like until the item to be selected is in the selected state, and then pressing the enter button.

  The sub CPU 71 performs display control of the liquid crystal display device 5, output control of the speakers 21L and 21R, light emission control of various LEDs 101 to 103, 111 to 114, and the like based on a program stored in the sub ROM 72. Specifically, the sub CPU 71 receives various commands and the like from the main control circuit 60 and stores various information included in the commands in the sub RAM 73-1.

  The sub CPU 71 is connected to a later-described SRAM 73-2 (also referred to as a “backup RAM 73-2”). The data copied to the sub RAM 73-1 when the power is turned on is backed up in the backup RAM 73-2.

  All information in the main control circuit 60 is transmitted by a command, and the sub control circuit 70 can determine the state of the main control circuit 60 one by one. The sub CPU 71 executes the program while referring to the game state information, the internal winning combination information, and the like stored in the DRAM 73-1 to thereby execute the program, so that the liquid crystal display device 5, the speakers 21L and 21R, and the various LEDs 101 to 103, 111 to 114 And the like, to determine the contents of the effect to be performed by the effect device.

  Further, the sub CPU 71 controls the liquid crystal display device 5 via the GPU 74 based on the determined effect data, and controls the sound output from the speakers 21L and 21R and the light emission of the various LEDs 101 to 103 and 111 to 114. I do.

  The upper panel LED 101, the waist panel LED 102, and the lower panel LED 103 are actually composed of a plurality of LEDs, respectively, and are controlled by input / output processing of individually provided ports (not shown). Is done. Therefore, light emission can be individually controlled by each port.

  Further, the sub CPU 71 executes a random number acquisition program stored in the sub ROM 72 to acquire a random number value used for determining effect data and the like. However, when a random number generator and a sampling circuit are provided in the sub-control circuit 70 as in the main control circuit 60, this processing is unnecessary.

  As shown in FIG. 97, the sub ROM 72 includes an OS area 72a for storing an operating system, a sub control program storage area 72b for storing a program to be executed by the sub CPU 71, a game initialization setting data area 72c, A setting data area 72d, various program table areas 72e for storing various tables and the like, a program management data area 72f, an image data (still image / moving image) area 72g, a sound data area 72h, and an accessory movable data area 72i. And

  The sub-control program storage area 72b includes a device driver, an inter-board communication process for controlling communication with the main control circuit 60, an effect registration process for determining the contents of the effect, and LEDs 101 to 101 based on the registered LED data. LED control task for controlling light output by 103, 111 to 114, voice control task for controlling sound output by speakers 21L and 21R based on registered sound data, and based on registered animation data And a drawing control task for controlling display of an image by the liquid crystal display device 5.

  The various program table area 72e stores an effect lottery table, an error code table of the sub control circuit shown in FIG. 104, an error code table of the sub device shown in FIG. 105, a sub device communication check table shown in FIG. 102, and the like.

  The program management data area 72f stores a magic code, a program version, and the like. The image data (still image / moving image) area 72g stores animation data such as character object data. The sound data area 72h stores sound data such as BGM and sound effects. Further, the accessory movable data area 72i stores, for example, LED control data for performing a light lighting pattern and the like.

  As shown in FIG. 98, the sub RAM 73-1 stores a sub control game data area 73a-1 as a game data storage area, a sub control game data sum value area 73b-1, an area 73c-1, and a clerk operation setting. It includes a data area 73g-1, an error information history storage area 73d-1, a communication log collection ring buffer area 73e-1, and a communication error storage area 73f-1. The staff operation setting data registered in the staff operation setting data area 73g-1 is data in which setting items on the menu screen are stored.

  The sub control game data area 73a-1 stores data stored in the sub RAM 73-1 among information including game data relating to the progress of the game. The sub-control game data sum value area 73b-1 stores a sum value for a checksum of the game data stored in the sub-control game data area 73a-1. The area 73c-1 stores data in various processes.

  The sub control game data area 73a-1 and the work area 73c-1 are used as temporary work storage when the sub CPU 71 executes each program. The sub-control game data area 73a-1 includes, for example, commands transmitted from the main control circuit 60, effect data information, game state information, internal winning combination information, display combination information, various counters, and 4 to 8 bytes. Information such as an arbitrary magic code and various flags is stored.

  The error information history storage area 73d-1 stores error codes (FIG. 103, FIG. 103) indicating all error information detected by the communication error detection unit 71a, the procedure detection unit 71b, the data destruction detection unit 71c, the sub device error detection unit 71h, and the like. 104 and 105). In the error information history storage area 73d-1, an error information history is created by sequentially storing error codes.

  In the error information history storage area 73d-1, an error detected by the communication error detection unit 71a is stored as a COM error, and an error detected by the procedure detection unit 71b is stored as a procedure error. Further, the error detected by the data destruction detection means 71c is stored as a data destruction error, and the error detected by the sub device error detection means 71h is stored as a scalar error.

  As shown in FIG. 99, the backup RAM 73-2 includes a backup data 1 area 73a-2, a backup data 1 sum value area 73b-2, and a backup data 2 area 73c- which is a mirroring of the backup data 1 area 73a-2. 2, a backup data 2 sum value area 73d-2, an attendant backup data area 73e-2, an error information history storage area 73f-2, and an attendant backup data sum value area 73g-2.

  In the present embodiment, the backup data 1 area 73a-2 and the backup data 2 area 73c-2 are configured as a single backup RAM 73-2. In this specification, "mirroring" is used to mean copying data, and is not limited to copying data to another storage.

  The backup data 1 area 73a-2 and the backup data 2 area 73c-2 each have an arbitrary magic code of 4 to 8 bytes.

  Here, the data format of the transmission / reception command between the sub CPU 71 and the sub device such as the touch sensor relay board 780 and the content of the transmission / reception data will be described with reference to FIGS.

  FIG. 100 shows an example of a transmission / reception command data format. "STX" indicates a start text, "ADR" indicates a source ID and a destination ID, "CMD" indicates a command, and "DATA1" to "DATA256" indicate a data group of up to 256 bytes corresponding to the command. "ETX" indicates end text, and "SUM" indicates a sum value up to the end text.

  FIG. 101 is a table showing the contents of the transmission / reception command data format from “STX” to “SUM”. The transmission / reception command data is, for example, “ADR” of the command data transmitted from the touch sensor relay board 780 to the sub CPU 71 is “03h” of the ID of the touch sensor relay board 780 as the transmission source and ID of the sub CPU 71 as the transmission destination. If “02h” is indicated, “CMD” indicates “83h”, and “DATA1” indicates operation XY coordinate data by touch operation, the command data is transmitted from the touch sensor relay board 780 to the sub CPU 71. 5 shows that the data of the XY coordinate values on the touch sensor module input by the detected touch operation is transmitted.

  FIG. 102 shows a check table for sub-device communication. This table is used, for example, to determine whether the command type and command packet size of the data received by the touch sensor relay board 780 are correct.

  Based on this table, the sub CPU 71 determines, for example, as a determination 4, that the CMD from the touch sensor relay board 780 is a flick operation of 84h, and that the DATA size of the command is 5 bytes. When the determination 4 is completed, the process proceeds to the determination 5. This table is used in the sub-device received data determination processing shown in FIG.

  As shown in FIG. 103, the error information history storage area 73d-1 of the sub RAM 73-1 stores an error code (ERROR CODE in the figure), an error occurrence time (“occurrence” in the figure), and an error release time ( In the figure, “cancellation”) can be stored as 128 sets.

  The error code is 1-byte data, and the contents of the error code relating to the sub-control circuit include a communication error (“COM error” in the figure) and a procedure error (“procedure error” in FIG. 104). )), A data destruction error (“sum error” in the figure), and other errors. Each of the error occurrence time and the error release time includes a year of 2-byte data, a month of 1-byte data, a day of 1-byte data, a time of 1-byte data, a minute of 1-byte data, and a second of 1-byte data. I have.

  As shown in FIG. 105, the contents of the error code relating to the sub device include an error when the sub device ID does not exist (“SD COM DVC” in the figure) and an error when the sub device is reset. (“SD RST” in the figure), an error when the data size exceeds 256 bytes (“SD COM SIZ” in the figure), a case where the communication between the sub CPU 71 and the sub device is interrupted, An error when restarting (“SD DSC” or “SCL RSM” in the figure) or an error when the luminance, contour, or interpolation setting is abnormal with respect to the scaler relay board (“SD SET ERR1” to “SD SET ERR3 ”) and the touch sensor relay board when the data size exceeds 256 bytes. An error (“TS COM SIZ” in the figure) or an error when communication between the sub CPU 71 and the touch sensor relay board 780 is interrupted or restarted (“TS DSC” or “TS RSM” in the figure) And other errors.

  As shown in FIG. 87, the communication log collection ring buffer area 73e-1 stores an appropriate number of data groups including 256 command and parameter data sets and one corresponding buffer index. It functions as a buffer.

  As shown in FIG. 88, the communication error storage area 73f-1 stores 1024 data groups each including a data set of 256 commands and parameters and one corresponding buffer index. Further, the communication error storage area 73f-1 is provided with one buffer selection index indicating which buffer index is selected from among 1024 buffer indexes.

  As shown in FIG. 9, the sub CPU 71 includes a communication error detection unit 71a, a procedure detection unit 71b, a data destruction detection unit 71c, an error information registration unit 71d, a reception data log storage unit 71e, an error information A history display unit 71f, a two-dimensional code conversion unit 71g, and a sub device error detection unit 71h are provided.

  The communication error detection means 71a detects the occurrence of a communication error between the main control circuit 60 and the sub control circuit 70 by executing a COM error check process shown in FIG. .

  The procedure detecting means 71b detects that the game has progressed in a procedure different from the normal game procedure, that is, an abnormal procedure by executing the inter-command elapsed time monitoring process shown in FIG. 95A described later. ing.

  The data destruction detecting means 71c performs a BCC check process of a sub-control game data storage area shown in FIG. In particular, it is possible to detect data destruction relating to information received from the main control circuit 60, such as commands, effect data information, game state information, internal winning combination information, display combination information, various counters, and various flags.

  The error information registration unit 71d stores the error code of the detected error in the error information history storage area 73d-1 of the sub RAM 73-1 when the error detection unit detects the occurrence of the error. I have.

  Specifically, the error information registration unit 71d stores an error code (COM ERR ALM) of a COM error in the error information history storage area 73d-1 when the occurrence of a communication error is detected by the communication error detection unit 71a. It is supposed to.

  The error information registration unit 71d stores an error code (for example, BLS123PE) of the procedure error in the error information history storage area 73d-1 when the occurrence of the procedure error is detected by the procedure detection unit 71b. I have.

  The error information registration means 71d stores the error code (MEM ERR ALM) of the sum error in the error information history storage area 73d-1 when the occurrence of the sum error is detected by the data destruction detection means 71c. ing.

  Further, when the sub-device error detecting unit 71h detects, for example, an error of abnormal brightness setting of the scalar, the error information registering unit 71d stores the scalar error code (SCL SET ERR1) in the error information history storage area 73d-1. ) Is stored.

  In the error information history storage area 73d-1, an error information history is created by sequentially storing error codes.

  The reception data log storage unit 71e collects information on a reception log (hereinafter, also referred to as a communication log) by executing a main board communication reception data log storage process illustrated in FIG. By executing the main board communication reception data log temporary area storage processing shown in the figure, only one communication log is temporarily stored in the communication log collection ring buffer area 73e-1.

  Further, the reception data log storage unit 71e executes a main board communication error history data storage process shown in FIG. 94, which will be described later, so that when the communication error detection unit 71a detects the occurrence of a communication error, Up to 1024 communication logs relating to communication errors (hereinafter, referred to as communication error logs) are stored in the buffer area 73f-1.

  The error information history display means 71f causes the liquid crystal display device 5 to display the error information history stored in the error information history storage area 73d-1 when the door key 2 is operated in a predetermined manner.

  When a communication error is detected by the communication error detection unit 71a, the two-dimensional code conversion unit 71g stores a communication error log relating to the communication error stored in the communication error storage buffer area 73f-1 and data management as a transmission destination. The domain of the server 500 is converted into a two-dimensional code 300 as transmission information and transmitted to the error information history display means 71f.

  The sub-device error detecting means 71h, for example, when detecting that a reset has occurred in a sub-device such as the touch sensor relay board 780, stores the error code (TS) in the error information history storage area 73d-1 as a reset occurrence. RST).

  83, when the "COM error alarm" item 23b is selected in the liquid crystal display area 23 where the error information history is displayed, as shown in FIG. 83, the "COM error alarm" item 23b A two-dimensional code 300 corresponding to the communication error is displayed on the right side of.

  Here, as shown in FIG. 84, the transmission information included in the two-dimensional code 300 created by the two-dimensional code conversion means 71g has 192 bytes. The transmission information has a general configuration so that error information recorded by not only the gaming machine 1 of the model described in the present embodiment but also other gaming machines can be transmitted. Alternatively, the transmission information may include a game record of the player. Hereinafter, items included in the transmission information will be described.

  In the 0th to 28th bytes of the transmission information, a domain of the data management server 500 and data indicating a request to the data management server 500 are set. A housing unique code for identifying the gaming machine 1 is set in the 29th to 39th bytes of the transmission information.

  The 40th to 61st bytes of the transmission information are reserved areas. The time when the transmission information is generated is set in the 62nd to 67th bytes of the transmission information. In the 68th to 71st bytes of the transmission information, a model code indicating the type of the gaming machine 1 is set.

  The type number is set in the 72nd to 73rd bytes of the transmission information. Here, both the 72nd byte and the 73rd byte are set to 3FH.

  The error type is set in the 74th to 75th bytes of the transmission information. Error information is set in the 76th to 188th bytes of the transmission information. A checksum is set in the 189th to 191st bytes of the transmission information.

  The error information set in the 76th to 188th bytes of the transmission information has a command type consisting of one character (6 bits). When the command type is accompanied by a parameter, a parameter consisting of two characters (12 bits) is also provided after the one-character command type. FIG. 85 shows examples of command types and parameters.

  In the present embodiment, a door key switch 2S is connected to the sub CPU 71. The door key switch 2S detects that the door key 2 has been rotated leftward, and outputs the rotation to the sub CPU 71.

  Here, the error of the gaming machine 1 is reset by rotating the door key 2 to the left. The setting key switch 20S detects that a setting key for operating a setting value of the game has been operated, and outputs a detection signal from the main control circuit 60 to the sub CPU 71.

  When the occurrence of a communication error is detected by the communication error detection unit 71a, the error information registration unit 71d stores the error code of the communication error in the error information history storage area 73d-1 of the sub RAM 73-1. Then, the reception data log storage unit 71e stores the communication log in the communication log collection ring buffer area 73e-1 and also stores the communication error log in the communication error storage area 73f-1.

  If an error other than a communication error is detected by the procedure detecting means 71b other than the communication error detecting means 71a, the data destruction detecting means 71c, and other error detecting means, the error information registering means 71d detects the error. The code is stored in the error information history storage area 73d-1 of the sub RAM 73-1. Then, the reception data log storage unit 71e stores the communication log in the communication log collection ring buffer area 73e-1, but does not store the communication log in the communication error storage area 73f-1.

  When a predetermined operation is performed on the door key 2, the error information history display unit 71f causes the liquid crystal display device 5 to display the error information history stored in the error information history storage area 73d-1. In this case, as shown in FIG. 83, when the “COM error alarm” item 23b is selected in the liquid crystal display area 23, the error information history display unit 71f displays the communication information on the right side of the “COM error alarm” item 23b. The two-dimensional code 300 corresponding to the error is displayed.

  In the present embodiment, in order to display the error information history shown in FIG. 83 on the liquid crystal display device 5, two types of operation methods, that is, a normal operation and a simple operation by a clerk, are employed.

  In the normal operation, the clerk turns the door key 2 clockwise to release the lock mechanism of the front door 1b, turns on the setting key to turn on the setting key switch 20S, and the liquid crystal display area 23 shown in FIG. The menu screen is displayed. When an operator operates the operation key and selects the “error information history” item 23a, an error information history screen shown in FIG. 83 is displayed in the liquid crystal display area 23.

  On the other hand, in the simple operation, the clerk turns the door key 2 counterclockwise to reset the error, and holds the state for a certain time, for example, 5 seconds or more, so that the error information history screen shown in FIG. It is displayed.

  The sub device error detecting means 71h detects the presence or absence of a communication error between the sub CPU 71 and a sub device such as the scaler control board 77 or other errors. For example, an error detected by executing a sub device command receiving process shown in FIG. 117 described below is stored in the error information history storage area 73d-1 by the error information registration unit 71d according to the content of the error. The head is stored as an error code other than STX or ETX not received (SD COM STX).

  The error code is included in the error information history created in the error information history storage area 73d-1.

  The sub CPU 71 has a built-in RTC 70a that is a dedicated circuit for clocking. An external RTC 70c is connected to the sub CPU 71 as a backup for the built-in RTC 70a. A battery 70b is connected to the external RTC 70c and the SRAM 73-2. The built-in RTC 70a and the external RTC 70c are processed by an RTC control task shown in FIG.

  The GPU 74 performs a process for displaying an image on the liquid crystal display device 5 based on an image display command or the like received from the sub CPU 71. Data required for the processing performed by the GPU 74 is expanded in the VRAM 75 at the time of startup. The GPU 74 generates image data by superimposing the image data developed in the VRAM 75 in order from the background image located at the rear to the image located at the front, and supplies the image data to the liquid crystal display device 5.

  As a result, an image corresponding to the effect data determined by the sub CPU 71 is displayed on the liquid crystal display area 23 by the liquid crystal display device 5. When the scaler control board 77 is provided, the size of the original image of the displayed image can be selected.

  The VRAM 75 has two frame buffers of a write image data area and a display image data area. The write image data area stores image data generated by the GPU 74 as a display image. The image data to be displayed on the liquid crystal display device 5 is stored.

  The GPU 74 causes the liquid crystal display device 5 to sequentially display image data by switching these frame buffers alternately (that is, switching banks).

  The A / D converter 78 converts digital sound data selected by the sub CPU 71 based on the effect data into analog sound data, and transmits the analog sound data to the amplifier 79. The amplifier 79 amplifies the analog sound data received from the A / D converter 78 based on a sound volume adjusted by a sound volume adjusting knob (not shown) provided in the gaming machine 1, and the speakers 21L and 21R. Send to As a result, a sound corresponding to the effect data determined by the sub CPU 71 is output from the speakers 21L and 21R.

[Game state]
Next, transition of the gaming state will be described with reference to FIG. The main gaming states managed by the main control circuit 60 include a general gaming state, an RT1 gaming state, an RT2 gaming state, an RT3 gaming state, an RT4 gaming state, and a BB gaming state (a general term for the BB1 gaming state to the BB4 gaming state). Although not shown, there are an SB game state where only one game coexists with another game state, an RB1 game state that operates in the BB1 game state to the BB3 game state, and an RB2 game state that operates in the BB4 game state.

  First, in the general gaming state, the SB spilled eyes (SB spilled eyes 1 to SB spilled eyes 12) are displayed on the activated line, and the state transits to the RT1 gaming state. Next, in the RT1 game state, the one-step-up lip 1 is displayed on the activated line, thereby transiting to the RT2 game state. Next, in the RT2 game state, the raising two-step lip (raising two-step lip 1, raising two-step lip 2) and the second raising (the second raising 1 to the second raising 3) are displayed on the activated line, so that RT3 is displayed. Transition to the gaming state.

  Further, in the RT2 game state or the RT3 game state, the SB spilled eyes (SB spilled eyes 1 to SB spilled eyes 12) are displayed on the activated line, thereby transiting to the RT1 game state. In the RT1 gaming state to the RT3 gaming state, the push order bell failure (the pushing order bell failure 1 to the pushing order bell failure 4) is displayed on the activated line, thereby transiting to the normal gaming state.

  In the general gaming state, the RT1 gaming state to the RT3 gaming state, when the BB (BB1 to BB4) is determined as the internal winning combination, the state transits to the RT4 gaming state. In the RT4 gaming state, a transition is made to the BB gaming state by displaying BB (BB1 to BB4). When a predetermined number of medals (270 or 60 medals) are paid out in the BB gaming state, the state transits to the normal gaming state.

  Next, an internal lottery table determination table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. FIG. 11 is a diagram showing an example of an internal lottery table determination table of gaming machine 1 in the present embodiment.

  The internal lottery table determination table includes an internal lottery table used to determine an internal winning combination in an internal lottery process described later, corresponding to a game state (on / off of each game state flag described later), and a number of lotteries. Is stipulated. Thus, for example, when only the SB gaming state flag and the RT1 gaming state flag are “1 (ON)”, the “internal SB1 RT1 gaming state internal lottery table” is selected as the internal lottery table, and the number of lotteries is determined. “49” is selected.

  Next, an internal lottery table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIGS. FIG. 12 is a diagram in which examples of the internal lottery table for the general gaming state and the internal lottery table for the RT1 gaming state to the internal lottery table for the RT4 gaming state of the gaming machine 1 according to the present embodiment are combined into one.

  FIG. 13 is a diagram showing an example of the RB1 gaming state internal lottery table of the gaming machine 1 according to the present embodiment.

  FIG. 14 is a diagram showing an example of the RB2 gaming state internal lottery table of gaming machine 1 in the present embodiment. The lottery values corresponding to the winning number “1” in FIG. 12 are “1000” in the internal lottery table for the general gaming state in SB, the internal lottery table for the RT1 gaming state in SB, and the internal lottery table for the RT4 gaming state in SB. ”Is omitted because it is only“ 1001 ”.

  The internal lottery table is a table used when performing internal lottery in an internal lottery process described later, that is, when determining an internal winning combination. In the internal lottery table, a lottery value and a data pointer are defined for each winning number. The lottery value is a numerical value used to determine the data pointer. There are two types of data pointers, a small combination / replay data pointer and a bonus data pointer, which correspond to one or more internal winning combinations.

  The abbreviation of the internal winning combination corresponding to the data pointer is shown in the right column of the winning number in the internal lottery tables shown in FIGS. On the right side of each internal lottery table shown in FIG. 13 and FIG. 14, symbols corresponding to the data pointer, which can be stopped and displayed on the line connecting the upper stage, the line connecting the middle stage, or the line connecting the lower stage, are displayed. The stop form is shown.

  For example, in the RB1 game state, when “25” is determined as the small role / replay data pointer, a stop operation is performed at a timing at which a don symbol can be stopped and displayed at the lower part of the left reel 3L and the lower part of the middle reel 3C. When the operation is performed, the don symbol is stopped and displayed at the lower part of the left reel 3L and the lower part of the middle reel 3C, but the stop operation is performed at the timing at which the don symbol can be stopped and displayed at the lower part of the right reel 3R. Even in this case, the don symbol is not stopped and displayed at the lower stage of the right reel 3R.

  On the other hand, if "28" is determined as the small role / replay data pointer, the stop operation is performed at a timing at which the don symbol can be stopped and displayed at the lower part of the left reel 3L, the lower part of the middle reel 3C, and the lower part of the right reel 3R. Is performed, the don symbol is stopped and displayed on the line connecting the lower tiers of the reels.

  In the stop form of the symbols aligned on the winning line in FIG. 13, “out of tempai” means that even when the stop operation is performed at a timing at which the don symbol can be stopped and displayed on the corresponding line, "Don symbol-Don symbol-Don symbol" means a stop form in which a line connecting the upper stage, a line connecting the middle stage, and a line connecting the lower stage of each reel are not stopped and displayed.

  On the other hand, “per tempai” means that a stop operation is performed on the corresponding line at a timing at which the don symbol can be stopped and displayed, so that “don symbol-don symbol-don symbol” connects the upper row of each reel. , A line connecting the middle line or a line connecting the lower line.

  Next, a method of determining a data pointer using a lottery value, that is, a method of internal lottery will be described. In the internal lottery, first, a random number value is extracted from a predetermined numerical value range “0-65535”, a lottery value corresponding to each winning number is sequentially subtracted from the extracted random number value, and a digit is performed. This is performed by determining whether or not the event has occurred. Significance is performed when the value to be subtracted is smaller, in other words, when the result of the subtraction is negative.

  For example, when the internal random determination table for the general gaming state is determined as the internal random determination table and the extracted random number value is “1500”, first, the main CPU 31 corresponds to the winning number “1” from “1500”. Subtracting the lottery value “1000” to be performed. The subtraction result is “1500−1000 = 500”, which is positive.

  Next, the main CPU 31 subtracts the lottery value “2100” corresponding to the winning number “2” from the value “500” after the subtraction. The subtraction result is "500-2100 = -1600", which is negative. Therefore, the main CPU 31 determines the winning number “2” as the internal winning combination, that is, “13” as the small combination / replay data pointer and “0” as the bonus data pointer.

  According to the internal lottery method, the larger the value specified as the lottery value, the higher the possibility that the data pointer of the corresponding winning number is determined. Note that the winning probability of each winning number is “the lottery value corresponding to each winning number / the number of all random numbers that may be extracted (“ 65536 ”)”.

  Note that various lotteries performed using a lottery value described later are the same as in the case of determining the data pointer. That is, in the lottery tables, lottery values are defined in association with items (for example, winning numbers) that may be selected by lottery. Hereinafter, the various lottery methods based on the lottery values are the same as the internal lottery methods, and a description thereof will be omitted.

  Next, the RT transition table will be described with reference to FIG. The RT transition table is a table used when updating a gaming state flag in an RT control process described later. As shown in FIG. 15, the RT transition table defines a display combination and, correspondingly, control contents for the gaming state flag.

  Specifically, when a combination of symbols related to any one of the pushing order bell failure 1 to the pushing order bell failure 4 is stopped and displayed on the activated line, all the game state flags are turned off. That is, the general game state is activated. Further, when the symbol combination relating to any one of the SB spilled eyes 1 to the SB spilled eyes 12 is stopped and displayed on the activated line, the RT1 game state flag is turned on. In addition, when the symbol combination related to the one-step-up lip 1 is stopped and displayed on the activated line, the RT2 gaming state flag is turned on. Also, when the combination of the symbols related to any one of the raising two-step lip 1, the raising two-step lip 2, and the raising two to the raising two 3 is stopped and displayed on the activated line, the RT3 gaming state flag is turned on. I do.

  In addition, pushing order bell failure 1 to pushing order bell failure 4, SB spilled 1 to SB spilled 12, raised 1 step lip 1, raised 2 step lip 1, raised 2 step lip 2, raised 2 to raised 2 3 is a case where the predetermined combination is determined as an internal winning combination, and when a stop operation is performed according to a predetermined stop operation sequence, the stop is performed in a stop operation sequence different from the predetermined stop operation sequence. This is a display combination that is likely to be stopped and displayed on the activated line when an operation is performed or when a stop operation is not performed at an appropriate timing, and the details will be described later.

  Next, with reference to FIG. 16 and FIG. 17, the bonus internal winning combination determination table and the small winning combination / replay internal winning combination determination table stored in the main ROM 32 of the main control circuit 60 will be described. FIG. 16 is a diagram illustrating an example of a bonus internal winning combination determination table of the gaming machine 1 according to the present embodiment. FIG. 17 is a diagram illustrating an example of a small winning combination / replay internal winning combination determination table of the gaming machine 1 according to the present embodiment. Hereinafter, the internal winning combination determination table for bonus and the internal winning combination determination table for small combination and replay are collectively referred to as an internal winning combination determination table.

  The internal winning combination determination table is a table used in determining an internal winning combination based on a data pointer in an internal lottery process described later. Each winning combination determined as an internal winning combination corresponding to the data pointer is defined in the internal winning combination determination table. Each winning combination corresponds to each bit stored in an internal winning combination storage area described later. Therefore, which winning combination is the internal winning combination can be identified by determining which bit in the internal winning combination storage area is “1”.

  In the bonus internal winning combination determination table shown in FIG. 16, the internal winning combinations corresponding to the bonus data pointers "1" to "5" are defined. When “5” is determined as the bonus data pointer, the combination of symbols related to SB is stopped and displayed on the activated line depending on whether or not the stop operation is performed in a predetermined stop order, or Then, the combination of the symbols related to any one of the SB spilled eyes 1 to the SB spilled eyes 12 is stopped and displayed on the activated line.

  In the small winning combination / replay internal winning combination determination table shown in FIG. 17, the internal winning combinations corresponding to the small winning combination / replay data pointers "1" to "31" are defined. For example, when "1" is determined as the small win / replay data pointer, the normal lip 1 and the one-step up lip 1 are the internal winning combination.

  When the small pointer / replay data pointer is determined to be “2”, the first stop operation is performed on the left reel 3L, the second stop operation is performed on the middle reel 3C, and the second stop operation is performed on the right reel 3R. Only when the three stop operations are performed, the combination of the symbols related to the one-step raise 1 is stopped and displayed on the activated line. On the other hand, when the stop operation is performed in any other stop operation order, the combination of the symbols related to the normal lip 1 is stopped and displayed on the activated line.

  Regarding the small pointer / replay data pointers "3" to "6", the stop operation order in which the symbol combination relating to the one-step-up rip 1 is stopped and displayed on the activated line is determined in advance. When the stop operation is performed in a stop operation sequence other than the above, the combination of the symbols related to the normal lip 1 is stopped and displayed on the activated line.

  Specifically, when the small part / replay data pointer “3” is determined, a first stop operation is performed on the left reel 3L, a second stop operation is performed on the right reel 3R, and a second stop operation is performed on the middle reel 3C. Only when the third stop operation is performed, the symbol combination related to the one-step lip 1 is stopped and displayed on the activated line.

  When the small part / replay data pointer "4" is determined, a first stop operation is performed on the middle reel 3C, a second stop operation is performed on the left reel 3L, and a third stop operation is performed on the right reel 3R. Is performed, the symbol combination relating to the one-step rip 1 is stopped and displayed on the payline.

  When the small part / replay data pointer “5” is determined, a first stop operation is performed on the middle reel 3C, a second stop operation is performed on the right reel 3R, and a third stop operation is performed on the left reel 3L. Is performed, the symbol combination relating to the one-step rip 1 is stopped and displayed on the payline.

  When the small pointer / replay data pointer “6” is determined, the symbol combination of the one-step lip 1 stops on the active line only when the first stop operation is performed on the right reel 3L. Is displayed.

  When “7” is determined as the small pointer / replay data pointer, only when the first stop operation is performed on the left reel 3L, the raising two-step lip 1, the raising two-step lip 2, The combination of the symbols related to any of the second raise 1, the second raise 2, and the second raise 3 is stopped and displayed on the payline.

  When the second raise 1, the second raise 2, and the second raise 3 are stopped and displayed on the activated line, the normal lip 1 or the raised one-step lip 1 is simultaneously stopped and displayed on the activated line. On the other hand, when the stop operation is performed in any other stop operation order, the combination of the symbols related to the normal lip 1 is stopped and displayed on the activated line.

  For the small role / replay data pointers "8" to "11", the combination of the symbols related to the raised two-step lip 1, the raised two-step lip 2, the raised second 1, the raised second 2, and the raised second 3 is valid. The stop operation sequence that is stopped and displayed on the line is predetermined, and when the stop operation is performed in a stop operation sequence other than this stop operation sequence, the combination of the symbols related to the normal lip 1 is displayed on the activated line. Stopped and displayed.

  Specifically, when the small part / replay data pointer “8” is determined, the first stop operation is performed on the middle reel 3C, the second stop operation is performed on the left reel 3L, and the second stop operation is performed on the right reel 3R. Only when the third stop operation is performed, the combination of the symbols related to one of the raising two-step lip 1, the raising two-step lip 2, the raising two stitches 1, the raising second stitch 2, and the raising second stitch 3 is on the active line. Will be stopped.

  When the small part / replay data pointer "9" is determined, the first stop operation is performed on the middle reel 3C, the second stop operation is performed on the right reel 3R, and the third stop operation is performed on the left reel 3L. Is performed, the combination of the symbols related to any of the raising two-step lip 1, the raising two-step lip 2, the raising second 1, the raising 2 and the raising 2 is stopped and displayed on the activated line. .

  When the small part / replay data pointer "10" is determined, a first stop operation is performed on the right reel 3R, a second stop operation is performed on the left reel 3L, and a third stop operation is performed on the middle reel 3C. Is performed, the combination of the symbols related to any of the raising two-step lip 1, the raising two-step lip 2, the raising second 1, the raising 2 and the raising 2 is stopped and displayed on the activated line. .

  When the small pointer / replay data pointer “11” is determined, the first stop operation is performed on the right reel 3L, the second stop operation is performed on the middle reel 3C, and the third stop operation is performed on the left reel 3L. Is performed, the combination of the symbols related to any of the raising two-step lip 1, the raising two-step lip 2, the raising second 1, the raising 2 and the raising 2 is stopped and displayed on the activated line. .

  When "12" is determined as the small pointer / replay data pointer, the symbol related to the bell is stopped and displayed in the middle of the middle reel 3C regardless of the stop operation order.

  If "13" is determined as the small role / replay data pointer, a first stop operation is performed on the left reel 3L, a second stop operation is performed on the middle reel 3C, and a third stop is performed on the right reel 3R. Only when an operation is performed, the symbol related to the bell is stopped and displayed in the middle of the middle reel 3C.

  On the other hand, when the stop operation is performed in any other stop operation order, a combination of symbols related to any one of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the activated line. When the symbol relating to the bell is stopped and displayed in the middle stage of the middle reel 3C, "bell 1 symbol (bell 2 symbol) -bell 1 symbol-" is displayed on any of the center line 8c, the cross-up line 8a, and the cross-down line 8e. Bell 1 symbol "is stopped and displayed.

  When a combination of symbols related to one of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the activated line, the symbols are displayed on the lower row of the left reel 3L, the lower row of the middle reel 3C, and the lower row of the right reel 3R. , "Bell 1 design (bell 2 design) -bell 1 design-bell 1 design" is stopped and displayed.

  Regarding the small pointer / replay data pointers "14" to "17", the stop operation order in which the symbol related to the bell is stopped and displayed in the middle stage of the middle reel 3C is determined in advance. When the stop operation is performed in the order, a combination of symbols related to any one of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the activated line.

  Specifically, when the small role / replay data pointer “14” is determined, a first stop operation is performed on the left reel 3L, a second stop operation is performed on the right reel 3R, and a second stop operation is performed on the middle reel 3C. Only when the third stop operation is performed, the symbol relating to the bell is stopped and displayed in the middle of the middle reel 3C.

  When the small part / replay data pointer “15” is determined, the symbol related to the bell is stopped and displayed in the middle stage of the middle reel 3C only when the first stop operation is performed on the middle reel 3C. .

  When the small part / replay data pointer “16” is determined, a first stop operation is performed on the right reel 3R, a second stop operation is performed on the left reel 3L, and a third stop operation is performed on the middle reel 3C. Is performed, the symbol relating to the bell is stopped and displayed in the middle of the middle reel 3C.

  When the small part / replay data pointer “17” is determined, a first stop operation is performed on the right reel 3R, a second stop operation is performed on the left reel 3L, and a third stop operation is performed on the middle reel 3C. Is performed, the symbol relating to the bell is stopped and displayed in the middle of the middle reel 3C.

  In the internal lottery table, when a small combination / replay pointer whose abbreviation indicates the stop operation order (push order) for the reels is determined, the suggested push order is a so-called correct answer push order. By performing the stop operation in the order of the pushing, each reel 3 is stopped so that the player is advantageous.

  For example, when the small role / replay pointer “2” (abbreviation “left center right bell”) is determined, a first stop operation is performed on the left reel 3L, a second stop operation is performed on the middle reel 3C, Only when the third stop operation is performed on the right reel 3R, the symbol related to the bell is stopped and displayed in the middle row of the middle reel 3C (payout number: 4 × 3 lines = 12), and the other pressing order In the case of, the symbol related to the bell is stopped and displayed at the lower stage of the middle reel 3C (payout number: 4 × 1 line = 4). The small combination / replay pointers whose abbreviations indicate the stop operation order (push order) for the reels are “2” to “11” and “13” to “17”.

  Next, the symbol combination table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. FIG. 18 is a diagram illustrating an example of a symbol combination table of the gaming machine 1 according to the present embodiment.

  In the symbol combination table, a combination of symbols related to the awarding of benefits displayed on the activated line, or a combination of symbols related to the transition of the game state, data indicating a display combination corresponding to the combination of the symbols, and a storage area type , And the number of payouts are defined. The data indicating the display combination is one of a display combination storage area 1 to a display combination storage area 7 (each of the display combination storage areas 1 to 7 is collectively referred to as a display combination storage area), each of which will be described later. Is the data stored in. In which display combination storage area the data is stored is defined by the storage area type.

  In the symbol combination table, BB1 to BB4, SB, normal lip 1, raising one-step lip 1, raising two-step lip 1, raising two-step lip 2, control lip 1 to control lip 3, bell, ice 1 , Cherry 1 to cherry 12, control role 1 to control role 3, BB middle role 1 to BB middle role 5, raising second 1 to raising second 3, pushing order bell failure 1 to pushing order bell failure 4, SB Spilled eyes 1 to SB spilled eyes 12 are defined.

  For example, the normal lip 1 is established when "replay symbol-replay symbol-replay symbol" is displayed on the activated line. Any one of various replays (normal lip 1, raising one-step lip 1, raising two-step lip 1, raising two-step lip 2, control lip 1 to control lip 3) is established, so that re-play is performed in the next game. Will be That is, the same number of medals as the number of inserted medals in a game in which any of the various replays is established are automatically inserted in the next game without being based on the insertion operation by the player.

  This allows the player to play the next game without consuming medals. Here, the above-mentioned payout of medals and re-games are examples of providing a game value. The bell is established when "ANY symbol-bell 1 symbol-ANY symbol" is displayed on the activated line. In addition, "ANY" indicates that any pattern may be used.

  Next, the bonus operation time table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. FIG. 19 is a diagram illustrating an example of a bonus operation table of the gaming machine 1 according to the present embodiment.

  The bonus operation time table is a table used when setting conditions for terminating the BB gaming state and the RB gaming state. The bonus operation time table defines end conditions for the BB1 game state to the BB4 game state, the RB1 game state, and the RB2 game state. Specifically, in the bonus operation time table, “270” is defined as the value of the bonus end number counter as the end condition of the BB1 gaming state to the BB3 gaming state.

  Also, as the end condition of the BB4 gaming state, “60” is defined as the value of the bonus end number counter. Note that the RB1 game state operates in the BB1 game state to the BB3 game state, and the RB2 game state operates in the BB4 game state. Further, in the bonus operation time table, “12” and “8” are defined for the values of the number of possible games and the number of possible winnings, respectively, as end conditions of the RB1 game state and the RB2 game state.

  Next, the pull-in priority table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIGS. FIG. 20 is a diagram illustrating an example of a pull-in priority table A of the gaming machine 1 according to the present embodiment, and FIG. 21 is a diagram illustrating an example of a pull-in priority table B of the gaming machine 1 according to the present embodiment. FIG. Hereinafter, the pull-in priority table A and the pull-in priority table B are collectively referred to as a pull-in priority table.

  When a plurality of winning combinations are determined as internal winning combinations, when the plurality of winning combinations can be drawn on the activated line, a symbol related to any of the winning combinations is preferentially displayed on the activated line. It specifies whether to stop. As described above, basically, the replay, the small combination (the larger the number of payouts, the higher the priority. In the case of JAC1 (7 out of 7 BBs), the priority is higher) and the bonus in the order of higher priority. It has become.

  However, in the present embodiment, there are a plurality of types of replays, and the priority of each replay differs depending on the condition. Therefore, a pull-in priority table A and a pull-in priority table B are provided for each condition.

  The pull-in priority table A is a table used at normal times (including during BB) and at the time of so-called correct push order, and the priority of each replay is raised two-step lip 1, raised two-step lip 2> raised one-step lip 1 > Normal lip 1> control lip 1−control lip 3.

  On the other hand, the pull-in priority table B is a table used when a so-called push order is incorrect, and the priority of each replay is a normal lip 1> a two-step lip 1, a two-step lip 2, a one-step lip 1> control The order is Lip 1 to Control Lip 3.

  Although not shown, when two or more hands related to the transition of the RT gaming state simultaneously serve as a display hand, which one is prioritized is determined in advance. In the present embodiment, in order from the role with the highest priority, two-step rip 1, two-step rip 2, two-step 1-two-step 3> one-step lip 1> SB spill-eye 1-SB spill Eye 12> push order bell failure 1−push order bell failure 4

  Next, a stop table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. FIG. 22 is a diagram showing an example of a stop table for the small reel / replay data pointer “15” at the time of winning and the first stop of the middle reel. In the stop table, stop data corresponding to the line data and the symbol positions “0” to “20” are defined. The symbol position is a symbol position located in the middle of the symbol display area when the stop operation is detected, and is a symbol position at which the rotation of the reel is started to stop.

  Although not shown, the main ROM 32 of the main control circuit 60 stores a small combination / replay data pointer and a plurality of stop tables according to the player's stop operation sequence. For example, when “5” is determined as the bonus data pointer, a first stop operation is performed on the right reel 3R, a second stop operation is performed on the left reel 3L, and a third stop operation is performed on the middle reel 3C. Is performed, a stop table in which the number of sliding frames in which none of the SB spilled lines 1 to 12 is stopped and displayed on the active line is selected.

  On the other hand, when the stop operation is performed in a stop operation order other than the stop operation order, when the stop operation for each reel is performed at a timing when the symbol combination related to the SB is not stopped and displayed, the SB spilling 1 A stop table in which the number of sliding frames is specified is selected such that a combination of symbols related to any one of the 〜SB spilled eyes 12 is stopped and displayed on the activated line.

  Next, the internal winning combination storage area, the display combination storage area, and the carryover combination storage area allocated to the main RAM 33 of the main control circuit 60 will be described with reference to FIGS. FIG. 23 is a diagram illustrating an example of an internal winning combination storing area of the gaming machine 1 according to the present embodiment. FIG. 24 is a diagram illustrating an example of a display combination storage area of gaming machine 1 according to the present embodiment. FIG. 25 is a diagram illustrating an example of a carryover combination storage area of the gaming machine 1 according to the present embodiment.

  As shown in FIG. 23, the internal winning combination storing area includes an internal winning combination storing area 1 to an internal winning combination storing area 5. The internal winning combination storage areas 1 to 5 are 8-bit data areas respectively allocated on the main RAM 33 and store internal winning combination information. Each internal winning combination storage area indicates which combination is an internal winning combination by storing data of “0” or “1” in an area of bits “0” to “7”.

  As shown in FIG. 24, the display combination storage area includes display combination storage areas 1 to 7. The display combination storage areas 1 to 7 are 8-bit data areas allocated on the main RAM 33, and store display combination information. Each display combination storage area indicates which combination is a display combination by storing data of “0” or “1” in an area of bits “0” to “7”.

  As shown in FIG. 25, the carryover combination storage area is an 8-bit data area allocated on the main RAM 33, and stores carryover combination information. The carryover combination storage area indicates which combination is a carryover combination by storing data of “0” or “1” in an area of bits “0” to “3”.

  Next, a game state flag storage area allocated to the main RAM 33 of the main control circuit 60 will be described with reference to FIG. FIG. 26 is a diagram illustrating an example of a gaming state flag storage area of the gaming machine 1 according to the present embodiment.

  As shown in FIG. 26, the game state flag storage area includes a game state flag storage area 1 and a game state flag storage area 2. The game state flag storage area is an 8-bit data area allocated on the main RAM 33, and indicates whether each game state flag is on or off. When the data in each area of the gaming state flag storage area are all “0”, it indicates that the game state is the normal gaming state.

  Next, the symbol storage area in the main RAM 33 of the main control circuit 60 will be described with reference to FIGS. FIG. 27 is a diagram illustrating a storage example of symbol storage area A (during non-RB) of gaming machine 1 in the present embodiment (when symbol position data of each reel is “0”). FIG. 28 shows a storage example of symbol storage area B (in RB) of gaming machine 1 according to the present embodiment (in the case where symbol position data of each reel is “9”, “8”, “9” from the left reel) FIG.

  The symbol storage area is an area for storing a symbol code corresponding to each of the symbol display areas 4L, 4C, and 4R constituting each activated line, and is provided for each activated line. For example, when the gaming state is a gaming state other than the RB gaming state, the center line 8c corresponds to the middle stage of the left symbol display region 4L, the middle stage of the middle symbol display region 4C, and the middle stage of the right symbol display region 4R. Stores the symbol code.

  Such a symbol storage area is also provided for other effective lines (cross down line 8e, bottom line 8d, cross up line 8a). When the gaming state is the RB gaming state, there is only one active line (the special line during RB 8f), and a special line during RB 8f is formed in the symbol storage area corresponding to the special line during RB 8f. A symbol code corresponding to each of the middle part of the left symbol display area 4L, the lower part of the middle symbol display area 4C, and the upper part of the right symbol display area 4R is stored.

  The symbol storage area shown in FIG. 27 shows a symbol storage area when a symbol code is stored when the symbol position data of each reel is “0”. The case where the symbol position data is “0” means that the symbol at the symbol position “0” on each of the reels 3L, 3C, and 3R (7 symbols on the left reel 3L, 7 symbols on the middle reel 3C, and red on the right reel 3R). 7 symbols are displayed in the middle of the left symbol display area 4L, the middle of the middle symbol display area 4C, and the middle of the right symbol display area 4R.

  Therefore, in this case, the symbol storage area corresponding to the upper part of the left symbol display area 4L is the symbol (wave symbol) of the symbol position "1", and the symbol storage area corresponding to the lower row of the left symbol display area 4L is the symbol position " A symbol code indicating the symbol “20” (replay symbol) is stored. The symbol storage area corresponding to the upper part of the middle symbol display area 4C has the symbol (replay symbol) of the symbol position “1”, and the symbol storage area corresponding to the lower row of the middle symbol display area 4C has the symbol position “20”. A symbol code indicating a symbol (one cherry symbol) is stored.

  Further, the symbol storage area corresponding to the upper part of the right symbol display area 4R is the symbol at the symbol position “1” (Cherry 1 symbol), and the symbol storage area corresponding to the lower row of the right symbol display area 4R is the symbol position “20”. (A bell 1 symbol) is stored.

  Next, various lottery tables stored in the sub-ROM 72 of the sub-control circuit 70 will be described with reference to FIGS. Each lottery table defines a lottery value (for each condition depending on the table), and the lottery is performed in the same manner as the lottery process in the internal lottery process described above. Note that the lottery values are defined so that their sum is “65536”.

  First, the navigation mode shift lottery table will be described with reference to FIGS. FIG. 29 is a diagram illustrating an example of the navigation mode shift lottery table A of the gaming machine 1 according to the present embodiment. FIG. 30 is a diagram illustrating an example of the navigation mode shift lottery table B of the gaming machine 1 according to the present embodiment. FIG. 31 is a diagram illustrating an example of the navigation mode shift lottery table C of the gaming machine 1 according to the present embodiment.

  The navigation mode shift lottery table is a table used when determining the shift destination navigation mode from the current navigation mode. In the navigation mode shift lottery table A, lottery values are specified according to the current navigation mode, the value of the small role / replay data pointer, and the like. In the navigation mode shift lottery table B, lottery values are defined according to the current navigation mode, the value of the bonus data pointer, and the like. In some cases, the same navigation mode as the current navigation mode is determined as the destination navigation mode (that is, the navigation mode does not transition).

  Next, with reference to FIG. 32, the navi game state transition standby number random determination table will be described. FIG. 32 is a view illustrating an example of a navi game state transition standby number random determination table of the gaming machine 1 according to the present embodiment.

  The navigation game state transition standby number lottery table is a table used when determining the navigation game state transition standby number. As shown in the figure, the navigation game state transition waiting number table defines a lottery value for each of three patterns A, B, and C, and each pattern is used properly according to conditions at the time of lottery.

  Next, with reference to FIG. 33, a description will be given of the navi game state 3 shift waiting number random determination table. FIG. 33 is a diagram illustrating an example of the navi game state 3 shift standby number random determination table of the gaming machine 1 according to the present embodiment.

  The navi game state 3 shift standby number lottery table is a table used when determining the navi game state 3 shift standby number. In the navigation game state 3 shift waiting number table, a lottery value is defined according to a value of a navigation game number counter described later or the like.

  Next, with reference to FIGS. 34 to 37, the navi game state 3 addition game number lottery table will be described. FIG. 34 is a diagram illustrating an example of the navi game state 3 addition game number lottery table A of the gaming machine 1 according to the present embodiment. FIG. 35 is a diagram illustrating an example of the navi game state 3 addition game number lottery table B of the gaming machine 1 according to the present embodiment. FIG. 36 is a diagram illustrating an example of the navi game state 3 addition game number lottery table C of the gaming machine 1 according to the present embodiment. FIG. 37 is a diagram illustrating an example of the navi game state 3 addition game number lottery table D of the gaming machine 1 according to the present embodiment.

  The navigation game state 3 addition game number lottery table is a table used when determining the navigation game state 3 addition game number. In the navigation game state 3 addition game number lottery tables A to C, lottery values are defined according to the current navigation mode, the value of the small combination / replay pointer, the value of the bonus data pointer, and the like. The same lottery value is used in the navigation game state 3 addition game number lottery table D regardless of the current navigation mode.

  Next, the navi game state 3 addition lottery mode lottery table will be described with reference to FIGS. FIG. 38 is a diagram illustrating an example of the navi game state 3 addition lottery mode lottery table A of the gaming machine 1 according to the present embodiment. FIG. 39 is a diagram illustrating an example of the navi game state 3 addition lottery mode lottery table B of the gaming machine 1 according to the present embodiment. FIG. 40 is a diagram illustrating an example of the navi game state 3 addition lottery mode lottery table C of the gaming machine 1 according to the present embodiment. FIG. 41 is a diagram illustrating an example of the navi game state 3 addition lottery mode lottery table D of the gaming machine 1 according to the present embodiment.

  The navigation game state 3 addition lottery mode lottery table is a table used when determining the navigation game state 3 addition lottery mode. In the navigation game state 3 addition lottery mode lottery table A and the navigation game state 3 addition lottery mode lottery table D, lottery values are defined according to the current navigation mode. In the navigation game state 3 addition lottery mode lottery table B, lottery values are defined according to the current navigation mode, bonus data pointer, and the like. In the navigation game state 3 addition lottery mode lottery table C, a lottery value is defined according to the current navigation mode and the small combination / replay data pointer.

  Next, the navigation set number random determination table will be described with reference to FIG. FIG. 42 is a diagram illustrating an example of a navigation set number random determination table of the gaming machine 1 according to the present embodiment.

  The navigation set number lottery table is a table used when determining the navigation set number. In the navigation set number lottery table, two patterns of a lottery value used when BB3 is won (determined as an internal winning combination) and the production game is stopped, and a lottery value used in other cases are provided. Stipulated.

  Next, the navi game state 3 navi game number addition lottery table will be described with reference to FIG. FIG. 43 is a diagram illustrating an example of a navi game state 3 navi game number addition lottery table of the gaming machine 1 according to the present embodiment.

  The navi game state 3 navi game number addition lottery table is a table used when performing the navi game state 3 navi game number addition lottery. In the navi game state 3 navi game number addition lottery table, lottery values are defined according to the navi game state 3 addition lottery mode, the value of the small combination / replay pointer, the value of the bonus data pointer, the game state, and the like. I have.

  Next, the navigation game number special addition lottery table will be described with reference to FIG. FIG. 44 is a view illustrating an example of the navi game number special addition lottery table of the gaming machine 1 according to the present embodiment.

  The navigation game number special addition lottery table is a table used when determining the number of navigation games to be added in the navigation game number special addition lottery. In the navigation game number special addition lottery table, lottery values are defined according to the value of the navi game state 3 continuation counter, the type of BB determined as the internal winning combination, and the like.

  Next, a billy get challenge occurrence random determination table will be described with reference to FIG. FIG. 45 is a diagram illustrating an example of a billy get challenge occurrence random determination table of gaming machine 1 according to the present embodiment.

  The billy get challenge occurrence random determination table is a table used when performing a billy get challenge occurrence random determination. In the billy get challenge occurrence lottery table, a lottery value is defined according to the current navigation mode, whether or not an effect game is stopped, and whether a billy get challenge success flag is on or off.

  Next, a billy get challenge control counter lottery table will be described with reference to FIG. FIG. 46 is a diagram illustrating an example of a billy get challenge control counter lottery table of the gaming machine 1 according to the present embodiment.

  The billy get challenge control counter lottery table is a table used when performing a billy get challenge control counter lottery. In the billy get challenge control counter lottery table, lottery values are defined in accordance with the presence / absence of the stoppage of the game for production, the value of the small combination / replay pointer, the value of the bonus data pointer, and the like.

  Next, a billy get challenge correct answer lottery table will be described with reference to FIG. FIG. 47 is a view illustrating an example of a billy get challenge correct answer lottery table of the gaming machine 1 according to the present embodiment.

  The billy get challenge correct answer lottery table is a table used when determining the correct answer (left, right, both) at the time of the billy get challenge. In the billy get challenge correct answer lottery table, a lottery value is defined according to a situation when a billy get challenge is generated. Specifically, when the game is not in the RB gaming state, or when the game is in the RB gaming state and there is no staging game stop, the left or right is determined with a probability of 50% each as a correct answer. On the other hand, when there is an effect game stop in the RB gaming state, both (the correct answer on the left and right) are determined with a probability of “2048/65536 (= 3.125%)” as the correct answer.

  Next, a lottery table when no billy get challenge is selected will be described with reference to FIG. FIG. 48 is a diagram illustrating an example of a lottery table when no billy get challenge is selected in the gaming machine 1 according to the present embodiment.

  The lottery table when no billy get challenge is selected is used to determine whether or not to win if the player does not select left or right in the billy get challenge (that is, when no billy get challenge is selected). It is a table that is used. In the lottery table when the billy get challenge is not selected, a lottery value is defined according to the result of the billy get challenge correct answer lottery performed based on the billy get challenge correct answer lottery table.

  According to the lottery table when the billy get challenge is not selected, even if the player does not select the left or right, if the result of the billy get challenge correct lottery is left or right, 50% Is won with a probability of. In addition, if the result of the billy get challenge correct lottery is both, the winning is performed with a probability of 100%.

[Control operation of main control circuit]
Next, the control operation of the main CPU 31 of the main control circuit 60 will be described with reference to the flowcharts shown in FIGS.

  First, the reset interrupt process by the main CPU 31 of the main control circuit 60 will be described with reference to FIG. FIG. 49 is a diagram showing a flowchart of the reset interrupt processing by the main CPU 31 performed by the main control circuit 60 of the present embodiment. Further, the main CPU 31 generates a reset interrupt by turning on the power and applying a voltage to the reset terminal, and sequentially executes the reset interrupt processing stored in the main ROM 32 based on the occurrence of the reset interrupt. Is configured to do so.

  First, the main CPU 31 clears the designated storage area (step S1). Specifically, the main CPU 31 clears the designated storage area of the main RAM 33 at the end of the previous game. More specifically, the main CPU 31 erases data in the writable area in the main RAM 33 used in the previous game, writes parameters necessary for the current game in the writable area in the main RAM 33, The start address is specified in the sequence program.

  Next, the main CPU 31 performs a bonus operation monitoring process (step S2).

  Next, the main CPU 31 performs a medal acceptance / start check process (step S3). In the medal acceptance / start check process, the insertion number counter is updated by checking the medal sensor 22S and the maximum BET switch 13S, and the input of the start switch 6S is checked. The main CPU 31 activates the winning line by a medal acceptance / start check process.

  Next, the main CPU 31 performs a process of extracting a random value and storing it in the random value storage area (step S4). Specifically, the main CPU 31 extracts a random value from the range of “0” to “65535” by the random number generator 36 and the sampling circuit 37 and stores the extracted random value in the random value storage area of the main RAM 33.

  Next, the main CPU 31 performs an internal lottery process (step S5). Specifically, the main CPU 31 refers to the internal lottery table determination table (see FIG. 11), the internal lottery table (see FIGS. 12 to 14), and the internal winning combination determination table (see FIGS. 16 and 17). To determine the internal winning combination.

  Next, the main CPU 31 transmits start command data to the sub control circuit 70 (step S6). The start command includes a “start” command accompanying the start operation of the player, game state information, internal winning combination information (small winning combination / replay data pointer, bonus data pointer and internal winning combination storing area), and bonus carryover state. It includes carryover status information indicating whether or not there is any information, and information such as a lock flag.

  When the sub-control circuit 70 receives the "start" command, a monitoring timer activation process (step S1824) of the inter-command elapsed time monitoring process in the main board communication process of the sub CPU of FIG. . The following command data is transmitted to the sub-control circuit 70 in the same manner.

  Next, the main CPU 31 determines whether or not the lock flag is on (step S7). When determining that the lock flag is on, the main CPU 31 turns off the lock flag and executes a lock effect (also referred to as effect game stop) for 5 seconds (step S8), and proceeds to the process of step S9. . The lock effect is an effect that delays the rotation start of the reel 3. On the other hand, when the main CPU 31 determines that the lock flag is not on, the process directly proceeds to step S9.

  Next, the main CPU 31 sends a "turning drum rotation start" command to the sub control circuit 70 to request the start of rotation of all reels (step S9). When the start of the rotation of all the reels is requested, the rotation start processing and the acceleration control processing of the reels 3L, 3C, 3R are performed. When the sub-control circuit 70 receives the “turning drum rotation start” command, a monitoring timer stop process (step S1826) of the inter-command elapsed time monitoring process in the main board communication process of the sub CPU of FIG. Will be.

  Next, the main CPU 31 waits for a constant speed of reel rotation (step S10).

  Next, the main CPU 31 performs a reel stop control process (step S11). In the reel stop control process, the main CPU 31 stops the rotation of each of the reels 3L, 3C, 3R based on a stop signal transmitted from the stop switches 7LS, 7CS, 7RS by a player's stop operation.

  Next, the main CPU 31 performs a display combination search process (step S12). In the display combination search process, the main CPU 31 determines the display combination and the payout number based on the combination of the symbols displayed on the activated line as a result of stopping the rotation of all the reels 3L, 3C, 3R.

  Next, the main CPU 31 performs an RT control process (step S13).

  Next, the main CPU 31 transmits display command data (step S14). The display command includes information such as display combination information indicating a display combination and payout number information indicating a payout number.

  Next, the main CPU 31 performs a medal payout process (step S15). Specifically, in the payout mode, the main CPU 31 drives and controls the hopper 40 by the hopper drive circuit 41 based on the number of payouts, and pays out medals. The credit counter set in the RAM 33 is updated.

  In the medal payout processing, when processing such as payout of medals is completed, the main CPU 31 transmits a “payout end” command to the sub control circuit 70. When the sub-control circuit 70 receives the “payout end” command, a monitoring timer operation status check process (step S1828) of the inter-command elapsed time monitoring process in the main board communication process of the sub CPU of FIG. Will be.

  Next, it is determined whether or not the bonus operation is being performed (step S16). Specifically, it is determined whether or not the game is in the BB1 game state to the BB4 game state or the SB game state. At this time, when the main CPU 31 determines that the bonus operation is being performed, the main CPU 31 performs a bonus end check process (step S17), and shifts to a process of step S18. On the other hand, when the main CPU 31 determines that the bonus operation is not being performed, or after ending the processing in step S17, the main CPU 31 next performs a bonus operation check process (step S18). The process proceeds to S1.

  As described above, the main CPU 31 executes the processing from step S1 to step S18 as the processing in one game (one game), and when the processing in step S18 ends, executes the processing in step S1 to execute the processing in the next game. Move to

  Next, the bonus operation monitoring process will be described with reference to FIG. FIG. 50 is a view illustrating a flowchart of the bonus operation monitoring process performed by the main control circuit 60 according to the present embodiment.

  First, the main CPU 31 determines whether or not the game is in the BB gaming state (step S31). At this time, when the main CPU 31 determines that the game is in the BB gaming state, the process proceeds to step S32. On the other hand, when the main CPU 31 determines that the game is not in the BB gaming state, the main CPU 31 ends the bonus operation monitoring process.

  When the main CPU 31 determines in the process of step S31 that it is in the BB gaming state, it then determines whether or not it is in the RB gaming state (step S32). At this time, when determining that the game is in the RB gaming state, the main CPU 31 ends the bonus operation monitoring process.

  On the other hand, when determining that the game is not in the RB gaming state, the main CPU 31 performs an RB operation process corresponding to the type of BB based on the bonus operation table (see FIG. 19) (step S33), and performs the bonus operation monitoring process. Terminate. Specifically, when the game state is the BB1 game state to the BB3 game state, the RB1 game state is operated, and when the game state is the BB4 game state, the RB2 game state is operated.

  Next, the internal lottery process will be described with reference to FIGS. FIGS. 51 and 52 are flowcharts showing the internal lottery processing performed by the main control circuit 60 according to the present embodiment.

  First, the main CPU 31 refers to the internal lottery table determination table (see FIG. 11) and determines the type of the internal lottery table and the number of lotteries based on the gaming state flag (step S61). Next, the main CPU 31 acquires a random number value from the random number value storage area and sets it as a judgment random number value (step S62). Next, the main CPU 31 sets “1” as an initial value of the winning number (step S63).

  Next, the main CPU 31 refers to the internal lottery table and acquires a lottery value based on the winning number (step S64). Next, the main CPU 31 subtracts the lottery value from the random number for determination, and sets the subtraction result as a random number for determination (step S65). Specifically, the main CPU 31 subtracts the lottery value obtained in the process of step S64 from the random number for determination stored in the random number storage area for determination, and updates the random number storage area for determination based on the subtraction result. .

  Next, the main CPU 31 determines whether or not a digit has been subtracted in the subtraction process of step S65, that is, whether or not the subtraction result has a negative value (step S66). At this time, when the main CPU 31 determines that the digit is carried out, the main CPU 31 acquires a small combination / replay data pointer and a bonus data pointer based on the winning number (step S70), and proceeds to the processing of step S71.

  On the other hand, when the main CPU 31 determines that the digit is not shifted, it then subtracts “1” from the number of lotteries and adds “1” to the winning number (step S67). Next, the main CPU 31 determines whether or not the number of lotteries is “0” (step S68).

  When the main CPU 31 determines that the number of lotteries is “0” in the processing of step S68, the small CPU / replay data pointer and the bonus data pointer are each set to “0” (step S69). Move on to processing. On the other hand, when the main CPU 31 determines that the number of lotteries is not “0”, the process proceeds to step S64. Thereafter, the main CPU 31 repeats the processing from step S64 to step S68 until the number of lotteries becomes “0” or a digit is performed.

  After ending the processing in step S69 or step S70, the main CPU 31 next refers to the small winning combination / replay internal winning combination determination table (see FIG. 17) and sets the internal winning combination based on the small combination / replay data pointer. A role is acquired (step S71). Next, the main CPU 31 updates the internal winning combination storing area according to the internal winning combination storing area (step S72).

  Next, the main CPU 31 determines whether or not the carryover combination storage area is “00000000” (step S73). At this time, when the main CPU 31 determines that the carryover combination storage area is not “00000000”, the process proceeds to step S80. On the other hand, when the main CPU 31 determines that the carryover combination storage area is “00000000”, the main CPU 31 refers to the bonus internal winning combination determination table (FIG. 16) and acquires the internal winning combination based on the bonus data pointer (FIG. 16). Step S74).

  Next, the main CPU 31 determines whether or not the SB is an internal winning combination (step S75). At this time, when the main CPU 31 determines that the SB is the internal winning combination, the main CPU 31 updates the internal winning combination storing area according to the SB (step S76), and proceeds to the process of step S80. On the other hand, when determining that SB is not the internal winning combination, the main CPU 31 determines whether BB is the internal winning combination (step S77).

  When the main CPU 31 determines that BB is not the internal winning combination in the process of step S77, the main CPU 31 shifts to a process of step S80. On the other hand, when determining that BB is the internal winning combination, the main CPU 31 updates the carryover combination storage area according to BB (step S78), turns on the RT4 gaming state flag (step S79), and performs the processing of step S80. Move to

  When the main CPU 31 determines that the carryover combination storage area is not “00000000” in the processing of step S73, and determines in the processing of step S77 that BB is not the internal winning combination, the processing of steps S76 and S79. Then, the logical sum of the carryover combination storage area and the internal winning combination storage area 1 is calculated, and the result is stored in the internal combination combination storage area 1 (step S80).

  Next, the main CPU 31 determines whether or not the game is in the RB2 game state (step S81). When determining that the game is not in the RB2 gaming state, the main CPU 31 ends the internal lottery process. On the other hand, when determining that the game is in the RB2 gaming state, the main CPU 31 performs a lock lottery in which the winning is achieved with a probability of 1/64 (step S82). Next, the main CPU 31 determines whether or not the result of the lock lottery is a winning (step S83). If the winning is determined, the main CPU 31 turns on the lock flag (step S84), and ends the internal lottery process. On the other hand, when the main CPU 31 determines that the result of the lock lottery is not a winning, the main CPU 31 ends the internal lottery process as it is.

  In addition, the main CPU 31 performs the lottery of the internal winning combination by repeatedly executing the processes of steps S64 to S68 in the internal lottery process. Specifically, the main CPU 31 sequentially subtracts the lottery value from the extracted random number value, and thereby sets the small combination / replay data pointer and the bonus data pointer corresponding to the winning number at the time of performing the digit shift. The internal winning combination is determined based on the determined data pointers and the internal winning combination determination table.

  Further, in the present embodiment, the lock lottery in which the RB2 game state is won with a probability of 1/64 is performed. However, the lock lottery is performed during the normal state (general game state, RT1 game state to RT3 game state). It may be. In the lock lottery, when a specific small combination (for example, a small combination replay data pointer of "18" to "22") or a bonus combination (BB1 to BB4) is internally won, the winning probability is high. The lottery may be performed by setting the winning probability so that

  Next, a reel stop control process will be described with reference to FIG. FIG. 53 is a diagram showing a flowchart of the reel stop control processing performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 sets “3” in the stop button inactivity counter (step S101), and then acquires a stop table corresponding to the internal winning combination (step S102).

  Next, the main CPU 31 determines whether a valid stop button has been pressed (step S103). An effective stop button is a stop button for which a stop operation has not been performed. At this time, when the main CPU 31 determines that a valid stop button has been pressed, the process proceeds to step S104. On the other hand, when determining that the valid stop button has not been pressed, the main CPU 31 executes the process of step S103 again. That is, the main CPU 31 repeats the process of step S103 until a stop operation corresponding to a valid stop button is detected.

  When the main CPU 31 determines in the process of step S103 that a valid stop button has been pressed, the operation of the corresponding stop button is invalidated (step S104). Next, the stop table is reselected according to the operation stop button (stop order) (step S105).

  Next, the main CPU 31 sets “5” as the number of checks (step S106). Next, the main CPU 31 refers to the pull-in priority table (see FIGS. 20 and 21) and, based on the internal winning combination, the symbol with the highest priority within the range of the number of checks from the symbol position corresponding to the symbol counter. A position is searched (step S107).

  Next, the main CPU 31 determines the number of sliding symbols based on the stop table, the symbol position corresponding to the symbol counter, and the search result, and sets the expected stop position (step S108). Next, the main CPU 31 transmits a reel stop command (step S109). The reel stop command includes information such as stop reel type information indicating which reel has stopped, stop start position information indicating a stop start position, and slip frame number information indicating the number of slip frames.

  Next, the main CPU 31 refers to the symbol arrangement table (see FIG. 3), acquires a symbol code based on the stop reel, the expected stop position, and the game state, and stores it in the symbol storage area (step S110).

  Finally, the main CPU 31 determines whether or not there is a valid stop button (step S111). At this time, when the main CPU 31 determines that there is no effective stop button, the main CPU 31 ends the reel stop control processing. On the other hand, when determining that there is a valid stop button, the main CPU 31 proceeds to the process of step S103. Thereafter, the main CPU 31 repeats the processing from step S103 to step S111 until it is determined that there is no effective stop button.

  Next, the display combination search process will be described with reference to FIG. FIG. 54 is a diagram showing a flowchart of the display combination search process performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 clears the display combination storage area (step S121).

  Next, the main CPU 31 specifies a head address of the symbol storage area (step S122). Specifically, the main CPU 31 designates the address corresponding to the center line 8c as the head address when the gaming state is a gaming state other than the RB gaming state, and when the gaming state is the RB gaming state, the main CPU 31 specifies RB. The address corresponding to the middle special line 8f is designated as the head address.

  Next, the main CPU 31 specifies the start address of the symbol combination table (see FIG. 18) (step S123). Specifically, the main CPU 31 designates an address corresponding to BB1 as a start address.

  Next, the main CPU 31 compares the symbol combination specified in the symbol combination table with the symbol combination stored in the symbol storage area (step S124).

  Next, as a result of the comparison in the process of step S124, the main CPU 31 determines whether or not the combination of the symbols defined in the symbol combination table matches the combination of the symbols stored in the symbol storage area (step S124). Step S125). At this time, when the main CPU 31 determines that the combination of the symbols defined in the symbol combination table does not match the combination of the symbols stored in the symbol storage area, the process proceeds to step S129, When it is determined that they match, data indicating the storage area type and the display combination is obtained from the symbol combination table (step S126).

  Next, the main CPU 31 stores the logical sum of the display combination storage area corresponding to the acquired storage area type and the data indicating the acquired display combination in the display combination storage area (step S127).

  Next, the main CPU 31 acquires the number of payouts from the symbol combination table and adds the number to the payout number counter (step S128).

  When the main CPU 31 determines that the combination of the symbols defined in the symbol combination table does not match the combination of the symbols stored in the symbol storage area in the process of step S125, or ends the process of step S128. Then, the address corresponding to the next combination in the symbol combination table is designated (step S129).

  Next, the main CPU 31 determines whether or not an end code is stored at the address specified in the processing of step S129 (step S130). At this time, when the main CPU 31 determines that the end code is not stored, the process proceeds to step S124. On the other hand, when determining that the end code is stored, the main CPU 31 then determines whether or not all the valid lines have been searched, that is, whether or not the processing of steps S124 to S130 has been performed on all the valid lines. It is determined (step S131).

  When the main CPU determines in the processing of step S131 that all the valid lines have been searched, the main CPU terminates the display combination search processing. On the other hand, when the main CPU determines that all the effective lines have not been searched, then the main CPU specifies an address corresponding to the next effective line in the symbol storage area (step S132), and proceeds to the process of step S123.

  Next, the RT control process will be described with reference to FIG. FIG. 55 is a diagram showing a flowchart of the RT control process performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not the BB is being carried over (RT4 gaming state) (step S161). At this time, when the main CPU 31 determines that the BB is being carried over, the main CPU 31 ends the RT control process. On the other hand, when determining that the BB is not being carried over, the main CPU 31 determines whether or not the BB is being carried out (step S162). Specifically, it is determined whether any of the BB gaming state flags is on.

  When the main CPU 31 determines that BB is being performed in the process of step S162, the main CPU 31 ends the RT control process. On the other hand, when determining that the game is not in the BB state, the main CPU 31 refers to the RT transition table (see FIG. 15), and updates the gaming state flag based on the display combination if necessary (step S163). ), Terminate the RT control process.

  Next, the bonus end check processing will be described with reference to FIG. FIG. 56 is a view showing a flowchart of the bonus end check processing performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not BB is being performed (step S141). At this time, when the main CPU 31 determines that it is not during BB, the main CPU 31 turns off the SB gaming state flag (step S142) and ends the bonus end check processing. On the other hand, when it is determined that BB is being performed, the main CPU 31 determines whether the value of the bonus end number counter is “0” (step S143).

  When determining that the value of the bonus end number counter is “0”, the main CPU 31 performs a bonus end time process (step S144). Specifically, the BB gaming state flag and the RB gaming state flag that are on are turned off. Next, the main CPU 31 transmits a bonus end command (step S145), and ends the bonus end check processing.

  On the other hand, when determining that the value of the bonus end number counter is not “0”, the main CPU 31 subtracts “1” from the value of the number-of-playable-times counter (step S146), and determines whether the display combination is a small combination. Is determined (step S147). At this time, when the main CPU 31 determines that the display combination is not the small combination, the main CPU 31 shifts to the processing of step S149. On the other hand, when determining that the display combination is the small combination, the main CPU 31 subtracts “1” from the value of the winning number counter (step S148), and proceeds to the process of step S149.

  Next, the main CPU 31 determines whether or not the value of the possible winning number counter or the number of available games counter is “0” (step S149). At this time, when the main CPU 31 determines that neither the value of the winning number counter nor the value of the game number counter is “0”, the main CPU 31 ends the bonus end check processing. On the other hand, when the main CPU 31 determines that the value of the possible winning number counter or the value of the possible number of games counter is “0”, the main CPU 31 performs an RB ending process (step S150), and ends the bonus ending check process. . In the RB end processing, processing such as turning off the RB gaming state flag that is on is performed.

  Next, the bonus operation check processing will be described with reference to FIG. FIG. 57 is a diagram showing a flowchart of the bonus operation check processing performed by main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not the display combination is BB (any of BB1 to BB4) (step S171). At this time, when the main CPU 31 determines that the display combination is not BB, the process proceeds to step S174. On the other hand, when determining that the display combination is BB, the main CPU 31 performs a bonus activation process (step S172). In the bonus operation time process, the game state flag is turned on and the value of the bonus end number counter is set according to the game state to be operated with reference to the bonus operation time table (FIG. 19). Next, the main CPU 31 turns off the RT4 gaming state flag, clears the carryover combination storage area (step S173), transmits a bonus start command (step S176), and ends the bonus operation check processing. The bonus start command includes information indicating the type of the bonus to be started and the like.

  When the main CPU 31 determines in the process of step S171 that the display combination is not BB, then the main CPU 31 determines whether the display combination is SB (step S174). At this time, when the main CPU 31 determines that the display combination is not SB, the process proceeds to step S177. On the other hand, when determining that the display combination is SB, the main CPU 31 performs a bonus operation-time process (step S175). In the bonus operation process, the SB game state flag is turned on with reference to the bonus operation table (FIG. 19). Next, the main CPU 31 transmits a bonus start command (step S176), and ends the bonus operation check processing.

  When the main CPU 31 determines in the process of step S174 that the display combination is not SB, then it determines whether the display combination is replay (step S177). At this time, when determining that the display combination is not the replay, the main CPU 31 ends the bonus operation check processing. On the other hand, when determining that the display combination is replay, the main CPU 31 copies the value of the inserted number counter to the automatically inserted number counter (step S178), and ends the bonus operation check processing. When a value is set in the automatic insertion number counter, the number of medals corresponding to the value is automatically inserted in the process of step S3 in the next game (the number of medals of the player does not decrease).

  Next, an interrupt process under the control of the main CPU will be described with reference to FIG. FIG. 58 is a diagram showing a flowchart of the interrupt processing under the control of the main CPU performed by the main control circuit 60 of the present embodiment. The interrupt processing under the control of the main CPU is an interrupt processing that occurs every predetermined cycle (1.1173 milliseconds in the present embodiment).

  First, the main CPU 31 interrupts the program that is being executed before calling the interrupt process under the control of the main CPU, and saves the address indicating the interrupted position and the values of various registers in predetermined areas of the main RAM 33. (Step S181). This is because when the interrupt processing under the control of the main CPU ends, the address indicating the interrupted position of the saved program and the values of various registers are restored, and the program is continuously executed from the interrupted point. It is.

  Next, the main CPU 31 performs an input port check process (step S182). Specifically, the main CPU 31 checks a signal from each switch such as the maximum BET switch 13S.

  Next, the main CPU 31 performs a reel control process (step S183). Specifically, when there is a request to start rotation of the reels in the reset interrupt processing (see FIG. 49), the main CPU 31 starts the rotation of the reels 3L, 3C, 3R and rotates the reels at a constant speed. Perform control. When the expected stop position is determined by the number of sliding frames determined in the reel stop control process (see FIG. 53), the main CPU 31 indicates the value of the symbol counter of the corresponding reel to indicate the expected stop position. When the value becomes the same as the value, control for stopping the reel is performed. For example, when the value indicating the expected stop position is “4”, the main CPU 31 performs control for stopping the corresponding reel when the value of the symbol counter becomes “4”.

  Next, the main CPU 31 performs a lamp drive control process (step S184). Next, the main CPU 31 restores the register with reference to the value saved in the main RAM 33 in the processing of step S181 (step S185). When this process ends, the interrupt process under the control of the main CPU is ended, and the program interrupted by the occurrence of the interrupt process under the control of the main CPU is continuously executed.

[Operation related to game of sub-control circuit]
Next, with reference to the flowcharts shown in FIGS. 59 to 79, the operation of the sub control circuit 70 relating to the game will be described.

  First, the effect registration process will be described with reference to FIG. FIG. 59 is a diagram showing a flowchart of the effect registration processing of the present embodiment.

  First, the sub CPU 71 sets a cycle of 4 ms in the effect registration process (step S310). Next, the sub CPU 71 extracts a message from the message queue (step S311). Next, the sub CPU 71 determines whether or not there is a message in the message queue (step S312). At this time, when the sub CPU 71 determines that there is no message in the message queue, the sub CPU 71 shifts to a process of step S316. On the other hand, when determining that there is a message in the message queue (step S314), the sub CPU 71 performs a backup creation process of creating backup data from the sub RAM 73-1 to the SRAM 73-2 (step S315).

  Next, the sub CPU 71 registers the animation data (step S316). Specifically, the sub CPU 71 registers the animation data based on the effect data registered in the effect content determination processing. Thereby, an image is displayed on the liquid crystal display device 5. That is, the sub CPU 71 transmits an image display command to the GPU 74 based on the effect data determined in the effect content determining process.

  The GPU 74 selects appropriate image data from the image data expanded in the VRAM 75 based on the received image display command, determines the display position and size of the image data, and prepares the image data in the VRAM 75. And store it in one of the specified frame buffers. The GPU 74 performs a bank switching process for exchanging the display image data area and the write image data area in the frame buffer area at a predetermined cycle (1/30 second). In the bank switching process, the GPU 74 outputs the image data written in the write image data area to the liquid crystal display device 5, replaces the display image data area with the write image data area, and outputs the image data to be displayed next. Write.

  Next, the sub CPU 71 registers sound data (step S317). Specifically, the sub CPU 71 registers sound data based on the effect data registered in the effect content determination processing. As a result, sound is output from the speakers 21L and 21R. Next, the sub CPU 71 registers the LED data (step S318). Specifically, the sub CPU 71 registers the LED data based on the effect data registered in the effect content determination processing. Thus, the various LEDs 101 to 103 and 111 to 114 are turned on and off. When this process ends, the sub CPU 71 returns to the process of step S311.

  Next, the effect content determination processing will be described with reference to FIG. FIG. 60 is a diagram showing a flowchart of the effect content determination processing of the present embodiment.

  First, the sub CPU 71 determines whether a start command has been received (step S351). At this time, when determining that the start command has not been received, the sub CPU 71 shifts to a process of step S354. On the other hand, when determining that the start command has been received, the sub-CPU 71 performs a start command receiving process (step S352), registers the start effect data (step S353), and ends the effect content determination process.

  Next, when the sub CPU 71 determines that the start command has not been received in the process of step S351, it then determines whether a reel stop command has been received (step S354). At this time, when the sub CPU 71 determines that the reel stop command has not been received, the sub CPU 71 shifts to a process of step S357. On the other hand, when determining that the sub CPU 71 has received the reel stop command, the sub CPU 71 performs a billy get challenge determination process (step S355), and registers the stop effect data according to the type of the operation stop button (step S355). S356), the effect content determination processing ends.

  Next, when the sub CPU 71 determines that the reel stop command has not been received in the process of step S354, it then determines whether a display command has been received (step S357). At this time, when determining that the display command has not been received, the sub CPU 71 shifts to a process of step S359. On the other hand, when determining that the display command has been received, the sub CPU 71 performs a display command receiving process (step S358), and terminates the effect content determination process.

  Next, when determining that the display command has not been received in the processing of step S357, the sub CPU 71 determines whether a BET command has been received (step S359). At this time, when determining that the BET command has not been received, the sub CPU 71 shifts to a process of step S361. On the other hand, when determining that the BET command has been received, the sub CPU 71 registers the effect data at the time of BET according to the number of inserted coins or the like (step S360), and ends the effect content determination processing.

  Next, when determining that the BET command has not been received in the process of step S359, the sub CPU 71 determines whether a bonus start command has been received (step S361). At this time, when the sub CPU 71 determines that the bonus start command has not been received, the sub CPU 71 shifts to a process of step S363. On the other hand, when the sub CPU 71 determines that the bonus start command has been received, it registers the bonus start effect data (step S362), and ends the effect content determination processing.

  Next, when determining that the bonus start command has not been received in the process of step S361, the sub CPU 71 determines whether a bonus end command has been received (step S363). At this time, when the sub CPU 71 determines that the bonus end command has not been received, the effect content determination processing ends. On the other hand, when determining that the bonus end command has been received, the sub CPU 71 performs a process at the time of receiving the bonus end command (step S364), registers the bonus end effect data (step S365), and ends the effect content determination process. Let it.

  Next, with reference to FIGS. 61 and 62, a process at the time of receiving a start command will be described. FIG. 61 and FIG. 62 are diagrams showing a flowchart of the processing at the time of receiving a start command according to the present embodiment.

  First, the sub CPU 71 determines whether or not BB is in progress (BB gaming state 1 to BB gaming state 4) (step S381). At this time, when it is determined that the BB is being performed, the sub CPU 71 performs the BB processing (step S382), and proceeds to the processing of step S400. On the other hand, when it is determined that the BB is not being performed, it is determined whether the BB carryover flag is on (step S383). The BB carry-over flag is a flag that is turned on from the next game in which one of BBs (BB1 to BB4) is internally won to the game in which the internally won BB is determined as a display combination. When determining that the BB carryover flag is ON, the sub CPU 71 shifts to a process of step S400, and when determining that the BB carryover flag is not ON, next, the navigation game state 3 addition game number and the lottery mode lottery The processing is performed (step S384).

  Next, the sub CPU 71 refers to the navigation mode transition lottery table A (FIG. 29) and performs the navigation mode transition lottery based on the current navigation mode, data pointer, and the like (step S385).

  The “navi mode” includes a navi mode 0 to a navi mode 4. The navigation is to notify the player of information that is advantageous to the player. The period during which the navigation is performed is called AT (assist time), and shifting the navigation mode from 0 to any of 1 to 4 is called AT winning (or ART winning).

  Next, the sub CPU 71 determines whether or not the game is a BB winning game (whether BB (BB1 to BB4) is won in the current game) (step S386). If the game is not a BB winning game, the process proceeds to step S388. On the other hand, if the game is a BB winning game, the navigation mode shift lottery is determined based on the current navigation mode, the bonus data pointer, and the presence or absence of the effect game stop by referring to the navigation mode shift lottery table B (FIG. 30). Is performed (step S387).

  Next, the sub CPU 71 determines whether or not the navigation mode has shifted from 0 to 1 to 4 as a result of the navigation mode shift lottery in the process of step S385 or the process of step S387 (step S388). At this time, if the navigation mode has not shifted from 0 to 1 to 4, the sub CPU 71 shifts to the processing of step S392, while if the navigation mode has shifted from 0 to 1 to 4, the ART first hit A time process is performed (step S389), and it is determined whether or not a BB winning game is performed (step S390). If it is not a BB winning game, the sub CPU 71 shifts to the process of step S400. On the other hand, if the game is a BB winning game, the standby number of navigation game state transition is randomly determined by referring to the navigation game state transition standby number lottery table (FIG. 32), and is set in the navigation game state transition standby counter (step S391). ), And proceeds to the process of step S400.

  Here, the navi game state includes a navi game state 0 to a navi game state 3. In the navi game state 0, navigation is not performed, and in the navi game state 1 to the navi game state 3, navigation is performed. Further, when the navigation mode shifts from 0 to 1 to 4, the navigation game state also shifts from 0 to 1 or 2. At this time, the game may be shifted immediately, or may be shifted after a predetermined number of games (the number of waiting for shifting to the navigation game state) has elapsed.

  In the navigation game state 1 or the navigation game state 3, the value of the navigation game number counter is not subtracted, and in the navigation game state 2, the value of the navigation game number counter is subtracted. The number of remaining games in the navigation game states 1 to 3 is managed by a navigation game number counter and a navigation set number counter. Even if the navigation game number counter changes from 1 to 0, the navigation set number counter is 1 or more. In this case, 50 is set in the navigation game number counter.

  Returning to the flowchart, if the sub CPU 71 determines in the processing of step S392 that the navigation mode has not shifted from 0 to 1 to 4, then the navigation game state shift waiting counter is 1 or more. Is determined (step S392). When the navi game state transition standby counter is 1 or more, the sub CPU 71 performs the navi game state transition processing during the standby state (step S393), and proceeds to the processing of step S400. On the other hand, when the navigation game state transition waiting counter is not 1 or more, it is determined whether or not the navigation game state is 1 (step S394).

  If the sub CPU 71 is in the navi game state 1, the sub CPU 71 performs the navi game state 1 navi game state transition process (step S395), and proceeds to the process of step S400. On the other hand, if it is not the navi game state 1, it is determined whether or not the navi game state 2 is present (step S396). At this time, if the navigation game state is 2, the sub CPU 71 performs a navigation game state transition process in the navigation game state 2 (step S397), and proceeds to the process of step S400.

  On the other hand, if it is not the navigation game state 2, it is determined whether or not the navigation game state 3 is present (step S398). At this time, if the navigation game state is 3, the sub CPU 71 performs a navigation game state transition process in the navigation game state 3 (step S399), and proceeds to a process of step S400. On the other hand, if it is not the navigation game state 3, the process proceeds to the process of step S400.

  Next, the sub CPU 71 performs a billy get challenge lottery process (step S400). The billy get challenge is an event that is performed when a predetermined condition is satisfied. Specifically, the billy get challenge is a billy get challenge effect (an effect of instructing to select left or right, for example, when "select left or right" is displayed on the liquid crystal display area 23). Meanwhile, before the player performs the third stop operation, the player holds his hand near one of the left selection panel 151L and the right selection panel 151R so as to be detected by the infrared sensors 120L and 120R (selection). Operation).

  At this time, when the correct answer (left, right, or both) determined by the billy get challenge correct answer lottery performed in advance matches the left and right selected by the player (when both correct answers are determined to match). , Billy Get Challenge succeeds and the navigation mode rises. It should be noted that even if the player does not hold the hand over any of them, if the lottery is determined by lottery when no billy get challenge is selected in advance, it is considered that the billy get challenge is successful.

  When the player holds his hand over a different one from the correct answer, the billy get challenge fails even if the lottery is won when no billy get challenge is selected. Further, in the present embodiment, it is determined whether or not the selection operation is performed before the third stop operation is performed. For example, the second stop operation is performed until the first stop operation is performed. It is also possible to determine whether or not the selection operation has been performed until is performed or until a predetermined time has elapsed.

  Furthermore, the determination as to whether or not the selection operation has been performed can be arbitrarily set, for example, after the start operation is performed and after the first stop operation is performed. In other words, the period for determining whether or not the selection operation has been performed can be an arbitrary period in one unit game (period in which the above-described steps S1 to S18 are performed). Any period (for example, from a start operation of a certain unit game to a third stop operation of the next unit game) over the game can be set.

  Next, the sub CPU 71 determines whether or not the navi game state is 1 to 3 and the pressing order is an internal winning combination (step S401). At this time, if the navi game state is 1 to 3 and the pushing sequence is the internal winning combination, the sub CPU 71 sets the navigating effect data (the navi for the player to establish a winning combination). The effect data to be performed is registered (step S402), and the process at the time of receiving the start command is ended. In other cases, the process upon receiving a start command is terminated.

  Next, the BB processing will be described with reference to FIG. FIG. 63 is a diagram showing a flowchart of the processing during BB of the present embodiment.

  First, the sub CPU 71 determines whether or not the game is in the BB gaming state 4 (step S421). At this time, if the game is in the BB4 gaming state, the sub CPU 71 performs a lottery process during BB4 (step S422) and ends the process during BB. On the other hand, when it is not the BB4 gaming state, the sub CPU 71 determines whether or not to change the navigation mode based on the data pointer, and updates the navigation mode according to the determination result (step S423). More specifically, if the small role / replay pointer is 28 to 31 (Don middle row, per Don lower row, per Don upper row, per Don middle row), the navigation mode is increased by 1 (however, (Navigation mode 4 is the upper limit.) Otherwise, the navigation mode remains unchanged.

  Although not shown, the sub CPU 71 registers don-matched effect data when the don symbols are aligned in the upper, middle or lower row. In the process of step S423, the navigation mode may be raised by a plurality of levels when a specific condition is satisfied. As the specific condition, for example, 31 out of 28 to 31 is determined as the small role / replay pointer, or a specific condition is determined when any of 28 to 31 is determined as the small role / replay pointer. Aligning to the line, etc.

  Next, the sub CPU 71 refers to the navi game state 3 addition game number lottery table C (FIG. 36), and determines the navi game state 3 addition game number according to the current navi mode and the small combination / replay pointer data pointer. A lottery is performed (step S424). Next, the sub CPU 71 determines whether or not five or more games have been won in this lottery (step S425). At this time, if five or more games have not been won (that is, 0 games), the sub CPU 71 ends the BB processing. On the other hand, when five or more games are won, the sub CPU 71 refers to the navi game state 3 addition lottery mode lottery table C (FIG. 40), and responds to the current navi mode and the small combination / replay data pointer. Then, the navigation game state 3 addition random determination mode is randomly determined (step S426).

  Next, the sub CPU 71 associates the number of navi game state 3 addition games won in the processing of step S424 and the navi game state 3 addition lottery mode determined in the processing of step S426 with each other, and stores them in the sub RAM 73-1. Is stored in the navigation game state 3 information storage area (step S427).

The navi game state 3 information storage area stores a maximum of 32 combinations of the number of navi game state 3 addition games and the navi game state 3 addition lottery mode. The stored information is processed by FIFO (First In, First Out). The number of combinations of the navi game state 3 addition game and the number of navi game state 3 addition lottery modes stored in the navi game state 3 information storage area are displayed on the liquid crystal display area 23 so that the player can grasp it. . Next, the navigation game state 3 transition flag is turned on (step S428), and the BB processing ends. The navigation game state 3 shift flag is a flag indicating whether or not information is stored in the navigation game state 3 information storage area (if stored, it is on).

  It should be noted that the number of sets of the navi game state 3 addition game and the number of navi game state 3 addition lottery modes stored in the navi game state 3 information storage area may be notified only in the navi 2 state. Further, the number of sets stored in the navigation game state 3 information storage area may be reported as it is (that is, “5” for 5 sets), or the number of sets stored in the navigation game state 3 information storage area. May be notified.

  For example, when the don-matched effect data described later is registered, or when the billy-get challenge successful effect data described later is registered during the BB4 game state, the navigation game state 3 is always added to the navigation game state 3 information storage area. Since the number of games and the navi game state 3 addition lottery mode are always stored, only the number of sets in which the effect data is registered may be displayed.

  In other words, only the number of pairs for which a definite effect (for example, a don-matched effect, a successful billy get challenge effect) in which the player can recognize the acquisition of the right to shift from the navi game state 2 to the navi game state 3 is performed is notified. It may be that. When the number of rights to shift from the navigation game state 2 to the navigation game state 3 is one or more, it is preferable to notify that at least the number of the rights is one or more.

  For example, in a case where only the number of pairs for which the above-described finalized effect has been performed is to be notified, the number of pairs stored in the navigation game state 3 information storage area is “5”, and the finalized effect is performed once. If this is not done, nothing is reported, but in such a case, it is reported that at least the number of sets stored in the navigation game state 3 information storage area is "1" or more. Is preferred.

  Next, the lottery process during BB4 will be described with reference to FIG. FIG. 64 is a diagram showing a flowchart of the lottery process during BB4 of the present embodiment.

  First, the sub CPU 71 refers to the billy get challenge occurrence lottery table (FIG. 45), and sets the current navigation mode, presence / absence of production game stoppage (on / off of the lock flag in the main control circuit), and billy get challenge success flag. In response, a billy get challenge occurrence lottery is performed (step S441). Next, the sub CPU 71 determines whether or not the lottery result is a winning (step S442).

  If the winning is not achieved, the sub CPU 71 performs the lottery process during BB4 as it is. On the other hand, if it is a winning, a billy get challenge process is performed (step S443), and then it is determined whether or not the effect game is stopped (the lock flag is turned on) (step S444). The sub CPU 71 performs lottery processing during BB4 when there is no production game stop. On the other hand, if there is an effect game stop, the sub CPU 71 registers the display panel unit effect data (step S445) and performs lottery processing during BB4.

  Next, the billy get challenge process will be described with reference to FIG. FIG. 65 is a diagram showing a flowchart of the billy get challenge process of the present embodiment.

  First, the sub-CPU 71 refers to the billy get challenge correct answer lottery table (FIG. 47), and performs the billy get challenge correct answer lottery in accordance with the occurrence state of the billy get challenge and the presence or absence of the effect game stop (step S461). Next, the sub CPU 71 performs lottery without billy get challenge selection according to the result of the billy get challenge correct answer lottery with reference to the billy get challenge non-selection lottery table (FIG. 48) (step S462).

  Next, the sub CPU 71 registers the above-mentioned billy get challenge effect (step S463), and ends the billy get challenge process. By registering the billy get challenge effect, the billy get challenge effect is executed immediately after the player presses the start lever 6.

  Next, with reference to FIG. 66, the navi game state 3 added game number and the lottery mode lottery process will be described. FIG. 66 is a view illustrating a flowchart of the navi game state 3 addition game number and the lottery mode lottery process of the present embodiment.

  First, the sub CPU 71 refers to the navigation game state 3 addition game number lottery table A (FIG. 34) and adds the navigation game state 3 according to the current navigation mode, the small combination / replay pointer, the bonus data pointer, and the like. The number of games is randomly determined (step S481). Next, the sub CPU 71 determines whether or not 5 or more games have been won as the number of games in the navi game state 3 addition game by this lottery (step S482).

  When five or more games have not been won, the sub CPU 71 shifts to the processing of step S486. When five or more games have been won, the sub CPU 71 then refers to the navigation game state 3 addition lottery mode lottery table A (FIG. 38). Then, the navigation game state 3 addition random determination mode is randomly determined according to the current navigation mode (step S483).

  Next, the sub CPU 71 associates the number of navi game state 3 addition games determined in the processing of step S481 with the navi game state 3 addition lottery mode determined in the processing of step S483, and associates the navi game state 3 information with each other. It is stored in the storage area (step S484).

  Next, the sub CPU 71 turns on the navigation game state 3 transition flag (step S485), and proceeds to the process of step S486.

  Next, the sub CPU 71 determines whether or not the game is a BB winning game (step S486). If the game is not a BB winning game, the navigation game state 3 added game number and the lottery mode lottery process are terminated. On the other hand, if the game is a BB winning game, the navigation game state, the bonus data pointer, and the presence / absence of the production game stop are referred to by referring to the navigation game state 3 addition game number lottery table B (FIG. 35). The number of gaming state 3 added games is randomly determined (step S487).

  Next, the sub CPU 71 determines whether or not five or more games have been won as the number of games for the navi game state 3 addition by this lottery (step S488). When five or more games have not been won, the sub CPU 71 ends the navigation game state 3 added game number and the lottery mode lottery process. On the other hand, when five or more games are won, the navigation game state 3 addition lottery mode lottery table B (FIG. 39) is then referred to according to the current navi mode, bonus data pointer, and presence / absence of production game stop. The lottery mode for the navi game state 3 addition is determined (step S489).

  Next, the sub CPU 71 associates the number of navi game state 3 addition games won in the processing of step S487 and the navi game state 3 addition lottery mode determined in the processing of step S489 with each other, and sets the navi game state 3 information It is stored in the storage area (step S490). Next, the sub CPU 71 turns on the navi game state 3 shift flag (step S491), and ends the navi game state 3 added game number and lottery mode lottery process.

  Next, the ART first hit processing will be described with reference to FIG. FIG. 67 is a diagram showing a flowchart of the ART first hit processing according to the present embodiment.

  First, the sub-CPU 71 refers to the number-of-navigation-set random determination table (FIG. 42) and randomly determines the number of navigation sets (step S501). Next, the sub CPU 71 sets the number of navi-sets determined by lottery in the navi-set number counter (step S502), and sets 50 in the navi-game number counter (step S503). Next, the sub CPU 71 subtracts 1 from the navigation set number counter (step S504), and terminates the ART initial hit processing.

  Next, with reference to FIG. 68, the navigation game state transition processing during the standby state will be described. FIG. 68 is a view illustrating a flowchart of the navigation game state transition processing during the standby state according to the present embodiment.

  First, the sub CPU 71 determines whether or not it is a BB winning game during which the navigation game state transition standby counter is being consumed (step S521). At this time, the sub CPU 71 clears the navigation game state transition standby counter (step S527) and shifts to the navigation game state 1 after the end of the BB when the BB winning game is being consumed during the navigation game state transition standby counter. (Step S528), and the navigation game state transition processing during the standby state ends.

  Although the processing for shifting to the navigation game state 1 after the end of BB is not described in detail, for example, processing for turning on the navigation game state 1 flag is performed. Then, although not shown, when the navigation game state 1 flag is on after the end of BB, the state is shifted to the navigation game state 1. In the following, in the flowchart, the same processing is performed in the portion described as “transition from next game to navigation game state 0 (or navigation game state 1, navigation game state 2, navigation game state 3)”. For example, when shifting from the next game to the navi game state 0, the navi game state 0 flag is turned on in the processing, and if the navi game state 0 flag is on at the start of the next game, the navi game state 0 is shifted. .

  On the other hand, if it is not the BB winning game in which the navigation game state transition standby counter is being consumed, the sub CPU 71 then subtracts 1 from the navigation game state transition standby counter (step S522), and determines whether or not the counter has become 0 (step S522). Step S523). At this time, if the value is not 0, the sub CPU 71 ends the navigation game state transition processing during the standby state.

  On the other hand, if it has become 0, it is determined whether or not it is in the RT3 gaming state (step S524). If it is not in the RT3 gaming state, processing for shifting from the next game to the navigating gaming state 1 is performed ( In step S525), the navigation game state transition processing in the standby state is terminated. On the other hand, in the case of the RT3 gaming state, processing for shifting from the next game to the navi gaming state 2 is performed (step S526), and the navi gaming state shifting processing in the standby state ends.

  Next, with reference to FIG. 69, the navigation game state transition processing in the navigation game state 1 will be described. FIG. 69 is a view illustrating a flowchart of the navigation game state transition processing in the navigation game state 1 according to the present embodiment.

  First, the sub CPU 71 determines whether or not it is a BB winning game (step S541). If it is a BB winning game, the sub CPU 71 performs a process for shifting to the navi game state 1 after the end of the BB (step S542), and ends the navi game state shift process in the navi game state 1.

  On the other hand, if the game is not the BB winning game, it is determined whether or not the game is an RT3 transition game (a game that has transitioned from another game state to the RT3 game state) (step S543). The sub CPU 71 proceeds to the process of step S545 when the game is the RT3 transition game, and determines whether or not the player does not follow the navigation and satisfies a specific condition if the game is not the RT3 transition game (step S544). ).

  It should be noted that the specific conditions are that (i) when the SB win during the normal gaming state did not shift to the RT1 gaming state, and (ii) when the push order lip during the RT1 gaming state wins, the RT2 gaming state did not shift. In this case, (iii) a transition is made to the general gaming state at the time of the pressing bell in the RT1 gaming state or the RT2 gaming state, (iv) a transition is made to the RT1 gaming state at the SB winning in the RT2 gaming state, (v) This is satisfied when the transition to the RT3 gaming state has not been performed at the time of winning the push order lip 2 in the RT2 gaming state.

  When the player does not follow the navigation and does not satisfy the specific condition, the sub CPU 71 ends the navigation game state transition process in the navigation game state 1 and the player satisfies the specific condition without following the navigation. In this case, the process shifts to step S545.

  Next, the sub CPU 71 determines whether or not the navigation game state 3 interruption flag is on (step S545). The navi game state 3 suspension flag is turned on when a BB is won in the navi game state 3, and is cleared when the BB is completed, the mode is shifted to the navi game state 1, and the state returns to the navi game state 3 again.

  If the navi game state 3 interruption flag is not on, the sub CPU 71 performs processing for shifting from the next game to the navi game state 2 (step S546), and ends the navi game state shift processing in the navi game state 1 I do. On the other hand, if the navi game state 3 interruption flag is on, processing for shifting from the next game to the navi game state 3 is performed (step S547), and the navi game state shift processing in the navi game state 1 is ended.

  Next, with reference to FIG. 70 and FIG. 71, the navigation game state transition processing in the navigation game state 2 will be described. 70 and 71 are diagrams showing a flowchart of the navigation game state transition process in the navi game state 2 of the present embodiment.

  First, the sub CPU 71 determines whether or not it is a BB winning game (step S561). If it is a BB winning game, the sub CPU 71 performs a process for shifting to the navi game state 1 after the BB ends (step S562), and ends the navi game state shift process in the navi game state 1.

  On the other hand, if it is not a BB winning game, it is determined whether or not BB carryover is being performed (step S563). If the BB is being carried over, the sub CPU 71 ends the navigation game state transition process in the navigation game state 1. On the other hand, if the BB is not being carried over, it is determined whether or not the navigation game state 3 transition flag is ON (step S564), and if it is on, the navigation game state 3 transition processing in the navigation game state 2 is performed. (Step S566), the navigation game state transition process in the navigation game state 2 is ended. On the other hand, if the navigation game state 3 transition flag is not on, then it is determined whether or not the navigation game state transition standby counter is 1 or more (step S565).

  If the navi game state transition standby counter is 1 or more, the sub CPU 71 performs the navi game state 2 navi game state 3 transition process (step S566), and ends the navi game state 2 navi game state transition process. . On the other hand, if the navigation game state transition standby counter is not 1 or more, the navigation game number counter is decremented by 1 (step S567), and it is determined whether the navigation game number counter has become 0 (step S568).

  When the navi game number counter is not 0, the sub CPU 71 ends the navi game state transition process in the navi game state 2. On the other hand, if the navi game number counter has become 0, it is then determined whether the navi set number counter is 0 (step S569). If not, 50 is set in the navi game number counter (step S569). In step S570, 1 is subtracted from the navigation set number counter (step S571), and the navigation game state transition process in the navigation game state 2 ends. On the other hand, when the navigation set number counter is 0, the navigation mode shift lottery is performed with reference to the navigation mode shift lottery table C (FIG. 41) (step S572).

  Next, the sub CPU 71 determines whether or not the transition destination navigation mode is determined to be 0 as a result of the navigation mode transition lottery (step S573). When the transition destination navigation mode is determined to be 0, the sub CPU 71 performs processing for shifting from the next game to the navigation game state 0 (step S578), and ends the navigation game state transition processing in the navigation game state 2 I do.

  On the other hand, when a value other than 0 is determined as the transition destination navigation mode, an ART first hit processing is performed (step S574). Next, the sub CPU 71 refers to the navi game state transition standby number lottery table C (FIG. 32) to randomly determine the navi game state transition standby number (step S575), and determines the determined navi game state transition standby number. The game state transition standby number counter is set (step S576).

  Next, the sub CPU 71 determines whether or not the navi game state transition standby number counter is 0 (step S577). If the navi game state transition standby number counter is not 0, the sub CPU 71 shifts from the next game to the navi game state 0. Is performed (step S578), and the navigation game state transition processing in the navigation game state 2 ends. On the other hand, if the navi game state transition standby number counter is 0, processing for transitioning from the next game to navi game state 2 is performed (step S579), and the navi game state transition processing in navi game state 2 ends. .

  Next, with reference to FIG. 72, the navigation game state 3 transition processing in the navigation game state 2 will be described. FIG. 72 is a diagram showing a flowchart of the navigation game state 3 transition processing in the navi game state 2 of the present embodiment.

  First, the sub CPU 71 determines whether or not the navigation game state 3 transition waiting number counter is 0 (step S591). The navi game state 3 shift waiting number counter is a counter indicating the number of games from the navi game state 2 to the navi game state 3. If the navi game state 3 shift standby number counter is not 0, the sub CPU 71 decrements the navi game state 3 shift standby number counter by 1 (step S597), and proceeds to the process of step S598. On the other hand, if the navi game state 3 shift standby number counter is 0, then it is determined whether or not the navi game state 3 shift flag was turned on when shifting to the navi game state 2 (step S592).

  If the sub CPU 71 determines that the navigation game state 3 transition flag has not been turned on when transitioning to the navigation game state 2, the sub CPU 71 refers to the navigation game state 3 transition standby number lottery table (FIG. 33) and executes the navigation game number counter. In accordance with the value or the like, the number of waiting for the navigation game state 3 to be shifted is randomly determined (step S593). Next, the sub CPU 71 sets the determined navigation game state 3 shift standby number in the navigation game state 3 shift standby number counter (step S594), and decrements the navi game state 3 shift standby number counter by 1 (step S597). The process moves to step S598.

  On the other hand, if the sub CPU 71 determines that the navigation game state 3 transition flag has been turned on when shifting to the navigation game state 2, then the sub CPU 71 determines whether the navigation game state was 0 or 1 before the transition to the navigation game state 2 It is determined (step S595). If the sub CPU 71 determines that the navigation game state is 0 or 1 before the transition to the navigation game state 2, the sub CPU 71 performs a process for transitioning from the next game to the navigation game state 3 (step S599), and the navigation game state. The middle navigation game state 3 transition processing ends.

  On the other hand, when the sub CPU 71 determines that the navigation game state is not the navigation game state 0 or 1 before the transition to the navigation game state 2, the sub CPU 71 sets 2 to the navigation game state 3 transition waiting number counter (step S596), and the navigation game is performed. The state 3 shift standby number counter is decremented by 1 (step S597), and the process shifts to step S598.

  In the process of step S598, the sub CPU 71 determines whether or not the navi game state 3 shift waiting number counter is 0 (step S598). When the sub CPU 71 determines that the navi game state 3 shift standby number counter is not 0, the sub CPU 71 ends the navi game state 2 navi game state 3 shift processing. On the other hand, when the sub CPU 71 determines that the navi game state 3 shift standby number counter is 0, it performs processing for shifting from the next game to the navi game state 3 (step S599), and the navi game in the navi game state 2 The state 3 transition processing ends.

  Next, with reference to FIG. 73, the navigation game state transition processing in the navigation game state 3 will be described. FIG. 73 is a view showing a flowchart of the navigation game state transition processing in the navigation game state 3 of the present embodiment.

  First, the sub CPU 71 determines whether or not the navigation game state 3 interruption flag is on (step S611). If the sub CPU 71 determines that the navi game state 3 interruption flag is ON, the number of navi game state 3 addition games, the navi game state 3 addition lottery mode, and the navi game state which are saved in the processing of step S621 described later. The continuation counter is reset (step S617), the navigation game state 3 shift flag is turned off (step S618), and the process shifts to step S619. On the other hand, if the sub CPU 71 determines that the navi game state 3 interruption flag is not ON, then the sub CPU 71 determines whether or not the game is a navi game state 3 transition game (a game transitioned from another navi game state to the navi game state 3). Is determined (step S612).

  When the game is not the navigation game 3 transition game, the sub CPU 71 proceeds to the process of step S619. On the other hand, when the game is the navigation game state 3 transition game, the sub CPU 71 obtains information from the navigation game state 3 information storage area, and sets the navigation game state 3 addition game number and the navigation game state 3 addition lottery mode ( Step S613).

  Next, the sub CPU 71 sets 1 to the navi game state 3 continuation counter (step S614). The navigation game state 3 continuation counter is a counter that manages the number of continuous games in the navigation game state 3. Next, the sub CPU 71 obtains information from the navigation game state 3 information storage area in the process of step S613, and thus determines whether the navigation game state 3 information storage area is empty (whether the stored information is lost). Is determined (step S615).

  When the navigation game state 3 information storage area becomes empty, the sub CPU 71 turns off the navigation game state 3 shift flag (step S616), shifts to the processing of step S619, and moves to the navigation game state 3 information storage area. If is not empty, the process proceeds directly to step S619.

  Next, the sub CPU 71 performs a navigation game number addition process (step S619). Next, the sub CPU 71 determines whether or not it is a BB winning game (step S620). If it is a BB winning game, the sub CPU 71 saves the navi game state 3 addition game number, the navi game state 3 addition lottery mode, and the navi game state continuation counter (step S621), and sets the navi game state 3 interruption flag. It is turned on (step S622).

  Next, the sub CPU 71 performs a process for shifting to the navigation game state 1 after the end of BB (step S623), and ends the navigation game state transition process in the navigation game state 1. On the other hand, if it is not a BB winning game, it is determined whether or not the result of the navi game state 3 navi game number addition lottery is a non-winning (step S624). If the winning has not been won, the sub CPU 71 performs a process for shifting from the next game to the navi game state 2 (step S625), ends the navi game state shifting process in the navi game state 1, and ends the win. If there is, the navigation game state transition process in the navigation game state 1 is terminated.

  Next, the navigation game number addition process will be described with reference to FIG. FIG. 74 is a diagram showing a flowchart of the navigation game number adding process of the present embodiment.

  First, the sub CPU 71 determines whether or not the navigation game state is 3 (step S641). The sub CPU 71 ends the navigation game number adding process when the navigation game state is not the third. On the other hand, if the navigation game state is 3, it is determined whether or not the game is a BB winning game (step S642). If it is a BB winning game, the sub CPU 71 refers to the navi game number special addition lottery table (FIG. 44) and performs the navi game number special addition lottery according to the type of the winning BB (step S643). The determined number of navigation games is added to the number-of-navigation-games counter (step S644), and the navi-game-number adding process ends.

  On the other hand, if the game is not a BB winning game, the sub CPU 71 determines whether or not it is the first game to return from the BB winning in the navi game state 3 (step S645). If it is the first return game, the sub CPU 71 shifts to the process of step S650. On the other hand, if it is not the first return game, then it is determined whether the navigation game state 3 continuation counter is 1 or 2 (step S646). If the navigation game state 3 continuation counter is 1 or 2, The process moves to step S650.

  On the other hand, if the navi game state 3 continuation counter is not 1 or 2, the navi game state 3 navi game number addition lottery table (FIG. 43) is referred to, and the navi game state 3 addition lottery mode, the small hand / replay pointer data In accordance with the pointer, the bonus data pointer, and the like, the navi game state 3 navi game number addition lottery is performed (step S647). Next, the sub CPU 71 determines whether or not the result of the navi game state 3 navi game number addition lottery is a win (step S648). If the result is a win, the process proceeds to step S650.

  On the other hand, if the winning is not won, the navi game state 3 addition lottery mode, the navi game state 3 addition game number, and the navi game state 3 continuation counter are cleared (step S649), and the navi game number addition process ends.

  Next, the sub CPU 71 adds the navi game state 3 added game number to the navi game number counter in the process of step S650. (Step S650). Next, the sub CPU 71 determines whether or not the navigation game state 3 continuation counter has a specific value (step S651). The specific value is a value (5, 7, 10, 15, 20, 25, 30, 35, 40...) Specified in the navi game number special addition lottery table (FIG. 44).

  When determining that the navi game state 3 continuation counter is not the specific value, the sub CPU 71 adds 1 to the navi game state 3 continuation counter (step S654), and ends the navi game number addition process. On the other hand, when the sub CPU 71 determines that the navi game state 3 continuation counter has the specific value, the sub CPU 71 refers to the navi game number special addition lottery table (FIG. 44), and according to the value of the navi game state 3 continuation counter. The number of navigation game special addition lottery is performed (step S652). Next, the sub CPU 71 adds the navi game number determined by the navi game number special addition lottery to the navi game number counter (step S653), and adds 1 to the navi game state 3 continuation counter (step S654). The addition processing ends.

  Next, the billy get challenge lottery process will be described with reference to FIG. FIG. 75 is a diagram showing a flowchart of the billy-get challenge lottery process of the present embodiment.

  First, the sub CPU 71 determines whether or not BB is being performed (step S671). If the BB is being performed, the billy get challenge lottery process is completed. Is determined (step S672). When the BB is being carried over, the sub CPU 71 ends the billy get challenge lottery process, while when the BB is not being carried over, the sub CPU 71 next determines whether or not the navigation mode is 0 (step S673).

  When the navigation mode is not 0, the sub CPU 71 ends the billy-get challenge lottery process. On the other hand, when the navigation mode is 0, the sub-CPU 71 refers to the billy-get challenge control counter lottery table (FIG. 46) and A billy get challenge control counter lottery is performed in accordance with the presence / absence of the role / replay pointer, the bonus data pointer, and the effect game stop (step S674).

  Next, the sub CPU 71 determines whether or not the result of the billy get challenge control counter lottery is a win (step S675). If the result is a win, the billing get challenge control counter is incremented by 1 (step S676). The process proceeds to step S677. On the other hand, if it is not a winning, the process directly proceeds to step S677. Next, the sub CPU 71 determines whether or not the billy get challenge control counter is 1 or more (step S677).

  If the billy get challenge control counter is not 1 or more, the sub CPU 71 ends the billy get challenge lottery process. If the billy get challenge control counter is 1 or more, the sub CPU 71 then proceeds to the next game after the end of the specific liquid crystal effect. It is determined whether or not it is (step S678). The specific liquid crystal effect is a continuous effect over a plurality of games in the liquid crystal display area 23, an effect that expects a bonus or an ART, and the like.

  If the sub CPU 71 determines that the game is not the next game after the end of the specific liquid crystal effect, the billy get challenge lottery process ends. On the other hand, when it is determined that the game is the next game after the end of the specific liquid crystal effect, the billy get challenge process is performed (step S679), the billy get challenge control counter is decremented by 1 (step S680), and the billy get challenge lottery process ends. .

  Next, a billy get challenge determination process will be described with reference to FIG. FIG. 76 is a diagram showing a flowchart of the billy get challenge determination process of the present embodiment.

  First, the sub CPU 71 determines whether or not a billy get challenge effect has been registered in step S463 (FIG. 65) in the game (step S701). When the billy get challenge effect has not been registered, the sub CPU 71 ends the billy get challenge determination process. On the other hand, when the billy get challenge effect has been registered, it is then determined whether or not the third stop has occurred (step S702). If it is not the third stop, the sub CPU 71 terminates the billy get challenge determination process.

  On the other hand, if it is the third stop time, it is determined whether or not the billy get challenge is successful (step S703). Specifically, the sub CPU 71 determines whether or not the player's selection operation has been performed by the infrared sensors 120L and 120R by the time of the third stop. If the selection operation has been performed, the billy get challenge correct answer lottery ( It is determined whether or not it matches the correct answer determined in step S461) of FIG.

  If they match, it is determined that the billet challenge is successful, and if they do not match, it is determined that the billy challenge has failed. If the selection operation has not been performed by the time of the third stop, the sub CPU 71 determines that if the result of the lottery without selection of the billy get challenge (step S462 in FIG. 65) is a win, the billy get If it is determined that the challenge is successful, and if it is not won, it is determined that the billy get challenge has failed. Although not shown, if the billy get challenge is successful, the sub CPU 71 registers the billy get challenge success effect data indicating that the billy get challenge is successful, and notifies the player of the registration.

  If the sub CPU 71 determines that the billy get challenge has not been successful (failed), the sub CPU 71 ends the billy get challenge determination process. On the other hand, when it is determined that the billy get challenge is successful, it is next determined whether or not BB4 is being performed (step S704). When not in BB4, the sub CPU 71 increases the navigation mode by one level (step S705), performs a navigation game state transition process (step S706) and an ART first hit process (step S707), and determines a billy get challenge. The process ends.

  On the other hand, when BB4 is in progress, the sub CPU 71 turns on the billy get challenge success flag (step S708), and increases the navigation mode by one step (step S709). At this time, the sub CPU 71 determines whether or not the navigation mode has shifted from 0 to 1 to 4 (step S710). When the sub CPU 71 determines that the navigation mode has shifted from 0 to 1 to 4, it performs an ART first hit processing (step S711), and shifts to the processing of step S712, while the navigation mode changes from 0 to 1 to 4. If it is determined that the process has not shifted to step S712, the process directly proceeds to step S712.

  Next, the sub-CPU 71 refers to the navi game state 3 addition game number lottery table D (FIG. 37) and randomly selects the navi game state 3 addition game number (step S712). Next, the sub CPU 71 determines whether or not the lottery result is a winning (a value other than 0 has been determined as the number of games to be added to the navi game state 3) (step S713). If it is not a winning, the sub CPU 71 ends the billy get challenge determination process.

  On the other hand, if it is a winning, the navigation game state 3 addition lottery mode lottery is determined according to the current navigation mode with reference to the navigation game state 3 addition lottery mode lottery table D (FIG. 41) (step S714). Next, the sub CPU 71 associates the number of navi game state 3 addition games won in the processing of step S712 and the navi game state 3 addition lottery mode determined in the processing of step S714 with each other and associates them with each other in the sub RAM 73-1. It is stored in the navigation game state 3 information storage area (step S715). Next, the sub CPU 71 turns on the navigation game state 3 transition flag (step S716), and ends the billing challenge determination process.

  Next, the navigation game state transition processing will be described with reference to FIG. FIG. 77 is a view showing a flowchart of the navigation game state transition processing of the present embodiment.

  First, the sub CPU 71 determines whether or not the game is in the RT3 game state (step S731). If the sub CPU 71 is in the RT3 gaming state, the sub CPU 71 performs processing for shifting from the next game to the navi gaming state 2 (step S732), and ends the navi gaming state shifting processing. On the other hand, when not in the RT3 gaming state, the sub CPU 71 performs processing for shifting from the next game to the navigation gaming state 1 (step S733), and ends the navigation gaming state shifting processing.

  Next, the display command receiving process will be described with reference to FIG. FIG. 78 is a diagram showing a flowchart of the display command receiving process according to the present embodiment.

  First, the sub CPU 71 determines whether or not it is a BB winning game (step S751). If it is a BB winning game, the sub CPU 71 determines whether or not the display combination is BB (BB that has been internally won) (step S752), and if the display combination is BB, the display command is If the display combination is not BB, the BB carryover flag is turned on (step S753), and the display command reception process ends.

  On the other hand, if it is not a BB winning game, the sub CPU 71 determines whether or not the BB carryover flag is ON (step S754). When the BB carryover flag is not on, the sub CPU 71 ends the display command receiving process. When the BB carryover flag is on, the display combination is BB (BB carrying over). It is determined whether or not. (Step S755). At this time, if the display combination is not BB, the sub CPU 71 ends the display command receiving process, and if the display combination is BB, the sub CPU 71 turns off the BB carryover flag (step S756), and displays the display command. The reception process ends.

  Next, with reference to FIG. 79, a process at the time of receiving a bonus end command will be described. FIG. 79 is a diagram showing a flowchart of the processing at the time of receiving a bonus end command according to the present embodiment.

  First, the sub CPU 71 determines whether or not the BB4 gaming state has ended (step S771). If not, the sub CPU 71 shifts to the processing of step S774. On the other hand, if it is the end of the BB4 gaming state, it is then determined whether or not the billy get challenge success flag is on (step S772). At this time, if the billy get challenge success flag is not on, the sub CPU 71 shifts to the processing of step S774. On the other hand, when the billy get challenge success flag is on, the billy get challenge success flag is turned off (step S773), and the process shifts to step S774.

  Next, the sub CPU 71 determines whether or not it is time to end any BB gaming state (step S774). When the sub CPU 71 determines that it is not the end of the BB gaming state, the process at the time of receiving the bonus end command is ended. On the other hand, when the sub CPU 71 determines that it is the end of the BB gaming state, it then determines whether the navigation mode is one of 1 to 4 (step S775). When the navigation mode is not any of 1 to 4, the sub CPU 71 performs a process for shifting from the next game to the navigation game state 0 (step S779), and ends the process at the time of receiving the bonus end command. On the other hand, when the navigation mode is any one of 1 to 4, the sub CPU 71 then determines whether or not the transition is to the lottery in the BB winning game (step S776).

  When the transition is not the lottery in the BB winning game, the sub CPU 71 performs a process for shifting from the next game to the navigation game state 1 (step S780), and ends the process at the time of receiving the bonus end command. On the other hand, if the transition is a lottery in the BB winning game, the sub CPU 71 determines whether or not the navigation mode transition lottery in the BB gaming state has been won (step S777). When the sub CPU 71 determines that the navigation mode shift lottery in the BB game state has been won, the sub CPU 71 performs a process for shifting from the next game to the navigation game state 1 (step S780), and performs a process when a bonus end command is received. finish.

  On the other hand, if the sub CPU 71 determines that the navigation mode transition lottery in the BB gaming state has not been won, the sub CPU 71 refers to the navigation game state transition standby number lottery table B (FIG. 32) and waits for the navigation game state transition. The number is determined by lottery and set in the navigation game state transition standby counter (step S778). Then, processing for transitioning from the next game to the navigation game state 0 is performed (step S779), and the processing at the time of receiving the bonus end command is terminated. .

  The navigation mode shift lottery may be performed at the end of the BB gaming state. At this time, lottery may be performed according to the game content in the BB game state to be ended. For example, if the JACs 1 to 7 (small role / replay pointers “25” to “31”) have never been won during the BB gaming states 1 to 3, the navigation mode is increased by one with a high probability. Lottery may be performed. In addition, when the billy get challenge in the BB gaming state has failed a specific number of times, lottery may be performed so that the navigation mode increases by one with a high probability.

  Next, a display panel unit effect executed when display panel unit effect data is registered in step S445 of the lottery process during BB4 (FIG. 64) will be described using FIG.

  When the display panel unit effect data is registered, the sub CPU 71 changes the brightness of the LEDs 111 to 114 corresponding to the respective display panels 110Pa to 110Pd according to the time series shown in FIG. In this case, the player initially looks like the character is slowly approaching the near side from the back, and then the front display panel 110Pa blinks at high speed with the light-off period in between. As a result, the player's sense of expectation can be improved.

[Gaming machine management system]
Next, an error information history transmission system using the gaming machine 1 of the present embodiment will be described. The error information history transmission system is a system that stores various errors occurring in the gaming machine 1 as error information, transmits the history of the error information to a remote server by using a mobile terminal, and analyzes the cause of the error. .

  As shown in FIG. 81, the error information history transmission system includes a gaming machine 1, a camera-equipped mobile communication terminal (hereinafter, referred to as “mobile terminal”) 400 as a mobile terminal owned by a clerk, and a data management server as a server. And an analysis PC 600 as analysis means. In the example of FIG. 81, one portable terminal 400 is shown for convenience of description, but actually, a large number of portable terminals 400 can access the data management server 500.

  The data management server 500 manages, for example, not only error information management but also information related to game records. The portable terminal 400 and the data management server 500 can mutually transmit and receive data via the network NW using, for example, TCP / IP as a communication protocol. The network NW is constructed by, for example, the Internet, a dedicated communication line (for example, a CATV (Community Antenna Television) line), a mobile communication network (including a base station, etc.), a gateway, and the like. Note that the gaming machine 1 is not connected to the network NW.

  Although not shown, the mobile terminal 400, the data management server 500, and the analysis PC 600 each include a control unit, a storage unit, a display unit, a communication unit, and the like. In addition, it is preferable that the data management server 500 and the analysis PC 600 be installed in an area 700 separated from the installation place of the gaming machine 1 such as a maker of the gaming machine 1 or a system management company.

  When providing a service by the error information history transmission system, the sub CPU 71 of the gaming machine 1 displays the two-dimensional code 300 on the liquid crystal display area 23 so that a clerk (mobile terminal 400) accesses the data management server 500. Specifically, as shown in FIG. 83, the attendant displays an error information history on the liquid crystal display area 23, and selects a predetermined item such as a COM error alarm (COM ERR ALM) 23b which is a communication error alarm. Thereby, the two-dimensional code 300 is displayed.

  The control unit of the portable terminal 400 reads the displayed two-dimensional code 300 with the camera 401 of the portable terminal 400, analyzes the two-dimensional code 300 using, for example, dedicated software of the portable terminal 400, and analyzes the domain in the code, a communication error log, and the like. , And accesses the data management server 500 according to the domain and the like included in the two-dimensional code 300, and transmits the information included in the two-dimensional code 300 as output-time transmission data.

  On the other hand, the control unit of the data management server 500 stores the communication error information included in the received transmission data in the storage unit.

  The control unit of the data management server 500 accumulates communication error information included in the transmission data at the time of output in an error information database DB (database) (not shown), and transmits the communication error information to the analysis PC 600. Further, the control unit of the data management server 500 generates display data (for example, a Web page) that allows the mobile terminal 400 to display the error content indicated by the received communication error information and the like, And reply (in the figure, when viewed with a dashed line arrow). Then, the control unit of the portable terminal 400 causes the display unit to display a screen 402 indicating the content of the error or the like based on the received display data. The attendant can check the error content and the like from the screen 402.

  Further, the analysis PC 600 that has received the communication error information analyzes the cause of the communication error based on the communication error information and various information stored in the error information database DB. The cause of the communication error analyzed by the analysis PC 600 may be that the manufacturer or system management company of the gaming machine 1 in which the analysis PC 600 is installed improves the game or the program of the gaming machine 1 or installs the gaming machine 1 It is used as appropriate, for example, to improve the management of the hall.

  Next, the gaming machine 1 when a clerk uses the error information history transmission service will be described. The sub CPU 71 of the gaming machine 1 employs two types of operation methods, a normal operation and a simple operation by a clerk, to display the error information history shown in FIG. 83 on the liquid crystal display device 5. When performing the normal operation, the clerk turns the door key 2 clockwise to release the lock mechanism of the front door 1b, and turns on the setting key to turn on the setting key switch 20S, so that the liquid crystal display area 23 is displayed. The menu screen shown in FIG. 82 is displayed.

  Then, the clerk operates the operation key to select the “error information history” item 23 a, so that the error information history screen shown in FIG. 83 is displayed in the liquid crystal display area 23. On the other hand, when performing a simple operation, the clerk resets the error by rotating the door key 2 counterclockwise when an error occurs or during a non-game, and holds the state for a predetermined time, for example, 5 seconds or more. As a result, the error information history screen shown in FIG. 83 is displayed in the liquid crystal display area 23.

  When the sub CPU 71 detects an operation of selecting the “error information history” item 23a using the selection button 24 and the determination button 25, the sub CPU 71 displays the error information history in the liquid crystal display area 23 as shown in FIG. . Further, when the sub CPU 71 detects an operation of selecting the “COM error alarm” item 23b using the selection button 24 and the determination button 25, the sub CPU 71 generates transmission information based on the error information history, and FIG. As shown, a two-dimensional code 300 based on the transmission information is displayed on the right side of the “COM error alarm” item 23b.

  Further, the sub CPU 71 does not display the COM error alarm when a communication error occurs once, but only when a communication error occurs again within 30 minutes after the first communication error occurs, the sub error does not appear. Is displayed. For this reason, the sub CPU 71 has a COM error timer for measuring an interval at which a communication error has occurred. The COM error timer performs measurement based on time measurement of the built-in RTC 70a or time measurement by a function provided by the OS.

  In the present embodiment, the sub CPU 71 creates the two-dimensional code 300 only when a communication error occurs. For this reason, if a communication error occurs accidentally, for example, during a normal game, the data to be placed as error information in the two-dimensional code 300 is transmitted during normal processing as shown in FIG. 86 (a). An error occurs, and normal processing is executed again immediately after that. Here, the numerical value in FIG. 85 is the number of data characters, one character data indicates a command type, and two character data indicates parameters for the immediately preceding command.

  When a communication error has occurred due to a goto action and the setting of the gaming machine 1 has been changed, the data to be placed as error information in the two-dimensional code 300 is, as shown in FIG. The setting is changed immediately after the occurrence. Further, when a communication error occurs and continuous transmission is performed by lever operation, the data to be placed as error information in the two-dimensional code 300 includes a command type immediately after the occurrence of the communication error as shown in FIG. 86 (c). A certain lever operation and a winning combination as a parameter are continuous.

  In the communication log collection ring buffer area 73e-1 shown in FIG. 87 and the communication error storage area 73f-1 shown in FIG. 88, the command is composed of one character data and the parameter is composed of two character data.

  FIG. 89 shows that when the data in the sub-RAM 73-1 of the sub-control circuit 70 is destroyed, the sub-control circuit 70 causes a sum abnormality to occur in the RAM data over substantially the entire liquid crystal display area 23 of the gaming machine 1, so that the An example of notifying that it is not possible to continue is shown. For example, when some or all of the data received from the main control circuit 60, such as commands, effect data information, gaming state information, internal winning combination information, display combination information, various counters, and various flags, is deleted, In the portion of the liquid crystal display area 23 of the gaming machine 1 other than the symbol display areas 4L, 4C, and 4R, a notification that "RAM data abnormal game cannot be continued. Please change the settings." By performing such notification, it can be expected that the goto action is suppressed.

  Next, the operation of the above-described error information history transmission system will be described with reference to the flowcharts shown in FIGS. First, the main board communication reception interrupt processing in the sub control circuit 70 will be described with reference to FIG. FIG. 90 is a diagram showing a flowchart of the main board communication reception interrupt processing in the sub control circuit 70 of the present embodiment. The program of the main board communication reception interrupt processing in the sub control circuit 70 is executed by the sub CPU 71 as the interrupt processing when the transmission data is transmitted from the main control circuit 60 to the sub control circuit 70.

  The sub CPU 71 acquires the reception data from the reception data register of the I / O port interposed between the sub CPU 71 and the main CPU 31 (step S800). Further, the sub CPU 71 obtains reception status data from the reception status register of the I / O port (step S801). Further, sub CPU 71 registers the reception data and the reception status data relating to the reception data in each queue buffer (step S802), and terminates the main board communication reception interrupt processing.

  The sub CPU 71 processes the 1-byte received data by executing the main board communication reception interrupt process of steps S800 to S802 once. In the present embodiment, one command is composed of 8-byte data. Therefore, the sub CPU 71 completes processing of one command by executing serial data communication by performing steps S800 to S802 eight times in a row.

  Next, the main board communication processing of the sub CPU 71 will be described with reference to FIG. FIG. 91 is a diagram showing a flowchart of the main board communication process of the sub CPU 71 of the present embodiment.

  Before starting the process, the sub CPU 71 sets a cycle so as to execute the main board communication processing program of the sub CPU 71 at a cycle of 2 ms in response to the scheduling function of the OS. This makes it possible to repeat this task at a cycle of 2 ms including the processing time. In this case, the sub CPU 71 waits for a cycle of 2 ms, and waits for the remaining time of 2 ms when the flowchart is repeated.

  Note that the cycle of this task processing is not limited to 2 ms, and may be executed between 2 ms to 4 ms. Further, the main board communication processing program of the sub CPU 71 is not limited to being executed at predetermined time intervals, and may be performed without setting a cycle and waiting for a cycle, for example, when a predetermined condition is satisfied regardless of a time interval. It may be executed.

  Next, the sub CPU 71 acquires the reception data from the queue in which the reception data is registered in step S802 of the main board communication reception interrupt processing shown in FIG. 90 (step S1801). The sub CPU 71 determines whether or not there is received data in the queue (step S1802). When determining that there is no received data in the queue, the sub CPU 71 acquires the received data from the queue again (step S1801).

  If the sub CPU 71 determines that there is received data in the queue, it determines whether a physical layer error has occurred in the received data (step S1803). When determining that there is no physical layer error in the received data, the sub CPU 71 checks the numerical range of the received command (step S1804). In the present embodiment, the numerical range of the received command is 01H to 10H as shown in FIG. Then, the sub CPU 71 determines whether or not the numerical value of the received command is within an appropriate range (step S1805).

  If the sub CPU 71 determines that the numerical value of the command is within the appropriate range, the sub CPU 71 performs a BCC check process on the received data (step S1806). Here, since one command is composed of 8 bytes of data, the sub CPU 71 performs an XOR operation on the data of the first byte to the seventh byte of each command in order, and sets the result to a correct result in advance. The check processing is performed by comparing the data with the data of the eighth byte.

  Then, the sub CPU 71 determines whether or not the result of the BCC check processing is normal (step S1807). If the sub CPU 71 determines that the result of the BCC check process is normal, the command type is extracted (step S1808).

  Then, the sub CPU 71 determines whether or not the extracted command is a no-operation command (step S1809). When determining that the extracted command is a no-operation command, the sub CPU 71 acquires the reception data from the queue again (step S1801).

  If the sub CPU 71 determines that the extracted command is not a no-operation command, the sub CPU 71 executes a received data log saving process (step 1810), which will be described later. Execute (step S1811).

  Then, the sub CPU 71 determines whether or not the command received this time is different from the command received last time (immediately before) (step S1812). If the sub CPU 71 determines that the command received this time is not different from the command received immediately before, that is, it is the same, the sub CPU 71 waits for a period of 2 ms according to the setting and acquires the reception data from the queue again (step S1801). .

  If the sub CPU 71 determines that the command received this time is different from the command received immediately before, the sub CPU 71 registers the command received this time in the message queue (step S1813), waits for a period of 2 ms depending on the setting, and queues again. The received data is acquired from (step S1801).

  The sub CPU 71 determines in step S1803 that there is a physical layer error in the received data, or determines that the command is not within the appropriate range in step S1805, or determines that the result of the BCC check processing is normal in step S1807. If it is determined that there is no communication error, it is determined that a communication error has occurred, and a COM error check process described later is executed (step S1814). Then, the sub CPU 71 waits for a period of 2 ms according to the setting, and acquires the reception data from the queue again (step S1801).

  Next, the received data log storage processing in step S1810 will be described with reference to FIG. FIG. 92 is a diagram showing a flowchart of the main board communication reception data log saving process performed by the sub control circuit 70 of the present embodiment. This main board communication reception data log storage processing is mainly executed by the reception data log storage means 71e of the sub CPU 71.

  When the main board communication reception data log saving process is executed, the sub CPU 71 executes a main board communication reception data log temporary area saving process described later (step S830). The main board communication reception data log temporary area saving process is a process for using the communication log collection ring buffer area 73e-1 shown in FIG. 87 and saving all communication logs regardless of whether an error has occurred. ing.

  Subsequently, the sub CPU 71 executes a main board communication error history data saving process described later (step S831). The main board communication error history data storage processing uses the communication error storage area shown in FIG. 88 and stores a related communication log when a communication error occurs. After that, the sub CPU 71 ends the main board communication reception data log storage processing.

  Next, the main board communication reception data log temporary area saving processing in step S830 will be described with reference to FIG. FIG. 93 is a diagram showing a flowchart of the main board communication reception data log temporary area saving processing performed by the sub control circuit 70 of the present embodiment.

  When the main board communication reception data log temporary area saving processing is executed, the sub CPU 71 acquires the communication log data buffer index of the communication log collection ring buffer area 73e-1 (step S840). The number of buffers here is set as appropriate.

  Then, the sub CPU 71 calculates the communication log data buffer storage position of the communication log collection ring buffer area 73e-1 (step S841). Here, the sub CPU 71 calculates the storage position in the communication log collection ring buffer area 73e-1 from the value of the buffer index.

  Further, the sub CPU 71 stores the received data in the communication log collection ring buffer area 73e-1 (step S842). In the present embodiment, as shown in FIG. 87, a maximum of 256 sets of numerical values in which a command and a parameter corresponding to each command are continuous are stored. Then, the sub CPU 71 updates the communication log data buffer index (step S843). Here, the sub CPU 71 adds one to the buffer index storing the received data.

  Then, the sub CPU 71 determines whether or not the value of the buffer index is the upper limit value (step S844). When determining that the value of the buffer index is the upper limit value, the sub CPU 71 returns the communication log data buffer index to 1 at the head (step S845), and makes this buffer function as a ring buffer. After that, the sub CPU 71 ends the main board communication reception data log temporary area saving processing. When the sub CPU 71 determines that the value of the buffer index is not the upper limit value, the main board communication reception data log temporary area saving processing is terminated as it is.

  Next, the main board communication error history data saving processing in step S831 will be described with reference to FIG. FIG. 94 is a diagram showing a flowchart of the main board communication error history data storage processing performed by the sub control circuit 70 of the present embodiment.

  When the main board communication error history data storage processing is executed, the sub CPU 71 acquires a storage buffer selection index of the communication error storage area 73f-1 (step S850). Then, the sub CPU 71 selects a communication error storage buffer based on the storage buffer selection index (step S851).

  Here, the sub CPU 71 determines whether or not a communication error (COM error) has occurred (step S852). If the sub CPU 71 determines that a COM error has occurred, the reception data log storage unit 71e stores the communication log related to the communication error in the communication error storage area 73f-1 selected in step S851 (step S853). ). Then, the sub CPU 71 updates the selected buffer index (step S854). After that, the sub CPU 71 ends the main board communication error history data storage processing.

  If the sub CPU 71 determines that no COM error has occurred, the sub CPU 71 acquires the selected buffer index (step S855). Then, sub CPU 71 determines whether or not the received data is being collected (step S856). When the sub CPU 71 determines that the reception data is not being collected, the main board communication error history data storage processing ends.

  When determining that the reception data is being collected, the sub CPU 71 determines whether or not the value of the buffer index is the upper limit value (step S857). In the present embodiment, the value of the buffer index is 0 to 255, and the upper limit is 255. When determining that the value of the buffer index is not the upper limit value, the sub CPU 71 stores the received data in the communication error storage buffer selected in step S851 (step S858). Then, the sub CPU 71 updates the selected buffer index (step S859). After that, the sub CPU 71 ends the main board communication error history data storage processing.

  When determining that the value of the buffer index is the upper limit value, the sub CPU 71 acquires a storage buffer selection index (step S860). Then, the sub CPU 71 determines whether or not the value of the storage buffer selection index is the upper limit value (step S861). In the present embodiment, the upper limit of the storage buffer selection index is 1024.

  When determining that the value of the storage buffer selection index is not the upper limit value (step S861), the sub CPU 71 updates the storage buffer selection index (step S862). Here, the sub CPU 71 adds one to the storage buffer selection index. After that, the sub CPU 71 ends the main board communication error history data storage processing. When the sub CPU 71 determines that the value of the buffer selection index is the upper limit value (step S861), the main board communication error history data saving processing ends.

  Next, the inter-command elapsed time monitoring process in step S1811 of the main board communication process of the sub CPU in FIG. 91 will be described with reference to FIG. 95A. FIG. 95A is a diagram illustrating a flowchart of the inter-command elapsed time monitoring processing performed by the sub-control circuit 70 of the present embodiment.

  In the inter-command elapsed time monitoring process, the sub CPU 71 first determines whether or not a sequence error has occurred (step S1821). When it is determined that a sequence error has occurred, the sub-CPU 71 has performed the inter-command elapsed time monitoring process. To end.

  When the sub CPU 71 determines in step S1821 that no sequence error has occurred, the sub CPU 71 obtains received data from the main control circuit 60 (step S1822).

  Upon obtaining the received data from the main control circuit 60 in step S1822, the sub CPU 71 determines whether or not the received command is "start" (step S1823). The monitoring timer activation process is executed (step S1824), and the inter-command elapsed time monitoring process ends.

  If the sub CPU 71 determines in step S1823 that the received command is not “start”, the sub CPU 71 determines whether the received command is “start of rotation of the body” (step S1825), and the received command is “start of rotation of the body”. When it is determined that the command is not satisfied, a monitoring timer stop process described later is executed (step S1826), and the inter-command elapsed time monitoring process ends.

  When the sub CPU 71 determines in step S1825 that the received command is not “rotation start”, the sub CPU 71 determines whether the received command is “payout end” (step S1827). If it is determined that there is, a monitoring timer operation status check process described later is executed (step S1828), and the inter-command elapsed time monitoring process ends.

  When the sub CPU 71 determines in step S1827 that the received command is not “payout end”, the inter-command elapsed time monitoring process ends.

  Next, a monitoring timer activation process of the inter-command elapsed time monitoring process of FIG. 95A will be described with reference to FIG. 95B. FIG. 95B is a diagram illustrating a flowchart of the monitoring timer activation process performed by the sub-control circuit 70 of the present embodiment.

  In the monitoring timer activation process, the monitoring timer A and the monitoring timer B are used. These monitoring timers can measure based on the timing of a software timer by the function of the OS. The reason why two monitoring timers are used is that if an illegal action is performed when only one monitoring timer is used, the monitoring timer remains activated and measurement cannot be started for each game. Therefore, the monitoring timer A and the monitoring timer B measure alternately for each game.

  In the monitoring timer activation process, the procedure detection means 71b of the sub CPU 71 determines whether both the monitoring timer A and the monitoring timer B are operating (step S1831), and determines whether both the monitoring timer A and the monitoring timer B are operating. If it is operating, the sub CPU 71 registers that a sequence error has occurred in the error information history storage area 73d-1 assuming that a sequence error has occurred due to a procedure error (step S1832), and ends the monitoring timer activation process.

  Registering the simultaneous operation of both timers as error information in this way is a condition for starting / stopping the monitoring timer A and the monitoring timer B. If the command is normally received, the sub CPU 71 issues a “start” command. At the time of reception, the timing at which both timers are operating does not occur, and both timers are operating because it can be determined that it is caused by a goto action.

  If the sub CPU 71 determines in step S1831 that both the monitoring timer A and the monitoring timer B are not operating at the same time, the sub CPU 71 determines whether both the monitoring timer A and the monitoring timer B are stopped ( Step S1833).

  When determining that both the monitoring timer A and the monitoring timer B are stopped in step S1833, the sub CPU 71 starts measurement of the monitoring timer A (step S1834) and ends the monitoring timer activation process. This is to start the measurement of the monitoring timer when the first “start” command is received after the power is turned on or after the power is restored, so that the timer check at the start of reel rotation is not performed.

  If the sub CPU 71 determines in step S1833 that both the monitoring timer A and the monitoring timer B are not stopped, in other words, if it determines that one of them is operating, it determines whether the monitoring timer A is operating. It is determined whether it is not (step S1835).

  When the sub CPU 71 determines in step S1835 that the monitoring timer A is operating, it starts the measurement of the monitoring timer B (step S1836), and subsequently turns on the monitoring start flag A (step S1837). The monitoring timer activation process ends. By these processes, since the monitoring timer A is operating, the monitoring timer B starts measurement, and the flag A for determining the operating state of the monitoring timer A is turned on.

  When determining that the monitoring timer A is not operating in step S1835, the sub CPU 71 starts measurement of the monitoring timer A (step S1838), and subsequently turns on the monitoring start flag B (step S1839). The monitoring timer activation process ends. Through these processes, since the monitoring timer B is operating, the monitoring timer A starts measurement, and the flag B for determining the operating state of the monitoring timer B is turned on.

  Next, the monitoring timer stop processing of the inter-command elapsed time monitoring processing of FIG. 95A will be described with reference to FIG. 95C. FIG. 95C is a diagram illustrating a flowchart of the monitoring timer stop processing performed by the sub control circuit 70 of the present embodiment.

  In the monitoring timer stop process, the sub CPU 71 determines whether both the monitoring flag A and the monitoring flag B are on (step S1841). Is registered in the error information history storage area 73d-1 (step S1852), and the monitoring timer stop processing ends.

  When the sub CPU 71 determines that both the monitoring flag A and the monitoring flag B are not on in step S1841, subsequently, determines whether the monitoring flag A is on (step S1842).

  When determining that the monitoring flag A is ON in step S1842, the sub CPU 71 stores the elapsed time of the monitoring timer A in the elapsed time check area of the other work area of the sub RAM 73-1 (step S1843). Then, the measurement of the monitoring timer A is stopped (step S1844), and the monitoring flag A is turned off (step S1845).

  When determining that the monitoring flag A is not on in step S1842, the sub CPU 71 determines whether or not the monitoring flag B is on (step S1846).

  When determining that the monitoring flag B is ON in step S1846, the sub CPU 71 stores the elapsed time of the monitoring timer B in the elapsed time check area of the other work area of the sub RAM 73-1 (step S1847). Then, the measurement of the monitoring timer B is stopped (step S1848), and the monitoring flag B is turned off (step S1849).

  After turning off the monitoring flag A in step S1845 or turning off the monitoring flag B in step S1849, the sub CPU 71 sets the elapsed time of the monitoring flag A or the elapsed time of the monitoring flag B to 4.1. It is determined whether it is less than a second (step S1850).

  As will be described later with reference to FIG. 95E, 4.1 seconds is the shortest required in one game from “start” to “start of rotation of the next game” when the game is performed in a normal procedure. Time. That is, the time is a time from when the sub CPU 71 receives the start command from the main control circuit 60 to when the sub CPU 71 receives the payout end command from the main control circuit 60, including the wait time. Therefore, if one game is completed in less than 4.1 seconds, it can be determined that the game has been played in an abnormal procedure.

  When the sub CPU 71 determines in step S1850 that the elapsed time is not less than 4.1 seconds, subsequently, it determines whether the monitoring flag A and the monitoring flag B are off (step S1851).

  When the sub CPU 71 determines in step S1851 that the monitoring flag A and the monitoring flag B are not off, it is contrary to the fact that the monitoring flag will not be turned on after the monitoring timer determination, and If it is determined in step S1850 that the elapsed time is less than 4.1 seconds, the elapsed time is not less than 4.1 seconds in a game in a normal procedure. In either case, the occurrence of a sequence error due to a procedure error is registered in the error information history storage area 73d-1 (step S1852), and the monitoring timer stop processing ends.

  If the sub CPU 71 determines in step S1846 that the monitoring flag B is not on, and if it determines in step S1851 that the monitoring flag A and the monitoring flag B are off, the sub CPU 71 ends the monitoring timer stop process. I do.

  Next, with reference to FIG. 95D, a description will be given of the monitoring timer operation status checking process after the payout of the inter-command elapsed time monitoring process of FIG. 95A. FIG. 95D is a diagram showing a flowchart of the monitoring timer operation status check processing performed by the sub control circuit 70 of the present embodiment.

  In the monitoring timer operation status check processing, the sub CPU 71 determines the operation state and the stop state of the monitoring timer A and the monitoring timer B, triggered by the payout end command output from the main control circuit 60. Specifically, in the monitoring timer operation status check processing, first, it is determined whether both the monitoring timer A and the monitoring timer B are operating (step S1861).

  If it is determined in step S1861 that both the monitoring timers A and B are not operating, then it is determined whether both the monitoring timers A and B are stopped (step S1862). If it is determined in this step that both the monitoring timers A and B are not stopped, then it is determined whether the monitoring flag A or the monitoring flag B is on (step S1863).

  When determining that both the monitoring timer A and the monitoring timer B are operating in step S1861, the sub CPU 71 determines that both the monitoring timer A and the monitoring timer B are stopped in step S1862. At this time, or when it is determined in step S1863 that the monitoring flag A or the monitoring flag B is on, the sequence error occurrence is registered in the error information history storage area 73d-1 assuming that a sequence error due to a procedure error has occurred ( Step S1864), and terminates the monitoring timer operation status check processing.

  If the sub CPU 71 determines in step S1863 that neither the monitoring flag A nor the monitoring flag B is ON, the sub CPU 71 ends the monitoring timer operation status check processing.

  In the above-described monitoring timer stop processing and monitoring timer operation status check processing, when the sub CPU 71 registers a sequence error as error information in the error information history storage area 73d-1, for example, as shown in FIG. As an important error, it indicates that the game cannot be continued due to an abnormality in the RAM data over almost the entire liquid crystal display area 23 of the gaming machine 1. Thereby, a goto action can be suppressed. The release of the notification is performed by, for example, changing settings such as power-off.

  Thereafter, as described above, the menu screen shown in FIG. 82 is displayed in the liquid crystal display area 23, and the clerk operates the operation key to select the “error information history” item 23a. An error information history screen shown in FIG. 83 can be displayed on 23.

  FIG. 95E shows reception of “start”, “turning drum rotation start”, and “payout end” commands in the game (GAME) of seven games, the start and stop timings of the monitoring timers A and B, the monitoring flag A and 6 is a timing chart showing a normal relationship between the ON and OFF timings of the monitoring flag B.

  In FIG. 95E, seven games denoted by 1 to 7 are performed in succession, and each game includes a “start” command at the start of a game, a “turning rotation start” command at the start of reel rotation, and a subsequent The processing is ended by the "payout end" command after the payout.

  The minimum time from the "start" of each game to the "start of the rotation of the torso" of the next game is set to a minimum time, and if it ends in a shorter time, it is determined that a goto action has been performed. . The predetermined time is, for example, 4.1 seconds.

  Hereinafter, the timing chart shown in FIG. 95E will be described.

  1) In the first game, upon receiving a start command from the main control circuit 60, the sub CPU 71 determines that the game has been started, activates the monitoring timer A at the time indicated by the start, and starts measurement.

  2) In the second game following the first game, when the sub CPU 71 receives the start command from the main control circuit 60, the monitoring timer A is in operation. The monitoring flag A is turned on to determine the state.

  3) In the second game, upon receiving the turn drum rotation start command from the main control circuit 60, the sub CPU 71 saves the elapsed time of the monitoring timer A in the elapsed time check area of the sub RAM 73-1. The measurement is stopped, and at the same time, the monitoring flag A is turned off. The elapsed time is the time from the start of the first game to the start of the rotation of the torso of the second game.

  4) In the third game following the second game, upon receiving the start command from the main control circuit 60, the sub CPU 71 activates the monitoring timer A because the monitoring timer B is operating. The monitoring flag B is turned on to determine the state.

  5) In the third game, when the sub CPU 71 receives the turn rotation start command from the main control circuit 60, the sub CPU 71 saves the elapsed time of the monitoring timer B in the elapsed time check area of the sub RAM 73-1. The measurement is stopped, and at the same time, the monitoring flag B is turned off.

  6) From the fourth game to the seventh game, the above steps 2) to 5) are sequentially repeated.

  If the time measured in each game by the monitoring timer A or the monitoring timer B is less than 4.1 seconds, the sub CPU 71 determines that this error has occurred as an illegal game sequence error due to a goto action and returns the error information history. It is registered in the storage area 73d-1, and as a fatal error, for example, as shown in FIG. 89, almost all of the liquid crystal display area 23 of the gaming machine 1 has an abnormality in RAM data, so that the game cannot be continued. Notify to the effect. As a result, it is possible to suppress RAM destruction due to goto. The release of the notification is performed by, for example, changing settings such as power-off.

  As is clear from the timing chart in the normal state shown in FIG. 95E, the monitoring timers A and B, and the monitoring flags A and B do not take the following operating states.

  1) When the sub CPU 71 receives the start command from the main control circuit 60 (at the “start”), both the monitoring timer A and the monitoring timer B are operating.

  2) The state in which both the monitoring timer A and the monitoring timer B are stopped after the sub CPU 71 receives the turning drum rotation start command from the main control circuit 60.

  3) The state where both the monitoring timer A and the monitoring timer B are stopped at the end of the payout.

  4) The state in which both the monitoring timer A and the monitoring timer B are operating at the time of dispensing completion.

  5) The state where the monitoring flag A or the monitoring flag B is turned on after the payout is completed.

  Therefore, when the monitoring timer A and the monitoring timer B take the above-mentioned operating state, or when the monitoring flag A or the monitoring flag B is turned on in the above-mentioned state, it is determined that an illegal game is played. Judgment is made and the occurrence of the sequence error is registered in the error information history storage area 73d-1, and as a fatal error, for example, as shown in FIG. 89, almost all over the liquid crystal display area 23 of the gaming machine 1 Alternatively, it may be notified that the game cannot be continued because an abnormality has occurred in the RAM data. Also in this case, the RAM destruction by the goto action can be suppressed, and the notification is canceled by, for example, changing the setting such as power-off.

  Thereafter, as described above, the menu screen shown in FIG. 82 is displayed in the liquid crystal display area 23, and the clerk operates the operation key to select the “error information history” item 23a. An error information history screen shown in FIG. 83 can be displayed on 23.

  Next, the COM error check processing in step S1814 of the main board communication processing of the sub CPU in FIG. 91 will be described with reference to FIG. FIG. 96 is a diagram showing a flowchart of the COM error check processing performed by the sub control circuit 70 of the present embodiment.

  When the COM error check processing is executed, the sub CPU 71 executes a reception data log storage processing (step S880). The procedure of the reception data log storage processing is as shown in the flowchart of the main board communication reception data log storage processing shown in FIG. In this case, in step S852 shown in FIG. 94, it is determined that a COM error has occurred, and the reception data log storage unit 71e stores the communication log related to the communication error in the communication error storage area 73f-1 (step S853). ).

  Then, the sub CPU 71 determines whether or not the COM error timer is counting (step S881). When determining that the COM error timer is counting, the sub CPU 71 determines whether or not the COM error timer is within 30 minutes (step S882).

  If the sub CPU 71 determines that the COM error timer is within 30 minutes, the error information registration unit 71d registers the occurrence of a communication error (COM error) in the error information history storage area 73d-1 (step S883). Then, the sub CPU 71 sets the count stop of the COM error timer (step S884), and ends the COM error check processing.

  If the sub CPU 71 determines that the COM error timer is not counting, or determines that the COM error timer is not within 30 minutes, the sub CPU 71 sets the count start of the COM error timer (step S885), and The check processing ends.

  As described above, the gaming machine management system according to the present embodiment acquires the error information from the two-dimensional code 300 received by the server 500 and analyzes the analysis PC 600 that analyzes the cause of the error based on the error information. Have. Therefore, it is not limited to simply specifying the content of the communication error in the gaming machine 1 as in the related art, and the cause of the error can be analyzed and specified from the error information using the separately installed analysis PC 600. The cause of the obtained error can be used for subsequent improvement of the gaming machine 1 or the like.

  Further, in the gaming machine 1 of the present embodiment, only when the occurrence of a communication error is detected by the sub CPU 71, the communication error information relating to the communication error is converted into the two-dimensional code 300. The control can be simplified as compared with the case of creating.

  Further, in the gaming machine 1 of the present embodiment, the error information history can be displayed on the liquid crystal display device 5 by operating the door key 2, so that the clerk can display the error information history without operating the setting key of the gaming machine 1. Be able to confirm. For this reason, the clerk can display the error information history of the gaming machine 1 even during business hours, so that the cause of the error can be more effectively identified.

  Moreover, in the gaming machine 1 of the present embodiment, the clerk rotates the door key 2 in the left-hand rotation direction and holds the state in which the error of the gaming machine 1 is reset for a certain period of time, so that the error information history is displayed. It has become. For this reason, the clerk holding the door key 2 can easily display the error information history, and the clerk holding the door key 2 usually has more clerks than the keeper holding the setting key, so that the convenience is improved. be able to.

  Also, in the gaming machine 1 of the present embodiment, when the occurrence of a communication error is detected, the sub CPU 71 uses the sub RAM 73 as error information to indicate that a communication error has occurred, its occurrence time, and its release time. -1 is sequentially stored. Further, the sub CPU 71 creates an error information history from the stored error information, and causes the liquid crystal display device 5 to display the error information history when an information disclosure request is made by operating the door key 2. For this reason, it is possible to confirm the unauthorized release of the communication error notification in the gaming machine 1 and to check the occurrence time and the release time of the communication error notification later.

  Further, in the gaming machine 1 of the present embodiment, the sub CPU 71, when the procedure detecting means 71b detects that the game has progressed in a procedure that cannot occur in a normal game, that is, an abnormal procedure, proceeds to such a case. The occurrence of an abnormal procedure and the procedure that is omitted from the normal procedures are sequentially stored as error information in the sub RAM 73-1. Further, the sub CPU 71 creates an error information history from the stored error information, and causes the liquid crystal display device 5 to display the error information history when an information disclosure request is made by operating the door key 2.

  For example, FIG. 83 shows an example of the error information history in the liquid crystal display area 23. For example, no. In the “BLS123PE” of the error content shown in FIG. 7, normally, the procedure of “B” indicating insertion of a medal or the like is followed by the procedure of “L” and “S” representing start of reel rotation by operating a lever, and reel 1 , The procedure of "2" indicating the stop of the reel 2, the procedure of "3" indicating the stop of the reel 3, and the procedure of "P" of the payment continue, and the game ends.

  However, in this case, the numeral "1" is circled to indicate that the procedure for stopping the reel 1 was omitted. For this reason, compared to the case where an abnormal procedure occurs as in the past, simply returning to the demo screen, the procedure that could not occur in the normal game occurred, the procedure that was omitted, the number of occurrences, whether there was continuous occurrence, etc. Since it can be confirmed, the occurrence of goto can be used as one of the judgment factors. It should be noted that, in addition to encircling the procedure, the lost procedure can be clearly represented by distinguishing it by the color of the character itself, using a different typeface, or making the character line thicker.

  Further, in the gaming machine 1 of the present embodiment, when the data destruction detecting means 71c detects data destruction in the sub RAM 73-1, the sub CPU 71 uses the sub RAM 73-1 as error information to indicate that data destruction has occurred. Is stored sequentially. Further, when an information disclosure request is made by operating the door key 2, the sub CPU 71 reads out the error information history from the error information history storage area 73 d-1 and displays the error information history on the liquid crystal display device 5.

  For this reason, according to the gaming machine 1, it is possible to detect data destruction of the sub RAM 73-1 during a game, and it is possible to suppress occurrence of goto by immediately reporting an error for data destruction. As the error notification, for example, as shown in FIG. 89, when the data in the sub RAM 73-1 of the sub control circuit 70 is destroyed, a fatal error is generated over almost the entire liquid crystal display area 23 of the gaming machine 1. Indicates that the game cannot be continued because an abnormality has occurred in the RAM data. As a result, it is possible to suppress RAM destruction due to goto. The release of the notification is performed by, for example, changing settings such as power-off.

  Further, in the gaming machine of the present embodiment described above, a case has been described in which gaming machine 1 is a pachislot machine. However, the gaming machine according to the present invention is not limited to this, and can be applied to, for example, a pachinko machine having a symbol change display device as described later. Further, in the above-described gaming machine of the present embodiment, the two-dimensional code 300 has been described as including only communication error history data. However, the gaming machine according to the present invention is not limited to this, and may include, for example, an error information history or a game record of a player.

  As described above, when a communication error occurs between the sub-control circuit and the scaler device, the gaming machine of the present embodiment can check the date and time of the error and the content of the error. Useful for managing machines and gaming machines.

[Sub CPU]
Next, the power-on process of the sub CPU 71 will be described with reference to FIG. FIG. 106 is a flowchart of the power-on process of the sub CPU 71.

  The power on process of the sub CPU 71 is an initialization process in the OS. When the power of the sub CPU 71 is turned on, the sub CPU initialization process is performed to initialize the CPU and internal devices and initialize peripheral ICs. The process is executed (Step S910). Next, the sub CPU 71 executes a mother task activation request process described later with reference to FIG. 108A for various task activation requests (step S911). Then, the sub CPU 71 executes a sub RAM management process described later with reference to FIG.

  Further, a power interruption detection circuit is provided in the sub control circuit 70. (Not shown). When the power interruption detection circuit detects a voltage drop, for example, a voltage drop to 4.5 V, it outputs a power interruption detection signal. The sub CPU 71 executes a power supply interruption process shown in FIG. 107 in response to an interruption input from an external interruption port (NMI).

  Unlike the main control, the sub CPU 71 does not calculate the sum value in the power interruption process. The calculation of the sum value by the sub CPU 71 is performed every time a valid command is received, when the effect mode is changed, and the like.

  The mother task request process shown in FIG. 108 (a) is a process of requesting the OS to activate a task necessary for the function of the gaming machine 1. First, the sub CPU 71 issues a start request for the main task (step S1001). Next, as subtask activation requests, a unimemo management task activation request (step S1002), an accessory control task activation request (step S1003), a lamp control task activation request (step S1004), a sound control task activation request (step S1005), A board communication task start request (step S1006), an animation task start request (step S1007), a communication control task start request between sub-devices (step S1008), and then an RTC control task start request (step S1009) are made.

  FIG. 108 (b) shows the game information providing system S. The game information providing system S provides a game information providing service. The game information providing service links a mobile phone with a dedicated site on the Internet, and the player starts playing a game through the dedicated site. This is a service (hereinafter, referred to as “unimemo”) for providing the game contents (game history) up to the time point to the player.

  As shown in FIG. 108 (b), the game information providing system S manages the gaming machine 1, a camera-equipped mobile communication terminal 400 (hereinafter, referred to as “mobile terminal”) owned by the player, and game information. And a data management server 500. In FIG. 108 (b), one portable terminal 400 is shown for convenience of description, but a plurality of portable terminals 400 can access the data management server 500 at the same time.

  The portable terminal 400 and the data management server 500 can mutually transmit and receive data via the network NW using, for example, TCP / IP as a communication protocol. The network NW is constructed by, for example, the Internet, a dedicated communication line (for example, a CATV (Community Antenna Television) line), a mobile communication network (including a base station and the like), a gateway, and the like. The gaming machine 1 is not connected to the network NW.

  Although not shown, the mobile terminal 400 and the data management server 500 each include a control unit, a storage unit, a display unit, a communication unit, and the like. The control unit of the portable terminal 400 according to the present embodiment constitutes a start-time transmitting unit, an output-time transmitting unit, an acquisition request transmitting unit, and a receiving unit of the present invention.

  The sub CPU 71 of the gaming machine 1 records the contents of the game since the player started the game in the game data area 73a-1 or the like of the sub RAM 73-1 and when the player is in the middle of the game or ends the game, When trying to acquire the game information indicating the content, the game information is provided to the player by the QR code (registered trademark) 330 of the two-dimensional code.

  The sub CPU 71 of the gaming machine 1 is recorded in the game data area 73a-1 or the like of the sub RAM 73-1 so that the portable terminal 400 of the player can access the data management server 500 when performing the game information providing service. The game information of the player is converted into a QR code (registered trademark) 330, and the QR code (registered trademark) 330 is displayed on the liquid crystal display area 23.

Specifically, i) when the player starts the game, ii) when the player tries to obtain the game information in the middle of the game, iii) the player tries to obtain the game information at the end of the game. At times, a QR code (registered trademark) 330 is displayed.

  In addition, instead of or together with the QR code (registered trademark) 330, a bar code obtained by converting the game information of the player may be displayed.

  The i) transmission information when the player starts the game includes information on the domain of the data management server 500, login number information indicating the number of logins from power-on, and discrimination between the own gaming machine and another gaming machine. Gaming machine identification information and the like.

  In addition, ii) when the player attempts to obtain game information during the game or iii) when the player attempts to obtain game information at the end of the game, And i) game information indicating the game content recorded after the player started the game.

  The control unit of the portable terminal 400 reads the QR code (registered trademark) 330 displayed on the liquid crystal display area 23 with a camera, and accesses the data management server 500 according to information such as a domain included in the QR code (registered trademark) 330. In the case of the above i), the login frequency information, the gaming machine identification information, etc. included in the QR code (registered trademark) 330 are transmitted as start transmission data. In the case of the above ii) or iii), The number-of-logins information, the gaming machine identification information, the game information, and the like included in the QR code (registered trademark) 330 are transmitted as transmission data at the time of output.

  If there is an access at the time of i), the control unit of the data management server 500 stores the number-of-logins information, the gaming machine identification information, and the like included in the received start transmission data in the storage unit.

  The control unit of the gaming information management server 500, when there is an access at the time of ii), iii), the login number information and the gaming machine identification information included in the received transmission data at the time of output, at the time of i) It is determined whether the stored login number information and gaming machine identification information match, and if they match, game information not shown includes the login number information, gaming machine identification information, game information, etc. included in the output transmission data. Store in DB (database).

  In addition, the control unit of the game information management server 500 generates display data (for example, a Web page) that allows the portable terminal 400 to display the content indicated by the received game information and the like, and Send back. The control unit of the portable terminal 400 causes the display unit to display an image indicating the game content or the like based on the received display data. The player can check the game content and the like from the displayed image.

  Next, a function of the gaming machine 1 when the player uses the game information providing service will be described. The sub CPU 71 of the gaming machine 1 displays a menu screen on the liquid crystal display area 23 when no game is played by any player.

  On the menu screen, items to be selected when a player who intends to use the game information providing service starts a game ("game record start" item) are displayed.

  When the player who wants to start the game selects the "game recording start" item with the selection button 24 and presses the determination button 25, the sub CPU 71 of the gaming machine 1 recognizes that the player starts the game. In addition to displaying the QR code (registered trademark) 330 at the start of the game, recording of the game content is started thereafter.

  Further, when the sub CPU 71 of the gaming machine 1 detects that the player has performed an operation of simultaneously pressing the selection button 24 and the determination button 25 when the player is not playing a game after starting the game, 23 displays a menu screen.

  On the menu screen, an item to be selected when the player acquires game information indicating the game content from the start of the game to that point in time (an “intermediate progress acquisition” item), the game is terminated, and the Items to be selected when obtaining game information indicating the game contents up to this point ("game record end" item) are displayed.

  When the sub CPU 71 of the gaming machine 1 detects that the player has performed an operation of selecting the “interim progress acquisition” item or the “game recording end” item by using the selection button 24 and the determination button 25, The game contents and the like recorded in the game data area 73a-1 and the like of the sub RAM 73-1 are read out, transmission information is generated based on the game contents, the transmission information is converted into a QR code (registered trademark) 330, and the QR code is registered. The code (registered trademark) 330 is displayed on the liquid crystal display area 23.

  Next, a unimemo management task executed by the sub CPU 71 to provide the game information providing service (unimemo) by the game information providing system S will be described. FIG. 109 shows a flowchart of the unimemo management task.

  First, the sub CPU 71 sets a period of 10 ms as time management of the OS (step S1501). When the period of 10 ms has elapsed, the sub CPU 71 determines whether or not the operation performed by the player is a menu activation operation (step S1502). If the sub CPU 71 determines that the operation is a menu activation operation, it makes a unimemo menu display request (step S1503), waits for a period of 10 ms (step S1517), and determines whether the operation performed by the player is a menu activation operation. The process proceeds to a determination process of whether or not there is (step S1502).

  In step S1502, when the sub CPU 71 determines that the operation performed by the player is not the menu activation operation, the sub CPU 71 determines whether the operation performed by the player is a recording start operation (step S1504).

  When the sub CPU 71 determines that the operation performed by the player is the recording start operation, for example, when the player selects the “game recording start” item with the selection button 24 and presses the determination button 25 Then, the recording area for unimemo is initialized (step S1505). For example, the sub CPU 71 initializes the game data area 73a-1 of the sub RAM 73-1.

  Subsequent to step S1505, the sub CPU 71 creates a game recording start QR code (registered trademark) (step S1506), and subsequently makes a game recording start request (step S1507). At this time, the game recording start QR code (registered trademark) is displayed on the liquid crystal display area 23, and the player reads it with the camera of the portable terminal 400. Thereafter, the sub CPU 71 waits for a period of 10 ms (step S1517), and then proceeds to a process of determining whether or not the operation performed by the player is a menu activation operation (step S1502).

  If the sub CPU 71 determines in step S1504 that the operation performed by the player is not a recording start operation, the sub CPU 71 determines whether the operation performed by the player is an intermediate progress acquisition operation (step S1508). .

  In step S1508, if the sub CPU 71 determines that the operation performed by the player is an intermediate progress acquisition operation, for example, the player selects the “intermediate progress acquisition” item with the selection button 24 and presses the determination button 25. If pressed, a password input process, which will be described in detail later, is executed (step S1509).

  Next, the sub CPU 71 determines whether or not the password input processing has been canceled (step S1510). If it is determined that the password input processing has been canceled, the sub CPU 71 waits for a period of 10 ms (step S1517). The process proceeds to a process of determining whether or not the operation performed by the player is a menu activation operation (step S1502).

  If the sub CPU 71 determines in step S1510 that the password input process has not been canceled, it creates a game record QR code (registered trademark) (step S1511). This QR code (registered trademark) is displayed on the liquid crystal display area 23, and when the player reads the QR code with the camera of the portable terminal 400, the game information in the middle of the game is recorded in an area unique to the player in the storage unit of the data management server 500. You.

  In step S1508, if the sub CPU 71 determines that the operation performed by the player is not an intermediate progress acquisition operation, the sub CPU 71 determines whether the operation performed by the player is a recording end operation (step S1512).

  If the sub CPU 71 determines in step S1512 that the operation performed by the player is not the recording end operation, the sub CPU 71 waits for a period of 10 ms (step S1517), and then the operation performed by the player is a menu activation operation. The process proceeds to a determination process of whether or not (step S1502).

  In step S1512, when the sub CPU 71 determines that the operation performed by the player is a recording end operation, for example, the player selects the “game recording end” item with the selection button 24 and presses the determination button 25. If so, a password input process, which will be described in detail later, is executed (step S1513). Next, the sub CPU 71 determines whether or not the password input processing has been canceled (step S1514). If it is determined that the password input processing has been canceled, the sub CPU 71 waits for a period of 10 ms (step S1517). The process proceeds to a process of determining whether or not the operation performed by the player is a menu activation operation (step S1502).

  If the sub CPU 71 determines in step S514 that the password input process has not been canceled, the sub CPU 71 creates a game record QR code (registered trademark) (step S1515). This QR code (registered trademark) is displayed on the liquid crystal display area 23. When the player reads the QR code with the camera of the portable terminal 400, the data is stored in a unique area of the player in the storage unit of the data management server 500 from the middle of the game to the end of the game. Game information is recorded.

  Subsequent to step S1515, the sub CPU 71 issues a game recording end request (step S1516), waits for a period of 10 ms (step S1517), and then determines whether or not the operation performed by the player is a menu activation operation. (Step S1502).

(password input)
FIG. 110 shows an example of a method of inputting a password required when receiving a game information providing service using the touch sensor module 781, for example. FIG. 110 (a) shows an example of an image displayed on the display unit M of the player's portable terminal 400, and FIG. 110 (b) shows an image of the touch sensor module 781 provided in the liquid crystal display area 23. 4 shows an example of a displayed image.

  Using the portable terminal 400, the player accesses a personal information site of the data management server 500 for receiving the game information providing service, and displays a password for receiving the game information providing service.

  FIG. 110A shows a screen M of portable terminal 400 displaying the password. As shown in the screen M, the password is displayed as a combination of white circles from m1 to m9 and lines from mp1 to mp6 connecting these white circles.

  Next, the player selects the game information providing service from the menu screen and displays the password input item on the liquid crystal display area 23 of the gaming machine. When the player touches this password input item with, for example, a fingertip, three rows of three white circles from t1 to t9 appear in the area where the touch sensor module 781 is provided, as shown in FIG. Displayed as a matrix of rows.

  In the same manner as the line connecting the white circles displayed on the screen of the mobile terminal 400, the player selects the white circles from t1 to t9 arranged in a matrix displayed in the area of the touch sensor module 781. When a predetermined white circle is connected with a line, the input of the password is completed.

  As shown in FIG. 110 (c), in the process of inputting the password, a line tp1 is drawn with a fingertip, for example, so as to connect the white circle t1 and the white circle t2, and then connects the white circle t2 and the white circle t5. The line tp2 is drawn by tracing as described above, and then the line tp3 is drawn by tracing the white circle t5 and the white circle t3. The order of drawing the lines does not matter. First, a line tp3 may be drawn by tracing the white circle t5 and the white circle t3.

  If you miss a line, trace it so that it intersects with the line you have drawn.

  Finally, the input operation is completed by drawing the lines from tp1 to tp6 as shown in FIG. 110 (d), similarly to the lines from mp1 to mp6 shown on the screen of the portable terminal 400 in FIG. 110 (a). Let it. As a result, information on the coordinate positions on the XY coordinate axes of the start point and the end point of each line from tp1 to tp6 is stored in the touch operation buffer of the touch sensor relay board 780.

  When the password is input, the sub CPU 71 determines whether the password is correct or not, and executes a predetermined process according to the correctness.

  Next, regarding the password input processing in steps S1509 and S1513 in the unimemo management task described in FIG. 109, the password input processing shown in FIG. 111 will be described. FIG. 111 is a flowchart of the password input process.

  First, the sub CPU 71 obtains coordinate data from the touch operation buffer (step S1601). These coordinate data are XY coordinate values representing the start point and end point of a line drawn so as to connect predetermined white circles on the touch sensor module 781. Next, the sub CPU 71 determines whether or not there is coordinate data in the touch operation buffer (step S1602). When it is determined that there is no coordinate data, the sub CPU 71 waits for a period of 10 ms, and again executes the touch operation buffer. The coordinate data is acquired from (step S1601).

  If the sub CPU 71 determines in step S1602 that there is coordinate data in the touch operation buffer, it determines whether or not the coordinate data matches the password trajectory (step S1604).

  In step S1604, when the sub CPU 71 determines that the coordinate data matches the password trajectory, the sub CPU 71 ends the password input processing.

  If the sub CPU 71 determines in step S1604 that the coordinate data does not match the password trajectory, it clears the touch operation buffer (step S1605) and displays a message indicating that the password is different in the liquid crystal display area 23 (step S1606). ).

  Subsequent to step S1606, the sub CPU 71 determines whether or not there is a cancel input (step S1607). If the sub CPU 71 determines that there is no cancel input, it returns to the step of acquiring coordinate data from the touch operation buffer (step S1601), and if it determines that there is a cancel input, ends the password input process. I do.

  Returning to the mother task flowchart shown in FIG. 108, when the main board communication task start request is issued from the OS in response to the main board communication task start request (step S1006), the main board communication task is executed as shown in FIG. Is executed according to the flowchart shown in FIG.

  Further, the RTC control task is executed according to a flow chat shown in FIG. First, the sub CPU 71 sets a period of 100 ms as OS time management (step S1011). Next, the sub CPU 71 reads the date and time from the external RTC 70c (step S1012), and sets the read date and time of the external RTC 70c as an initial value of the internal RTC 70a (step S1013).

  Next, the sub CPU 71 reads the status information from the external RTC 70c (step S1014), determines whether or not the status information could be read normally (step S1015). It is determined whether there is an abnormality (step S1016). If there is no power supply abnormality, it is determined whether there is an oscillation abnormality (step S1017). If there is no oscillation abnormality, a reset signal is detected. It is determined whether or not this is the case (step S1018). If no reset signal is detected, the date and time are read from the external RTC 70c (step S1019).

  When reading the date and time, the sub CPU 71 determines whether there is an abnormality in the date and time range (step S1020). For example, if the value of year, month, day or time exceeds two digits, it is determined that there is an abnormality in the date and time range. When the sub CPU 71 determines that there is an abnormality in the date and time range, as shown in the table of FIG. 104, the sub CPU 71 sets the error code (RTC TIM) to the error information history storage area 73d-1 of the sub RAM 73-1 as the RTC time abnormality. (Step S1021).

  On the other hand, if the sub CPU 71 determines in step S1015 that the status information cannot be read normally from the external RTC 70c, the error code (RTC) is stored in the error information history storage area 73d-1 as an RTC communication line error. DSC) is registered (step S1021).

  If the sub CPU 71 determines in step S1016 that there is an abnormality in the power supply with respect to the external RTC 70c, it registers an error code (RTC POWER) as the RTC voltage drop in the error information history storage area 73d-1 (step S1016). S1021).

  If the sub CPU 71 determines in step S1017 that the external RTC 70c has an oscillation abnormality, the sub CPU 71 registers an error code (RTC CLK) in the error information history storage area 73d-1 as oscillation stop detection (step S1017). Step S1021).

  When the error code corresponding to the error type of the external RTC 70c is registered as the error information in step S1021 as described above, the sub CPU 71 initializes the external RTC 70c, and sets the current date and time of the built-in RTC 70a in the external RTC 70c. (Step S1022).

  As described above, when the external RTC 70c is initialized and the current date and time of the internal RTC 70a are set in the external RTC 70c, or when it is determined in step S1020 that there is no abnormality in the date and time range read from the external RTC 70c in step S1019. In step S1023, the sub CPU 71 determines whether the date and time setting of the external RTC 70c has been changed from the attendant operation screen (step S1023). It is set to the RTC 70c (step S1024).

  If the date and time data of the internal RTC 70a is set in the external RTC 70c in step S1024, or if it is determined in step S1023 that there is no change in the date and time setting of the external RTC 70c, the sub CPU 71 waits for a period of 100 ms. Then, the status information is read from the external RTC 70c again (step S1014).

  Next, a management process of the sub-control backup memory (SRAM) 73-2 will be described with reference to FIG. FIG. 113 shows a flowchart of the sub management process.

  First, the sub CPU 71 calculates a sum value of the backup data 1 area 73a-2 of the SRAM 73-2 to obtain a 4-byte backup data 1 sum value (step S1031). Next, the sub CPU 71 determines whether the obtained sum value is normal and whether the magic code of the backup data 1 area 73a-2 is the same as the magic code of the program management data area 72f of the sub ROM 72. Then, in the case of YES, the backup data 1 area 73a-2 of the backup RAM 73-2 is copied to the game data area 73a-1 of the sub RAM 73-1 (step S1033).

  In step S1032, if the sub CPU 71 determines NO, it calculates the sum value of the backup data 2 area 73c-2 that is the mirroring of the backup data 1 area 73a-2, and calculates the 4-byte backup data 2 sum value. Is obtained (step S1034).

  Subsequent to step S1034, the sub CPU 71 determines whether the obtained sum value is normal and whether the magic code of the backup data 2 area 73c-2 is the same as the magic code of the program management data area 72f of the sub ROM 72. A determination is made (step S1035).

  If the determination in step S1035 is YES, the sub CPU 71 copies the backup data 2 area 73c-2 of the backup RAM 73-2 to the game data area 73a-1 of the sub RAM 73-1 (step S1036).

  If the determination in step S1035 is NO, the sub CPU 71 copies the game data initialization setting data area 72c of the sub ROM 72 to the game data area 73a-1 of the sub RAM 73-1 (step S1037).

  When step S1036 or step S1037 is executed, the sub CPU 71 registers an error code (MEM ERR 1) in the error information history storage area 73d-1 as a game data sum error (step S1038). However, a screen for notifying the RAM data abnormality as shown in FIG. 89 is not displayed.

  After executing the processing in step S1033 or the processing in step S1038, the sub CPU 71 calculates a 4-byte sum value from the attendant backup data area 73e-2 and stores it in the attendant backup data sum value area 73g-2. (Step S1039).

  Next, the sub CPU 71 determines whether or not the stored sum value of the staff backup data area 73g-2 is normal (step S1040). The data is copied to the staff operation setting data area 73h-1 of the RAM 73-1 (step S1041).

  If the determination in step S1040 is NO, the sub CPU 71 copies the data of the staff operation initial setting data area 72d of the sub ROM 72 to the staff operation setting data area 73g-1 of the sub RAM 73-1 (step S1042).

  After executing step S1042, the sub CPU 71 registers an error code (MEM ERR 2) as a staff operation setting data sum error in the error information history storage area 73d-1 (step S1043). Also for this RAM data abnormality, a screen for notifying the abnormality as shown in FIG. 89 is not displayed.

  Next, after executing Step S1041 or Step S1043, the sub CPU 71 executes a backup creation process shown in FIG. 114 described later (Step S1044).

  As described above, the sub CPU 71 determines whether the obtained sum value is normal and whether the magic code of the backup data 2 area 73c-2 is the same as the magic code of the program management data area 72f of the sub ROM 72. If the sum value or the magic code is not the same (step S1035), the sub CPU 71 copies the game data initialization setting data area 72c of the sub ROM 72 to the game data area 73a-1 of the sub RAM 73-1 (step S1035). Step S1037).

  The sub CPU 71 determines whether the sum value of the staff backup data area 73g-2 is normal (step S1040). If the sum value is abnormal, the data in the staff operation initial setting data area 72d of the sub ROM 72 is stored in the sub RAM 73. -1 is copied to the staff operation setting data area 73g-1 (step S1042).

  Thus, when the power is turned on, it is possible to confirm whether the data in the sub RAM 73-1 is damaged, and it is possible to automatically set the initial value without using the damaged SRAM data.

  FIG. 114 is a flowchart of the backup creation process of the sub RAM management process shown in FIG. 113. With this processing, even if the data is destroyed, the correct value can be stored as a backup.

  First, the sub CPU 71 creates a sum value for the game data area 73a-1, and stores the created sum value in the game data sum value area 73b-1 (step S1051). Next, the sub CPU 71 copies the game data area 73a-1 to the backup data 1 area 73a-2, and stores the sum value saved in step S1051 in the backup data 1 sum value area 73b-2 (step S1052).

  Next, the sub CPU 71 copies the game data area 73a-1 to the backup data 2 area 73c-2 as a mirroring of the backup data 1 area 73a-2, and stores the sum value stored in step S1051 in the backup data 2 sum value area. 73d-2 (step S1053).

  Next, the sub CPU 71 creates a sum value of the attendant operation setting data area 73g-1 and stores the created sum value in the attendant operation setting data sum value area 73h-1 (step S1054).

  Next, the sub CPU 71 copies the attendant operation setting data area 73g-1 to the attendant backup data area 73e-2, and saves the sum value saved in step S1054 to the attendant backup data sum value 73g-2 (step S1055). . Thus, the backup creation processing ends.

  Next, the inter-sub-device communication control task shown in FIG. 115 will be described. FIG. 115 is a diagram illustrating a flowchart of the inter-sub-device communication control task.

  First, the sub CPU 71 sets a period of 4 ms (step S1061). Subsequently, the sub CPU 71 performs the initial setting of the serial port for the sub device at a time (step S1062).

  Next, the sub CPU 71 waits for a period of 4 ms (step S1063), and subsequently executes a sub device command receiving process shown in FIG. 117 described later (step S1064).

  After executing the sub device command receiving process in step S1064, the sub CPU 71 determines whether or not a command has been received (step S1065). If the command has not been received, the sub device communication interruption shown in FIG. The processing is executed (step S1070).

  When receiving the command in step S1065, the sub CPU 71 executes a sub-device communication return process shown in FIG. 122 described later (step S1066), and thereafter performs a reception process of the sub-device communication shown in FIG. 118 described later. Is executed (step S1067).

  After executing the sub-device communication reception process in step S1067, the sub CPU 71 determines whether there is a command to be transmitted (step S1068), and if there is a transmission command, executes the sub-device command transmission process. (Step S1069).

  After executing the sub device command transmission process in step S1069, or when determining that there is no transmission command in step S1068, or after executing the sub device communication disconnection process in step S1070, the sub CPU 71 proceeds to step S1063. The process returns to wait for a period of 4 ms, and executes the sub device command receiving process again (step S1064).

  Next, the sub-device serial reception interrupt processing shown in FIG. 116 will be described. FIG. 116 is a view showing a flowchart of the sub-device serial reception interrupt processing. The sub CPU 71 reads the reception status (step S1081), and determines whether there is an error in the physical layer (step S1082).

  If the sub CPU 71 determines in step S1082 that there is no error in the physical layer, it stores the received data in the communication log collection ring buffer area 73e-1 (step S1083). The size of the buffer for storing the received data is 512 bytes. The storage of the received data ends the sub-device serial reception interrupt processing.

  If the sub CPU 71 determines in step S1082 that there is an error in the physical layer, it stores the error code (SD COM) in the error information history storage area 73d-1 as a subdevice physical layer error (step S1084). Then, the sub-device serial reception interrupt processing ends. Since the sub-device physical layer error is not as serious as the COM error, it is registered separately from the COM error.

  Next, the sub-device command receiving process in the inter-sub-device communication control task shown in FIG. 115 will be described with reference to FIG. FIG. 117 is a diagram showing a flowchart of the sub device command receiving process.

  First, the sub CPU 71 sets the reception buffer address in the communication log collection ring buffer area 73e-1, and turns off the STX reception flag (step S1091). Next, the sub CPU 71 attempts to acquire one byte of the received data from the communication log collection ring buffer area 73e-1 (step S1092), and determines whether or not there is received data (step S1093).

  In step S1093, when determining that there is no received data, the sub CPU 71 registers an error code (SD COM STX) in the error information history storage area 73d-1 (step S1105).

  In step S1093, when determining that there is received data, the sub CPU 71 determines whether the received data is STX and the STX reception flag is off (step S1094). If the sub CPU 71 determines in step S1094 that the received data is STX and the STX reception flag is off, the sub CPU 71 turns on the STX reception flag (step S1095), clears the command registration buffer (step S1096), and sets the reception buffer address. Is updated and 1 byte is added (step S1097), and one byte of received data is acquired from the reception buffer again (step S1092). The sub CPU 71 repeats this for the number of data.

  If the sub CPU 71 determines in step S1094 that the received data is STX and the STX reception flag is not off, the sub CPU 71 determines whether the received data is ETX and the STX reception flag is on (step S1098).

  If the sub CPU 71 determines in step S1098 that the received data is ETX and the STX reception flag is ON, the sub CPU 71 creates a sum value from the received data, and updates the sum value of the received data stored in the reception buffer. It is acquired (step S1099).

  Next, the sub CPU 71 determines whether the sum value of the received data is normal by comparing the created sum value with the stored sum value (step S1100). If it is determined, the sub device command receiving process ends. When the sub device error detecting means 71h of the sub CPU 71 determines that the sum value of the received data is abnormal, the sub CPU 71 sets the error code in the error information history storage area 73d-1 as an error of the sub device SUM. (SD COM SUM) is registered (step S1101).

  If the sub CPU 71 determines in step S1098 that the received data is ETX and the STX reception flag is not on, the sub CPU 71 determines whether the reception data is ETX and the STX reception flag is off (step S1102).

  In step S1102, when the sub device error detecting means 71h of the sub CPU 71 determines that the received data is ETX and the STX reception flag is off, the sub CPU 71 stores the error information in the error information history storage area 73d-1. The code (SD COM STX) is registered (step S1105), and the sub device command reception processing ends.

  In step S1102, when the sub CPU 71 determines that the received data is ETX and the STX reception flag is not off, the sub CPU 71 stores the received data in the command registration buffer (step S1103), updates the reception buffer address, and Bytes are added (step S1104), and one byte of reception data is acquired from the reception buffer again (step S1092). The sub CPU 71 repeats this for the number of data.

  Next, the reception process of the sub-device communication in the inter-sub-device communication control task shown in FIG. 115 will be described with reference to FIG. FIG. 118 is a diagram illustrating a flowchart of the process at the time of reception of sub device communication.

  The sub CPU 71 first obtains a device ID from the command “ADR” stored in the command registration buffer (step S1111), and determines whether or not the destination of the device ID is the sub CPU 71 (step S1112). In step S1112, when the sub device error detecting unit 71h of the sub CPU 71 determines that the transmission destination of the device ID is not the sub CPU 71, the sub CPU 71 stores the sub device ID error in the error information history storage area 73d-1. , An error code (SD COM DVC) is registered (step S1119). Thus, the sub CPU 71 ends the reception process of the sub device communication.

  In step S1112, when the sub CPU 71 determines that the transmission destination of the device ID is the sub CPU 71, the sub CPU 71 further determines whether the transmission source of the device ID is the scaler control LSI of the scaler control board 77 ( Step S1113).

  If the sub CPU 71 determines in step S1113 that the source of the device ID is the scalar control LSI of the scalar control board 77, it executes a scalar control command reception process (step S1114), and receives the sub device communication. The time processing ends.

  If the device error detection means 71h of the sub CPU 71 determines in step S1113 that the source of the device ID is not the scalar control LSI of the scalar control board 77, the sub CPU 71 subsequently transmits the device ID. It is determined whether the source is the touch sensor control LSI of the touch sensor relay board 780 (step S1115). If it is determined that the source of the device ID is the touch sensor control LSI of the touch sensor relay board 780, the sub CPU 71 However, the process at the time of receiving a touch sensor relay command shown in FIG. 119 described later is executed (step S1116), and the process at the time of reception of sub device communication is terminated.

  If the sub CPU 71 determines in step S1115 that the source of the device ID is not the touch sensor, then the sub CPU 71 determines whether the source of the device ID is a camera (step S1117).

  If it is determined in step S1117 that the transmission source of the device ID is the camera, the sub CPU 71 executes a camera relay command receiving process (step S1118), and ends the sub device communication receiving process.

  In step S1117, when the device error detecting means 71h of the sub CPU 71 determines that the transmission source of the device ID is not the camera, the device ID is not any of the sub devices connected to the sub CPU 71. Then, an error code (SD COM DVC) is registered as an abnormal sub device ID in the error information history storage area 73d-1 (step S1119). Thus, the sub CPU 71 ends the reception process of the sub device communication.

  As described above, when a plurality of sub-devices are connected to the sub-CPU 71, the common program executes the command reception processing based on the consistency check table set for each device by the common program. Can be checked for consistency.

  Next, with reference to FIG. 119, the process at the time of receiving the touch sensor relay command in the process at the time of receiving the sub device communication shown in FIG. At this time, reference is made to FIG. 100, FIG. 101 and FIG. 100 shows a transmission / reception command data format, FIG. 101 shows a transmission / reception data content, FIG. 102 shows a sub-device communication data consistency check table, and FIG. 119 shows a touch sensor relay command reception process. It is a figure which shows a flowchart.

  First, the sub CPU 71 reads the touch sensor reception data consistency check table shown in FIG. 102 from the various program table areas 72e and sets it in the work area 73c-1 (step S1121). The sub CPU 71 passes the set table as an argument for the reception data determination processing in the next step, and thereby executes the sub device reception data determination processing shown in FIG. 120 described later (step S1122).

  Next, the sub CPU 71 determines whether or not the received data after the sub device received data determination processing is normal (step S1123). In step S1123, when the sub device error detecting means 71h determines that there is inconsistency in the received data, the sub device 71 returns the error information as a return value, and the sub CPU 71 returns an error corresponding to the error information based on the returned error information. The code is registered (step S1124). The error code is shown in FIG. Thus, the sub CPU 71 ends the process at the time of receiving the touch sensor relay command.

  In step S1123, when the sub CPU 71 determines that the received data is normal and has no error code, the sub CPU 71 determines whether the CMD of the received data is a “touch operation” (step S1125). In step S1125, when the sub CPU 71 determines that the CMD of the received data is “touch operation”, the sub CPU 71 stores the XY coordinate data on the touch sensor module by the touch operation in the touch operation buffer of the touch sensor relay board. Then (step S1126), the process at the time of receiving the touch sensor relay command is terminated.

  If the sub CPU 71 determines in step S1125 that the CMD of the received data is not a “touch operation”, the sub CPU 71 determines whether the CMD of the received data is a “flick operation” (step S1127).

  In step S1127, if the sub CPU 71 determines that the CMD of the received data is “flick operation”, the sub CPU 71 stores the XY coordinate data on the touch sensor module by the flick operation in the flick operation buffer of the touch sensor relay board. (Step S1128), and the process at the time of receiving a touch sensor relay command is ended.

  If the sub CPU 71 determines in step S1127 that the CMD of the received data is not a “flick operation”, then the sub CPU 71 determines whether the CMD of the received data is a “pinch operation” (step S1129).

  In step S1129, when the sub CPU 71 determines that the CMD of the received data is “pinch operation”, the sub CPU 71 stores the XY coordinates on the touch sensor module by the pinch operation in the pinch operation buffer of the touch sensor relay board. The data is saved (step S1130), and the process at the time of receiving the touch sensor relay command is terminated.

  If the sub CPU 71 determines in step S1129 that the CMD of the received data is not “pinch operation”, the sub CPU 71 determines whether the CMD of the received data is “reset notification” (step S1131). ).

  In step S1131, when the sub device error detecting means 71h of the sub CPU 71 determines that the CMD of the received data is “reset notification”, the sub CPU 71 notifies the error information history storage area 73d-1 of the occurrence of the reset. The touch sensor reset notification code (TS RST) is registered as error information (step S1132). Thus, the sub CPU 71 ends the process at the time of receiving the touch sensor relay command.

  In step S1131, if the sub CPU 71 determines that the CMD of the received data is not the “reset notification”, the sub CPU 71 ends the process at the time of receiving the touch sensor relay command.

  Next, the sub-device received data determination processing in the touch sensor relay command reception processing shown in FIG. 119 will be described with reference to FIG. FIG. 120 is a diagram showing a flowchart of the sub-device received data determination processing.

  First, the sub CPU 71 acquires the size of the DATA section of the reception buffer. In this case, the sub CPU 71 passes the target position address of the sub device communication check table shown in FIG. 102 in the various program table areas 72e as an argument address. Regarding the touch sensor relay board 780, the sub-device communication check table No. 3 and No. 3 This is the position corresponding to No. 4.

  The sub CPU 71 checks the presence or absence and size of the data in the received data based on the data (step S1161), and then determines whether the DATA size is 256 bytes or less (step S1162).

  In step S1162, when the sub device error detecting unit 71h of the sub CPU 71 determines that the DATA size is not smaller than 256 bytes, the sub CPU 71 determines that the data size is abnormal and stores the error in the error information history storage area 73d-1. The code (TS COM SIZ) is registered (step S1163). The sub CPU 71 ends the sub device reception data determination processing.

  In step S1162, when the sub device error detecting means 71h of the sub CPU 71 determines that the DATA size is 256 bytes or less, the sub CPU 71 determines whether or not there is a type registration in the sub device communication check table. (Step S1164).

  In step S1164, when the sub device error detecting means 71h of the sub CPU 71 determines that the type is not registered in the sub device communication check table, the sub CPU 71 determines that the command type is abnormal and stores the command type in the error information history storage area 73d-1. Register the error code (SD COM TYP).

  In step S1164, when the sub CPU 71 determines that the type is registered in the sub device communication check table, the sub CPU 71 acquires the determination condition in the CMD type from the sub device communication check table (step S1165), and It is determined whether or not the type of CMD matches the determination condition (step S1166).

  If the sub CPU 71 determines in step S1166 that the CMD type does not match the determination condition, the sub CPU 71 updates the check table, for example, updates the check table from the CMD of determination 1 to the CMD of determination 2 (step S1167). ). After updating the check table, the sub CPU 71 again determines whether or not the type is registered in the sub device communication check table (step S1164).

  If the sub CPU 71 determines in step S1166 that the type of CMD matches the determination condition, the sub CPU 71 updates the check table and moves to the DATA determination corresponding to CMD (step S1168). For example, in the case of determination 3 for the touch sensor, The check table is updated to the position of the judgment 3 of 4. Subsequently, the sub CPU 71 acquires a determination condition regarding the DATA size from the check table (step S1169).

  After the execution of step S1169, the sub CPU 71 determines whether or not the DATA size of the received data matches the determination condition (step S1170). In step S1170, when the sub CPU 71 determines that the DATA size of the received data matches the determination condition, the sub CPU 71 ends the sub device received data determination processing.

  In step S1170, if the sub device error detecting means 71h of the sub CPU 71 determines that the DATA size of the received data does not match the determination condition, the sub CPU 71 determines that the packet size is abnormal and stores it in the error information history storage area 73d-1. Register the error code (TS COM PKT). Thus, the sub CPU 71 ends the sub device received data determination processing.

  Next, the sub-device communication disconnection process in the inter-sub-device communication control task shown in FIG. 115 will be described with reference to FIG. FIG. 121 is a diagram showing a flowchart of the sub-device communication disconnection process.

  Since the sub-CPU 71 first executes the inter-sub-device communication control task shown in FIG. 115 at a cycle of 4 ms, it updates the scalar communication disconnection counter at 4 ms and adds 1 (step S1141), and the scalar communication disconnection counter. Is determined to be, for example, 1250 or more (step S1142). This is because if the sub CPU 71 does not receive data from the scaler control board 77 for 5 seconds, for example, it is determined that communication has been disconnected, and 4 ms × 1250 = 5 s.

  In step S1142, when the sub CPU 71 determines that the scaler communication disconnection counter is 1250 or more, the sub CPU 71 determines whether the scaler communication disconnection flag is on (step S1143).

  If the sub CPU 71 determines in step S1143 that the scalar communication disconnection flag is not on, the sub CPU 71 turns on the scalar communication disconnection flag (step S1144). An error code (SCL DSC) is registered as disconnection (step S1145).

  When the sub CPU 71 determines in step S1142 that the scalar communication disconnection counter is not equal to or greater than 1250, or determines in step S1143 that the scalar communication disconnection flag is on, or executes step S1145, the touch sensor The communication interruption counter is updated and 1 is added (step S1146), and it is determined whether the touch sensor communication interruption counter is, for example, 1250 or more (step S1147).

  In step S1147, when determining that the touch sensor communication disconnection counter is 1250 or more, the sub CPU 71 determines whether or not the touch sensor communication disconnection flag is ON (step S1148).

  If the sub CPU 71 determines in step S1148 that the touch sensor communication disconnection flag is not on, the sub CPU 71 turns on the touch sensor communication disconnection flag (step S1149), and then stores the error information history storage area 73d-1 in the error information history storage area 73d-1. An error code (TS DSC) is registered as the disconnection of the touch sensor communication (step S1150).

  When the sub CPU 71 determines in step S1147 that the touch sensor communication disconnection counter is not equal to or greater than 1250, in step S1148 determines that the touch sensor communication disconnection flag is on, or executes step S1150, The camera communication disconnection counter is updated and 1 is added (step S1151), and it is determined whether the camera communication disconnection counter is, for example, 1250 or more (step S1152).

  If the sub CPU 71 determines in step S1152 that the camera communication disconnection counter is 1250 or more, it determines whether the camera communication disconnection flag is on (step S1153).

  If the sub CPU 71 determines in step S1153 that the camera communication disconnection flag is not on, it turns on the camera communication disconnection flag (step S1154), and then stores the camera communication disconnection flag in the error information history storage area 73d-1. An error code (CCD DSC) is registered as disconnection (step S1155).

  When the sub CPU 71 determines in step S1152 that the camera communication disconnection counter is not equal to or greater than 1250, or determines in step S1153 that the camera communication disconnection flag is ON, or executes step S1155, the sub device The communication disconnection process ends.

  In the inter-sub-device communication control task shown in FIG. 115, when the sub-device communication disconnection process shown in FIG. 121 ends, the task process returns to the sub-device command reception process (step S1064), and the task does not end. When the sub-device communication restoration process shown in FIG. 122 described below is executed and communication is resumed, the communication restoration is registered as an error history.

  Therefore, even if an error occurs in which the communication between the sub CPU 71 and the sub control board 77 is interrupted, the communication task is not terminated, and the communication can be restarted. Further, since the communication restart is registered in the error history, the date and time of the communication interruption and the communication restart can be confirmed in the error history.

  Next, the sub-device communication return processing in the inter-sub-device communication control task shown in FIG. 115 will be described with reference to FIG. FIG. 122 is a diagram showing a flowchart of the sub-device communication return processing.

  The sub CPU 71 first determines whether or not the received transmission source ID is the scalar control board 77 (step S1181). If the sub CPU 71 determines that the received transmission source ID is the scalar control board 77, the scalar communication is performed. It is determined whether the disconnection flag is on (step S1182).

In step S1182, when the sub device error detecting means 71h of the sub CPU 71 determines that the scalar communication disconnection flag is on, the sub CPU 71 stores the error code in the error information history storage area 73d-1 as communication recovery. (SCL RSM) is registered (step S1183).

  In step S1182, when the sub device error detecting means 71h of the sub CPU 71 determines that the scalar communication disconnection flag is not on or after registering the error in step S1183, the sub CPU 71 turns off the scalar communication disconnection flag. At the same time, the scalar communication disconnection counter is cleared to 0 (step S1184).

  In step S1181, when the sub CPU 71 determines that the received transmission source ID is not the scaler control board 77, the sub CPU 71 determines whether the received transmission source ID is the touch sensor relay board 780 (step S1185). If it is determined that the transmitted source ID is the touch sensor relay board 780, it is determined whether or not the touch sensor communication disconnection flag is on (step S1186).

  In step S1186, when the sub device error detection unit 71h of the sub CPU 71 determines that the touch sensor communication disconnection flag is on, the sub CPU 71 stores the error in the error information history storage area 73d-1 as communication recovery. The code (TS RSM) is registered (step S1187).

  In step S1186, if the sub device error detecting means 71h of the sub CPU 71 determines that the touch sensor communication disconnection flag is not on, or after registering the error in step S1187, the sub CPU 71 turns off the touch sensor communication disconnection flag. At the same time, the touch sensor communication disconnection counter is cleared to 0 (step S1188).

  In step S1185, when the sub CPU 71 determines that the received transmission source ID is not the touch sensor relay substrate 780, the sub CPU 71 determines whether the received transmission source ID is the camera relay substrate 790 (step S1189). If it is determined that the transmitted source ID is the camera relay board 790, it is determined whether the camera communication disconnection flag is on (step S1190).

In step S1190, if the sub device error detecting means 71h of the sub CPU 71 determines that the camera communication disconnection flag is ON, the sub CPU 71 stores the error code in the error information history storage area 73d-1 as communication recovery. Register (CCD RSM) (
Step S1191).

  In step S1190, if the sub device error detecting means 71h of the sub CPU 71 determines that the camera communication disconnection flag is not on, or after registering the error in step S1191, the sub CPU 71 turns off the camera communication disconnection flag. At the same time, the camera communication disconnection counter is cleared to 0 (step S1192).

  In step S1184, when the sub CPU 71 turns off the scalar communication disconnection flag and clears the scalar communication disconnection counter to 0, in step S1188, the sub CPU 71 turns off the touch sensor communication disconnection flag and sets the touch sensor When the communication disconnection counter is cleared to 0, the sub CPU 71 determines in step S1189 that the received transmission source ID is not the camera relay board 790, or in step S1192, the sub CPU 71 sets the camera communication disconnection flag to When the camera is turned off and the camera communication disconnection counter is cleared to 0, the sub CPU 71 ends the sub device communication return processing.

  Next, a control flow in the touch sensor relay board will be described with reference to FIG. FIG. 123 is a view illustrating a flowchart of the control main task of the touch sensor relay board.

  In the flowchart of the touch sensor relay main task in FIG. 123, “U1” indicates the touch sensor control of the touch sensor relay board 780 in order for the sub device (the touch sensor control LSI of the touch sensor relay board 780) to perform transmission and reception with the sub CPU 71. This is a serial port U1 provided in the LSI.

  “U2” indicates, for example, when the scaler control board 77 or the camera relay board 790 is connected to the sub CPU 71 via the touch sensor relay board 780 as another sub device, the touch sensor of the touch sensor relay board 780 This is a serial port U2 included in the touch sensor relay board 780 for passing received data from the control LSI to those other devices.

  In addition, U1 and U2 both receive the reception data in units of one byte at the reception interruption. The processing of the touch sensor relay main task is almost the same as the sub device serial reception interrupt processing of the sub CPU 71 shown in FIG. 116, but the error registration processing is not performed in the processing of the touch sensor relay main task.

  In the touch sensor relay main task of FIG. 123, the touch sensor control LSI of the touch sensor relay board 780 first performs an initial setting process (step S1201). The touch sensor control LSI sets, for example, a timer and a serial port in the touch sensor relay board 780, initializes a work RAM, and performs initial settings such as a resolution of the touch sensor module.

  Next, the touch sensor control LSI performs a 10 ms cycle setting (step S1202). This waits for the remaining processing time so far. For example, if the processing time so far is 1.5 ms, 8.5 ms is the standby time. However, the reception interrupt processing operates even during standby.

  Next, the touch sensor control LSI executes a sub-control reception process shown in FIG. 124 described later (step S1203), and then executes a touch sensor module input process shown in FIG. 125 described later (step S1204).

  After the execution of step S1204, when the scaler control board 77 and the camera relay board 790 are connected as sub-devices in addition to the touch sensor relay board 780, and when the transmission destination is the sub CPU 71, the touch sensor control LSI In the other device reception processing, transmission is executed through (step S1205).

  After execution of step S1205, the touch sensor control LSI determines whether or not there is a transmission to the sub CPU 71 (step S1206). If it is determined that there is a transmission to the sub CPU 71, the touch sensor control LSI executes a sub control transmission process (step S1206). Step S1207).

  When the touch sensor control LSI determines in step S1206 that there is no transmission to the sub CPU 71, or after executing step S1207, it determines whether or not there is transmission to another sub device (step S1208).

  If it is determined in step S1208 that there is a transmission to another sub device, the touch sensor control LSI performs through transmission when transmission is performed from the sub CPU 71 to the other sub device (step S1209). If there is no connection of another sub device, no transmission / reception data is generated.

  After executing step S1209 or when determining in step S1208 that there is no transmission to another sub device, the touch sensor control LSI executes an operation state determination process illustrated in FIG. 127 described below (step S1210). ). After execution of step S1210, the touch sensor control LSI waits for the remaining time of the 10 ms period (step S1211), and executes the sub-control reception process again (step S1203).

  Next, the sub-control reception processing in the touch sensor relay main task shown in FIG. 123 will be described with reference to FIG. FIG. 124 is a diagram showing a flowchart of the sub-control reception process.

  The touch sensor control LSI determines whether or not there is received data (step S1221), and when it is determined that there is received data, determines whether or not the transmission destination ID of the received data is the touch sensor control LSI. (Step S1222).

  In step S1222, when the touch sensor control LSI determines that the transmission destination ID of the received data is not the touch sensor control LSI, the touch data is copied to another sub-device transmission buffer and the received data is transmitted through ( Step S1223).

  The touch sensor control LSI ends the sub-control reception process when determining in step S1222 that the destination ID of the received data is the touch sensor control LSI, or when copying the received data in step S1223. I do.

  Next, the touch sensor module input processing in the touch sensor relay main task shown in FIG. 123 will be described with reference to FIG. FIG. 125 is a view illustrating a flowchart of the touch sensor module input processing.

  When the operation information is input from the touch sensor module (step S1231), the touch sensor control LSI determines whether or not there is an operation input from the touch sensor (step S1232). If the touch sensor control LSI determines in step S1232 that there is no operation input from the touch sensor, the touch sensor module input processing ends.

  If the touch sensor control LSI determines in step S1232 that there has been an operation input from the touch sensor, the touch sensor control LSI reads the operation type and the XY coordinate data of the operation input (step S1233), and determines whether the input operation type is touch. It is determined whether or not it is (step S1234).

  If the touch sensor control LSI determines in step S1234 that the input operation type is touch, the touch operation command and the XY coordinate data are set in the sub-control transmission buffer (step S1235), and the touch sensor module The input processing ends.

  If the touch sensor control LSI determines in step S1234 that the input operation type is not touch, the touch sensor control LSI determines whether the input operation type is flick (step S1236).

  If the touch sensor control LSI determines in step S1236 that the input operation type is flick, the flick operation command and the XY coordinate data are set in the sub control transmission buffer (step S1237), and the touch sensor module The input processing ends.

  If it is determined in step S1236 that the input operation type is not flick, the touch sensor control LSI determines whether the input operation type is pinch (step S1238).

  If the touch sensor control LSI determines in step S1238 that the input operation type is pinch, the touch sensor control LSI sets a pinch operation command and XY coordinate data in the sub-control transmission buffer (step S1239), and the touch sensor module The input processing ends.

  If the touch sensor control LSI determines in step S1238 that the input operation type is not pinch, it determines that an impossible operation type has been input, and turns on the touch sensor input abnormality flag (step S1240). The input processing is completed and a reset request is issued to the sub CPU 71.

  Next, the sub-control transmission process in the touch sensor relay main task shown in FIG. 123 will be described with reference to FIG. FIG. 126 is a diagram illustrating a flowchart of the sub-control transmission process.

  The touch sensor control LSI updates the sub control transmission interval counter of the transmission data to the sub CPU 71 and adds 1 (step S1241).

  Next, the touch sensor control LSI determines whether the data transmission interval to the sub CPU 71 is equal to or longer than 200 ms (step S1242). If the touch sensor control LSI determines in step S1242 that the data transmission interval to the sub CPU 71 is 200 ms or more, the touch sensor control LSI determines whether there is transmission data in the transmission buffer (step S1243). On the other hand, when the touch sensor control LSI determines in step S1242 that the data transmission interval to the sub CPU 71 is less than 200 ms, the sub control transmission process ends.

  If the touch sensor control LSI determines in step S1243 that there is no transmission data in the transmission buffer, it sets an operation confirmation command in the sub-control transmission buffer (step S1244).

  If the touch sensor control LSI determines in step S1243 that there is transmission data in the transmission buffer, or after executing step S1244, the touch sensor control LSI transmits the transmission data to the sub-control (step S1245), and the sub-control transmission interval The counter is cleared to 0 (step S1246). Thereby, the touch sensor control LSI ends the sub-control transmission processing.

  In step S1245, when the operation confirmation command set in step S1244 and the transmission data set in the touch sensor module input processing are transmitted from the touch sensor control LSI to the sub CPU 71, the sub CPU 71 In order to confirm that the signal has been received from the board 780, it is not determined that the communication has been disconnected.

  Next, the operation state determination processing in the touch sensor relay main task shown in FIG. 123 will be described with reference to FIG. FIG. 127 is a view illustrating a flowchart of the operation state determination processing.

  First, the touch sensor control LSI updates the determination interval counter and adds 1 (step S1251).

  Next, the touch sensor control LSI determines whether or not the determination interval is equal to or longer than 500 ms (step S1252). If the touch sensor control LSI determines in step S1252 that the determination interval is equal to or longer than 500 ms, it clears the determination interval counter to 0 (step S1253), and reads the data in the self-diagnosis area of the ROM into the register (step S1253). (S1254) Then, the data read into the register is written into the self-diagnosis area of the RAM (step S1255).

  Next, the touch sensor control LSI determines whether or not the value read into the register in step S1254 is the same as the value in the self-diagnosis area of the ROM (step S1256). If the touch sensor control LSI determines in step S1256 that the read value is the same as the value in the self-diagnosis area of the ROM, the touch sensor control LSI determines the value read in the register in step S1254 and the value of the self-diagnosis area in the RAM. It is determined whether or not the value is the same (step S1257).

  In step S1257, when the touch sensor control LSI determines that the value read into the register in step S1254 is not the same as the value in the self-diagnosis area of the RAM, or in step S1256, the value read into the register in step S1254 is used. If it is determined that the value is not the same as the value of the self-diagnosis area of the ROM, a reset notification (1) command is set in the sub-control transmission buffer (step S1258).

  On the other hand, the touch sensor control LSI determines in step S1252 that the determination interval is less than 500 ms, or in step S1257, the value read into the register in step S1254 is the same as the value in the self-diagnosis area of the RAM. If determined, the touch sensor setting state is read (step S1259), and it is determined whether the setting state is the same as the initial setting value (step S1260).

  If it is determined in step S1260 that the setting state is the same as the initial setting value, the touch sensor control LSI determines whether the touch sensor abnormality flag is on (step S1261).

  If the touch sensor control LSI determines in step S1261 that the touch sensor abnormality flag is ON, or if it determines in step S1260 that the setting state is not the same as the initial setting value, the sub control transmission buffer A reset notification (2) command is set (step S1262).

  When the reset notification (1) command is set in step S1258 or the reset notification (2) command is set in step S1262, the touch sensor control LSI transmits the transmission data to the sub CPU 71. It transmits (step S1263).

  This is for notifying the sub CPU 71 that an abnormality has occurred in the touch sensor relay board 780 by detecting an input abnormality, a setting state abnormality, and a self-diagnosis abnormality of the touch sensor module. By generating a WDT reset, a reset of the sub-control circuit 70 and the touch sensor relay board 780 is generated, and self-recovery is performed. The WDT counter register is cleared once every 10 ms, for example, and the WDT times out at 15 ms, for example.

  On the other hand, if the touch sensor control LSI determines in step S1261 that the touch sensor abnormality flag is not on, the WDT is cleared because it is not abnormal (step S1264). After the WDT is cleared, it automatically starts counting.

  This reset is detected by the sub-device error detecting means 71h, and an error code (TS RST) is registered in the error information history storage area 73d-1 as occurrence of the reset. Thus, the date and time of the occurrence of the error due to the reset can be confirmed later.

[Configuration of pachinko machines]
The present invention is not limited to a pachislot, but can also be applied to a pachinko game machine. Hereinafter, the pachinko gaming machine will be described.

  First, an overview of the pachinko gaming machine 10 will be described with reference to FIGS. FIG. 128 is a perspective view showing an overview of a pachinko gaming machine 1010 according to another embodiment of the present invention. FIG. 129 is a front view showing an overview of pachinko gaming machine 1010 in the present embodiment. FIG. 130 is an exploded perspective view showing an overview of pachinko gaming machine 1010 according to the present embodiment. FIG. 131 is a front view of the gaming board of the pachinko gaming machine 1010 in the present embodiment.

  As shown in FIGS. 128 to 130, the pachinko gaming machine 1010 includes a glass door 1011, a wooden frame 1012, a base door 1013, a game board 1014, a plate unit 10, a liquid crystal display device 1032 for displaying an image, and a game ball. It comprises a firing device 1130 for firing, a payout unit 1500, a substrate unit 1600, and the like.

  The above-described glass door 1011 is attached to the base door 1013 so as to be freely opened and closed by a rotation shaft. An opening 1011a is formed in the center of the glass door 1011. A transparent protective glass 1019 is provided in the opening 1011a. The protective glass 1019 is disposed so as to face the front of the game board 1014 with the glass door 1011 closed.

  The plate unit 1020 is a unit body in which the upper plate 1021 and the lower plate 1022 are integrated, and is disposed below the glass door 1011 in the base door 1013. The lower plate 1022 is located below the upper plate 1021. In the upper plate 1021 and the lower plate 1022, payout holes 1021a and 1022a for renting out game balls and paying out game balls (prize balls) are formed, and when a predetermined payout condition is satisfied, a game is performed. The ball is discharged, and particularly, in the upper plate 1021, a game ball to be fired to a game area 15 described later is stored.

  The firing device 1130 is provided at the lower right of the base door 1013. The firing device 1130 includes a firing handle 1026 that can be operated by a player, and a panel body 1027 that fits a lower right portion of the dish unit 1020. The firing handle 1026 is provided on the front side of the panel body 1027. On the back side of the panel body 1027, a driving device for firing game balls is provided.

  A plate unit 1021 and a firing device 1130 are provided on a base door 1013, and a panel body 1027 is integrated with a lower right portion of the plate unit 1020. Then, when the firing handle 1026 is operated by the player, the pachinko game can be advanced.

  The game board 1014 described above is disposed in front of the base door 1013 so as to be located behind the protective glass 1019. Behind the game board 1014, a spacer 1031, a liquid crystal display device 1032, and the like are provided. Behind the base door 1013, a payout unit 1500 and a board unit 1600 are provided. Further, a speaker 1046 is provided below the lower plate 1022.

  The game board 1014 is entirely formed of a plate-shaped resin having transparency (a member having transparency). Various materials such as an acrylic resin, a polycarbonate resin, and a methacrylic resin correspond to the transparent member. In addition, the game board 1014 has a game area 1015 on the front side of the game board 1014 where the shot game balls can roll down.

  The game area 1015 is surrounded by a guide rail 1030 (specifically, an outer rail 1030a shown in FIG. 131 described later), and is an area where game balls can roll. A plurality of gaming nails 1018 are driven into a gaming area 1015 of the gaming board 1014. Thus, the game board 1014 is an example of a game board provided with a game area in which a game ball can roll.

  The liquid crystal display device 1032 is disposed behind (on the back side of) the game board 1014. That is, the liquid crystal display device 1032 is arranged behind the transparent member of the game board 1014. The liquid crystal display device 1032 has a display area 1032a that enables display of an image related to a game. The display area 1032a is provided so as to overlap the whole or a part of the game board 1014 from the back side.

  In other words, the display area 1032a is disposed behind the game board 1014 so as to overlap at least all or part of the game area 1015 in the game board 1014. Specifically, the liquid crystal display device 1032 is disposed behind the game board 1014 so that the display area 1032a overlaps all or a part of the game area 1015 and all or part of the game area outside area 1016. . In the display area 1032a of the liquid crystal display device 1032, various images such as an effect identification symbol, an effect image, and a decorative image for decoration are displayed.

  The spacer 1031 is disposed behind the game board 1014 (back side), and a game ball that rolls the game board 1014 between the back of the game board 1014 and the front (front side) of the liquid crystal display device 1032. The space which becomes the flow path of is constituted. An LED unit 1053 (see FIG. 131) is provided below the spacer 1031. The spacer 1031 is formed of a material having transparency. In this embodiment, the spacer 1031 is formed of a material having transparency, but the present invention is not limited to this. For example, the spacer 1031 may be partially formed of a material having transparency. Further, it may be formed of a material having no transmissivity.

  The firing handle 1026 is rotatable, and a firing solenoid (not shown) as a driving device is provided on the back side of the firing handle 1026. Further, a touch sensor (not shown) is provided on the periphery of the firing handle 1026. Inside the firing handle 1026, there is provided a firing volume that changes the resistance value according to the amount of rotation of the firing handle 1026 and changes the power supplied to a firing solenoid (not shown).

  When the player contacts a touch sensor (not shown), it is detected that the firing handle 1026 is gripped by the player. When the firing handle 1026 is gripped and rotated clockwise by the player, the resistance value of the firing volume (not shown) changes according to the rotation angle and corresponds to the resistance value at this time. Power is supplied to a firing solenoid (not shown). As a result, the game balls stored in the upper plate 1021 are sequentially fired to the game area 1015 of the game board 1014, and the game proceeds. When a firing stop button (not shown) is pressed, firing of the game ball is stopped even when the firing handle 1026 is gripped and rotated.

  At the lower left of the game board 1014, members forming the general winning openings 1056a, 1056b, and 1056c are arranged, and a portion of the member facing the LED unit 1053 is transparent. Therefore, as shown in FIG. 131, the LED unit 1053 can be visually recognized from the lower left of the game board 1014. The LED unit 1053 is provided with a special symbol display device, a normal symbol display device 1033, first special symbol hold display LEDs 1034a and 1034b, second special symbol hold display LEDs 1034c and 1034d, normal symbol hold display LEDs 1050a and 1050b, and the like. .

  The special symbol display device is constituted by 16 LEDs. These sixteen LEDs are divided into two groups of eight LEDs, which will be described in detail later. One of the groups performs a variable display when the first winning opening 1025 receives a winning prize. The other group has a variable display that is triggered by a winning start in the second starting port 1044. For convenience of the following description, one LED group is referred to as a first special symbol display device 1035a (see FIG. 132), and the other LED group is referred to as a second special symbol display device 1035b (see FIG. 132).

  The LEDs of the first and second special symbol display devices 1035a and 1035b perform variable display that repeats lighting and extinguishing in group units when a predetermined special symbol variable display start condition is satisfied. Then, a display pattern formed by turning on and off the eight LEDs is stopped and displayed as a special symbol (also referred to as an identification symbol). In the case where the special symbol stopped and displayed has a specific stop display mode, the gaming state shifts from the normal gaming state to a hit gaming state (special gaming state) which is a state advantageous to the player. When the hit game state is reached, as described later, the shutter 1040 (see FIG. 131) is controlled to the open state, and the game ball can be received in the special winning opening 1039 (see FIG. 131).

  In other words, a game in which the special winning opening 1039 is opened is a hit game, and according to the present embodiment, there are two types of hit games, a big hit game and a small hit game. The stop display mode in which the special symbol shifts to the big hit game state is the big hit, and the stop display mode in which the special symbol shifts to the small hit game state is the small hit.

  The difference between a big hit and a small hit will be described later, but in the case of a big hit, there is a high possibility that many hits will be obtained. On the other hand, when a lost symbol is stopped and displayed as a special symbol, the gaming state is maintained. As described above, a game in which the special symbol is fluctuated and then stopped, and the game state is shifted or maintained according to the result is referred to as a “special symbol game”.

  Below the special symbol display device, a normal symbol display device 1033 is provided. The normal symbol display device 1033 is composed of two display lamps, and the display lamps are alternately turned on and off to alternately display as a normal symbol. Then, a game in which the normal symbol is fluctuated and then stopped and displayed, and the opening / closing state of the ordinary electric accessory 1048 (see FIG. 131) differs depending on the result is referred to as a “normal symbol game”.

  Below the ordinary symbol display device 1033, ordinary symbol holding display LEDs 1050a and 1050b are provided. The ordinary symbol hold display LEDs 1050a and 1050b indicate the number of times of execution of the variable display of the ordinary symbol held by turning on, off or blinking (so-called “number of held”, “number of held related to the ordinary symbol”). Specifically, when the execution of the fluctuation display of the normal symbol is held for one time, the normal symbol hold display LED 1050a is turned on, and the normal symbol hold display LED 1050b is turned off.

  When the execution of the variable display of the normal symbol is held twice, the normal symbol hold display LED 1050a is turned on, and the normal symbol hold display LED 1050b is turned on. When the execution of the variable display of the ordinary symbol is suspended three times, the ordinary symbol suspension display LED 1050a flashes, and the ordinary symbol suspension display LED 1050b is turned on. When the execution of the variable display of the normal symbol is suspended for four times, the normal symbol hold display LED 1050a flashes, and the normal symbol hold display LED 1050b flashes.

  Below the normal symbol holding display LEDs 1050a and 1050b, there are provided first special symbol holding display LEDs 1034a and 1034b and second special symbol holding display LEDs 1034c and 1034d. The first special symbol hold display LEDs 1034a and 1034b and the second special symbol hold display LEDs 1034c and 1034d are the number of times of execution of the variable display of the special symbol held by turning on, off or blinking (so-called “number of hold”, “special number”). The number of reserved symbols)). The display mode of the number of special symbols held by the first special symbol hold display LEDs 1034a and 1034b and the second special symbol hold display LEDs 1034c and 1034d is the same as the display mode of the number of normal symbols held by the normal symbol hold display LEDs 1050a and 1050b. is there.

  On the side of the normal symbol display device 1033, a hit notification LED or the like which is lit regardless of whether a big hit or a small hit is provided. According to this embodiment, there is no LED for displaying the number of rounds because the number of rounds is constant. Therefore, on the display of the hit notification LED controlled by the main control circuit 1060, there is no discrimination in the notification of the big hit and the small hit. In addition, the sudden large hit and the small hit are selected from the same opening / closing pattern of the shutter 1040 when the hit occurs as described later, and the effect on the liquid crystal display device 1032 or the like controlled by the sub-control circuit 1200 is also determined. Are identical. For this reason, the sudden big hit and the small hit cannot be visually distinguished by the player.

  Also, in the display area of the liquid crystal display device 1032 disposed behind (on the back side of) the gaming board 1014, the display area is related to the special symbols displayed on the first special symbol display device 1035a and the second special symbol display device 1035b. The effect image is displayed.

  For example, during the variable display of the special symbol displayed on the first special symbol display device 1035a and the second special symbol display device 1035b, the display area 1032a of the liquid crystal display device 1032 is formed of numerals except for a specific case. An identification symbol (which is also identification information for effect), for example, a number such as "1 to 8" is displayed in a variably manner. In addition, the special symbol that has been variably displayed on the first special symbol display device 1035a (see FIG. 132) and the second special symbol display device 1035b (see FIG. 132) is stopped and displayed, and the display area 1032a of the liquid crystal display device 1032 is displayed. However, the identification symbol for the effect is stopped and displayed.

  Further, in the first special symbol display device 1035a and the second special symbol display device 1035b, if the special symbol that has fluctuated and stopped has a specific stop display mode, an effect image that allows the player to know that it is a hit is displayed. The image is displayed in the display area 1032a of the liquid crystal display device 1032.

  Specifically, in one of the first special symbol display device 1035a and the second special symbol display device 1035b, the special symbol is stopped and displayed, for example, in a specific display mode corresponding to a big hit in which many balls can be obtained. In this case, the combination of the effect identification symbols displayed in the display area 1032a of the liquid crystal display device 1032 is stopped in a specific display mode (for example, a state where all the same symbols are arranged in each of a plurality of symbol rows). The effect image for the big hit is displayed in the display area 32 a of the liquid crystal display device 32.

  In the case of a hit in which it is difficult to obtain a ball (small hit, 15 times big hit, 16 times big hit), the effect image for allowing the player to know that the hit is a display area of the liquid crystal display device 1032 is displayed. It may not be displayed in 1032a.

  As shown in FIG. 131, two guide rails 1030 (1030a and 1030b), a stage 1055, a first starting port 1025, a second starting port 1044, a passage gate 1054, a shutter 1040 are provided on a game board 1014 of the gaming machine 1010. , A special winning opening 1039, a general winning opening 1056a, 1056b, 1056c, 1056d, an ordinary electric accessory 1048, and the like.

  A stage 1055 having a substantially inverted L-shape is provided on an upper portion of the game board 1014. A guide rail 1030 is provided so as to surround the game area 1015.

  The guide rail 1030 includes an outer rail 1030a that divides (defines) the game area 1015, and an inner rail 1030b disposed inside the outer rail 1030a. The launched game ball is guided by a guide rail 1030 provided on the game board 1014, moves to the upper portion of the game board 1014, and is provided on the game board 1014 with a plurality of game nails (not shown) described above. Due to the collision with the stage 1055 or the like, the water flows downward under the game board 1014 while changing its traveling direction. Specifically, a system that flows down the left side of the stage 1055 (so-called left-handed), and the firing handle 1026 is rotated to the right to the maximum, and a game ball is driven into the right side of the stage 1055 and flows down the right side of the stage 1055. There is a system (so-called right-handed).

  Further, below the stage 1055 and below the center of the game board 1014, a first starting port 1025 is provided. Further, a passage gate 1054 is provided on the upper right side of the stage 1055, and a second starting port 1044 is provided below the passage gate 1054. The second starting port 1044 is provided with a normal electric accessory 1048. The ordinary electric accessory 1048 includes a tongue-shaped member 1048a that projects and retracts in the front-rear direction with respect to the plate surface of the game board 1014. When the tongue-shaped member 1048a protrudes, the game ball riding on the tongue-shaped member 1048a wins the second starting port 1044, and when the tongue-shaped member 1048a is retracted, the game ball wins the second starting port 1044. It is impossible.

  Then, when the ordinary symbol is stopped and displayed at the predetermined symbol on the ordinary symbol display device 1033, the tongue-shaped member 1048a of the ordinary electric accessory 1048 is brought out of the retracted state for a predetermined time, and the second starting port 1044 is opened. Gaming balls are easier to enter. Note that the ordinary electric accessory 1048 is not limited to the one that projects and retracts the tongue-shaped member 1048a, and may be, for example, one that opens and closes a pair of blade members (a so-called electric tulip).

  Also, when a game ball is driven into the right side of the stage 1055, a game nail 1018 is driven into the path where the game ball rolls from the right side of the stage 1055 to the first starting port 1025. The game ball cannot enter the first starting port 1025 from the right side of the stage 55.

  When the game ball passes through the passing gate 1054 during the normal symbol change display, the display mode of the normal symbol hold display LEDs 1050a and 1050b is switched until the normal symbol in the variable display is stopped and displayed. Execution (start) of the normal symbol change display based on the passing of the game ball to 1054 is suspended. Thereafter, when the normally displayed variable symbols are stopped and displayed, the variable display of the suspended ordinary symbols is started.

  When a specific symbol is stopped and displayed as the ordinary symbol on the ordinary symbol display device 1033, an effect image for allowing the player to understand that the ordinary symbol lottery has been won is displayed in the display area of the liquid crystal display device 1032. You may make it.

  A shutter 1040 that opens and closes the special winning opening 1039 is disposed immediately below the first starting opening 1025. An out port 1057 is formed at the lowest portion of the game area 1015 immediately below the shutter 1040. In the lower left portion of the game area 1015, general winning openings 1056a, 1056b, and 1056c are provided. In addition, a general winning opening 1056d is provided in a lower right portion of the game area 1015.

  Further, a winning area is provided in the first starting port 1025 described above. The winning area is provided with a first start winning port switch 1116 (see FIG. 132). A winning area is provided in the second starting port 1044, and a second starting winning port switch 1117 (see FIG. 132) is provided in the winning area. When a game medium such as a game ball is detected by the first start winning opening switch 1116, the variable display of the special symbol by the first special symbol display device 1035a is started.

  Also, when a game ball enters the first starting port 1025 during the special symbol change display, the game ball enters the first start port 1025 until the special symbol during the change display is stopped and displayed. The execution (start) of the special symbol change display based on is suspended. Thereafter, when the special symbol that has been variably displayed is stopped and displayed, the variably displayed special symbol that has been suspended is started. In the following description, a special symbol variably displayed on the first special symbol display device 1035a based on a game ball entering the first starting port 1025 is referred to as a first special symbol.

  Also, when a game medium such as a game ball is detected by the second start winning opening switch 1117, the variable display of the special symbol by the second special symbol display device 1035b is started. Also, when a game ball enters the second starting port 1044 during the special symbol change display, the game ball enters the second start port 1044 until the special symbol during the change display is stopped and displayed. The execution (start) of the special symbol change display based on is suspended. Thereafter, when the special symbol that has been variably displayed is stopped and displayed, the variably displayed special symbol that has been suspended is started.

  In the following description, a special symbol that is variably displayed on the second special symbol display device 1035b based on a game ball entering the second starting port 1044 is referred to as a second special symbol.

  Here, the first special symbol display device 1035a and the second special symbol display device 1035b do not change their special symbols at the same time. Further, in the present embodiment, a special symbol change display is performed with priority given to the start winning at the second starting port 1044. As described above, the first start port 1025 and the second start port 1044 are provided in the game area of the game board 1014 and are examples of a start area through which game balls can pass.

  Note that an upper limit is set for the number of times the execution of the special symbol change display is suspended, and in this embodiment, the special symbol change caused by the ball entering the first start port 1025 and the second start port 1044 is set. The maximum number of display suspensions is four each. Specifically, when the special symbol game of the first special symbol is suspended four times, information of the special symbol game corresponding to the changing first special symbol is stored in the main RAM 1070 (see FIG. 132). The information of the four special symbol games that are stored as the start memory in the one special symbol start storage area (0) and are held are stored in the first special symbol start storage area (1) to the first special symbol start storage area (4). ) Is stored as a start memory.

  Similarly, in the case of the special symbol game of the second special symbol, when the special symbol game of the second special symbol is suspended four times, the information of the special symbol game corresponding to the changing second special symbol is stored in the main symbol. The information of the four special symbol games that are stored as the start memory in the second special symbol start storage area (0) of the RAM 70 (see FIG. 132) are stored in the second special symbol start storage area (1) to the second special symbol start storage area. 2 It is stored in the special symbol start storage area (4) as start memory. Therefore, a maximum of eight reservations are possible.

  Another condition (start of changing the display of a predetermined special symbol) is that the special symbol is stopped and displayed. That is, each time the predetermined special symbol change display start condition is satisfied, the special symbol change display is started.

  When the special symbol has a specific stop display mode in the first special symbol display device 1035a and the second special symbol display device 1035b, and the game state is shifted to the big hit game state, the shutter 1040 is easy to receive the game ball. It is driven to be in an open state. As a result, the special winning opening 1039 is in an open state (first state) in which game balls can be easily received.

  On the other hand, the special winning opening 1039 provided on the rear side (rear side) of the shutter 1040 has an area (not shown) having a count switch 1104 (see FIG. 132), and the area has a predetermined number of game balls (for example, 7) or the shutter 1040 is driven to the open state until a predetermined time (for example, about 0.1 second or about 30 seconds) elapses. Then, when any of the conditions of winning a predetermined number of game balls into the special winning opening 1039 or the lapse of a predetermined time in the open state is satisfied, the shutter 1040 is driven so as to be in a closed state where it is difficult to receive the game balls. . As a result, the special winning opening 1039 is in a closed state in which it is difficult to receive a game ball (second state).

  Note that a game in which the special winning opening 1039 is in a state of easily accepting a game ball during a certain time is called a round game. Therefore, the shutter 1040 is opened during the round game and closed between the round games. The round game is counted as the number of rounds such as “1” round, “2” round, and the like. For example, the first round game may be referred to as a first round, and the second round game may be referred to as a second round. Note that in this embodiment, the shutter 1040 may be opened and closed a plurality of times in one round, and the time during which the shutter 1040 is opened may be a fixed time.

  Subsequently, the shutter 1040 driven from the open state to the closed state (second state) is driven again to the open state. That is, when the round game ends, it is possible to continue to the next round game. Note that a game from the first round game to the end of the (final) round game in which the game cannot continue to the next round game is called a special game or a big hit game. In this embodiment, all jackpots are 15 rounds.

  In the present embodiment, when the special symbol is in a specific stop display mode on the first special symbol display device 1035a and the second special symbol display device 1035b, and the gaming state is shifted to the small hitting gaming state. The shutter 1040 is driven such that the special winning opening 1039 is in an open state in which game balls can be easily received 15 or 16 times. Note that the small hit game is a game in which the big winning port 1039 is opened 15 or 16 times, and there is no concept of a round game like a big hit. As described above, the special winning opening 1039 and the shutter 1040 are provided on the game board 1014, and are an example of a variable member that can be changed between an open state in which game balls easily enter and a closed state in which game balls are difficult to enter. It is.

  When a game ball has won the first starting opening 1025, the second starting opening 1044, the general winning opening 1056a to 1056d, and the special winning opening 1039, the number set in advance according to the type of each winning opening. Are paid out to the upper plate 1021 or the lower plate 1022.

  Also, in the present embodiment, when the winning probability of the ordinary symbol lottery is in a high probability state after the end of the big hit game, and a transition is made to a time-saving state in which the reserved balls of the special symbol game are easily accumulated by the support of the ordinary electric auditors character 1048. There is. Here, in the time-saving state, passing a game ball through the passage gate 1054 is a condition for executing a normal symbol lottery, so that the game proceeds while right-handed.

  When a big hit occurs in the right-handed state, the right-handed player can continue the right-handed game so that the big winning opening 1039 can be won. In addition, when the support by the ordinary electric accessory 1048 cannot be received, the game proceeds while the player is left-handed.

  Further, as shown in FIG. 129, effect buttons 1080a, 1080b, and 1080c are provided on the front surface of the upper plate 1021, and these effects are provided during mini-games such as eye-catching games, card turning, and sugoroku. By depressing the button, the effect display content on the liquid crystal display device 1032 can be changed.

  In the present embodiment, a liquid crystal display device has been described as an example of the production means, but the present invention is not limited to this. The effect means may be effect means such as a plasma display, a rear projection display, a CRT display, a lamp, a speaker, and a movable character.

[Electrical configuration of pachinko machines]
FIG. 132 is a block diagram showing a control circuit of pachinko gaming machine 1010 in this embodiment.

  As shown in FIG. 132, the pachinko gaming machine 1010 mainly includes a main control circuit 1060 for controlling the game and a sub-control circuit 1200 for controlling an effect according to the progress of the game.

  The main control circuit 1060 includes a main CPU 1066, a main ROM 1068 (read only memory), and a main RAM 1070 (read / write memory).

  The main CPU 1066 is connected to a main ROM 1068, a main RAM 1070, and the like, and has a function of executing various processes according to a program stored in the main ROM 1068.

  The main ROM 1068 stores a program for controlling the operation of the pachinko gaming machine 1010 by the main CPU 1066, a program for causing the main CPU 1066 to execute main processing and the like, various tables, and the like.

  The main RAM 1070 has a function of storing values of various flags and variables as a temporary storage area of the main CPU 1066. Although the main RAM 1070 is used as a temporary storage area of the main CPU 1066 in the present embodiment, the present invention is not limited to this, and any storage medium that can be read and written may be used.

  The main control circuit 1060 includes an initial reset circuit 1064 for generating a reset signal when power is turned on, an I / O port 1071, and a command output port 1072. The initial reset circuit 1064 is connected to the main CPU 1066. The I / O port 1071 transmits input signals from various devices to the main CPU 1066, and transmits output signals from the main CPU 1066 to various devices.

  The command output port 1072 transmits a command from the main CPU 1066 to the sub control circuit 1200. The main control circuit 1060 includes a backup capacitor 1074. The backup capacitor 1074 is used for retaining various data stored in the main RAM 1070 by, for example, quickly supplying power to the main RAM 1070 at the time of power failure.

  In addition, various devices are connected to the main control circuit 1060.

  For example, as various devices that respond to signals from the main control circuit 1060, the main control circuit 1060 includes a first special symbol display device 1035a and a second special symbol display device 1035b that variably display a special symbol in a special symbol game. The first special symbol hold display LEDs 1034a and 1034b and the second special symbol hold display LEDs 1034c and 1034d for displaying the number of reserved special symbols in the special symbol game, and the variable display of the ordinary symbol as the identification symbol in the ordinary symbol game is performed. Ordinary symbol display device 1033, ordinary symbol holding display LEDs 1050a and 1050b for displaying the number of variable symbols to be held in the ordinary symbol game, and a starting port solenoid for setting the tongue-shaped member 1048a of the ordinary electric accessory 1048 in a protruding state or a retracted state. 1118, shutter 1040 Is dynamic, special winning hole solenoid 1120 such that an open state or closed state winning opening 1039 is connected.

  Further, the main control circuit 1060 has a calling device (not shown) having a function of calling a hall clerk and a function of displaying the number of hits, and an external terminal used for transmitting data to a hall computer which manages a pachinko gaming machine of the whole hall. Plate 1310 is connected.

  The main control circuit 1060 includes, for example, a count switch 1104 for supplying a predetermined detection signal to the main control circuit 1060 when a game ball passes through the area at the special winning opening 1039, and a general winning opening 1056 for the game ball. When the game ball passes through the general winning opening switches 1106, 1108, 1110, and 1112, and the passing gate 1054, the predetermined detection signal is supplied to the main control circuit 60 when a predetermined detection signal is passed to the main control circuit 60. When the game ball wins the passing gate switch 1114 and the first starting port 1025 that supply to the 1060, the first starting winning port switch 1116 and the second starting port 1044 that supply a predetermined detection signal to the main control circuit 1060 are played. When the ball has won, a second starting winning opening switch 1117 for supplying a predetermined detection signal to the main control circuit 1060, Such as backup clear switch 1124 to clear depending on the administrator of the operation of the game arcade is connected to a backup data in such.

  Also, a payout / firing control circuit 1126 is connected to the main control circuit 1060. The payout / firing control circuit 1126 is connected to a payout device 1128 for paying out game balls, a firing device 1130 for firing game balls, and a card unit 1300. The card unit 1300 can transmit and receive a ball lending operation panel 1155 that outputs a signal requesting lending of a game ball to the card unit 1300 by a player's operation.

  The payout / firing control circuit 1126 receives the prize ball control command supplied from the main control circuit 1060, the lending ball control signal supplied from the card unit 1300, and transmits a predetermined signal to the payout device 1128, The payout device 1128 pays out game balls. When the firing handle 1026 is gripped and rotated clockwise by the player, the payout / firing control circuit 1126 supplies power to the firing solenoid in accordance with the rotation angle, and Control to fire a ball.

  Further, a sub control circuit 1200 is connected to the command output port 1072. The sub-control circuit 1200 performs display control in the liquid crystal display device 1032, control relating to sound generated from the speaker 1046, control of a lamp including a decorative lamp, and the like in accordance with various commands supplied from the main control circuit 1060. . The sub-control circuit 1200 has the same configuration as that of the sub-control circuit 70 described in the pachislo gaming machine, and can execute various processes. Further, a sub-device such as a touch panel relay board 780 may be connected to the sub-control circuit 1200, similarly to the sub-control circuit 70 of the pachislo gaming machine described above.

  In this embodiment, a command is supplied from the main control circuit 1060 to the sub-control circuit 1200, and no signal is supplied from the sub-control circuit 1200 to the main control circuit 1060. The present invention is not limited to this, and a configuration may be adopted in which a signal can be transmitted from the sub control circuit 1200 to the main control circuit 1060.

  As described above, according to the pachinko gaming machine according to the present embodiment, the same effects as those of the pachislo gaming machine according to the above embodiment can be obtained.

Reference Signs List 1 gaming machine 1a housing 1b front door 2 door keys 3L, 3C, 3R reels 4L, 4C, 4R symbol display area (symbol display means)
5 Liquid crystal display (display unit)
6S start switch (start operation detecting means)
7LS, 7CS, 7RS stop switch (stop operation detecting means)
23 Liquid crystal display area (touch panel, touch panel device)
31 main CPU (internal winning combination determination means, command transmission means)
39 motor drive circuit (symbol changing means, stop control means)
49L, 49C, 49R stepping motor (symbol changing means, stop control means)
50 Reel position detection circuit (symbol change means, stop control means)
60, 1060 Main control circuit (main control unit)
70, 1200 Sub-control circuit (sub-control unit)
71 Sub CPU (effect content determination means, effect control means, command receiving means, processing means)
71a Communication error detecting means (error detecting means)
71b Procedure detection means 71c Data destruction detection means 71d Error information registration means 71e Received data log storage means 71f Error information history display means 71g Two-dimensional code conversion means 71h Subdevice error detection means 72 SubROM
72a OS area 72b Sub-control program area 72c Game data initialization setting data area 72d Staff operation initial setting data area 72e Various program table areas 72f Program management data area 72g Image data (still image / moving image)
72h sound data 72i movable object data 73-1 DRAM (storage unit)
73a-1 Sub-control game data area (game data storage area)
73b-1 Sub-control game data sum value area 73c-1 Work area 73d-1 Error information history storage area 73e-1 Communication log collection ring buffer area 73f-1 Communication error storage area (buffer)
73-2 SRAM
73a-2 Backup data 1 area 73b-2 Backup data 1 sum value 73c-2 Backup data 2 area 73d-2 Backup data 2 sum value 73e-2 Staff backup data area 73f-2 Error information history storage area 73g-2 Staff backup Data sum value 74 GPU
75 VRAM
76 Serial communication relay board 77 Scaler control board 300 Two-dimensional code 400 Mobile communication terminal with camera (mobile terminal)
500 data management server (server)
600 PC for analysis (analysis means)
780 Touch sensor relay board (touch panel device)
781 Touch sensor module (touch panel, touch panel device)
790 Camera relay board 791 Camera module

Claims (2)

A display unit capable of displaying predetermined information;
A control unit that is connected to the display unit and controls an effect,
A contact input unit connected to the control unit and transmitting a signal to the control unit ,
The control unit monitors the presence or absence of a signal from the contact input unit to the control unit, regardless of the presence or absence of a contact input to the contact input unit, and detects a state in which the signal does not exist for a predetermined time as a communication disconnection. Equipped with communication disconnection detection means,
The contact input unit includes a contact input signal indicating contact information of the contact input when there is a contact input to the contact input unit, and the contact input unit when a predetermined time or more has elapsed and the contact input has not been performed. An operation confirmation signal for confirming the operation by the control unit, and transmits as the signal,
The gaming machine, wherein the control unit determines that communication is to be resumed when the signal is received from the contact input unit after the communication disconnection detecting unit detects the communication disconnection. The touch input unit includes a plurality of input method, and transmits the contact information corresponding to the input method as the signal to the control unit,
Wherein, in the storage area corresponding to the input method of the contact information received from the touch input unit, storing the contact information, receiving the contact information corresponding to the input method from the touch input unit The gaming machine according to claim 1, wherein even in such a case, it is determined that the communication is restarted.

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