JP6659914B2 - Redundant array column decoder for memory - Google Patents

Description

<Cross reference>
This patent application, filed on September 7, 2 016 years, claims of "Redundancy Array Column Decoder for Memory" of the name, the priority of US patent application Ser. No. 15 / 258,852 by Vimercati, et al., 2017 Claims PCT Application No. PCT / US2017 / 047779, filed August 21, 2016, entitled "Redundancy Array Column Decoder for Memory" . These applications are assigned to their assignees, and these applications are expressly incorporated herein by reference in their entirety.

  The following relates generally to memory devices, and more particularly to redundant array column decoders for non-volatile memories such as ferroelectric memories.

Memory devices are widely used to store information on various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, often represented by logic "1" or logic "0" . In other systems, more than two states may be stored. To access the stored information, the electronic device reads or senses the stored state in the memory device.
Sense). To store information, the electronic device can write or program the state into the memory device.

  Random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistance change RAM (RRAM) There are various types of memory devices including, but not limited to, flash memory, and others. Memory devices can be volatile or nonvolatile. A non-volatile memory (for example, a flash memory) can store data for a long period without an external power supply. Volatile memory devices (eg, DRAM) may lose their stored state over time unless periodically refreshed by an external power supply. Binary memory devices may include, for example, charged or discharged capacitors. However, charged capacitors can be discharged over time due to leakage currents, resulting in the loss of stored information. Some schemes with volatile memory may provide advantageous performance, such as faster read or write speed, while schemes with non-volatile memory may have advantages such as being able to store data without periodic refresh. possible.

FeRAM may use a device architecture similar to volatile memory, but may have non-volatile properties due to the use of ferroelectric capacitors as storage devices. Thus, FeRAM devices may have improved performance as compared to other non-volatile and volatile memory devices. In some FeRAM designs (among other design types), components of the cell may be processed or manufactured with non-ideal or undesirable characteristics or communications that render the cell or other components unusable. . Building redundancy into the array can help mitigate some of these problems and avoid having to scrap the entire array, but unused redundant cells or components use valuable die area inefficiently. I can do it.

An exemplary embodiment of the present disclosure will be described with reference to the following figures.
FIG. 4 illustrates an exemplary memory array supporting a redundant array column decoder for memory according to embodiments of the present disclosure. FIG. 4 illustrates an exemplary circuit of a memory cell supporting a redundant array column decoder for a memory according to an embodiment of the present disclosure. FIG. 4 illustrates an exemplary hysteresis curve for a ferroelectric memory cell supporting a redundant array column decoder for a memory according to an embodiment of the present disclosure. FIG. 3 illustrates an example of a memory array and other components that support a redundant array column decoder for a memory according to embodiments of the present disclosure. FIG. 4 illustrates an example of digit lines and other components supporting a redundant array column decoder for a memory according to embodiments of the present disclosure. 9 illustrates an example of one or more relationships between a memory array and other components that support a redundant array column decoder for a memory according to embodiments of the present disclosure. 4 illustrates an example of a memory array and other components of the memory array that support a redundant array column decoder for the memory according to embodiments of the present disclosure. FIG. 4 illustrates a memory array supporting a redundant array column decoder for a memory according to an embodiment of the present disclosure. FIG. 2 illustrates a system including a memory array that supports a redundant array column decoder for a memory, according to an embodiment of the disclosure. 5 is a flowchart illustrating a method for a redundant array column decoder for a memory according to an embodiment of the present disclosure. 5 is a flowchart illustrating a method for a redundant array column decoder for a memory according to an embodiment of the present disclosure.

  In memory designs, the printing of long traces or contiguous portions of memory elements increases the risk of unintended defects. Building redundancy, such as part of an array with cells connected in a way that provides redundancy to some other cells, can reduce problems due to manufacturing defects, efficiently use available die space. The method used to help mitigate this.

  By way of example, process or manufacturing defects can cause operational problems and can render some or all of the memory array unusable. In some array designs, cell plates and other elements are close together and may have unintended currents and other relationships between cell plates, including but not limited to adjacent cell plates. Based on manufacturing or other effects, a cell plate may have a current relationship with an adjacent cell plate or other defects with respect to an adjacent cell plate. Such a relationship or defect may weaken or hinder the performance of one or more cell plates. Examples of such a relationship include a short circuit, a parasitic field, or a parasitic signal.

  Some cell plates include vertically cut cell plates that may be common between a small number of digit lines (eg, 2-16) and a relatively large number of word lines (eg, 512-1024). obtain. The method of forming cell plates during manufacturing can affect array performance. In some examples, because the distance between each cell plate is relatively small (eg, the distance between digit lines, the distance between word lines, etc.), a current relationship may exist between the cell plates. Current relationships between cell plates of a group (eg, short circuits) can render a group, section, or some other memory element inoperable. In some cases, there is a risk of short circuits between cells, so that manufacturers can employ large-scale redundancy and / or local redundancy at a great cost. And the risk of such defects may facilitate other relatively complex solutions involving more robust design parameters (eg, increased spacing between plates). These alternatives increase cost and reduce memory design capabilities and capabilities.

  As described herein, memory arrays can be created and operated to reduce the risk of defects. For example, a redundant group of cell plates can be constructed in a memory array. If one or more cell plates become unavailable due to one or more of the above defects or relationships, the memory array is set to select an associated redundant cell plate of the defective cell plate. Areas on the memory array may be assigned to redundant cell plates. Allocating space for redundant cell plates increases the cost of manufacturing a memory array. As described herein, groups of redundant cell plates may be designed to reduce the amount of area occupied by redundant cell plates. For example, a redundant cell plate may be associated with a plurality of cell plates in a normal cell plate group.

  Further, memory arrays using FeRAM technology may be designed to isolate unselected memory cells, or regions of memory, from selected memory cells, cell plates, or regions during access operations. In some examples, when another memory cell or cell plate is selected as part of an access operation, an undesired voltage or current can occur in the unselected memory cell or unselected cell plate. As described herein, a set of shunt control lines and shunt switching components are used to unselect memory cells or unselect by grounding (or virtually grounding) unselected elements of the memory array during an access operation. It can be set to reduce the bias across the memory plate. In some embodiments, the redundant cell plate group of the memory array may also include a shunt switching component for separating the redundant group of cell plates during an access operation. In some examples, the selection switching component may also be located on a shunt control line of the redundancy group. In this way, additional areas of the memory array may be kept.

  The features of the present disclosure introduced above are further described below in connection with memory arrays and others. Next, specific embodiments are described for cell plates, including, inter alia, vertically cut cell plates, cell plate selection and related operations. These and other embodiments of the present disclosure are further described by, and described with reference to, device diagrams, system diagrams, and flowcharts for redundant array column decoders for ferroelectric memories.

  In the present disclosure, cell plate and plate are used interchangeably, unless the specific embodiment or embodiments indicate otherwise. In the present disclosure, a normal cell group can refer to a portion of a memory array that is intended to be used as part of normal operation of the memory array when the array is manufactured without defects, and the redundant cell group Can refer to a portion of the memory array designed as a backup cell group when a normal cell group or a cell in the normal cell group has a defect.

  FIG. 1 illustrates an exemplary memory array 100 that supports a redundant array column decoder for a ferroelectric memory according to various embodiments of the present disclosure. This disclosure refers to, but is not limited to, ferroelectric memories for ease of understanding. It should be understood that various aspects of the present disclosure may be applied to other memory technologies. The memory array 100 is also called an electronic memory device. Memory array 100 includes memory cells 105 that can be programmed to store different states. Memory array 100 may include a number of cells 105 or portions of an array designated as redundant to other cells 105 in the array. If a defect is identified in the array (eg, as a result of processing), a redundant cell 105 may be used in place of the cell 105 having or associated with the identified defect.

Each memory cell 105 may be programmable to store two states, denoted as logic 0 and logic 1. In some cases, memory cell 105 is set to store more than two logic states. Memory cell 105 may include a capacitor for storing a charge representing a programmable state. For example, a charged capacitor and an uncharged capacitor may each represent two logic states. DRAM architectures can generally use such a design, and the capacitors used can include a dielectric material with linear electrical polarization characteristics. In contrast, a ferroelectric memory cell may include a capacitor having a ferroelectric as the dielectric material. Different charge levels of a ferroelectric capacitor can represent different logic states. Ferroelectric materials have nonlinear polarization characteristics. Some details and advantages of the ferroelectric memory cell 105 are described below.

  By activating or selecting the appropriate word line 110 and digit line 115, operations such as reading and writing can be performed on the memory cell 105. Word line 110 is also called an access line, and digit line 115 is also called a bit line. Activating or selecting a word line 110 or a digit line 115 may include applying a voltage to each line. Word line 110 and digit line 115 are made of a conductive material. For example, word lines 110 and digit lines 115 can be made of metals (copper, aluminum, gold, tungsten, etc.), metal alloys, other conductive materials, and the like. According to the example of FIG. 1, each row of the memory cells 105 is connected to one word line 110, and each column of the memory cells 105 is connected to one digit line 115.

  By activating one word line 110 and one digit line 115 (eg, applying a voltage to word line 110 or digit line 115), one memory cell 105 at their intersection may be accessed. . Accessing memory cell 105 may include reading and writing to memory cell 105. The intersection of the word line 110 and the digit line 115 can be called the address of the memory cell. In some embodiments, one or more read or write operations may be based on or derived from the selection of one or more cell plates.

  In some architectures, the logic storage devices (eg, capacitors) of the cells may be electrically isolated from the digit lines by a select component. Word line 110 may be connected to and control the selected component. For example, the selected component can be a transistor, and word line 110 can be connected to the gate of the transistor. Activating the word line 110 creates an electrical connection or closed circuit between the capacitor of the memory cell 105 and the corresponding digit line 115. Therefore, the memory cell 105 can be read and written by accessing the digit line.

Access to memory cells 105 may be controlled via row decoder 120 and column decoder 130. In some examples, row decoder 120 receives a row address from memory controller 140 and activates the appropriate word line 110 based on the received row address. Similarly, column decoder 130 receives the column address from memory controller 140 and activates the appropriate digit line 115. For example, memory array 100 may include a plurality of word lines 110 and a plurality of digit lines 115. Thus, by activating word line 110 and digit line 115, memory cell 105 at their intersection can be accessed. As discussed herein, in various embodiments, the address or location of one or more cells or cell plates affects the identification, determination, or selection of a cell plate, among other elements or components. obtain. In some embodiments, the address or location of the memory cell may affect a selection, such as an absolute address or location, or a selection based on a relative address or location. In some embodiments, the address or location of a memory cell, as well as the existence of a current relationship, can affect the selection of a plate pair within a cell plate group or across a cell plate group.

  Upon access, memory cell 105 may be read or sensed by sense component 125 to determine the storage state of memory cell 105. For example, after accessing memory cell 105, the ferroelectric capacitor of memory cell 105 may discharge onto its corresponding digit line 115. Discharging the ferroelectric capacitor may be based on biasing or applying a voltage to the ferroelectric capacitor. The discharge can cause a change in the voltage on digit line 115 that sense component 125 can compare to a reference voltage (not shown) to determine the state stored in memory cell 105. For example, if digit line 115 has a higher voltage than the reference voltage, sense component 125 may determine that the stored state in memory cell 105 is a logic one, and vice versa. Sense component 125 may include various transistors or amplifiers to detect and amplify signal differences, sometimes referred to as latches. Thereafter, the detected logic state of the memory cell 105 may be output as an output 135 via the column decoder 130.

  A memory cell 105 may be set or written by activating the associated word line 110 and digit line 115. As described above, activating a word line 110 electrically connects the memory cells 105 of the corresponding row to their respective digit lines 115. By controlling the associated digit line 115 while the word line 110 is activated, the memory cell 105 can be written. That is, a logic value can be stored in the memory cell 105. Column decoder 130 can receive data (eg, input 135) written to memory cell 105. The ferroelectric memory cell 105 can be written by applying a voltage to a ferroelectric capacitor. This process is discussed in further detail below.

  In some memory architectures, accessing the memory cell 105 may degrade or destroy the stored logic state, and a rewrite or refresh operation may be performed to return the original logic state to the memory cell 105. For example, in a DRAM, a capacitor may be partially or completely discharged during a sensing operation, destroying a stored logic state. Thus, the logic state can be rewritten after the sensing operation. Further, activating one word line 110 may result in the discharge of all memory cells in that row. Thus, some or all memory cells 105 in a row may have to be rewritten.

  Some memory architectures, including DRAM, can lose their stored state over time unless they are periodically refreshed by an external power supply. For example, a charged capacitor may be discharged over time due to leakage current, resulting in a loss of stored information. The refresh rate of these so-called volatile memory devices is relatively high (eg, tens of refresh operations per second for DRAM arrays), which can result in significant power consumption. With even larger memory arrays, especially in mobile devices that rely on finite power supplies such as batteries, increased power consumption can hinder the placement or operation of the memory array (eg, power supply, heat generation, material limitations, etc.). is there. As described below, the ferroelectric memory cell 105 may have beneficial properties that may improve performance as compared to other memory architectures. For example, memory arrays 100 using ferroelectric memory cells 105 require fewer or no refresh operations because ferroelectric memory cells tend to be less susceptible to stored charge degradation. Therefore, less power is required for the operation.

  Memory controller 140 can control the operation (eg, read, write, rewrite, refresh, etc.) of memory cell 105 through various components such as row decoder 120, column decoder 130, and sense component 125. The memory controller 140 may generate a row address signal and a column address signal to activate the desired word line 110 and digit line 115. Memory controller 140 may also generate and control various potentials used during operation of memory array 100. In general, the amplitude, shape, or duration of the applied voltages discussed herein can be adjusted or changed and can be different for various operations to operate the memory array 100. Further, one, multiple, or all memory cells 105 in memory array 100 may be accessed simultaneously. For example, during a reset operation in which all memory cells 105 or groups of memory cells 105 are set to a single logic state, multiple or all cells of memory array 100 may be accessed simultaneously.

  In some embodiments, the memory controller 140 may be associated with or electronically communicate with the first plate line and the second plate line, each of which may be coupled to a plate of the various cells 105. . A group of cells 105 that are in electronic communication with the same plate line may be referred to as a cell group or cell plate group. The first digit line may be in electronic communication with a first plate line and a first sense component (eg, a sense amplifier) via a first select component (eg, a transistor). The second digit line may be in electronic communication with the second plate line and ground or virtual ground (eg, Vss) via a second selected component (eg, a transistor). Based at least in part on the electronic communication, memory controller 140 initiates one or more access operations that may include applying a voltage to one or more plate lines to increase the voltage on cell 105 plate. Or it may be operable to perform. This process may be referred to as moving a cell plate, which can excite the cell and thus facilitate manipulation of access to the cell.

  In some embodiments, the memory controller 140 applies the voltage to the plate lines of the redundant cell groups in the memory array based at least in part on the corresponding defective group of normal cells being defective. Or may be operable to apply a voltage. In some embodiments, the memory controller 140 operates to use switching components and shunt control lines to separate unselected cells from selected memory plate lines in both normal and redundant cell groups. It may be possible.

FIG. 2 illustrates an exemplary circuit 200 that supports a redundant array column decoder for a ferroelectric memory according to various embodiments of the present disclosure. This disclosure refers to, but is not limited to, ferroelectric memories for ease of understanding. It should be understood that various aspects of the present disclosure may be applied to other memory technologies. The circuit 200 includes a memory cell 105-a, a word line 110-a, a digit line 115-a, and a sense component 125-a, each of which is the memory cell 105, word line 110, It may be an example of a digit line 115 and a sense component 125. The memory cell 105-a may include a logic storage component such as a first plate, a cell plate 210 and a second plate, a capacitor 205 having a cell bottom 215. Cell plate 210 and cell bottom 215 can be capacitively coupled via a ferroelectric material located therebetween. The orientation of cell plate 210 and cell bottom 215 can be reversed without changing the operation of memory cell 105-a. The circuit 200 also includes a selection component 220 and a reference line 225. Cell plate 210 may be accessed via plate lines in electronic communication with some cells of the cell group, and cell bottom 215 may be accessed via digit line 115-a. As described above, various states may be stored by charging or discharging the capacitor 205.

  The stored state of capacitor 205 may be read or sensed by operating various elements represented in circuit 200. Capacitor 205 can be in electronic communication with digit line 115-a. For example, capacitor 205 may be disconnected from digit line 115-a when select component 220 is deactivated, and capacitor 205 may be connected to digit line 115-a when select component 220 is activated. Activating the selection component 220 may be referred to as selecting the memory cell 105-a. In some cases, the selection component 220 is a transistor, the operation of which is controlled by applying a voltage to the gate of the transistor, where the magnitude of the voltage is greater than the magnitude of the threshold of the transistor. Word line 110-a can activate select component 220. For example, the voltage applied to word line 110-a is applied to the gate of the transistor, connecting capacitor 205 to digit line 115-a.

  In another example, the selection component 220 and the capacitor are connected such that the selection component 220 is connected between the plate 210 and the cell plate 230 and the capacitor 205 is between the digit line 115-a and the other terminal of the selection component. The position of 205 can be switched. In this embodiment, selection component 220 may remain in electronic communication with digit line 115-a via capacitor 205. This configuration may relate to alternative timing and bias for read and write operations.

  Due to the ferroelectric material between the plates of the capacitor 205, and as described in more detail below, the capacitor 205 may not discharge when connected to the digit line 115-a. In one scheme, word line 110-a may be biased and voltage applied to plate 210 to select memory cell 105-a to sense the logic state stored by ferroelectric capacitor 205. . In some cases, digit line 115-a is virtually grounded and then separated from virtual ground before biasing plate 210 and word line 110-a, which may be referred to as "floating". Biasing plate 210 may result in a voltage difference across capacitor 205 (eg, the voltage on plate 210 minus the voltage on digit line 115-a). The voltage difference may cause a change in the charge stored in the capacitor 205, and the magnitude of the change in the stored charge depends on the initial state of the capacitor 205, for example, whether the initial state is logic 1 or logic 0. It may depend on what you remember. As a result, the voltage of digit line 115-a may change based on the charge stored in capacitor 205. The operation of the memory cell 105-a by changing the voltage applied to the cell plate 210 may be called a movement of the cell plate.

  The change in the voltage of digit line 115-a may depend on its intrinsic capacitance. That is, as the charge flows through digit line 115-a, some finite charge may accumulate on digit line 115-a, and the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance may depend on physical properties, including the dimensions of digit line 115-a. Since digit line 115-a may connect many memory cells 105, digit line 115-a may have a length that provides a non-negligible capacitance (eg, on the order of picofarads (pF)). The resulting voltage on digit line 115-a is then compared by sense component 125-a to a reference (eg, the voltage on reference line 225) to determine the logic state stored in memory cell 105-a. Can be done. In some cases, other sensing processes can be used.

Sense component 125-a may include various transistors or amplifiers for detecting and amplifying signal differences, sometimes referred to as latches. Sense component 125-a may include a sense amplifier that receives and compares the voltage on digit line 115-a with the voltage on reference line 225, which may be a reference voltage. The sense amplifier output may be driven to a higher (eg, positive) or lower (eg, negative or ground) supply voltage based on the comparison. For example, if digit line 115-a has a higher voltage than reference line 225, the sense amplifier output may be driven to a positive supply voltage.

  In some cases, the sense amplifier can further drive digit line 115-a to a supply voltage. Sense component 125-a can then latch the output of the sense amplifier and / or the voltage on digit line 115-a, which is used to determine the storage state in memory cell 105-a, eg, logic one. Can be done. Alternatively, if digit line 115-a has a lower voltage than reference line 225, the sense amplifier output may be driven to a negative or ground voltage. Sense component 125-a can also latch the sense amplifier output to determine the state of storage in memory cell 105-a, eg, logic zero. Thereafter, the latched logic state of memory cell 105-a may be output, for example, via column decoder 130, as output 135 with respect to FIG.

  A voltage may be applied across capacitor 205 to write to memory cell 105-a. Various methods can be used. In one example, select component 220 may be activated via word line 110-a to electrically connect capacitor 205 to digit line 115-a. By controlling the voltage at cell plate 230 (via plate 210) and cell bottom 215 (via digit line 115-a), a voltage can be applied to capacitor 205. To write a logic 0, the cell plate 230 can be high, ie, a positive voltage can be applied to the plate 210, the cell bottom 215 can be low, and the digit line 115- a can be virtually grounded or a negative voltage can be applied. The opposite process of bringing cell plate 230 low and cell bottom 215 high is performed to write logic one.

  Each of the two or more sense components 125-a may sense a voltage or other characteristic on two or more digit lines 115-a corresponding to one or more plates 210, respectively. In some embodiments, each of these plates 210 may be associated with at least one redundant cell, and the redundant cell may be accessed if the associated healthy cell is determined to be defective. In some embodiments, plate lines of adjacent cells may be separated from each other during an access operation to prevent unwanted voltages or currents on unselected memory cells. By using the redundancy and isolation techniques of the present disclosure, the area occupied by the memory array can be reduced and redundant cell plates can be isolated.

  FIG. 3 shows examples of non-linear electrical properties having hysteresis curves 300-a and 300-b for a ferroelectric memory cell operating in accordance with various embodiments of the present disclosure. Hysteresis curves 300-a and 300-b show an example of a write and read process, respectively, of a ferroelectric memory cell. The hysteresis curve 300 represents the charge Q stored on a ferroelectric capacitor (eg, the capacitor 205 of FIG. 2) as a function of the voltage difference V.

Ferroelectric materials are characterized by a naturally occurring electrical polarization (ie, maintaining a non-zero electrical polarization in the absence of an electric field). Examples of ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconate titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. Electrical polarization in a ferroelectric capacitor results in a net charge on the surface of the ferroelectric material, attracting opposite charges through the terminals of the capacitor. Thus, charge is stored at the interface between the ferroelectric material and the terminals of the capacitor. Electrical polarization can be maintained over a relatively long period of time (even indefinitely) without an externally applied electric field, so charge leakage is significantly reduced compared to, for example, capacitors used in DRAM arrays. You. This reduces the need to perform such refresh operations for some DRAM architectures.

  Hysteresis curve 300 can be understood in terms of a single terminal of the capacitor. As an example, if the ferroelectric material has a negative polarization, positive charges will accumulate at the terminals. Similarly, if the ferroelectric material has a positive polarization, negative charges will accumulate at the terminals. Further, it should be understood that the voltages in the hysteresis curve 300 represent voltage differences across the capacitors and are directional. For example, a positive voltage can be achieved by applying a positive voltage to the terminal in question (eg, cell plate 230) and keeping the second terminal (eg, cell bottom 215) at ground (or near zero volts (0V)). A negative voltage can be applied by keeping the terminal in question at ground and applying a positive voltage to the second terminal, ie applying a positive voltage to polarize the terminal in question negatively be able to. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages can be applied to the appropriate capacitor terminals to generate the voltage difference shown in the hysteresis curve 300.

  As shown in the hysteresis curve 300-a, the ferroelectric material can maintain positive or negative polarization with zero voltage difference, resulting in two possible states of charge: charge state 305 and charge state 310. . In some examples, charge state 305 represents logic 0 and charge state 310 represents logic 1. In some examples, the logic value of each state of charge may be reversed to accommodate other schemes for operating the memory cell.

  Logic 0 or 1 can be written to the memory cell by controlling the electrical polarization of the ferroelectric material, and thus the charge on the capacitor terminals, by applying a voltage. For example, applying a net positive voltage 315 across the capacitor results in the accumulation of charge until reaching the state of charge 305-a. Upon removal of voltage 315, state of charge 305-a follows path 320 until it reaches state of charge 305 at zero potential. Similarly, charge state 310 is written by applying a net negative voltage 325, resulting in charge state 310-a. After removing the negative voltage 325, the charge state 310-a follows the path 330 until the charge state 310 is reached at zero voltage. Charge states 305-a and 310-a are also referred to as residual polarization (Pr) values, ie, polarizations (or charges) that remain when an external bias (eg, voltage) is removed. The coercive voltage is a voltage at which the charge (or polarization) becomes zero.

  A voltage can be applied to the ferroelectric capacitor to read or detect the stored state of the capacitor. In response, the stored charge Q changes, and the extent of the change depends on the initial state of charge, ie, the final stored charge (Q) is the state of charge 305-b or 310-b that is stored first. Depends on what. For example, hysteresis curve 300-b shows two possible stored states of charge 305-b and 310-b. As described with reference to FIG. 2, a voltage 335 may be applied to the capacitor. In other cases, a fixed voltage may be applied to the cell plate. Although shown as a positive voltage, voltage 335 may be negative. In response to voltage 335, state of charge 305-b may follow path 340. Similarly, if the state of charge 310-b was first stored, it would follow path 345. The final positions of charge state 305-c and charge state 310-c depend on several factors, including the particular sensing scheme and circuit.

In some cases, the final charge may depend on the intrinsic capacitance of the digit line connected to the memory cell. For example, if a capacitor is electrically connected to the digit line and a voltage 335 is applied, the voltage on the digit line can increase due to its inherent capacitance. Thus, the voltage measured at the sense component may not be equal to the voltage 335, but instead may depend on the voltage on the digit line. Thus, the location of the final state of charge 305-c and 310-c on the hysteresis curve 300-b may depend on the capacitance of the digit line and may be determined by load line analysis. That is, charge states 305-c and 310-c can be defined in relation to digit line capacitance. As a result, the voltage of the capacitor, voltage 350 or voltage 355, can be different and depend on the initial state of the capacitor.

  By comparing the digit line voltage with the reference voltage, the initial state of the capacitor can be determined. The digit line voltage may be the difference between voltage 335 and the final voltage across capacitor (voltage 350 or voltage 355), ie, (voltage 335-voltage 350) or (voltage 335-voltage 355). In order to determine the stored logic state (ie, whether the digit line voltage is higher or lower than the reference voltage), its magnitude is between two of the two possible digit line voltages. The reference voltage may be generated as described above. For example, the reference voltage may be the average of two quantities (voltage 335-voltage 350) and (voltage 335-voltage 355). Upon comparison by the sense component, the sensed digit line voltage is determined to be higher or lower than the reference voltage, and the stored logic value (ie, logic 0 or 1) of the ferroelectric memory cell is determined.

  As described above, reading a memory cell without using a ferroelectric capacitor can degrade or destroy the stored logic state. However, a ferroelectric memory cell may maintain an initial logic state after a read operation. For example, if the state of charge 305-b is stored, the state of charge follows the path 340 during the read operation and proceeds to the state of charge 305-c. Can return to the initial state of charge 305-b as follows. In some embodiments, redundant memory cells can be included in a memory array. Redundant cells may be composed of the same material as other cells in the array, and thus may have the same ferroelectric properties. In some embodiments, to further protect the stored logic on the ferroelectric memory cells, unselected memory cells can be separated from selected memory cells during access operations.

  FIG. 4 illustrates an exemplary array 400 supporting a redundant array column decoder for a ferroelectric memory according to various embodiments of the present disclosure. This disclosure refers to, but is not limited to, ferroelectric memories for ease of understanding. It should be understood that various aspects of the present disclosure may be applied to other memory technologies. Array 400 includes a plate (eg, 210-a-210-t) and one or more word lines (eg, 110-a-110-h), digit lines (eg, 115-a-115-h, 115-). i-115-1, 115-m-115-t, etc.), sense components (e.g., 125-a-125-d, 125-h-125-1, etc.), and shunt control lines (e.g., from 405-a). 405-d). These may be examples of the memory cell 105 (and plate 210), word line 110, digit line 115, sense component 125, and select component 220, respectively, described with reference to FIGS. 1, 2 and other figures. . These terminals may be separated by an insulating ferroelectric material. As described above, various states can be stored by charging or discharging the capacitor 205.

Cell plates 210 of array 400 may be grouped such that plates 210 of various memory cells operate simultaneously or during a common access operation. Array 400 may include cell plate groups 410-a, 410-b, and 410-c. Each of the plate groups 410 may include one or more cell plates 210 or plate lines in electrical communication with the cell plates 210. For example, plate group 410-a may include cell plates 210-a through 210-h, plate group 410-b may include cell plates 210-i through 210-1, and plate group 410-c may include cell plates 210-a. m-210-t. In some examples, different plate groups 410 may perform different functions within array 400. For example, plate groups 410-a and 410-c may include normal cell plates 210 designed to be used during normal operation of array 400. As such, plate groups 410-a and 410-c may be referred to as normal cell plate groups. A first set of switching components may be associated with each cell plate group 410-a and 410-c. In some examples, the first set of switching components may include a first subset of switching components that provide a first function and a second subset of switching components that provide a second function. Switching components are described in further detail below.

  Plate group 410-b may include redundant cell plates 210 designed to be used only when a healthy cell plate is defective. Accordingly, plate group 410-b may be referred to as a redundant plate group because the cell plates in plate group 410-b are redundant with respect to certain cell plates in plate groups 410-a and 410-c. . A second set of switching components may be associated with plate group 410-b. In some examples, the second set of switching components may include a first subset of switching components that provide a first function and a second subset of switching components that provide a second function. Switching components are described in further detail below.

  In some examples, redundant cell plate group 410-b may be associated with multiple normal cell plate groups (eg, plate groups 410-a, 410-c). In some examples, redundant cell plate group 410-b may be associated with a single regular plate group 410. Cell plate group 410 may include any number of cell plates. In the illustrative example of FIG. 4, the normal cell plate group 410-a, 410-c includes eight cell plates 210, and the redundant cell plate group 410-b includes four cell plates 210. However, in other examples, each of these plate groups 410 may include more or fewer cell plates 210. For example, in the illustrative example of FIG. 7, the normal cell plate group 710 includes 16 cell plates 210 and the redundant cell plate group 720 includes 4 cell plates 210. In some examples, the number of cell plates 210 in the redundant cell plate group may be an integer multiple of the number of cell plates 210 in the associated normal cell plate group. In some examples, the number of cell plates 210 in the redundant plate group corresponds to the number of shunt control lines 405 in array 400. For example, in the illustrative example, there are four shunt control lines and four redundant cell plates (e.g., 210-i through 210-l). However, in other examples, the number of shunt control lines and the number of redundant cell plates in the redundant plate group are not always equal.

Array 400 may also include selection switching components 415 (e.g., 415-a-415-h, 415-i-415-1, and 415-m-415-t, etc.). In some examples, select switching component 415 may be located at the intersection of word line 110 and digit line 115 and may be connected to digit line 115 and word line 110. In some examples, selection switching component 415 may be located at the intersection of shunt control line 405 and digit lines (eg, 415-k through 415-n). Select switching component 415 may be configured to electronically couple cell plate 210 to sense component 125 based at least in part on a selected select line (eg, word line 110 or shunt control line 405). For example, select switching component 415-a may be configured to connect cell plate 210-a to sense component 125-a based at least in part on selected word line 110-a. Selection switching component 415 can be implemented similarly to selection component 220 described above. In some embodiments, the selection switching component 415 can be or include a transistor, the operation of which can be controlled by applying a voltage to the gate of the transistor. Here, the voltage is larger than the threshold value of the transistor.

  Array 400 may also include shunt switching components 420 (eg, 420-a-420-h, 420-i-420-1, and 420-m-420-t, etc.). The shunt switching component 420 can be located at the intersection of the shunt control line 405 and the digit line 115. Shunt switching component 420 may be configured to electronically couple cell plate 210 to ground, virtual ground, or a voltage source (eg, Vss). As shown in more detail in FIG. 5, the shunt switching component 420 is connected in parallel with the selection switching component 415. The shunt switching component 420 is depicted in FIGS. 4, 6 and 7 to show the position of the shunt switching component 420 relative to the other components of the arrays 400, 600, and 700. The shunt switching component 420 is designed to separate unselected memory cells or unselected cell plates from selected memory cells or selected cell plates during an access operation. During an access operation, voltages and / or currents may be induced in unselected memory cells, which may change or affect the logic state stored in the unselected memory cells. By connecting the digit line 115 of the unselected memory cell or unselected cell plate 210 to ground or virtual ground, no voltage can be induced on the digit line 115 and the logic state of the memory cell is not disturbed. May remain. The shunt switching component 420 can be implemented similarly to the selection component 220 or the selection switching component 415 described above. In some embodiments, the shunt switching component 420 can be or include a transistor, the operation of which can be controlled by applying a voltage to the gate of the transistor. Here, the voltage is larger than the threshold value of the transistor. In the figure, the shunt switching component 420 is indicated by the circled transistor symbol.

  During an access operation, a memory controller of array 400 (eg, memory controller 140) can determine a selected memory cell to perform an access operation. As part of the access operation, the memory controller may select a cell plate to bias the ferroelectric memory cells, select an associated word line 110 to connect the cell plate to a sense component, and Associated digit line 115 may be selected. When selecting these different lines, one or more unselected memory cells may be disturbed. For example, two or more memory cells or cell plates 210 may be accessed via a single plate 210. When plate 210 is accessed, unselected memory cells associated with plate 210 may be disturbed. The memory controller may attempt to mitigate interference with unselected memory cells by isolating those memory cells from selected memory cells. For example, a memory controller can electronically couple one or more unselected memory cells or unselected cell plates to ground or virtual ground. To couple the virtual ground to ground, the controller can select one or more shunt control lines 405 based at least in part on isolating unselected memory cells. Once selected, the shunt switching component 420 coupled to the selected shunt control line 405 is activated, and each digit line 115 may be connected to ground or virtual ground.

  As shown in FIG. 4, cell plate group 410-b may be separated from word lines 110 (e.g., 110-a through 110-h) such that access lines do not communicate electronically with cell plate group 410-b. Good. No type of switching component (e.g., selective switching component 415 and shunt switching component 420) is located at the intersection of word line 110 and digit lines 115-i through 115-l. Instead, select switch components 415-i through 415-l are located at the intersections of shunt control line 405 and digit lines 115-i through 115-l. In this way, the structure of the redundant portion of the array 400 can be designed to occupy less space in the array 400.

  FIG. 5 illustrates an example of an access circuit 500 of a redundant cell plate 210 according to various embodiments of the present disclosure. For example, FIG. 5 may show an example of an access circuit to the cell plate 210-i. However, the access circuit 500 can also be used to describe an access circuit to another cell plate 210.

  Cell plate 210-i may be coupled to either sense component 125-e or 125-f, or to virtual ground 505 (eg, Vss). For example, if shunt control line 405-b is selected, shunt switching component 420-i may be closed and node 510 on digit line 115-i may be coupled to virtual ground. When shunt control line 405-d is selected, select switching component 415-i is closed and node 510 on digit line 115-i may be coupled to sense component 125-e or 125-f. As discussed herein, the settings of the shunt control line 405 and the switching components 415, 420 are controlled by the cell plate so that any given digit line 115 is not connected to both virtual ground 505 and sense component 125 simultaneously. The selection may be based on some relationships between groups 410-a, 410-b, 410-c.

  In some examples, the relative positions of the selection switching component 415 and the shunt switching component 420 may be switched such that the selection switching component 415 is located closer to the cell plate 210. See, for example, the access circuits associated with cell plates 210-k, 210-1. In some examples, select switching component 415 may be electronically coupled to word line 110. See, for example, the access circuits associated with cell plates 210-a-210-h and 210-m-210-t.

  Each redundant cell plate 210-i, 210-j, 210-k, 210-1 may be associated with one or more normal cell plates 210-a-210-h, 210-m-210-t. For example, in the illustrative example of FIG. 4, redundant cell plate 210-j may be associated with normal cell plate 210-a and normal cell plate 210-e. These associations between redundant cell plates and normal cell plates may be based at least in part on one or more relationships between normal cell plate groups 410-a, 410-c and shunt control lines 405. The association between the redundant cell plate 210 and the normal cell plate 210 may be based at least in part on a subset of the cell plates 210 of the normal plate group (eg, 410-a) electronically coupled to one shunt control line 405. .

FIG. 6 illustrates an example of a portion 600 of an array 400 according to various embodiments of the present disclosure. Portion 600 has been selected to illustrate one or more relationships between a normal cell plate and a redundant cell plate. The configuration of the shunt switching component 420 associated with the cell plate group 410-b may be based at least in part on the subset 605 of memory cells of the cell plate group 410-a. The configuration of the selection switching component 415 associated with the cell plate group 410-b may be based at least in part on a subset 610 of the memory cells of the cell plate group 410-a. For the purpose of explanation, FIG. 6 shows only the settings related to one shunt control line 405-a. However, it should be understood that the principles disclosed below may be adapted and applied to other shunt control lines (eg, shunt control lines 405-b, 405-c, 405-d, etc.).

  Subset 605 includes cell plate 210-a and cell plate 210-e. Cell plate 210-j may be associated with a cell plate of subset 605 based at least in part on the location of shunt switching components 420-a, 420-e on shunt control line 405-a. Subset 605 may be determined based on which cell plates 210 of cell plate group 410-a are electronically coupled to shunt control line 405-a via shunt switching component 420. Shunt switching component 420-j is disposed on shunt control line 405-a and is configured to connect cell plate 210-j to virtual ground when shunt control line 405-a is selected.

Subset 610 includes cell plate 210-c and cell plate 210-g. Cell plate 210-1 may be associated with a cell plate of subset 610 based at least in part on a location of the cell plate of subset 610 relative to subset 605. In the exemplary embodiment, the at least one cell plate is between the subset 605 and the subset 610 cell plates. In some examples, the cell plates of subset 610 may be determined based on their distance from the cell plates of subset 605 (related to the position of the shunt switching component on one shunt control line). In this way, the coupling between the activated cell plate and the branched cell plate can be further reduced. Selection switching component 415-1
Are placed on shunt control line 405-a and are configured to connect cell plate 210-1 to sense component 125-g or sense component 125-h when shunt control line 405-a is selected. You. In some examples, the subset 610 may include shunt switching components that are different from the shunt control lines 405 (eg, shunt control lines 405-b, 405-c, 405-d) of which cell plates 210 of the cell plate group 410-a. A determination may be made based on whether it is electronically coupled via 420.

  Returning to FIG. 4, the sense components 125 can be arranged to electronically couple to the different digit lines 115 of their respective cell plate groups 410. In some examples, the number of sense components 125 coupled to cell plate group 410-a is equal to the number of sense components 125 coupled to cell plate group 410-b.

  According to various embodiments of the present disclosure, additional elements are contemplated, but each element may not be explicitly labeled or shown. For example, in addition to digit lines 115-a (for cell plate 210-a), array 400 may include additional digit lines 115 for other cell plates 210. In some examples, the plurality of digit lines 115-a extend from the cell plate. For example, in addition to the selection switching component 415-a (for the cell plate 210-a), the array 400 may include additional selection switching components 415 for the other cell plates 210. For example, in addition to the shunt switching component 420-a (for the cell plate 210-a), the array 400 may include additional selective switching components 415 for other cell plates 210.

FIG. 7 illustrates an example of a memory array 700 and other components that support a redundant array column decoder for a ferroelectric memory, according to various embodiments of the present disclosure. The memory array 700 can be implemented similarly to the memory array 400 described above. The array 700 includes a normal cell plate 705 in the normal cell plate group 710 (for example, the normal cell plates 705-a, 705-b, and 16) when there are 16 normal cell plates 705 and 4 redundant cell plates 715. 705-c, 705-d, 705-e, 705-f, 705-g, 705-h, 705-i, 705-j, 705-k, 705-1, 705-m, 705-n, 705- o or 705-p) are redundant cell plates 715 (eg, redundant cell plates 715-a, 715-b, 715) in the redundant cell plate group 720.
c or 715-d). In the illustrative example, each redundant cell plate 715 may be associated with four regular cell plates 705. The relationships that define the settings of the switching components can be the same relationships described above with respect to array 400. In some examples, the number of redundant cell plates 715 may be an integer multiple of the number of normal cell plates 705.

  FIG. 8 shows a block diagram 800 of a memory array 805 supporting a redundant array column decoder for a memory, according to various embodiments of the present disclosure. Memory array 805 may be referred to as an electronic memory device and may be an example of a component of memory array 100 described with reference to FIG. In some examples, array 805 may be an example of a component of array 400 described with reference to FIG.

The memory array 805 may include one or more memory cells 810, a memory controller 815, word lines 820, plate lines 825, reference components 830, sense components 835, digit lines 840, and latches 845. These components may be in electronic communication with one another and may perform one or more of the functions described herein. In some cases, memory controller 815 may include a bias component 850, a timing component 855, and an isolation component 870.

  Memory controller 815 may be in electronic communication with word line 820, digit line 840, sense component 835, and plate line 825, which may include word line 110, the word line 110 described with reference to FIGS. It may be an example of a digit line 115, a sense component 125, and a plate line 210. Memory array 805 may also include reference component 830 and latch 845. The components of the memory array 805 may be in electronic communication with one another and may perform embodiments of the functions described with reference to FIGS. In some cases, reference component 830, sense component 835, and latch 845 may be components of memory controller 815.

  In some examples, memory controller 815 may support a means for accessing memory cells 810 of a first portion of memory array 805 during an access operation. In some examples, the first number of memory cells 810 in the first portion of the memory array 805 includes a first number of memory cells 810 in the memory array 805 that includes at least one cell that is redundant to cells in the first portion of the memory array. It may include an integer multiple of a second number of the second memory cells 810 in the second portion. In another example, the memory controller 815 can support a means for isolating the memory cells 810 of the second portion of the memory array 805 during an access operation. In some examples, the memory cells 810 of the second portion of the memory array 805 can be separated based at least in part on accesses to the memory cells 810 of the first portion of the memory array 805.

Additionally or alternatively, for example, the memory controller 815 supports a means for selecting a shunt control line during an access operation based at least in part on a memory cell 810 of a first portion of the memory array 805 that can be accessed. obtain. In another example, memory controller 815 can support a means for isolating a set of memory cells 810 of a first portion of memory array 805 during an access operation. In some examples, the set of memory cells 810 can be separated based at least in part on a selected shunt control line. In another example, the memory controller 815 may identify an identifier of a memory cell 810 of a first portion of the memory array 805, and may store each memory cell 810 of the first portion of the memory array 805 in a memory of a second portion of the memory array 805. A means for comparing with an array mapping index associated with the cell 810 may be supported. In another example, memory controller 815 can support means for accessing a second memory cell 810 of a second portion of memory array 805 based at least in part on a selected shunt control line. it can.

  In some examples, digit line 840 is in electronic communication with sense component 835 and ferroelectric capacitors of ferroelectric memory cell 810. Ferroelectric memory cell 810 may be writable to a logic state (eg, a first or second logic state). Word line 820 may be in electronic communication with memory controller 815 and selected components of ferroelectric memory cell 810. Plate line 825 may be in electronic communication with the plates of the memory controller 815 and the ferroelectric capacitors of the ferroelectric memory cells 810. Sense component 835 may be in electronic communication with memory controller 815, digit line 840, latch 845, and reference line 860. Reference component 830 may be in electronic communication with memory controller 815 via reference line 860. Sense control line 865 may be in electronic communication with sense component 835 and memory controller 815. These components may also communicate electronically, via other components, connections, or buses, with other components, both internal and external to memory array 805, in addition to components not listed above.

  Memory controller 815 may be configured to activate word line 820, plate line 825, or digit line 840 by applying voltages to their various nodes. For example, bias component 850 may be set to apply a voltage to operate memory cell 810 to read or write to memory cell 810 as described above. In some cases, memory controller 815 may include a row decoder, a column decoder, or both, as described with reference to FIG. This may allow memory controller 815 to access one or more memory cells 105. Bias component 850 may also provide a potential to reference component 830 to generate a reference signal for sense component 835. Further, bias component 850 may provide a potential for operation of sense component 835.

  In some cases, memory controller 815 may perform its operations using timing component 855. For example, timing component 855 can control various word line selection or plate bias timings, including switching and voltage application timings to perform memory functions such as read and write as discussed herein. In some cases, timing component 855 can control the operation of bias component 850.

  In some cases, memory controller 815 may perform its operations using isolation component 870. For example, the isolation component 870 may control which memory cells or cell plates are electronically coupled to ground or virtual ground during an access operation.

  Reference component 830 may include various components for generating a reference signal for sense component 835. Reference component 830 may include circuitry configured to generate a reference signal. In some cases, reference component 830 may be implemented using other ferroelectric memory cells 105. Sense component 835 can compare the signal from memory cell 810 (via digit line 840) with the reference signal from reference component 830. Having determined the logic state, the sense component can then store the output in latch 845 and use it according to the operation of the electronic device of which memory array 805 is a part. Sense component 835 may include a sense amplifier in electronic communication with the latches and the ferroelectric memory cells.

  The memory controller 815 may be an example of the memory controller 915 described with reference to FIG. 9 or an element of the memory controller 915.

  In some examples, memory array 805 is a first portion of a memory array that includes a first number of memory cells and a second portion of a memory array that includes a second number of memory cells. Wherein the first number is an even multiple of the second number and the set of shunt control lines is electronically associated with the memory cells of the first portion of the memory array and at least one memory cell of the second portion of the memory array. A first set of switching components coupled to the second portion, the shunt control line and associated with the first portion of the memory array, and a second set of the memory array coupled to the shunt control line. A second set of switching components associated with the portion, wherein the settings of the second set of switching components for the memory cells of the second portion of the memory array are: The no even partially, associated with the first set of settings for the switching components regarding memory cells of the first portion of the memory array, and a second set of the switching component, it may include.

  In some examples, the setting of the first set of switching components for the memory cells of the first portion of the memory array may be based at least in part on a cyclic shift of the memory cells of the first portion of the memory array. In some examples, the second set of switching components may include a first subset of switching components and a second subset of switching components. In some examples, a first subset of the switching components can couple memory cells of a second portion of the memory array to ground or virtual ground. In some examples, a second subset of the switching components can couple each memory cell of the second portion of the memory array to a sense amplifier.

  In some examples, the setting of the first subset of switching components for the memory cells of the second portion of the memory array includes at least the setting of the first set of switching components for the memory cells of the first portion of the memory array. May be based in part. The setting of the second subset of switching components for the memory cells of the second portion of the memory array may be based at least in part on the setting of the first set of switching components for the memory cells of the first portion of the memory array. it can. The settings of the first subset of switching components may be different from the settings of the second subset of switching components.

In some examples, the settings of the first subset of the switching components and the settings of the second subset of the switching components are associated with a subset of the memory cells of the first portion of the memory array coupled to one shunt control line. It can be based at least in part. In some examples, a first memory cell of a second portion of the memory array can be associated with a subset of memory cells of a first portion of the memory array, and at least one switching of the first subset of switching components can be performed. The component may be located on a single shunt control line and is in electronic communication with a first memory cell of a second portion of the memory array. In some examples, the second memory cells of the second portion of the memory array are not associated with any memory cells in the subset of memory cells of the first portion of the memory array and are not associated with the second subset of switching components. At least one switching component may be disposed on one shunt control line and is in electronic communication with a second memory cell of a second portion of the memory array.

  In some examples, memory array 805 may include a set of access lines that are in electronic communication with a first portion of the memory array and that are separate from a second portion of the memory array. In some examples, memory array 805 can include a third portion of the memory array that can include a first number of memory cells, and a third set of switching components can be coupled with a shunt control line, The setting of the third set of switching components for the memory cells of the third portion of the memory array may be associated with the third portion of the array, the first set of switching components for the memory cells of the first portion of the memory array. It may be based at least in part on the settings of the set.

  In some examples, at least one memory cell of the second portion of the memory array may be redundant with respect to at least one memory cell of the first portion of the memory array. In some examples, at least one memory cell of the second portion of the memory array may be redundant with respect to at least one memory cell of the first portion of the memory array. In some examples, the number of switching components in the second set may be an integer multiple of the second number of memory cells. In some examples, array 805 includes a first set of sense amplifiers coupled to memory cells of a first portion of the memory array and a sense amplifier coupled to memory cells of a second portion of the memory array. A second set.

  In another example, the memory array 805 includes a first portion of the memory array including a first number of memory cells, a second portion of the memory array including a second number of memory cells (where the first The number is an integer multiple of the second number), and a plurality of shunt control lines (here, shunt control lines) in electronic communication with the memory cells of the first portion of the memory array and the memory cells of the second portion of the memory array. , The second number of memory cells in the second portion of the memory array is equal to the number of shunt control lines).

  In some examples, a subset of memory cells from the first portion of the memory array may be coupled to one shunt control line, and one memory cell of the second portion of the memory array corresponds to the subset of memory cells And may be coupled to the single shunt control line.

  In some examples, the memory array 805 may include a first set of switching components in electronic communication with the plurality of shunt control lines. The first set of switching components can couple the memory cells of the first portion of the memory array and the memory cells of the second portion of the memory array to ground or virtual ground. In some examples, memory array 805 may include a second set of switching components in electronic communication with the plurality of shunt control lines. A second set of switching components can couple memory cells of a second portion of the memory array to a sense amplifier.

In another example, the memory array 805 can include a first portion and a second portion having at least one cell redundant to the cells of the first portion (where the first portion The first number of memory cells is an integer multiple of the second number of memory cells in the second portion), at least one shunt control line, and a memory array and at least one shunt control line. An electronically communicating controller, wherein the controller accesses a memory cell of a first portion of the memory array during an access operation and uses at least one shunt control line to at least partially , The memory cells of the second part of the memory array can be separated during the access operation based on the access to the memory cells of the first part of the memory array.

  FIG. 9 illustrates a diagram of a system 900 that includes a device 905 that supports a redundant array column decoder for a memory, according to various embodiments of the present disclosure. Device 905 can be, for example, or include one example of the components of memory array 100 described above with reference to FIG.

  Device 905 is for two-way voice and data communications, including components for sending and receiving communications, including memory controller 915, memory cells 920, BIOS component 925, processor 930, I / O control component 935, and peripheral components 940. Components.

  Memory controller 915 may operate one or more memory cells as described herein. Specifically, the memory controller 915 may be set to support full bias detection in a three-dimensional memory array. In some cases, memory controller 915 may include a row decoder, a column decoder, or both, as described with reference to FIG.

  Memory cell 920 can store information (ie, in the form of a logic state) as described herein.

  The BIOS component 925 is a software component that includes a basic input / output system (BIOS) that operates as firmware, and can initialize and execute various hardware components. The BIOS component 925 may also manage data flow between the processor and various other components, such as peripheral components, input / output control components, and the like. BIOS component 925 may include programs or software stored in read only memory (ROM), flash memory, or any other non-volatile memory.

  Processor 930 includes intelligent hardware devices (eg, general purpose processors, digital signal processors (DSPs), central processing devices (CPUs), microcontrollers, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic Devices, discrete gate or transistor logic components, discrete hardware components, or any combination thereof). In some cases, processor 930 may be configured to operate a memory array using a memory controller. In other cases, the memory controller may be integrated with the processor 930. Processor 930 may be configured to execute computer-readable instructions stored in memory to perform various functions (eg, functions or tasks that support full bias sensing in a three-dimensional memory array).

Input / output (I / O) control component 935 may manage input / output signals for device 905. The input / output control component 935 may also manage peripherals that are not integrated with the device 905. In some cases, input / output control component 935 may represent a physical connection or port to an external peripheral. In some cases, the I / O control component 935 may be an iOS (registered trademark), ANDROID (registered trademark), MS-DOS (registered trademark), MS-WINDOWS (registered trademark), OS / 2 (registered trademark), UNIX
An operating system may be utilized, such as LINUX, or other known operating systems.

  Peripheral component 940 may include any input or output device, or interface for such a device. Examples include disk controllers, sound controllers, graphics controllers, Ethernet controllers, modems, universal serial bus (USB) controllers, serial or parallel ports, or peripheral component interconnect (PCI) slots or accelerated graphics port (AGP) slots Peripheral card slots.

  Input 945 may represent a device or signal external to device 905 that provides input to device 905 or a component thereof. This may include a user interface or an interface with other devices. In some cases, input 945 may be managed by I / O control component 935 and may interact with device 905 via peripheral component 940.

  Output 950 may also represent a device or signal external to device 905 configured to receive output from device 905 or any component thereof. Examples of output 950 may include a display, audio speakers, a printing device, another processor or a printed circuit board, or the like. In some cases, output 950 may be a peripheral component that interfaces with device 905 via peripheral component 940. In some cases, output 950 may be managed by I / O control component 935.

  Components of device 905 may include circuits designed to perform their functions. This may include various circuit elements, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements, configured to perform the functions described herein. May be included.

  FIG. 10 shows a flowchart illustrating a method 1000 for a redundant array column decoder for a memory according to various embodiments of the present disclosure. The operations of method 1000 may be implemented by memory controller 140 or a component thereof, as described herein. For example, the operations of method 1000 may be performed by a memory controller as described with reference to FIGS. 1, 8, and 9. In some examples, memory controller 140 may execute a set of codes for controlling functional elements of the device to perform the functions described below. Additionally or alternatively, the memory controller 140 may perform some or all of the functions described below using dedicated hardware.

  At block 1005, the memory controller 140 may access a memory cell of a first portion of the memory array during an access operation, wherein a first number of the first memory cell in the first portion of the memory array. Includes an integer multiple of a second number of memory cells in a second portion of the memory array, including at least one cell redundant to cells of the first portion of the memory array. The operations of block 1005 may be performed according to the methods described with reference to FIGS. In some examples, the operations of block 1005 may be performed by separation component 870 as described with reference to FIG.

  In some cases, the method may also include selecting a shunt control line during an access operation based at least in part on a memory cell of a first portion of the memory array to be accessed.

At block 1010, the memory controller 140 can isolate a memory cell of a second portion of the memory array during an access operation, wherein the memory cell of the second portion of the memory array is connected to the first portion of the memory array. Separation is based at least in part on access to portions of the memory cells. The operations of block 1010 may be performed according to the methods described with reference to FIGS. In some examples, the operations of block 1010 may be performed by separation component 870 as described with reference to FIG.

  In some cases, the method can also include isolating the set of memory cells of the first portion of the memory array during an access operation, wherein the set of memory cells is connected to a selected shunt control line. Separated based at least in part on. In some cases, the method compares the identifier of the memory cell of the first portion of the memory array with an array mapping index that associates each memory cell of the first portion of the memory array with a memory cell of the second portion of the memory array. It can also include In some cases, the method can also include determining a shunt control line to be selected based at least in part on the comparison. In some cases, the method may also include accessing a second memory cell of a second portion of the memory array based at least in part on the selected shunt control line.

  FIG. 11 shows a flowchart illustrating a method 1100 for a redundant array column decoder for a memory according to various embodiments of the present disclosure. The operations of method 1100 may be performed by memory controller 140 or a component thereof, as described herein. For example, the operations of method 1100 may be performed by separation component 870, as described with reference to FIG. In some examples, memory controller 140 may execute a set of codes for controlling functional elements of the device to perform the functions described below. Additionally or alternatively, the memory controller 140 may perform the functions described below using dedicated hardware.

  At block 1105, the memory controller 140 may access a memory cell of a first portion of the memory array during an access operation, wherein the first number of memory cells of the first portion of the memory array is A second number of memory cells of the memory array of the second portion of the memory array including at least one cell that is redundant to the cells of the first portion of the memory array. The operations of block 1105 may be performed according to the methods described with reference to FIGS. In some examples, the operations of block 1105 may be performed by separation component 870 as described with reference to FIG.

  At block 1110, the memory controller 140 may select a shunt control line during an access operation based at least in part on a memory cell of a first portion of the memory array being accessed. The operations of block 1110 may be performed according to the methods described with reference to FIGS. In some examples, the operations of block 1110 may be performed by separation component 870 as described with reference to FIG.

  At block 1115, the memory controller 140 can isolate the memory cells of the second portion of the memory array during an access operation, wherein the memory cells of the second portion of the memory array are separated from the first portion of the memory array. Separation is based at least in part on accessing memory cells. The operations of block 1115 may be performed according to the methods described with reference to FIGS. In some examples, the operations of block 1115 may be performed by separation component 870, as described with reference to FIG.

In some cases, method 1100 can separate a set of memory cells of a first portion of a memory array during an access operation, wherein the set of memory cells is at least partially connected to a selected shunt control line. Is separated based on In some cases, method 1100 may include identifying an identifier of a memory cell in a first portion of the memory array with an array mapping index that associates each memory cell in the first portion of the memory array with a memory cell in a second portion of the memory array. A comparison can be made and a selected shunt control line can be determined based at least in part on the comparison. In some cases, method 1100 can access a second memory cell of a second portion of the memory array based at least in part on the selected shunt control line.

  Note that the above method describes a possible implementation, and that operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Further, elements or features from more than one method may be combined.

  The term "access line" may be used interchangeably with "common conductive line", "word line", "digit line", "bit line", or other similar words. The word "word line" may be used interchangeably with the word "digit select line." The term “shunt control line” may be used interchangeably with the term “digit line shunt line”.

  The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips, referred to throughout the foregoing description, may be voltages, currents, electromagnetic waves, magnetic or magnetic particles, light fields or particles, or Can be represented by any combination of Some figures may show multiple signals as one signal, but those skilled in the art may refer to that signal as representing a bus of signals, where the bus has various bit widths. You will understand.

  As described herein, the term "virtual ground" refers to a node in an electronic circuit that holds a voltage of approximately 0 volts (0V) but is not directly connected to ground. Thus, the virtual ground voltage can fluctuate temporarily and return to approximately 0V in a stable state. The virtual ground can be implemented using various electronic circuit elements, such as a voltage divider consisting of an operable amplifier and a resistor. Other implementations are possible. "Virtual grounding" or "virtually grounded" means connected to approximately 0V.

  The term "electronic communication" describes a relationship between components that supports the flow of electrons between components. This may include direct connections between the components, or may include components in between. Components that are in electronic communication may dynamically exchange electrons or signals (eg, in a voltage-applied circuit), or may be electronic (eg, in a non-voltage-applied circuit). Or, the signal may not be dynamically exchanged, but may be configured or operable to exchange electronics or signals in response to a voltage being applied to the circuit. As an example, two components physically connected through a switch (eg, a transistor) are in electronic communication regardless of the state of the switch (ie, open or closed).

  The term "isolated" refers to a relationship between components where electrons cannot currently flow between the components. Components are separated from each other if there is an open circuit between them. For example, two components physically connected by a switch may be separated from each other when the switch is open.

As used herein, the term "shorting" refers to a component between components in which a conductive path is established between components through activation of a single intermediate component between the two components in question. Refers to a relationship. For example, a first component shorted to a second component can exchange electrons when a switch between the two components is closed. Thus, a short circuit can be a dynamic operation that allows the flow of charge between multiple components (or lines) that communicate electronically.

  The devices discussed herein, including the memory array 100, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or a semiconductor on another substrate. It may be an epitaxial layer of a material. The conductivity of the substrate or a subregion thereof can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, or by ion implantation, or by any other doping means

  One or more of the transistors discussed herein may represent a field effect transistor (FET) and may include a three terminal device including a source, a drain, and a gate. The terminals can be connected to other electronic devices through a conductive material (eg, metal). The source and drain may be conductive and may include heavily doped (eg, modified) semiconductor regions. The source and drain may be separated from the lightly doped semiconductor region or channel. If the channel is n-type (ie, the primary carrier is electrons), the FET may be referred to as an n-type FET. If the channel is p-type (ie, the main carrier is holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to each of an n-type FET or a p-type FET can make the channel conductive. A transistor is "activated" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor is "turned off" or "inactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

  The descriptions set forth herein in connection with the accompanying drawings illustrate exemplary settings and do not represent all examples that could be implemented or are within the scope of the claims. . As used herein, the word "exemplary" means "serving as an example, instance, or illustration" and does not mean "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the described technology. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

  In the accompanying drawings, similar components or features may have the same reference label. Further, various components of the same type can be distinguished by placing a dash after the reference label and a second label that distinguishes similar components. Where only a first reference label is used herein, the description is applicable to any similar component having the same first reference label, regardless of the second reference label.

  The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may include voltages, currents, electromagnetic waves, magnetic or magnetic particles, light or light particles, or any combination thereof. Can be represented by

  The various illustrative blocks and modules described in connection with the disclosure herein may be implemented with a general purpose processor, DSP, ASIC, FPGA, or other device designed to perform the functions described herein. Or discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be a combination of computing devices (eg, a combination of a digital signal processor (DSP) and a microprocessor, one or more microprocessors cooperating with a DSP core, or any other similar device). Configuration).

  The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other embodiments and implementations are within the scope of the disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hard wiring, or any combination thereof. The mechanisms that implement the functions may also be physically located at various locations, including distributing some of the functions such that each is implemented at a different physical location. Also, as used herein, including the claims, lists of items (eg, such as "at least one of ..." or "one or more of ..."). "Or" as used in a list of items beginning with a phrase) indicates a comprehensive list. For example, a list of at least one of A, B, or C means A, or B, or C, or AB, or AC, or BC, or ABC (ie, A and B and C).

  Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Non-transitory storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, non-transitory computer readable media includes RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other A magnetic storage device or a computer which can be used to carry or store the desired program code means in the form of instructions or data structures and which is a general purpose or special purpose computer, or a general purpose or special purpose computer It may include, but is not limited to, other non-transitory media accessible by the processor. Also, any connection is properly termed a computer-readable medium. For example, if the software uses a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, radio frequency, and microwave, a website, server, or other remote source When transmitted from, coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio frequency, and microwave are included in the definition of the medium. As used herein, disks and discs include CDs, laser disks, optical disks, digital versatile disks (DVDs), floppy disks, and Blu-ray disks. A disk normally reproduces data magnetically, while a disc reproduces data optically with a laser. Combinations thereof may also be included within the scope of computer readable media.

  What has been described herein is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. . Accordingly, the disclosure is not to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features described herein.

Claims (23)

A first portion of a memory array including a first number of memory cells;
A second portion of the memory array including a second number of memory cells, wherein the first number is an even multiple of the second number;
A set of shunt control lines in electronic communication with the memory cells of the first portion of the memory array and at least one memory cell of the second portion of the memory array;
A first set of switching components coupled to the shunt control line and associated with the first portion of the memory array; and coupled to the shunt control line and associated with the second portion of the memory array A second set of switching components, wherein the setting of the second set of switching components for the memory cells of the second portion of the memory array comprises the memory of the first portion of the memory array. An apparatus comprising: the second set of switching components based at least in part on a configuration of the second set of switching components for a cell. Wherein the first portion of the memory array of the first set of the switching component concerning the memory cell configuration, at least partly based on the shift of the memory cell of the first portion of the memory array,
The device according to claim 1. Wherein said second set of switching components comprises:
A first subset of the switching components, and a second subset of the switching component according to claim 1. The first subset of switching components couples the memory cells of the second portion of the memory array to ground or virtual ground;
Apparatus according to claim 3. The apparatus of claim 3, wherein the second subset of switching components couples each memory cell of the second portion of the memory array to a sense amplifier. Setting the first subset of switching components for the memory cells of the second portion of the memory array comprises setting the first set of switching components for the memory cells of the first portion of the memory array. Based at least in part on
Setting the second subset of switching components for the memory cells of the second portion of the memory array comprises setting the first set of switching components for the memory cells of the first portion of the memory array. Based at least in part on
The apparatus according to claim 3, wherein the settings of the first subset of switching components are different from the settings of the second subset of switching components. The settings of the first subset of switching components and the settings of the second subset of switching components are associated with a subset of memory cells of the first portion of the memory array coupled to one shunt control line. Based at least in part on,
An apparatus according to claim 6. A first memory cell of the second portion of the memory array is associated with the subset of memory cells of the first portion of the memory array;
At least one switching component of the first subset of switching components is located on the one shunt control line and is in electronic communication with the first memory cell of the second portion of the memory array. The apparatus according to claim 7. A second memory cell of the second portion of the memory array is not associated with any memory cell in the subset of memory cells of the first portion of the memory array;
At least one switching component of the second subset of switching components is disposed on the one shunt control line and is in electronic communication with the second memory cell of the second portion of the memory array. Item 8. The apparatus according to Item 7. The apparatus of claim 1, further comprising: a set of access lines in electronic communication with the first portion of the memory array and separate from the second portion of the memory array. A third portion of the memory array including the first number of memory cells; and a third set of switching components coupled to the shunt control line and associated with the third portion of the memory array. Setting the third set of switching components for the memory cells of the third portion of the memory array comprises setting the first set of switching components for the memory cells of the first portion of the memory array. Further comprising the third set of switching components based at least in part on the settings of
The device according to claim 1. The at least one memory cell of the second portion of the memory array is redundant to at least one memory cell of the first portion of the memory array;
The device according to claim 1. The at least one memory cell of the second portion of the memory array is redundant to a plurality of memory cells of the first portion of the memory array;
An apparatus according to claim 12. The number of switching components of the second set of switching components is an integer multiple of the second number of memory cells;
The device according to claim 1. A first set of sense amplifiers coupled to the memory cells of the first portion of the memory array, and a second set of sense amplifiers coupled to the memory cells of the second portion of the memory array The device of claim 1, further comprising: A first portion of a memory array including a first number of memory cells;
A second portion of the memory array including a second number of memory cells, wherein the first number is an integer multiple of the second number; and
A plurality of shunt control lines in electronic communication with the memory cells of the first portion of the memory array and the memory cells of the second portion of the memory array; The apparatus comprising: the plurality of shunt control lines, wherein the second number of memory cells in a portion is the same as the number of shunt control lines. A subset of memory cells from the first portion of the memory array are coupled to a single shunt control line;
The apparatus of claim 16, wherein one memory cell of the second portion of the memory array corresponds to the subset of memory cells and is coupled to the one shunt control line. A first set of switching components in electronic communication with a plurality of shunt control lines, wherein the first set of switching components includes the memory cells of the first portion of the memory array and the memory cells of the memory array; The apparatus of claim 16, further comprising the first set of switching components connecting the memory cells of the second portion to ground or virtual ground. A second set of switching components in electronic communication with the plurality of shunt control lines, wherein the second set of switching components couples the memory cells of a second portion of the memory array to a sense amplifier. 19. The apparatus of claim 18, further comprising: the second set of switching components. Accessing a memory cell of a first portion of a memory array during an access operation, wherein a first number of memory cells in the first portion of the memory array are configured to access the first number of memory cells of the memory array. Including an integer multiple of a second number of memory cells in a second portion of the memory array including at least one cell redundant to a portion of cells;
Selecting a shunt control line during the access operation based at least in part on the memory cells of the first portion of the memory array accessed; and a second one of the memory arrays during the access operation. Isolating memory cells of a portion, wherein the memory cells of the second portion of the memory array are at least partially based on accessing the memory cells of the first portion of the memory array. And separating. Isolating the set of memory cells of the first portion of the memory array during the access operation, the set of memory cells being based at least in part on the selected shunt control line. 21. The method of claim 20, further comprising: separating. Comparing an identifier of the memory cell of the first portion of the memory array with an array mapping index that associates each memory cell of the first portion of the memory array with a memory cell of the second portion of the memory array; 21. The method of claim 20, further comprising: determining a shunt control line to be selected based at least in part on the comparison. 21. The method of claim 20, further comprising: accessing a second memory cell of the second portion of the memory array based at least in part on the selected shunt control line.

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