JP6636526B2 - データ処理方法、メモリ管理ユニット、およびメモリ制御デバイス - Google Patents
データ処理方法、メモリ管理ユニット、およびメモリ制御デバイス Download PDFInfo
- Publication number
- JP6636526B2 JP6636526B2 JP2017533440A JP2017533440A JP6636526B2 JP 6636526 B2 JP6636526 B2 JP 6636526B2 JP 2017533440 A JP2017533440 A JP 2017533440A JP 2017533440 A JP2017533440 A JP 2017533440A JP 6636526 B2 JP6636526 B2 JP 6636526B2
- Authority
- JP
- Japan
- Prior art keywords
- page table
- control device
- management unit
- memory control
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003672 processing method Methods 0.000 title claims description 31
- 238000012545 processing Methods 0.000 claims description 65
- 239000000872 buffer Substances 0.000 claims description 60
- 238000013519 translation Methods 0.000 claims description 56
- 238000004891 communication Methods 0.000 claims description 15
- 230000003213 activating effect Effects 0.000 claims description 2
- 238000012856 packing Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 52
- 230000008569 process Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- 230000009471 action Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 230000003993 interaction Effects 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 2
- 239000012634 fragment Substances 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000013475 authorization Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1024—Latency reduction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
- G06F2212/684—TLB miss handling
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2015/075205 WO2016154789A1 (fr) | 2015-03-27 | 2015-03-27 | Procédé de traitement de données, unité de gestion de mémoire et dispositif de commande de mémoire |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018503903A JP2018503903A (ja) | 2018-02-08 |
JP6636526B2 true JP6636526B2 (ja) | 2020-01-29 |
Family
ID=57003847
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017533440A Active JP6636526B2 (ja) | 2015-03-27 | 2015-03-27 | データ処理方法、メモリ管理ユニット、およびメモリ制御デバイス |
Country Status (6)
Country | Link |
---|---|
US (1) | US10353824B2 (fr) |
EP (1) | EP3211534B1 (fr) |
JP (1) | JP6636526B2 (fr) |
KR (1) | KR101994952B1 (fr) |
CN (1) | CN107209724B (fr) |
WO (1) | WO2016154789A1 (fr) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20180009217A (ko) * | 2016-07-18 | 2018-01-26 | 삼성전자주식회사 | 데이터 저장 장치의 작동 방법과 이를 포함하는 데이터 처리 시스템의 작동 방법 |
US11048644B1 (en) * | 2017-12-11 | 2021-06-29 | Amazon Technologies, Inc. | Memory mapping in an access device for non-volatile memory |
US10817338B2 (en) * | 2018-01-31 | 2020-10-27 | Nvidia Corporation | Dynamic partitioning of execution resources |
US11307903B2 (en) | 2018-01-31 | 2022-04-19 | Nvidia Corporation | Dynamic partitioning of execution resources |
US11216592B2 (en) * | 2018-08-02 | 2022-01-04 | Qualcomm Incorporated | Dynamic cryptographic key expansion |
US11360704B2 (en) | 2018-12-21 | 2022-06-14 | Micron Technology, Inc. | Multiplexed signal development in a memory device |
DE112020002497T5 (de) | 2019-05-23 | 2022-04-28 | Hewlett Packard Enterprise Development Lp | System und verfahren zur dynamischen zuweisung von reduktionsmotoren |
CN112860600A (zh) * | 2019-11-28 | 2021-05-28 | 深圳市海思半导体有限公司 | 一种加速硬件页表遍历的方法及装置 |
US11461237B2 (en) | 2019-12-03 | 2022-10-04 | International Business Machines Corporation | Methods and systems for translating virtual addresses in a virtual memory based system |
US11163695B2 (en) | 2019-12-03 | 2021-11-02 | International Business Machines Corporation | Methods and systems for translating virtual addresses in a virtual memory based system |
CN113347239B (zh) * | 2021-05-27 | 2023-01-10 | 北京奇艺世纪科技有限公司 | 通信请求处理方法、装置、系统、电子设备及存储介质 |
CN115072502B (zh) * | 2022-07-01 | 2023-11-07 | 猫岐智能科技(上海)有限公司 | 电梯终端服务器系统及控制方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04148352A (ja) * | 1990-10-11 | 1992-05-21 | Fujitsu Ltd | 複数プロセッサを備える情報処理装置におけるアドレス変換方式 |
JPH0561772A (ja) * | 1991-09-03 | 1993-03-12 | Nec Corp | 情報処理システム |
US6665788B1 (en) * | 2001-07-13 | 2003-12-16 | Advanced Micro Devices, Inc. | Reducing latency for a relocation cache lookup and address mapping in a distributed memory system |
US7752417B2 (en) | 2006-06-05 | 2010-07-06 | Oracle America, Inc. | Dynamic selection of memory virtualization techniques |
US8700883B1 (en) * | 2006-10-24 | 2014-04-15 | Nvidia Corporation | Memory access techniques providing for override of a page table |
US8170042B2 (en) * | 2007-11-27 | 2012-05-01 | Cisco Technology, Inc. | Transmit-side scaler and method for processing outgoing information packets using thread-based queues |
US8015361B2 (en) | 2007-12-14 | 2011-09-06 | International Business Machines Corporation | Memory-centric page table walker |
US8140781B2 (en) | 2007-12-31 | 2012-03-20 | Intel Corporation | Multi-level page-walk apparatus for out-of-order memory controllers supporting virtualization technology |
US8533429B2 (en) * | 2009-06-24 | 2013-09-10 | Panasonic Corporation | Memory access control device, integrated circuit, memory access control method, and data processing device |
US8397049B2 (en) * | 2009-07-13 | 2013-03-12 | Apple Inc. | TLB prefetching |
US8244978B2 (en) | 2010-02-17 | 2012-08-14 | Advanced Micro Devices, Inc. | IOMMU architected TLB support |
EP2416251B1 (fr) | 2010-08-06 | 2013-01-02 | Alcatel Lucent | Procédé de gestion de la mémoire d'un ordinateur, produit de programme informatique correspondant et dispositif de stockage de données correspondant |
US20120331265A1 (en) | 2011-06-24 | 2012-12-27 | Mips Technologies, Inc. | Apparatus and Method for Accelerated Hardware Page Table Walk |
GB2501274B (en) * | 2012-04-17 | 2020-05-13 | Advanced Risc Mach Ltd | Management of data processing security in a secondary processor |
US9213649B2 (en) * | 2012-09-24 | 2015-12-15 | Oracle International Corporation | Distributed page-table lookups in a shared-memory system |
CN103116556B (zh) * | 2013-03-11 | 2015-05-06 | 无锡江南计算技术研究所 | 内存静态划分虚拟化方法 |
US9135183B2 (en) * | 2013-03-13 | 2015-09-15 | Samsung Electronics Co., Ltd. | Multi-threaded memory management |
CN104239238B (zh) * | 2013-06-21 | 2018-01-19 | 格芯公司 | 用于管理转换旁视缓冲的方法和装置 |
US20160147667A1 (en) * | 2014-11-24 | 2016-05-26 | Samsung Electronics Co., Ltd. | Address translation in memory |
-
2015
- 2015-03-27 KR KR1020177015484A patent/KR101994952B1/ko active IP Right Grant
- 2015-03-27 CN CN201580073000.7A patent/CN107209724B/zh active Active
- 2015-03-27 JP JP2017533440A patent/JP6636526B2/ja active Active
- 2015-03-27 WO PCT/CN2015/075205 patent/WO2016154789A1/fr active Application Filing
- 2015-03-27 EP EP15886776.2A patent/EP3211534B1/fr active Active
-
2017
- 2017-06-02 US US15/612,714 patent/US10353824B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2018503903A (ja) | 2018-02-08 |
CN107209724A (zh) | 2017-09-26 |
KR101994952B1 (ko) | 2019-07-01 |
EP3211534A4 (fr) | 2017-12-13 |
US20170270051A1 (en) | 2017-09-21 |
WO2016154789A1 (fr) | 2016-10-06 |
CN107209724B (zh) | 2020-02-14 |
KR20170083584A (ko) | 2017-07-18 |
US10353824B2 (en) | 2019-07-16 |
EP3211534A1 (fr) | 2017-08-30 |
EP3211534B1 (fr) | 2020-03-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6636526B2 (ja) | データ処理方法、メモリ管理ユニット、およびメモリ制御デバイス | |
JP6434168B2 (ja) | スイッチへのアドレスキャッシュ | |
US9619387B2 (en) | Invalidating stored address translations | |
JP6133896B2 (ja) | 物理アドレスを用いる非割当てメモリアクセス | |
US9460024B2 (en) | Latency reduction for direct memory access operations involving address translation | |
US8402248B2 (en) | Explicitly regioned memory organization in a network element | |
US10095631B2 (en) | System address map for hashing within a chip and between chips | |
JP2018503181A (ja) | キャッシュ一貫性を有するマルチコアプロセッサ | |
US8185692B2 (en) | Unified cache structure that facilitates accessing translation table entries | |
US11693805B1 (en) | Routing network using global address map with adaptive main memory expansion for a plurality of home agents | |
JP2008507019A (ja) | メモリ管理システム | |
US10977192B1 (en) | Real-time memory-page state tracking and its applications | |
WO2009107048A2 (fr) | Procédés et systèmes de partitionnement de mémoire cache dynamique pour des applications réparties fonctionnant sur des architectures multiprocesseurs | |
WO2018027839A1 (fr) | Procédé d'accès à une entrée de table dans une mémoire cache de traduction d'adresses (tlb) et puce de traitement | |
JP6088951B2 (ja) | キャッシュメモリシステムおよびプロセッサシステム | |
US20170228164A1 (en) | User-level instruction for memory locality determination | |
US10810133B1 (en) | Address translation and address translation memory for storage class memory | |
US9798674B2 (en) | N-ary tree for mapping a virtual memory space | |
US9984003B2 (en) | Mapping processing method for a cache address in a processor to provide a color bit in a huge page technology | |
US10762137B1 (en) | Page table search engine | |
US10366008B2 (en) | Tag and data organization in large memory caches | |
US10754789B1 (en) | Address translation for storage class memory in a system that includes virtual machines | |
US10210083B1 (en) | Address remapping for efficient use of distributed memory | |
US10839019B2 (en) | Sort function race |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170620 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20170620 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20180522 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180709 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181009 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20190401 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190619 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20191118 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20191218 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6636526 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |