JP6636526B2 - データ処理方法、メモリ管理ユニット、およびメモリ制御デバイス - Google Patents

データ処理方法、メモリ管理ユニット、およびメモリ制御デバイス Download PDF

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JP6636526B2
JP6636526B2 JP2017533440A JP2017533440A JP6636526B2 JP 6636526 B2 JP6636526 B2 JP 6636526B2 JP 2017533440 A JP2017533440 A JP 2017533440A JP 2017533440 A JP2017533440 A JP 2017533440A JP 6636526 B2 JP6636526 B2 JP 6636526B2
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page table
control device
management unit
memory control
address
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JP2018503903A (ja
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云 ▲陳▼
云 ▲陳▼
广▲飛▼ ▲張▼
广▲飛▼ ▲張▼
昆鵬 宋
昆鵬 宋
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ホアウェイ・テクノロジーズ・カンパニー・リミテッド
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1009Address translation using page tables, e.g. page table structures
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement
    • G06F2212/1024Latency reduction
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65Details of virtual memory and virtual address translation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68Details of translation look-aside buffer [TLB]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68Details of translation look-aside buffer [TLB]
    • G06F2212/684TLB miss handling

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2017533440A 2015-03-27 2015-03-27 データ処理方法、メモリ管理ユニット、およびメモリ制御デバイス Active JP6636526B2 (ja)

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PCT/CN2015/075205 WO2016154789A1 (fr) 2015-03-27 2015-03-27 Procédé de traitement de données, unité de gestion de mémoire et dispositif de commande de mémoire

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JP2018503903A JP2018503903A (ja) 2018-02-08
JP6636526B2 true JP6636526B2 (ja) 2020-01-29

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US (1) US10353824B2 (fr)
EP (1) EP3211534B1 (fr)
JP (1) JP6636526B2 (fr)
KR (1) KR101994952B1 (fr)
CN (1) CN107209724B (fr)
WO (1) WO2016154789A1 (fr)

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US11048644B1 (en) * 2017-12-11 2021-06-29 Amazon Technologies, Inc. Memory mapping in an access device for non-volatile memory
US10817338B2 (en) * 2018-01-31 2020-10-27 Nvidia Corporation Dynamic partitioning of execution resources
US11307903B2 (en) 2018-01-31 2022-04-19 Nvidia Corporation Dynamic partitioning of execution resources
US11216592B2 (en) * 2018-08-02 2022-01-04 Qualcomm Incorporated Dynamic cryptographic key expansion
US11360704B2 (en) 2018-12-21 2022-06-14 Micron Technology, Inc. Multiplexed signal development in a memory device
DE112020002497T5 (de) 2019-05-23 2022-04-28 Hewlett Packard Enterprise Development Lp System und verfahren zur dynamischen zuweisung von reduktionsmotoren
CN112860600A (zh) * 2019-11-28 2021-05-28 深圳市海思半导体有限公司 一种加速硬件页表遍历的方法及装置
US11461237B2 (en) 2019-12-03 2022-10-04 International Business Machines Corporation Methods and systems for translating virtual addresses in a virtual memory based system
US11163695B2 (en) 2019-12-03 2021-11-02 International Business Machines Corporation Methods and systems for translating virtual addresses in a virtual memory based system
CN113347239B (zh) * 2021-05-27 2023-01-10 北京奇艺世纪科技有限公司 通信请求处理方法、装置、系统、电子设备及存储介质
CN115072502B (zh) * 2022-07-01 2023-11-07 猫岐智能科技(上海)有限公司 电梯终端服务器系统及控制方法

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US8140781B2 (en) 2007-12-31 2012-03-20 Intel Corporation Multi-level page-walk apparatus for out-of-order memory controllers supporting virtualization technology
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Publication number Publication date
JP2018503903A (ja) 2018-02-08
CN107209724A (zh) 2017-09-26
KR101994952B1 (ko) 2019-07-01
EP3211534A4 (fr) 2017-12-13
US20170270051A1 (en) 2017-09-21
WO2016154789A1 (fr) 2016-10-06
CN107209724B (zh) 2020-02-14
KR20170083584A (ko) 2017-07-18
US10353824B2 (en) 2019-07-16
EP3211534A1 (fr) 2017-08-30
EP3211534B1 (fr) 2020-03-11

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