JP6618591B2 - Power semiconductor device - Google Patents

Description

  The present invention relates to a power semiconductor device.

According to Japanese Patent Laying-Open No. 2012-231111 (Patent Document 1), in an IGBT (Insulated Gate Bipolar Transistor), an extraction region is disposed between a transistor region and a termination region disposed around the transistor region. In the extraction region, a p-type layer is provided on the n ⁻ -type drift layer. The p-type layer is connected to the emitter electrode. A dummy gate electrode is provided on the p-type layer via an insulating film. The dummy gate electrode is connected to the gate electrode. At the boundary between the extraction region and the termination region, that is, the outer end of the p-type layer, the current density tends to increase during the turn-off operation of the IGBT, and as a result, thermal breakdown can occur. This phenomenon limits the current interrupt capability during turn-off operation.

  According to the description in the above publication, lattice defects are introduced into the termination region. As a result, carriers existing in the termination region easily disappear, so that the carrier concentration in the extraction region decreases during the IGBT turn-off operation. Therefore, depletion from the p-type layer to the collector side is promoted, and the electric field strength is reduced. As a result, the current interruption capability during the IGBT turn-off operation is improved. On the other hand, lattice defects are not introduced into the extraction region. This is intended to avoid an increase in on-voltage. As described above, the technique of the above publication is intended to improve the shut-off capability during the turn-off operation without adversely affecting the on-voltage of the IGBT.

JP 2012-231011 A

  With the above technique, both low on-voltage and high shut-off capability can be ensured to some extent. However, the trade-off relationship between the two still requires improvement in the IGBT, and further technology is required. Similar problems also exist in other power semiconductor devices. For example, in a diode, an improvement in the trade-off relationship between a low on-voltage and a high shut-off capability during a recovery operation is required. In addition, there is a strong demand to reduce the manufacturing cost of semiconductor devices while ensuring the basic performance as described above. If the chip size of the semiconductor device can be reduced without sacrificing performance, the number of chips that can be manufactured from one wafer increases, so that the manufacturing cost can be reduced.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a power semiconductor device having a high cutoff capability.

  The power semiconductor device of the present invention includes an active area, an interface area provided on the outer periphery of the active area, and an edge termination area provided on the outer periphery of the interface area. The power semiconductor device includes a semiconductor substrate, a first electrode, a second electrode, and a gate wiring portion. The semiconductor substrate has a first surface and a second surface opposite to the first surface. Each of the first and second surfaces straddles the active area, the interface area, and the edge termination area. The semiconductor substrate includes a first conductivity type drift region, a second conductivity type first well region different from the first conductivity type, a second conductivity type collector region, and a second conductivity type second region. 2 well regions. The drift region is provided across the active area, the interface area, and the edge termination area. The first well region is provided on the first surface and is at least partially included in the interface area, and has an end portion between the interface area and the edge termination area on the first surface. The first electrode is provided in the active area, has an end portion between the active area and the interface area, and is in contact with the first surface of the semiconductor substrate. The second electrode is in contact with the second surface of the semiconductor substrate. The gate wiring portion is provided on the first surface of the semiconductor substrate in the active area via an insulating film. The collector region is provided only in the active area and partially forms the second surface. The second well region is in contact with the insulating film below the gate wiring portion and partially forms the first surface. The collector region is not provided on the second surface of the portion facing the gate wiring portion.

  According to the present invention, the collector region is not provided on the second surface of the portion facing the gate wiring portion. Thereby, it can have a high interruption | blocking capability.

  The objects, features and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

It is a top view which shows roughly the structure B of IGBT as a power semiconductor device in Embodiment 1 of this invention. FIG. 2 is a schematic partial cross-sectional view taken along line II-II in FIG. 1 (IGBT 900B, structure B). FIG. 3 is a plan view schematically showing a configuration of a second surface of the semiconductor substrate in FIG. 2. It is a fragmentary sectional view which shows structure A of IGBT of a comparative example by the same visual field as FIG. 2 (IGBT900A, structure A). It is a fragmentary sectional view which shows roughly the structure C of IGBT as a power semiconductor device in Embodiment 1 of this invention in the visual field similar to FIG. 2 (IGBT900C, structure C). It is a fragmentary sectional view which shows roughly the structure D of IGBT as a power semiconductor device in Embodiment 1 of this invention in the visual field similar to FIG. 2 (IGBT900D, structure D). It is a circuit diagram used for simulation of turn-off operation of IGBT. It is a graph which shows the turn-off waveform obtained by the simulation using the circuit of FIG. It is a graph which shows temperature distribution of device upper surface S1 in line DD 'in structure A (broken line) of a comparative example, and structure C (solid line) of an example. FIG. 10 is a graph showing the relationship between the peak temperature T _max and the ballast resistance region width (L _EEBR ) in FIG. 9. Comparative Example having the structure A (dashed line), in the embodiment having the structure D (solid line) is a graph showing the respective turn-off waveform of the collector-emitter voltage V _CE and the collector current I _C. It is a distribution map which shows the current potential and hole density | concentration in t = _tON (FIG. 11) of the structure A as a comparative example. It is a distribution map which shows the current potential and hole density | concentration in t = _tpeak (FIG. 11) of the structure A as a comparative example. It is a distribution map which shows the current potential and hole density | concentration in t = _tON (FIG. 11) of the structure D as an Example. It is a distribution map which shows the current potential and hole density | concentration in t = _tpeak (FIG. 11) of the structure D as an Example. It is a distribution map which shows the carrier concentration inside a device in t = _tON (FIG. 11) of the structure A as a comparative example. It is a distribution map which shows the carrier concentration inside a device in t = _tON (FIG. 11) of the structure D as an Example. It is a distribution map which shows the carrier concentration inside a device in t = _tpeak (FIG. 11) of the structure A as a comparative example. It is a distribution map which shows the carrier concentration inside a device in t = _tpeak (FIG. 11) of the structure D as an Example. It is a distribution map which shows the carrier concentration inside a device in t = _ttail (FIG. 11) of the structure A as a comparative example. It is a distribution map which shows the carrier concentration inside a device in t = t _tail (FIG. 11) of the structure D as an Example. It is a distribution map which shows the electric field strength inside a device in t = _tON (FIG. 11) of structure A as a comparative example. It is a distribution map which shows the electric field strength inside a device in t = _tON (FIG. 11) of the structure D as an Example. It is a distribution map which shows the electric field strength inside a device in t = _tpeak (FIG. 11) of the structure A as a comparative example. It is a distribution map which shows the electric field strength inside a device in t = _tpeak ( _Drawing 11) of structure D as an example. It is a distribution map which shows the electric field strength inside a device in t = t _tail (FIG. 11) of the structure A as a comparative example. It is a distribution map which shows the electric field strength inside a device in t = t _tail (FIG. 11) of the structure D as an Example. Ratio λ of p collector layer in structure D and various electrical characteristics, ie, saturation current density J _C (sat), ON voltage V _CE (sat), turn-off maximum cutoff current density J _C (break), and short-circuit maximum is a graph showing an example of a relationship between cutoff energy E _SC. It is a graph which shows the relationship between the dose amount of a collector, and maximum cutoff current density _JC (break) at the time of turn-off in structure A (broken line) as a comparative example and structure D (solid line) as an example. It is a graph which shows RBSOA (Reverse Bias Safe Operating Area) of structure A (broken line) as a comparative example and structure D (solid line) as an example. It is a fragmentary sectional view (IGBT900Z) which shows the structure of the planar type IGBT as another comparative example by the cross section corresponding to line II-II (FIG. 1). The ON voltage V _CE (sat) and the turn-off loss E _{OFF in} the structure D (solid line) as an example, the structure A (dashed line) as a comparative example, and the planar type IGBT (one-dot chain line) as another comparative example It is a graph which shows the trade-off characteristic between. It is a fragmentary sectional view which shows roughly the structure E of a modification with the visual field similar to FIG. 2 (IGBT900E, structure E). It is a fragmentary sectional view showing roughly structure F of a modification (IGBT900F, structure F). It is a fragmentary sectional view which shows roughly the structure G of IGBT as a power semiconductor device in Embodiment 2 of this invention (IGBT900G, structure G). It is a fragmentary sectional view which shows area | region XXVIII of FIG. 27 in detail. FIG. 29 is a partial cross-sectional view schematically showing a configuration of a pseudo well by the field limiting ring of FIG. 28. It is a graph which shows the simulation result of each turn-off waveform of collector-emitter voltage _VCE and collector current density _{JC in} the comparative example (broken line) which has the structure A, and the Example (solid line) which has the structure G. It is a graph which shows the simulation result of the peak temperature inside a device in the comparative example (broken line) which has structure A, and the example (solid line) which has structure G. It is a distribution map which shows the simulation result of the temperature inside a device in the comparative example which has the structure A, and the Example which has the structure G. It is a distribution map which shows the simulation result of the impact ionization rate inside a device in the comparative example which has the structure A, and the Example which has the structure G. It is a graph which shows the relationship between the position X in the comparative example which has the structure A, and the electric field strength _{Eedge in} the upper surface of a board _| substrate about each of a dynamic state (solid line) and a static state (broken line). It is a graph which shows the relationship between the position X in the Example which has the structure G, and the electric field strength _{Eedge in} the upper surface of a board _| substrate about each of a dynamic state (solid line) and a static state (broken line). The position X _edge along the line FF ′ in the comparative example (broken line) having the structure A (FIG. 4) and the example (solid line) having the structure G (FIG. 27), and the electric field strength in the static state It is a graph which shows the relationship with E. It is a graph which shows the relationship between the pressure | voltage resistant class V _class and the required width W _edge of an edge termination area in the comparative example which has the structure A, and the Example which has the structure G. It is a fragmentary sectional view showing roughly structure H of a modification of Drawing 28 (IGBT900H, structure H). FIG. 29 is a partial cross-sectional view schematically showing structure I of the modification example of FIG. 28 (IGBT 900I, structure I). It is a fragmentary sectional view which shows roughly the structure I of the modification of FIG. 28 (IGBT900J, structure J). It is a fragmentary sectional view which shows roughly the structure of the diode as a power semiconductor device in Embodiment 3 of this invention (diode 800A). It is a fragmentary sectional view which shows the structure of the diode of a comparative example (diode 800Z). For each example (solid line) and Comparative Example (broken line) is a graph showing the waveform of the voltage V _AK and current density J _A of the recovery operation, the internal device and the peak temperature T. For each of the example (solid line) and the comparative example (dashed line), the relationship between the position X along the line GG ′ (FIGS. 37 and 38) and the current density J _{A at} time t _d (FIG. 39). FIG. For each of the example (solid line) and the comparative example (dashed line), the position X along the line GG ′ (FIGS. 37 and 38) at the time t _d (FIG. 39), the temperature T of the device upper surface S1, and It is a graph which shows the relationship. FIG. 40 is a distribution diagram showing the relationship between the widths L _ABR and W _{p0 of} FIG. 37 and the temperature inside the device at time t _d (FIG. 39). FIG. 40 is a distribution diagram showing the relationship between the widths L _ABR and W _{p0 of} FIG. 37 and the current density inside the device at time t _d (FIG. 39). FIG. 42B is an enlarged view of each broken line region in FIG. 42A. The area S ratio of _abr gamma ballast resistance region relative to the area S _{active cell} of the active area is a graph showing the relationship between the maximum blocking of the recovery operation current density J _A (break) and a device internal maximum temperature T _max. It is a top view explaining area S _{active cell of} an active area and area _Sabr of a ballast resistance area _| region. It is a fragmentary sectional view which shows roughly the structure of the diode as a power semiconductor device in Embodiment 4 of this invention (diode 800B). FIG. 45B is a partial cross-sectional view showing a configuration of a modified example of FIG. 45A (diode 800C). FIG. 45B is a partial cross-sectional view showing a configuration of a modified example of FIG. 45A (diode 800D). FIG. 45B is a partial cross-sectional view showing a configuration of a modified example of FIG. 45A (diode 800E). For each example (solid line) and Comparative Example (broken line) is a graph showing a simulation result of a waveform of the voltage V _AK and current density J _A of the recovery operation. It is a graph which shows the simulation result of the peak temperature T inside a device at the time of a recovery operation | movement about each of an Example (solid line) and a comparative example (broken line). Line H-H 'of Comparative Example is a graph showing the position X and the electric field strength E _Surface and relationship t = t ₁ (FIG. 46A and FIG. 46B) in (Figure 38). Line H-H 'of Comparative Example is a graph showing the position X and the electric field strength E _Surface the relationship between t = t ₂ (FIG. 46A and FIG. 46B) in (Figure 38). Line H-H 'of Comparative Example is a graph showing the position X and the relationship between the electric field strength _E surface t = t ₃ (FIG. 46A and FIG. 46B) in (Figure 38). Line H-H 'of Comparative Example is a graph showing the position X and the relationship between the electric field strength _E surface t = t ₄ (FIG. 46A and FIG. 46B) in (Figure 38). Line H-H 'of Example is a graph showing the position X and the electric field strength E _Surface and relationship t = t ₁ (FIG. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Example is a graph showing the position X and the electric field strength E _Surface the relationship between t = t ₂ (FIG. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Example is a graph showing the position X and the relationship between the electric field strength _E surface t = t ₃ (FIG. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Example is a graph showing the position X and the relationship between the electric field strength _E surface t = t ₄ (FIG. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Example is a graph showing the position X and the electric field strength _E surface t = t ₅ the relationship between (FIGS. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Example is a graph showing the position X and the electric field strength E _Surface and the relationship t = t ₆ (FIGS. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Comparative Example is a graph showing the position X and the current density j _Surface and relationship t = t ₁ (FIG. 46A and FIG. 46B) in (Figure 38). Line H-H 'of Comparative Example is a graph showing the position X and the current density j _Surface relationship between the t = t ₂ (FIG. 46A and FIG. 46B) in (Figure 38). Line H-H 'of Comparative Example is a graph showing the position X and the current density j _Surface the relationship between t = t ₃ (FIG. 46A and FIG. 46B) in (Figure 38). Line H-H 'of Comparative Example is a graph showing the position X and the current density j _Surface and relationship t = t ₄ (FIG. 46A and FIG. 46B) in (Figure 38). Line H-H 'of Example is a graph showing the position X and the current density j _Surface and relationship t = t ₁ (FIG. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Example is a graph showing the position X and the current density j _Surface relationship between the t = t ₂ (FIG. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Example is a graph showing the position X and the current density j _Surface the relationship between t = t ₃ (FIG. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Example is a graph showing the position X and the current density j _Surface and relationship t = t ₄ (FIG. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Example is a graph showing the position X and the current density j _Surface and t = t ₅ the relation (FIGS. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Example is a graph showing the position X and the current density j _Surface the relationship between t = t ₆ (FIGS. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Comparative Example is a graph showing the position X and temperature T _Surface and relationship t = t ₁ of the device the upper surface S1 (FIG. 46A and FIG. 46B) in (Figure 38). Line H-H 'of Comparative Example is a graph showing the position X and the device upper surface temperature T _Surface and the relationship t = t ₂ of S1 (Fig. 46A and Fig. 46B) in (Figure 38). FIG. 46 is a graph showing a relationship between a position X on a line HH ′ (FIG. 38) of the comparative example and a temperature T _surface of the device upper surface S1 at t = t ₃ (FIGS. 46A and 46B). Line H-H 'of Comparative Example is a graph showing the position X and temperature T _Surface and relationship t = t ₄ of the device upper surface S1 (FIG. 46A and FIG. 46B) in (Figure 38). Line H-H 'of Example is a graph showing the position X and temperature T _Surface and relationship t = t ₁ of the device the upper surface S1 (FIG. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Example is a graph showing the position X and the device upper surface temperature T _Surface and the relationship t = t ₂ of S1 (Fig. 46A and Fig. 46B) in (Figure 45). Line H-H 'of Example is a graph showing the position X and temperature T _Surface and t = t ₃ the relationship of the device upper surface S1 (FIG. 46A and FIG. 46B) in (Figure 45). It is a graph showing the line H-H 'of Example Temperature T _Surface and relationship t = t ₄ of the position X and the device top surface S1 of (FIG. 45) (FIGS. 46A and FIG. 46B). Line H-H 'of Example is a graph showing the position X and relationship t = t ₅ between the temperature T _Surface device top S1 (FIG. 46A and FIG. 46B) in (Figure 45). Line H-H 'of Example is a graph showing the position X and t = t ₆ the relationship between the temperature T _Surface device top S1 (FIG. 46A and FIG. 46B) in (Figure 45). It is a graph explaining the recovery safe operation | movement area | region in a comparative example (represented by a triangular point) and an Example (represented by a circular point).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
(About IGBT900B)
Referring to FIG. 1, IGBT 900B (power semiconductor device) includes an active area AR1, an interface area AR2 provided on the outer periphery of active area AR1, and an edge termination area AR3 provided on the outer periphery of interface area AR2. Is included. The active area AR1 is a part that bears the basic function of the power semiconductor device, and is the part that bears the basic function of the IGBT in the present embodiment. The edge termination area AR3 is a portion for improving the breakdown voltage characteristics in the static state of the power semiconductor device, stabilizing and improving the reliability, and ensuring the breakdown tolerance in the dynamic state. The interface area AR2 is a portion that joins the active area AR1 and the edge termination area AR3 to each other, and is a particularly important portion for securing the destruction resistance in the dynamic state.

  The active area AR1 of the IGBT 900B includes an emitter electrode 13a having an emitter potential, a gate pad 29 having a gate potential, and a gate wiring portion 28 extending from the gate pad 29.

A structure (referred to as structure B) included in IGBT 900B will be described with reference to FIG. FIG. 2 shows a cross-sectional structure taken along line II-II in FIG. The IGBT 900B includes a substrate SB (semiconductor substrate), an emitter electrode 13a (first electrode), a gate connection electrode 13b, electrodes 13c and 13d, a collector electrode 4 (second electrode), a gate electrode 22, Gate wiring layer 22w, capacitor electrodes 23 and 32, trench insulating film 10, interlayer insulating films 12a and 12b, and passivation films 14 and 15 are provided. In the present embodiment, the substrate SB is made of silicon (Si). The substrate SB has an upper surface S1 (first surface) and a lower surface S2 (second surface opposite to the first surface). Each of the upper surface S1 and the lower surface S2 straddles the active area AR1, the interface area AR2, and the edge termination area AR3. Substrate SB includes n ⁻ drift layer 1 (drift region), n buffer layer 2, p collector layer 3 (collector region), n ⁺ emitter layer 5, p ⁺ layer 6, p base layer 8, N layer 24 and p guard ring 9 are included.

The n ⁻ drift layer 1 is provided across the active area AR1, the interface area AR2, and the edge termination area AR3. N ⁻ drift layer 1 has an n type (first conductivity type) and has an impurity concentration of, for example, about 1 × 10 ¹² to 1 × 10 ¹⁵ cm ⁻³ . The n ⁻ drift layer 1 can be prepared by an FZ wafer manufactured by a floating zone (FZ) method or an epitaxial wafer manufactured by an epitaxial method. In this case, portions of the substrate SB other than the n ⁻ drift layer 1 can be formed by ion implantation and annealing techniques.

N layer 24 is provided between n ⁻ drift layer 1 and p base layer 8. N layer 24 has an n type, and has an impurity peak concentration that is higher than that of n ⁻ drift layer 1 and lower than that of p base layer 8, for example, 1 × 10 ¹⁵ to The impurity peak concentration is about 1 × 10 ¹⁷ cm ⁻³ . The depth position from the upper surface S1 in the substrate SB reached by the n layer 24 is deeper than the p base layer 8, for example, about 0.5 to 1.0 μm.

N buffer layer 2 has a portion located between n ⁻ drift layer 1 and p collector layer 3 in active area AR1, and in this embodiment, n ⁻ drift layer in interface area AR2 and edge termination area AR3 1 and a portion located between the collector electrode 4. N buffer layer 2 is of an n type and has a higher impurity concentration than the impurity concentration of n ⁻ drift layer 1, for example, an impurity peak concentration of about 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ^−3. Have The depth position from the lower surface S2 in the substrate SB reached by the n buffer layer 2 is, for example, about 1.5 to 50 μm.

The n ⁻ drift layer 1, the n layer 24 and the n buffer layer 2 described above constitute an n-type region (first region) as a whole. One or both of the n layer 24 and the n buffer layer 2 may be omitted.

P base layer 8 (second region) is provided on a region (first region) having n ⁻ drift layer 1 and n layer 24, and is provided immediately above n layer 24 in the present embodiment. It has been. The depth position from the upper surface S 1 in the substrate SB reached by the p base layer 8 is deeper than the n ⁺ emitter layer 5 and shallower than the n layer 24. The p base layer 8 has p type (second conductivity type different from the first conductivity type), and has an impurity peak concentration of about 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ^−3, for example.

The n ⁺ emitter layer 5 (third region) is provided on the p base layer 8 and is disposed on the upper surface S1. The n ⁺ emitter layer 5 has a depth of about 0.2 to 1.0 μm, for example. N ⁺ emitter layer 5 has an n-type and has an impurity peak concentration of, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ .

The p ⁺ layer 6 is provided on the p base layer 8 and is disposed on the upper surface S1. For example, p ⁺ layer 6 has a surface impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . The depth position from the upper surface S1 in the substrate SB reached by the p ⁺ layer 6 is preferably the same as or deeper than that of the n ⁺ emitter layer 5.

The p collector layer 3 is provided only in the active area AR1 and partially forms the lower surface S2. The p collector layer 3 has a p-type and has a surface impurity concentration of, for example, about 1 × 10 ¹⁶ to 1 × 10 ²⁰ cm ⁻³ . The depth of p collector layer 3 from lower surface S2 of substrate SB is, for example, about 0.3 to 1.0 μm.

The p guard ring 9 is provided on the upper surface S1 and has a p-type. The p guard ring 9 has a p well region 9a and a p edge region 9b. The p well region 9a is connected to the emitter electrode 13a via the p ⁺ layer 6 provided on the upper surface S1 in the active area AR1. The p-well region 9a is at least partially included in the interface area AR2, and has an end portion between the interface area AR2 and the edge termination area AR3 on the upper surface S1. Due to the p-well region 9a, the blocking ability of the IGBT 900B is further enhanced.

  The p edge region 9b is included in the edge termination area AR3 and is away from the interface area AR2. In FIG. 2, only one p edge region 9b is schematically shown, but a plurality of p edge regions 9b are designed to be spaced apart from each other according to the voltage to be held.

In the active area AR1, a gate trench TG and a capacitor trench TC are provided on the upper surface S1 of the substrate SB. The sidewall of the gate trench TG faces each of the n ⁻ drift layer 1 and the n layer 24 (first region), the p base layer 8, and the n ⁺ emitter layer 5. In the present embodiment, the sidewall of capacitor trench TC faces n ⁻ drift layer 1, n layer 24, and p base layer 8. In addition, the capacitor trench TC located on the outermost side in the active area AR1 reaches the p well region 9a of the p guard ring 9. The trench insulating film 10 covers the gate trench TG and the capacitor trench TC of the substrate SB.

The gate electrode 22 has a portion embedded in the gate trench TG via the trench insulating film 10, and p between the n ⁺ emitter layer 5 and the n layer 24 (first region) via the trench insulating film 10. Opposite the base layer 8. The capacitor electrode 23 has a portion embedded in the capacitor trench TC via the trench insulating film 10. By providing the capacitor electrode 23, the saturation current density of the IGBT 900B is suppressed, and the oscillation phenomenon of the gate voltage when the load of the IGBT 900B is short-circuited is suppressed. Note that the capacitor trench TC and the capacitor electrode 23 may be omitted.

The interlayer insulating film 12a is provided on the upper surface S1 of the substrate SB. On the interlayer insulating film 12a, an emitter electrode 13a, a gate connection electrode 13b, and electrodes 13c and 13d are provided. The emitter electrode 13a is provided in the active area AR1, and is in contact with the upper surface S1 of the substrate SB. Specifically, emitter electrode 13a is in contact with each of n ⁺ emitter layer 5 and p ⁺ layer 6 through a contact hole provided in interlayer insulating film 12a. The gate connection electrode 13b is in contact with the gate wiring layer 22w through the contact hole. Therefore, the gate connection electrode 13b is short-circuited with the gate electrode 22 and has a gate potential. Electrode 13c is in contact with p well region 9a through a contact hole. The electrode 13c may be short-circuited with the emitter electrode 13a. The electrode 13d is a floating electrode, and is in contact with the p edge region 9b through a contact hole in the IGBT 900B.

  The interlayer insulating film 12b is provided on the upper surface S1 of the substrate SB. The interlayer insulating film 12b insulates the substrate SB and the gate wiring layer 22w from each other. The interlayer insulating film 12b may have a portion located between a part of the interlayer insulating film 12a and the substrate SB.

  The collector electrode 4 is provided on the lower surface S2 of the substrate SB. The collector electrode 4 is in contact with the p collector layer 3 in the active area AR1. As shown in FIG. 2, the collector electrode 4 may be in contact with the n buffer layer 2 (more generally, the first region described above) in the interface area AR2 and the edge termination area AR3.

A channel stop structure CS is preferably provided in the edge termination area AR3. In the present embodiment, an n region 34, a p region 38, and an n ⁺ region 35 are sequentially formed on the upper surface S1 of the substrate SB. Further, a channel stop trench TS extending through these regions and reaching the n ⁻ drift layer 1 is provided on the upper surface S1. A channel stop electrode 32 is provided in the channel stop trench TS via the trench insulating film 10. A floating potential electrode 13 d may be provided on the channel stop electrode 32. Note that another structure may be used in place of the above-described channel stop structure CS, for example, a structure formed simply by the n ⁺ region 35 may be used.

Referring to FIG. 3, λ is preferably 55% or more and 70% or less, where λ is the ratio of the area occupied by p collector layer 3 on lower surface S2 of substrate SB. That is, it is preferable that 55 ≦ 100 × (X _p × Y _p ) / (X _n × Y _n ) ≦ 70 is satisfied. Here, X _n and Y _n indicate the chip size of the IGBT 900B. When λ <55%, hole injection from the p collector layer 3 in the active area AR1 of the IGBT becomes insufficient, and the on-voltage (V _CE (sat)) increases. When λ> 70%, as will be described later, the electric field intensity of the weak spot (arrow WS in FIG. 2) due to a local temperature rise during the turn-off operation of the IGBT causes carrier injection from the p collector layer 3 from the on state of the IGBT. Occurring and not mitigated by the presence of carriers in the arrow WS portion, and the blocking ability is reduced. As described above, there is an appropriate region for the λ value from the performance balance of the IGBT. The total ratio of the active area AR1 and the interface area AR2 in the lower surface S2 is preferably more than 70%, for example, about 75%.

(About IGBT900A)
Referring to FIG. 4, IGBT 900A of the comparative example is provided with p collector layer 3 in addition to active area AR1, unlike IGBT 900B. Specifically, the p collector layer 3 is provided on the entire lower surface S2 of the substrate SB. The other configuration is almost the same as that of the IGBT 900B described above.

  When the IGBT 900A repeats the turn-off operation, a local temperature rise at the boundary between the active area AR1 and the interface area AR2 on the upper surface S1 of the substrate SB, that is, the arrow WS (FIG. 2) is particularly likely to occur. This phenomenon can limit the blocking capability of the IGBT 900A.

(About the effect of IGBT900B)
Unlike IGBT 900A, according to IGBT 900B shown in FIG. 2, p collector layer 3 is not provided in edge termination area AR3 and interface area AR2. Thereby, in the interruption operation of IGBT 900B, the temperature rise at arrow WS is suppressed. Further, since the configuration of the active area AR1 is the same as that of the IGBT 900A, there is no adverse effect that the on-voltage increases. From the above, the IGBT 900B has both a low on-voltage and a high blocking capability.

(About IGBT900C)
Referring to FIG. 5, in IGBT 900C, contact of electrode 13c (see FIG. 4) to p well region 9a is not provided. The p-well region 9a forms an electrical path connecting the emitter electrode 13a and the end of the p-well region 9a (arrow WS in the drawing) with a p-type region on the upper surface S1. This electrical path traverses the interface area AR2 between the active area AR1 and the edge termination area AR3 and has a resistive region having a width L _EEBR . The entire resistance region is covered with the interlayer insulating film 12b. As will be described in detail later, the width L _EEBR is determined so as to suppress a local temperature increase at one end of each end by sharing the temperature increase at both ends of the resistance region during the IGBT cutoff operation. In the IGBT 900A (FIG. 4), the local temperature rise occurs at the location indicated by the arrow WS. In the IGBT 900C, the temperature rise is shared at both ends of the resistance region by providing the resistance region. Such an effect is referred to as a ballast resistor, and the resistance region is also referred to as a ballast resistor region.

  The configuration other than the above is substantially the same as that of the IGBT 900B described above.

According to the IGBT 900C, at the time of operation, only the position of one end (the right end of the width L _{EEBR in} the figure) of the ballast resistance region corresponding to the position of the boundary between the interface area AR2 and the edge termination area AR3 (arrow WS in FIG. 5). There is also a local temperature rise at the position of the other end (the left end of the width L _{EEBR in} the figure). As a result, the temperature rise is dispersed, and the local temperature rise at the arrow WS can be mitigated. Here, since the configuration of the active area AR1 is the same as that of the IGBT 900A, no adverse effect on the on-voltage is observed. As described above, the IGBT 900C has both a low on-voltage and a high blocking capability.

(About IGBT900D)
Referring to FIG. 6, IGBT 900D has the characteristics of each of IGBT 900B and 900C described above. Specifically, the p collector layer 3 is provided only in the active area AR1 as in the IGBT 900B. Similarly to the _{IGBT 900C} , a ballast resistor region having a width L _EEBR is provided. Configurations other than these are substantially the same as those of the above-described IGBT 900B or 900C. According to the IGBT 900D, both the low on-voltage and the high blocking ability can be obtained by the action of each of the above-described IGBTs 900B and 900C.

(Verification of the effect of IGBT900C)
FIG. 7 is a circuit diagram used for the simulation of the turn-off operation of the 4500 V class IGBT. FIG. 8 shows the turn-off waveform obtained using the circuit of FIG. 7, that is, the relationship between time t and collector-emitter voltage V _CE . FIG. 9 shows the IGBT 900A (broken line) as a comparative example and the IGBT 900C (solid line) as an example with L _EEBR = 200 μm immediately before the collector current density J _C rapidly decreases (at the time indicated by the arrow in FIG. 8). ) Shows the temperature distribution at the coordinate X along the line DD ′ (FIGS. 4 and 5). FIG. 10 shows the relationship between the peak temperature T _max inside the device and L _EEBR .

From the result of the simulation, voltage sharing is performed in the ballast resistance region, so that the peak temperature T _max inside the device can be suppressed. In particular, by _setting L _EEBR to 100 μm or more, T _{max is set} to 800 _K or less. I was able to. As described above, it has been found that by providing the ballast resistance region, it is possible to prevent destruction due to heat generation, in other words, the IGBT's ability to cut off is enhanced.

(Verification of effects of IGBT 900B and 900D)
FIG. 11 shows examples of turn-off waveforms of IGBT 900A (broken line) as a comparative example and IGBT 900D (solid line) as an example. FIG. 12A shows the current potential and the hole concentration in the on state of the comparative example (t _{ON in} FIG. 11) in the field of view of FIG. 12B shows the current potential and the hole concentration at the peak of the collector-emitter voltage V _CE during the turn-off of the comparative example (t _peak of the broken line in FIG. 11) in the field of view of FIG. FIG. 13A shows the current potential and hole concentration in the on state of the example (t _{ON in} FIG. 11) in the field of view of FIG. 13B shows the current potential and the hole concentration at the peak of the collector-emitter voltage V _CE during the turn-off of the embodiment (solid line t _{peak in} FIG. 11) in the field of view of FIG. Each of FIG. 14A and FIG. 14B shows the carrier concentration inside the device at t = t _ON (FIG. 11) of the comparative example and the example. Each of FIG. 15A and FIG. 15B shows the carrier concentration inside the device at t = t _peak (FIG. 11) of the comparative example and the example. Each of FIG. 16A and FIG. 16B shows the carrier concentration inside the device at t = t _tail (FIG. 11) of the comparative example and the example. Each of FIG. 17A and FIG. 17B shows the electric field strength inside the device at t = t _ON (FIG. 11) of the comparative example and the example. Each of FIG. 18A and FIG. 18B shows the electric field strength inside the device at t = t _peak (FIG. 11) of the comparative example and the example. Each of FIG. 19A and FIG. 19B shows the electric field strength inside the device at t = t _tail (FIG. 11) of the comparative example and the example.

  From FIGS. 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, and 16B, the carrier concentration of the IGBT 900D (structure D) of the example is compared in the active area AR1. Although it is similar to the IGBT 900A in the example, it is lower in the edge termination area AR3. This is considered because hole injection from the p collector layer 3 does not occur in the interface area AR2 and the edge termination area AR3. This effect is also considered to be the same in the IGBT 900B (structure B) having the same collector structure as the IGBT 900D.

  Also, the above action promotes electric field relaxation and depletion in the interface area AR2 and the edge termination area AR3 during the turn-off operation, as shown in FIGS. 17A, 17B, 18A, 18B, 19A, and 19B. With particular reference to FIGS. 19A and 19B, the electric field relaxation at the boundary between the interface area AR2 and the edge termination area AR3 on the upper surface S1 contributes to the improvement of the blocking capability.

Referring to FIG. 20, in order to achieve an appropriate balance between a high blocking capability and a low on-voltage, it is necessary that an area ratio λ of p collector layer 3 on lower surface S2 of substrate SB is appropriate. In the figure, λ = 100% corresponds to the collector structure of the IGBT 900A of the comparative example. From the results shown in the figure, λ is preferably 55% or more and 70% or less. By setting the λ value to 55 to 70%, both the high turn-off maximum cutoff current density J _C (break) can be realized without adversely increasing the on-voltage V _CE (sat).

The result of λ = 75% in the graph corresponds to a structure in which the p collector layer 3 is provided in the active area AR1 and the interface area AR2 but not in the edge termination area AR3. When λ increased to 75%, a significant decrease in the maximum cutoff current density J _C (break) at turn-off was observed. From this, it was found that not providing the p collector layer 3 in the interface area AR2 is important for increasing J _C (break).

FIG. 21 shows the dose amount of ion implantation for forming the p collector layer 3 and the maximum cutoff current density J _C (break) at the turn-off in the IGBT 900A (broken line) as a comparative example and the IGBT 900D (solid line) as an example. An example of the relationship is shown. FIG. 22 shows the relationship between the power supply voltage V _CC , the saturation current density J _C (sat), and the maximum power density P _max as RBSOA of the comparative example (broken line) and the example (solid line). An area surrounded by each line in FIG. 22 is an area called a recovery safe operating area (SOA). The efficiency of hole injection from the p collector layer 3 affects the blocking capability at the time of turn-off of the IGBT. The dose amount of the p collector layer 3 is a parameter for controlling a trade-off characteristic between the on-voltage V _CE (sat) and the turn-off loss E _OFF in the IGBT. Even when the dose amount of the p collector layer 3 is adjusted for the control of the trade-off characteristics between V _CE (sat) and E _OFF , the example ( The solid line) can secure a higher J _C (break), and the dose dependency of the p collector layer 3 with respect to J _c (break) is small, which is an excellent IGBT. In addition, as shown in FIG. 22, the embodiment expands RBSOA and improves the power density to be cut off at the time of turn-off, and exhibits an excellent effect.

Table 1 below summarizes the relationship between the structural characteristics of the IGBTs 900A to 900D (structures A to D) and the turn-off maximum breaking current density J _C (break) with reference to the rated current density Jc (rated).

As described above, the structures B to D (IGBT 900B to 900D) have a high J _C (break), that is, a high turn-off cutoff capability as compared with the structure A (IGBT 900A), and the structure D (IGBT 900D) is particularly prominent. Has high ability.

FIG. 23 shows a configuration of an IGBT 900Z as another comparative example. The IGBT 900Z has a planar gate electrode 11 unlike the IGBTs 900A to 900D described above. FIG. 24 shows the trade-off characteristics between the on-voltage V _CE (sat) and the turn-off loss E _{OFF in} the IGBT 900D (solid line) as an example, the IGBT 900A (broken line), and the IGBT 900Z (one-dot chain line) as comparative examples. . From this result, the IGBT 900D has an excellent trade-off characteristic between the on-voltage V _CE (sat) and the turn-off loss E _OFF while having a high turn-off cutoff capability as described in FIG. 21 and Table 1. I understand that.

(About IGBT900E and 900F)
Referring to FIG. 25, in IGBT 900E which is a modified example of IGBT 900D (FIG. 6), n buffer layer 2 is provided only in active area AR1, and is not provided in interface area AR2 and edge termination area AR3. The pattern of the n buffer layer 2 may be the same as the pattern of the p collector layer 3. Such a structure may be combined with IGBT 900B instead of IGBT 900D.

  Referring to FIG. 26, in IGBT 900F which is a modified example of IGBT 900B (FIG. 2), active area AR1 has a MIS structure portion in which a MIS (Metal Semiconductor Semiconductor) structure cell is arranged (left and right portions in the figure). And a non-MIS structure portion (central portion in the figure) where no MIS structure cell is arranged. In the drawing, the central portion is a portion AR1g provided with the gate wiring portion 28 and the gate pad 29 (FIG. 1) in the active area AR1. The portion AR1g is not provided with the p collector layer 3, and as a result, the buffer layer 2 and the collector electrode 4 are in contact with each other at the lower surface S2. The MIS structure is typically a MOS (Metal Oxide Semiconductor) structure. Such a structure also exhibits the same effect as that of the IGBT 900D.

<Embodiment 2>
With reference to FIG. 27, a structure (referred to as structure G) included in IGBT 900G of the present embodiment will be described.

In structure G, substrate SB includes n ⁻ drift layer 1, n buffer layer 2, p collector layer 3, n ⁺ emitter layer 5, p ⁺ layer 6, p base layer 8, n layer 24, and a field limiting ring 9 g ^- and p-well regions 9a, p ^- the extension region 9j, multiple by p. The p well region 9a is covered with the interlayer insulating film 12b in the interface area AR2.

The p ⁻ extension region 9 j extends outward from the p well region 9 a (right side in the drawing) on the upper surface S 1 and is shallower than the p well region 9 a. The p ⁻ extension region 9j has a p-type and has a lower peak impurity concentration and surface impurity concentration than the p well.

Still referring to FIG. 28, p ^- field limiting ring 9g has p-type. The p ⁻ field limiting ring 9g is provided on the upper surface S1 outside the p ⁻ extension region 9j in the edge termination area AR3. On the upper surface S1, an n ⁻ drift layer 1 is positioned inside each of the p ⁻ field limiting rings 9g, and each of the p ⁻ field limiting rings 9g includes a unit structure US1 together with the n ⁻ drift layer 1 positioned inside. ~ US6 (collectively referred to as US). The width W _cellpitch of the unit structure US is a constant value. p ^- field (right side in the figure) limiting ring 9g more outer small proportions with respect to the width W _Cellpitch unit structure US on as the upper surface S1 things, p ^- the width of the field limiting ring 9g W _p- Have The unit structure US has a smaller average dose amount on the outer side. Here, the average dose amount of the unit structure US is obtained by dividing the number of ions implanted for forming the p ^- field limiting ring 9g of the specific unit structure US by the area of the unit structure US on the upper surface S1. It is a numerical value. In other words, the average dose amount of the unit structure US is a dose amount from a more macroscopic viewpoint ignoring the internal structure of the unit structure US.

In the structure illustrated in FIG. 28, each of the unit structures US has a certain width W _cellpitch on the upper surface S1 of the substrate SB. The p ⁻ field limiting ring 9g has a smaller width W _p− on the upper surface S1 on the outer side (right side in the figure). In order to obtain such a unit structure US, for example, in an ion implantation step for forming the field limiting ring 9g, an ion implantation mask in which a plurality of openings having smaller widths are provided at a constant pitch toward the outer side. May be used. It should be noted that the final depth after activation annealing, that is, after diffusion, becomes smaller as the field limiting ring 9g in which ion implantation is performed with a narrower width. In FIG. 28, the p ⁻ field limiting rings 9g are shown to exist individually, but 1/3 to 1/2 of the plurality of p ⁻ field limiting rings 9g originally formed as impurity regions. The degree is linked to the p ⁻ extension region 9j due to the activation annealing.

Preferably, the width W _p− decreases toward the outside by a certain dimension for each unit structure US. In this case, under the condition that the width W _{cellpitch is} constant, the average dose of the unit structure US changes linearly for each unit structure US toward the outside. From a macroscopic viewpoint ignoring the internal structure of the unit structure US, as shown in FIG. 29, a pseudo p ^- well 9p is provided in which the impurity concentration decreases in a constant concentration gradient in the arrow direction in the figure. Will be. In this configuration, on the upper surface S1, the impurity concentration in the p ⁻ extended region 9j (FIG. 27) is substantially constant, whereas in the pseudo p ⁻ well 9p located on the outer side, the impurity concentration is increased outward. Becomes linearly smaller.

  Since the configuration other than the above is substantially the same as the configuration of IGBT 900D of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

According to the present embodiment, the unit structure US constituted by the p ⁻ field limiting ring 9g provided in the edge termination area AR3 has a smaller average dose amount toward the outer side. With this configuration, the electric field strength in the interface area AR2 can be sufficiently suppressed even in the edge termination area AR3 that is smaller than that in which the average dose is not controlled as described above. Therefore, the temperature rise at the boundary between the active area AR1 and the interface area AR2 can be suppressed without sacrificing the area of the active area AR1. That is, it can have both a low on-voltage and a high shut-off capability. In particular, when each of the unit structures US has a certain width W _cellpitch , it is possible to more reliably obtain both a low on-voltage and a high cutoff capability.

  Next, the verification results of the above-described effects will be described below.

30A shows turn-off waveforms of the collector-emitter voltage V _CE and the collector current density J _C in the IGBT 900A (FIG. 4) as a comparative example (broken line) and the IGBT 900G (FIG. 27) as an example (solid line). The simulation results are shown. FIG. 30B is a graph showing the simulation results of the peak temperature inside the device in these comparative examples (broken line) and examples (solid line). “X” in FIG. 30A and FIG. 30B means destruction of the device. FIG. 31A and FIG. 31B show more detailed simulation results regarding the internal state of the device at the time indicated by the arrows in FIG. 30A. FIG. 31A shows the temperature inside the device in the comparative example and the example. FIG. 31B shows the impact ionization rate inside the device in the comparative example and the example. In FIG. 31A and FIG. 31B, a broken line portion indicated by an arrow corresponds to the interface area AR2. From this simulation result, the local temperature rise in the interface area AR2 is smaller in the example than in the comparative example. Therefore, it is considered that the example has a smaller device internal temperature rise at the time of the IGBT turn-off operation, and has a higher blocking ability.

FIG. 32A shows the relationship between the position X and the electric field strength E _{edge on} the upper surface of the substrate in each of the dynamic state (solid line) and the static state (broken line) in the IGBT 900A (FIG. 4) as a comparative example. . FIG. 32B shows the relationship between the position X and the electric field intensity E _{edge on} the upper surface of the substrate in each of the dynamic state (solid line) and the static state (broken line) in the IGBT 900G (FIG. 27) as an example. . Here, as the conditions of the static state, collector-emitter voltage V _CES = 3600 V, gate voltage V _G = 0 V, and temperature T = 423 K were used. As the dynamic state, a state indicated by an arrow in FIG. 30A was used. From this result, the field intensity E _{edge of} the IGBT 900G is smaller in the vicinity of the boundary between the interface area AR2 and the edge termination area AR3 than in the IGBT 900A, not only in the static state but also in the dynamic state. Thus, in IGBT900G, it is thought that a local temperature rise is suppressed (FIG. 31A) by suppressing an impact ionization by suppressing electric field strength from IGBT900A (FIG. 31B).

  As described above, according to the present embodiment, the turn-off cutoff capability can be increased. In addition, since the configuration of the active area AR1 can be the same as that of the IGBT 900A (FIG. 4) of the comparative example, there is no particular adverse effect on other characteristics. Therefore, also in the present embodiment, various characteristics similar to those of the above-described IGBT 900D (FIG. 6) can be ensured.

  Further, according to the present embodiment, the width of the edge termination area AR3 can be reduced. In the estimation by simulation, the width dimension can be reduced by about 40 to 50%. This will be described below.

FIG. 33 shows an IGBT 900A (FIG. 4) as a comparative example (broken line) and an IGBT 900G (FIG. 27) as an example (solid line) under the collector-emitter voltage V _CES = 4500V and the temperature T = 298K. The relationship between the position X _edge along the line FF ′ and the electric field intensity E is shown. From this result, when the same collector-emitter voltage V _CES is maintained, the embodiment requires the position X _edge while suppressing the electric field strength E more than the comparative example (see the downward arrow in the figure). Dimensions are suppressed (see left arrow in the figure).

FIG. 34 is a graph showing the relationship between the breakdown voltage class V _class and the required width W _edge of the edge termination area AR3 in the comparative example (broken line) and the example (solid line). Compared with the comparative example, the embodiment can reduce the required width W _edge of the edge termination area AR3 by 40 to 50% regardless of the withstand voltage class V _class . That is, with the device structure of FIG. 27 of the present embodiment, the chip size shrink that reduces the chip sizes X _n and Y _n of the semiconductor device shown in FIG. 3 without changing the size of the active area AR1 in the semiconductor device. The effect is expected. That is, according to this embodiment, the number of semiconductor devices (theoretical number of chips) per wafer on which a semiconductor device is formed can be increased, and the chip cost can be reduced.

Next, a modified example will be described. Referring to FIG. 35, IGBT 900H has floating electrode 13e on each of p ⁻ field limiting rings 9g with interlayer insulating films 12a and 12b interposed. Each of floating electrodes 13e is arranged inside p ^- field limiting ring 9g directly below via interlayer insulating films 12a and 12b in the width direction (lateral direction in FIG. 35). Referring to FIG. 36A, in IGBT900I, gate connection electrode 13b (see FIG. 27), p ^- via an interlayer insulating film 12a and 12b to cover the extension area 9j, p ^- extends to an extension region 9j . However, in the width direction (lateral direction in the figure), the gate connection electrode 13b is formed so as to be located inside the p ⁻ extension region 9j, and the floating electrode 13e is located inside the p ⁻ field limiting ring 9g as described above. It is formed so that it may be located in. Referring to FIG. 36B, IGBT 900J has a structure in which floating electrode 13e is omitted from IGBT 900I (FIG. 36A). With these structures, the characteristic electric field strength distribution of the edge termination area AR3 by the IGBT 900G in FIGS. 32B and 33 can be changed over time even when an electrical stress is applied in an operating temperature range that ensures the performance of the IGBT. Therefore, higher pressure resistance and higher shut-off capability can be obtained after stabilization.

<Embodiment 3>
In this embodiment, a diode having the same configuration as that of the ballast resistor region described in Embodiment 1 (FIG. 5: a portion having the width L _EEBR of the p-well region 9a in the _{IGBT 900C} ) will be described. In addition, about the structure similar to IGBT900C, description is not repeated partially.

  Referring to FIG. 37, diode 800A (power semiconductor device) of the present embodiment is similar to IGBT shown in FIG. 11, and includes active area AR1, interface area AR2 provided on the outer periphery of active area, and interface. And an edge termination area AR3 provided on the outer periphery of the area AR2. The active area AR1 is a part that bears the basic function of the diode in the present embodiment.

The diode 800A includes a substrate SB (semiconductor substrate), an anode electrode 13 (first electrode), a cathode electrode 4D (second electrode), and an interlayer insulating film 12. Substrate SB includes n ⁻ drift layer 1 (drift region), n buffer layer 2, anode layer 8D, p guard ring 9, p layer 26, n ⁺ layer 27, and n ⁺ region 35. . The anode electrode 13 is provided in the active area AR1, and is in contact with the anode layer 8D on the upper surface S1 of the substrate SB. The anode layer 8D is provided on the n ⁻ drift layer 1. Cathode electrode 4D is in contact with the semiconductor layer formed of p layer 26 and n ⁺ layer 27 on lower surface S2 of substrate SB. The n ⁺ layer 27 is provided only in the active area AR1. The n buffer layer 2 is provided between the semiconductor layer and the n ⁻ drift layer 1. The interlayer insulating film 12 has an opening in the active area AR1.

The anode layer 8D has a depth of about 0.5 to 10 μm, for example. Anode layer 8D has a p-type and has a peak impurity concentration of, for example, about 1 × 10 ¹⁶ to 1 × 10 ²⁰ cm ⁻³ . The p guard ring 9 has a depth of about 5 to 10 μm, for example. The p guard ring 9 has a peak impurity concentration of about 1 × 10 ¹⁶ to 1 × 10 ²⁰ cm ^−3, for example. For example, n ⁺ region 35 has a depth of about 0.2 to 1 μm. N ⁺ region 35 has an n-type, and has a peak impurity concentration of, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . The p layer 26 has a depth of about 0.3 to 5 μm, for example. The p layer 26 has a surface impurity concentration of, for example, about 1 × 10 ¹⁶ to 1 × 10 ²⁰ cm ⁻³ . For example, n ⁺ layer 27 has a depth of about 0.3 to 5 μm. For example, n ⁺ layer 27 has a surface impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ .

In the diode 800A, the p-well region 9a forms an electrical path connecting the anode electrode 13 and the end of the p-well region 9a (the right end in the figure) with a p-type region on the upper surface S1. This electrical path traverses the interface area AR2 between the active area AR1 and the edge termination area AR3 and has a resistive region having a width L _ABR . The entire resistance region is covered with the interlayer insulating film 12. The p well region 9a has a width _Wp0 . The boundary between the interface area AR2 and the edge termination area AR3 and the outer peripheral edge of the n ⁺ layer 27 have an interval of the width _WGR .

The widths L _ABR , W _p0 and W _GR are important parameters in designing the diode 800A. The width L _ABR is determined so as to obtain a ballast resistance effect that suppresses a local temperature increase at one of both ends by sharing the temperature increase at both ends of the resistance region during the diode recovery operation. Specifically, the local temperature rise is suppressed by sharing the temperature rise due to local current concentration at the arrow WS shown in FIG. From this viewpoint, the width L _ABR is specifically set to 100 μm or more.

  The diode 800Z (FIG. 38) of the comparative example is not provided with the above-described ballast resistance region. FIG. 38 schematically shows one p-edge region 9b, but there are a plurality of p-edge regions 9b similar to FIG. In the recovery operation, the diode 800Z is likely to cause a local temperature rise at the boundary between the active area AR1 and the interface area AR2 on the upper surface S1 of the substrate SB, that is, the arrow WS. This phenomenon limits the blocking capability of the diode 800Z.

  On the other hand, according to the present embodiment, during the recovery operation of the diode, as shown in FIG. 40A described later, the current is distributed in the ballast resistance region corresponding to the boundary position between the interface area AR2 and the edge termination area AR3. The local temperature rise due to current concentration at the boundary between the interface area AR2 and the edge termination area AR3 is suppressed. Here, since the configuration of the active area AR1 can be the same as that of a conventional diode, there is no adverse effect such as an increase in on-voltage. As described above, like the IGBT 900C, the diode 800A also has both a low on-voltage and a high blocking capability.

  Next, the verification results of the above-described effects will be described below.

Figure 39, for each of the diodes 800Z as diodes 800A and Comparative Examples as Example (solid line) (broken line), and the waveform of the voltage V _AK and current density J _A of the recovery operation, and the peak temperature T inside the device Indicates. 40A shows the position X along the line GG ′ (FIGS. 37 and 38) and the current density J at time t _d (FIG. 39) for each of the example (solid line) and the comparative example (broken line). shows the relationship between _a, Figure 40B shows the relationship between the position X and temperature T. In Comparative Example provided with no ballast resistance region (dashed line), at the end of the interface area AR2 is located near the boundary of the interface area AR2 and the edge termination area AR3, concentration occurs in the current density J _A, also the temperature T A local rise occurs. As a result, as shown in FIG. 39, the diode 800Z cannot complete the shut-off operation and is destroyed. On the other hand, in the diode 800A, the current density J _A is dispersed without extreme concentration in the interface area AR2, and there is no portion where the temperature rise of 800K or more, which is a standard for device destruction, occurs. The diode 800A performs a cut-off operation without being destroyed by the ballast resistor region sharing current. Therefore, the cutoff capability of the diode of the embodiment is improved.

41, 42A, and 42B show the relationship between the widths L _ABR and W _p0 (FIG. 37) of the diode 800A and the temperature and current density inside the device at time t _d (FIG. 39). From this result, it is necessary to _satisfy L _ABR <W _p0 in order to suppress the concentration of current density and local temperature rise in order to improve the cutoff capability of the diode.

FIG. 43 shows the ratio γ of the area S _abr of the ballast resistance region to the area S _{active cell} (that is, the area of the anode electrode 13) of the active area AR1 (FIG. 37) and the maximum breaking current density J _A (break) during the recovery operation. And the relationship with device internal maximum temperature _Tmax is shown. In the example of FIG. 37, as shown in FIG. 44, the area _Sabr is substantially the same as the area of the interface area AR2. J _A (break) is an experimental result with an actual device, and T _max is a simulation result. When γ having T _max of 800K or less is selected by simulation (in the figure, safety region SZ), an actual device having a high J _A (break) is obtained. Specifically, it can be seen that a high J _A (break) is obtained when γ is 2% or more and 40% or less.

Referring to FIG. 37, it is preferable that width W _GR is larger than width W _p0 . To summarize the discussion of various parameters, it is necessary to satisfy the following relationship in order to increase the cutoff capability of the diode 800A.

L _ABR <W _p0
2% ≤ γ ≤ 40%
W _GR > W _p0

<Embodiment 4>
In the present embodiment, a diode having the same structure as the unit structure US included in the IGBT 900G (FIG. 28) described in the second embodiment will be described. A description of the same configuration as that of IGBT 900G or the above-described diode 800A (FIG. 37) will not be repeated.

Referring to FIG. 45A, diode 800B of the present embodiment has interlayer insulating films 12a and 12b on upper surface S1 of substrate SB in interface area AR2 and edge termination area AR3. The substrate SB includes a p-type anode layer 8D (impurity layer) provided on the upper surface S1. Substrate SB has p ⁻ extension region 9j and a plurality of p ⁻ field limiting rings 9g on upper surface S1 in edge termination area AR3. Similar to the third embodiment, n ⁻ drift layer 1 is positioned inside each of p ⁻ field limiting rings 9g on upper surface S1, and each of p ⁻ field limiting rings 9g is n positioned inside. ^The unit structure US (FIG. 28) is formed together with the drift layer 1. 45B to 45D respectively show modified diodes 800C to 800E. The diode 800C (FIG. 45B) has the floating electrode 13e similarly to the IGBT 900H (FIG. 35). In diode 800D (FIG. 45C), anode electrode 13 extends onto p ⁻ extension region 9j through interlayer insulating films 12a and 12b, similarly to gate connection electrode 13b of IGBT 900I (FIG. 36A). The diode 800E (FIG. 45D) has a structure in which the floating electrode 13e is omitted from the diode 800D (FIG. 45C).

Figure 46A is a diode 800B as an embodiment (solid line), for each of the diodes 800Z as a comparative example (broken line) (Fig. 38) shows the waveform of the voltage V _AK and current density J _A of the recovery operation, FIG. 46B shows the peak temperature T inside the device during the recovery operation. In the comparative example, a rapid decrease in V _AK and a rapid temperature increase to T> 800 K occur at t = 5.5 μs. That is, the diode is broken during the recovery operation. On the other hand, in the embodiment, the blocking is completed without destruction.

Each of FIGS. 47A to 47D shows the relationship between the position X and the surface electric field intensity E _{surface on} the line HH ′ (FIG. 38) of the comparative example at t = t ₁ to t ₄ (FIGS. 46A and 46B). . Each of FIGS. 48A to 48F shows the relationship between the position X and the surface electric field intensity E _{surface on} the line HH ′ (FIG. 45A) of the embodiment at t = t ₁ to t ₆ (FIGS. 46A and 46B). . 49A to 49D respectively show the relationship between the position X and the current density j _{surface on} the line HH ′ of the comparative example at t = t ₁ to t ₄ . Each of FIGS. 50A to 50F shows the relationship between the position X and the current density j _{surface on} the line HH ′ in the example at t = t ₁ to t ₆ . Each of FIG. 51A to FIG. 51D shows the relationship between the position X on the line HH ′ of the comparative example and the temperature T _surface of the device upper surface S1 at t = t ₁ to t ₄ . Each of FIGS. 52A to 52F shows the relationship between the position X on the line HH ′ of the example and the temperature T _surface of the device upper surface S1 at t = t ₁ to t ₆ .

  From these results, compared with the comparative example, in the embodiment, the electric field strength of the interface area AR2 and the edge termination area AR3, particularly the interface area AR2, is low during the recovery operation, and the temperature rise of the interface area AR2 is suppressed. It was. Therefore, it is considered that the diode 800B has a high blocking ability like the IGBT 900G. As a result, the effect of expanding the SOA can be obtained.

FIG. 53 is a graph for explaining the recovery SOA in the comparative example (indicated by a triangle) and the example (indicated by a circle). Here, (dj / dt) _max is the maximum value of time differentiation of current density allowed at the time of interruption, and _Pmax is the maximum power density. The dj / dt value is, for example, the slope of the current density waveform in the region as shown in FIG. 46A. The larger this value, the faster the diode can perform the recovery operation (that is, the cutoff capability of the diode during the recovery operation). Is great). From this result, according to the embodiment, the recovery SOA is improved because a high-speed recovery operation is possible with a dj / dt value that is about three times larger than the conventional example, and the power density can be cut off by 50 times or more. I understand that

  The power semiconductor device of each of the above embodiments is particularly suitable for a high breakdown voltage class of about 3300 to 6500V, but the magnitude of the breakdown voltage of the power semiconductor device is not particularly limited. It may be. The material of the semiconductor substrate is not limited to silicon, and may be a wide band gap material such as silicon carbide (SiC) or gallium nitride (GaN). The n-type and p-type as the first and second conductivity types of the semiconductor substrate may be interchanged.

  In the present invention, the embodiments can be appropriately modified and omitted within the scope of the invention. Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.

1 n ⁻ drift layer (drift region), 2 n buffer layer (buffer layer), 3 p collector layer (collector region), 4 collector electrode (second electrode), 4D cathode electrode (second electrode), 5 n ⁺ emitter layer, 6 p ⁺ layer, 8 p base layer, 8D anode layer (impurity layer), 9 p guard ring, 9a p-well region, 9b p edge region, 9 g p ^- field limiting rings, 9j p ^- extending region DESCRIPTION OF SYMBOLS 10 Trench insulating film, 11 Gate electrode, 12, 12a, 12b Interlayer insulating film, 13 Anode electrode (1st electrode), 13a Emitter electrode (1st electrode), 13b Gate connection electrode, 13c, 13d Electrode, 13e Floating electrode, 14, 15 Passivation film, 22 Gate electrode, 22w Gate wiring layer, 23 Capacitor electrode, 24 n layer, 26 p layer, 2 n ⁺ layer, 28 a gate wiring portion 29 a gate pad, 32 channel stop electrode, 34 n region, 35 n ⁺ region, 38 p region, 800A, 800B diode, 900A~900I IGBT, AR1 active area, AR2 interface area, AR3 Edge termination area, CS channel stop structure, S1 upper surface (first surface), S2 lower surface (second surface), SB substrate (semiconductor substrate), TC capacitor trench, TG gate trench, TS channel stop trench, US, US1 ~ US6 Unit structure.

Claims (9)

A power semiconductor device including an active area, an interface area provided on an outer periphery of the active area, and an edge termination area provided on an outer periphery of the interface area,
A semiconductor substrate having a first surface and a second surface opposite to the first surface, wherein each of the first and second surfaces includes an active area, an interface area, and an edge termination area; The semiconductor substrate is straddling
A drift region having a first conductivity type provided across the active area, the interface area, and the edge termination area;
The first surface is provided at least partially in the interface area and has an end portion between the interface area and the edge termination area on the first surface, and is different from the first conductivity type. A first well region having two conductivity types;
The power semiconductor device is further provided in the active area, has an end between the active area and the interface area, and is in contact with the first surface of the semiconductor substrate When,
A second electrode in contact with the second surface of the semiconductor substrate;
A gate wiring portion provided on the first surface of the semiconductor substrate in the active area via an insulating film;
The semiconductor substrate is further provided only in the active area, partially forming the second surface, and having a collector region having the second conductivity type,
A second well region of the second conductivity type in contact with the insulating film below the gate wiring portion and partially forming the first surface;
With
The power semiconductor device, wherein the collector region is not provided on the second surface of the portion facing the gate wiring portion.   2. The power semiconductor device according to claim 1, wherein the collector region is not provided in the second surface of the interface area and the edge termination area. A buffer layer of a first conductivity type in contact with the drift region on the second surface side and having a first conductivity type impurity concentration higher than that of the drift region;
3. The power semiconductor device according to claim 1, wherein the buffer layer forms the second surface in the interface area and the edge termination area.   4. The power semiconductor device according to claim 1, wherein the collector region has an area of 55% or more and 70% or less on the second surface of the semiconductor substrate. 5.   The first well region is connected to the first electrode only in the active area, and a region of the second conductivity type is formed between the first electrode and the end portion of the first well region. 5. The power semiconductor device according to claim 1, further comprising a ballast resistance region connected by 6. The power semiconductor device according to claim 5, wherein the ballast resistor region has a width of 100 μm or more between the first electrode and the end portion of the first well region. In the active area, the first surface of the semiconductor substrate has an area S _act , and in the interface area, the ballast resistor region has an area _Sabr in the first surface of the semiconductor substrate, and an area _Sabr The semiconductor device for electric power according to claim 5 or 6, wherein is 2% or more and 40% or less of the area _Sact . The semiconductor substrate further includes a plurality of field limiting rings having the second conductivity type in the edge termination area of the first surface;
The drift region is positioned inside each of the field limiting rings on the first surface, and each of the field limiting rings constitutes a unit structure together with the drift region positioned inside, 8. The power semiconductor device according to claim 1, wherein the unit structure has a smaller average dose amount toward the outer side. 9.   The power semiconductor device according to claim 8, further comprising a floating electrode provided on the field limiting ring.