JP6598614B2 - Printed circuit board and semiconductor package - Google Patents

Description

  The present invention relates to a printed circuit board in which a semiconductor package is mounted on a printed wiring board, and a semiconductor package mounted on the printed wiring board.

  The semiconductor package has a semiconductor integrated circuit as a semiconductor element and a package substrate on which the semiconductor integrated circuit is mounted, and operates by being mounted on a printed wiring board. A power supply circuit that supplies a DC voltage necessary for operation to the semiconductor package is mounted on the printed wiring board, and the DC voltage is supplied from the power supply circuit to the semiconductor package through the power supply line of the printed wiring board. When a semiconductor integrated circuit operates, a current due to the operation of the semiconductor integrated circuit flows through the power supply path of the semiconductor integrated circuit, the package substrate, and the printed wiring board, and a power source determined by the product of the power supply impedance of the power supply path and the current flowing through the power supply path Potential fluctuation occurs.

  In general, high power supply impedance peaks called anti-resonance occur at various frequencies in the power feeding path. When the frequency at which anti-resonance occurs coincides with the operating frequency of the semiconductor integrated circuit, the power supply potential fluctuation increases. If the power supply potential fluctuation is large at the operating frequency of the semiconductor integrated circuit, there is a concern about malfunction of the semiconductor integrated circuit such as signal delay in communication with another semiconductor package. Therefore, to prevent malfunction of the semiconductor integrated circuit, it is important to reduce the antiresonance peak value.

  On the other hand, in Patent Document 1, by adding a resistance element in series with the internal capacitance of the semiconductor integrated circuit, the resistance component in the parallel circuit of the internal capacitance of the semiconductor integrated circuit and the external inductance is increased, resulting in an anti-resonance peak. The value is reduced.

JP 2008-251571 A

However, in Patent Document 1 described above, a resistance element exists in series with the internal capacitance of the semiconductor integrated circuit in the power supply path. Here, assuming that the power supply impedance of the power supply path including the internal capacitance of the semiconductor integrated circuit is Z, the internal capacitance is C _die , and the resistance value of the installed resistance element is Rdie, the power supply impedance Z is expressed as 1).

  That is, the power source impedance Z is approximated by (Equation 1) because the current due to the operation of the semiconductor integrated circuit flows in a loop near the semiconductor integrated circuit in the higher frequency band, and the resistance value Rdie is higher at a frequency higher than the antiresonance frequency. The impedance rises for a minute. Therefore, if an attempt is made to suppress an increase in the power supply impedance Z in a high frequency band, there is a problem that the effect of reducing the power supply impedance in a frequency band where anti-resonance occurs is reduced.

  Therefore, an object of the present invention is to reduce power supply impedance in a frequency band where anti-resonance occurs while suppressing an increase in power supply impedance in a frequency band higher than the frequency where anti-resonance occurs.

The printed circuit board of the present invention includes a first semiconductor element capable of transmitting a plurality of digital signals simultaneously, a second semiconductor element capable of receiving the plurality of digital signals , the first semiconductor element, and the second semiconductor element. A ground line, a main power line, a first power line branched from the main power line and connected to a power terminal of the first semiconductor element, and the first power line or the main power line A substrate group formed with a second power supply line branched from the connection portion and connected to a power supply terminal of the second semiconductor element; and mounted on the substrate group; the first power supply line and the ground line; a first capacitor connected between the, is mounted on the substrate group, and a second capacitor connected between said ground line and said second power supply line, is mounted on the substrate group, the connecting portion Arranged, the second power supply A resistance element of higher resistance than is mounted on the board group, which is connected to the main power line, comprising: a power supply circuit for generating a DC voltage, wherein the first semiconductor element, the resistive element by said power supply circuit the basic power line and the DC voltage through the first power supply line and said Rukoto applied not through.

According to the present invention, in a frequency band where anti-resonance occurs, a resistance element is added to the parallel circuit including the first and second capacitors and the parasitic inductances of the first power supply line, the second power supply line, and the main power supply line. It will be. Even if the resistance element has an electrical resistance value higher than the electrical resistance value of the second power supply line, the resistance element does not contribute to an increase in resistance in series with the internal capacitance of the first or second semiconductor element. Accordingly, it is possible to effectively reduce the anti-resonance peak in the power supply impedance while suppressing an increase in the power supply impedance in a frequency band higher than the frequency at which the anti-resonance occurs.

(A) is the schematic which shows the printed circuit board which concerns on 1st Embodiment. (B) is a top view which shows the printed wiring board in (a). It is an equivalent circuit diagram showing the power supply wiring structure of the printed circuit board according to the first embodiment. 6 is a graph showing frequency characteristics of power supply impedance viewed from the first semiconductor element side in the first embodiment, comparative example 1 and comparative example 2; (A) is the equivalent circuit schematic of the printed circuit board seen from the 1st semiconductor element side in the printed circuit board of the comparative example 3. FIG. (B) is a graph which shows the frequency characteristic of power supply impedance. (C) And (d) is an equivalent circuit diagram at the time of occurrence of anti-resonance. (A) is the equivalent circuit schematic of the printed circuit board seen from the 1st semiconductor element side in the printed circuit board of 1st Embodiment. (B) and (c) are equivalent circuit diagrams when anti-resonance occurs. (D) is a graph which shows the frequency characteristic of power supply impedance. It is a graph which shows the anti-resonance peak value reduction rate with respect to the electrical resistance value of a resistive element in 1st Embodiment. (A) is the schematic which shows the printed circuit board based on 2nd Embodiment. (B) is a top view which shows the printed wiring board in (a). It is an equivalent circuit diagram which shows the power supply wiring structure of the printed circuit board which concerns on 2nd Embodiment. It is a graph which shows the frequency characteristic of the power supply impedance seen from the 1st semiconductor element side in 2nd Embodiment, the comparative example 4, and the comparative example 5. FIG. It is a graph which shows the anti-resonance peak value reduction rate with respect to the electrical resistance value of a resistive element in 2nd Embodiment. (A) is the schematic which shows the printed circuit board which concerns on 3rd Embodiment. (B) is a top view which shows the printed wiring board in (a). (A) is the schematic which shows the printed circuit board based on 4th Embodiment. (B) is a top view which shows the printed wiring board in (a). It is the schematic which shows the printed circuit board which concerns on 5th Embodiment.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1A is a schematic diagram illustrating a printed circuit board according to the first embodiment. FIG.1 (b) is a top view which shows the printed wiring board in Fig.1 (a). The printed circuit board 100 includes a printed wiring board 200 and a semiconductor package 300 mounted on the printed wiring board 200. The printed circuit board 100 includes a bypass capacitor 205 that is a first capacitor and a bypass capacitor 206 that is a second capacitor. The printed circuit board 100 includes a resistance element (chip resistor) 207 which is a connection part and is a resistance component, and a power supply circuit 208. The power supply circuit 208 is a circuit that generates a DC voltage applied to the semiconductor element in order to supply power to the semiconductor element of the semiconductor package 300, and is mounted on the printed wiring board 200.

  The semiconductor package 300 is a PoP (Package on Package) type stacked semiconductor device, and includes a semiconductor device 301 that is a first semiconductor device and a semiconductor device 302 that is a second semiconductor device mounted on the semiconductor device 301. . The semiconductor devices 301 and 302 are, for example, BGA type or LGA type semiconductor packages.

  The semiconductor device 301 includes a package substrate 311 that is a first package substrate and a semiconductor integrated circuit 321 that is a first semiconductor element mounted on the package substrate 311. The semiconductor device 302 includes a package substrate 312 that is a second package substrate, and a semiconductor integrated circuit 322 that is a second semiconductor element mounted on the package substrate 312. The package substrate 311 is mounted (bonded) to the printed wiring board 200, and the package substrate 312 is mounted (bonded) to the package substrate 311.

  The package substrate group 350 is configured by including the plurality of package substrates 311 and 312, and the substrate group 400 is configured by including the package substrate group 350 and the printed wiring board 200.

  The semiconductor integrated circuit 321 is an ASIC or the like, and functions as a controller, for example, and transmits a signal (digital signal). The semiconductor integrated circuit 322 is a memory, for example, and receives a signal (digital signal) from the semiconductor integrated circuit 321. In the first embodiment, the semiconductor integrated circuit 321 has a plurality of signal transmission units, and the semiconductor integrated circuit 322 has a plurality of signal reception units. Each signal transmission unit of the semiconductor integrated circuit 321 is connected to each signal reception unit of the semiconductor integrated circuit 322 via a signal line (not shown) formed on the substrate group 400 (the package substrate group 350 in the first embodiment). Yes. As a result, the semiconductor integrated circuits 321 and 322 operate by applying a DC voltage from the power supply circuit 208, and exchange signals.

  The substrate group 400 includes a ground line 401, a main power line 402, a power line 410 that is a first power line, and a second power line that constitute a power supply path that supplies power from the power circuit 208 to the semiconductor integrated circuits 321 and 322. A power supply line 420 which is a power supply line is formed.

  The main power supply line 402 is connected to the power supply terminal 209 of the power supply circuit 208. The power supply line 410 branches from the main power supply line 402 and is connected to the power supply terminal 323 of the semiconductor integrated circuit 321. The power supply line 420 branches from the power supply line 410 via the resistance element 207 and is connected to the power supply terminal 324 of the semiconductor integrated circuit 322.

  The main power supply line 402 is formed on the printed wiring board 200 of the board group 400. The power supply line 410 is formed across the printed wiring board 200 and the package substrate 311 of the substrate group 400. The power supply line 420 is formed across the printed wiring board 200 of the board group 400 and the package boards 311 and 312. Therefore, the power supply line 410 includes a power supply line 411 on the printed wiring board 200 side and a power supply line 412 on the package board group 350 side. The power supply line 420 includes a power supply line 421 on the printed wiring board 200 side and a power supply line 422 on the package substrate group 350 side. The ground line 401 is formed on each of the substrates 200, 311, and 312 and is electrically connected to each other.

  The power supply line 411 on the printed wiring board 200 side and the power supply line 412 on the package substrate 311 side are connected by a package terminal (solder ball) 351 of the package substrate 311. The power supply line 421 on the printed wiring board 200 side and the power supply line 422 on the package substrate 311, 312 side are connected by a package terminal (solder ball) 351 of the package substrate 311. Note that the package substrate 312 side of the power supply line 422 and the package substrate 311 side of the power supply line 422 are connected by package terminals (solder balls) 352 of the package substrate 312. In the package substrate 311, the power supply line 412 and the power supply line 422 are physically separated.

  FIG. 1B shows the ground line 401 and part of the main power supply line 402, the power supply line 411 and the power supply line 421 formed on the printed wiring board 200.

  The bypass capacitor 205 is mounted on any one of the boards 400 (the printed wiring board 200 in the first embodiment), and between the power line 410 (the power line 411 in the first embodiment) and the ground line 401. It is connected. Specifically, of the pair of terminals of the bypass capacitor 205, one terminal is connected to the power line 411 and the other terminal is connected to the ground line 401.

  The bypass capacitor 206 is mounted on any of the boards 400 in the board group 400 (the printed wiring board 200 in the first embodiment), and between the power line 420 (the power line 421 in the first embodiment) and the ground line 401. It is connected. Specifically, of the pair of terminals of the bypass capacitor 206, one terminal is connected to the power supply line 421 and the other terminal is connected to the ground line 401.

  As shown in FIG. 1B, a plurality of connection pads 250 to which the package terminals 351 of the package substrate 311 are bonded are formed on the printed wiring board 200. The plurality of connection pads 250 include ground connection pads 251, power connection pads 252 and 253, and other signal connection pads 254. The connection pad 252 for power supply of the semiconductor integrated circuit 321, the connection pad 253 for power supply of the semiconductor integrated circuit 322, and the connection pad 251 for ground exist on four sides.

  The connection pad 252 for power supply is a part of the conductor pattern 416 constituting the power supply line 411 formed on the surface layer of the printed wiring board 200. The connection pad 253 for power supply is a part of the conductor pattern that forms the power supply line 421 formed on the surface layer of the printed wiring board 200. The ground connection pad 251 is a part of the conductor pattern constituting the ground line 401 formed on the surface layer of the printed wiring board 200.

  Here, the surface layer means a surface on which the semiconductor package 300 is mounted on the printed wiring board 200 and means an outermost wiring layer (a conductor layer on which a conductor pattern is arranged). The surface layer and the back layer are relative, and the surface layer is also referred to as one surface layer or the first surface layer, and the back layer opposite to the surface layer is also referred to as the other surface layer or the second surface layer. Further, the surface layer of the printed wiring board 200 is also referred to as the front surface, and the back layer is also referred to as the back surface. Between the surface layer (conductor layer) and the back layer (conductor layer), an inner layer (conductor layer) is disposed via an insulator layer.

  In the first embodiment, the power supply line 411 includes a via conductor (conductor formed in the via) 415 branched from the main power supply line 402 and a conductor pattern 416 connected to the via conductor 415. . In the first embodiment, the main power supply line 402 is a conductor pattern wired to a conductor layer (inner layer or back layer) other than the surface layer.

  The power supply line 411 and the power supply line 421 are connected via a resistance element 207. The resistance element 207 is mounted on any substrate in the substrate group 400, that is, the printed wiring board 200 in the first embodiment.

  FIG. 2 is an equivalent circuit diagram showing the power supply wiring structure of the printed circuit board according to the first embodiment. The semiconductor integrated circuit 321 is represented by a series circuit of an internal capacitor (internal power supply capacitor) 601 and a parasitic resistor 602. The power supply line 412 of the package substrate 311 is represented by a series circuit of a parasitic inductance 603 and a parasitic resistance 604. The power supply line 411 of the printed wiring board 200 is represented by a series circuit of a parasitic inductance 605 and a parasitic resistance 606. The bypass capacitor 205 is represented by a series circuit of a capacitor 607, a parasitic resistance 608 and a parasitic inductance 609.

  The semiconductor integrated circuit 322 is represented by an internal capacity (internal power supply capacity) 610. The power supply line 422 of the package substrate 312 is represented by a series circuit of a parasitic inductance 611 and a parasitic resistance 612. The power supply line 421 of the printed wiring board 200 is represented by a series circuit of a parasitic inductance 613 and a parasitic resistance 614. The bypass capacitor 206 is represented by a series circuit of a capacitor 615, a parasitic resistance 616 and a parasitic inductance 617.

  The main power supply line 402 is represented by a series circuit of a parasitic inductance 618 and a parasitic resistance 619, and the power supply circuit 208 is represented by a DC power supply 620.

  A connection portion between the power supply line 411 and the power supply line 412 is represented by a series circuit of an inductance 621 and a resistor 622. In the first embodiment in which the connection portion is the resistance element 207, the resistance 622 is the resistance of the resistance element 207. Further, the inductance 621 includes a parasitic inductance inside the resistance element 207.

  Based on the equivalent circuit shown in FIG. 2, the printed circuit board 100 of the first embodiment and the printed circuit boards of Comparative Examples 1 and 2 were simulated. In the printed circuit board of Comparative Example 1, the resistance 622 at the connection portion was lower than that of the power supply line 420 (1 [mΩ]). In the first embodiment, the resistance element 207 has a higher resistance (250 [mΩ]) than the power supply line 420. In the printed circuit board of Comparative Example 2, the parasitic resistance 602 of the semiconductor integrated circuit 321 was set to 0 [Ω] with respect to the configuration of Comparative Example 1. The parameters of Comparative Example 1, Comparative Example 2 and the first embodiment are shown in Tables 1 to 3 below.

  The difference between the first comparative example and the first embodiment is the parameter (resistor 622) of the connection portion between the power supply line 421 and the power supply line 422. The resistor 622 in the first embodiment is an electric resistance of the resistor element 207, and the resistor 622 in the comparative example 1 is a parasitic resistance of only the wiring without the resistor element 207 shown in FIG.

  Further, the difference between the comparative example 2 and the first embodiment is a resistor 622 that is a parameter of the connection portion and a parasitic resistor 602 of the semiconductor integrated circuit 321. The resistor 622 in the first embodiment is an electrical resistance of the resistor element 207, and the resistor 622 in the comparative example 2 is a parasitic resistor of only wiring without the resistor element 207 shown in FIG. Further, the parasitic resistance 602 in the first embodiment is 50.0 [mΩ], and the parasitic resistance 602 in the comparative example 2 is 0 [Ω].

  FIG. 3 is a graph showing the frequency characteristic of the power supply impedance as viewed from the semiconductor integrated circuit 321 side, which is the first semiconductor element, in the first embodiment, comparative example 1, and comparative example 2. In FIG. 3, the solid line is the simulation result of the first embodiment based on Table 3, the chain line is the simulation result of Comparative Example 1 based on Table 1, and the one-dot chain line is the simulation result of Comparative Example 2 based on Table 2. In FIG. 3, the anti-resonance of the power source impedance is set to anti-resonance 1, anti-resonance 2, anti-resonance 3, and anti-resonance 4 in order from the lower frequency side.

  In FIG. 3, when Comparative Example 1 and Comparative Example 2 are compared, the peak values of anti-resonance 2, anti-resonance 3, and anti-resonance 4 are lower in Comparative Example 1 than in Comparative Example 2 due to parasitic resistance 602. Although the amount of reduction is small, there is no change when anti-resonance 1 is reached.

  Specifically, the peak value of anti-resonance 1 remains unchanged at 0.42 [Ω]. The peak values of anti-resonance 2 to anti-resonance 4 are 2.02 [Ω] to 1.87 [Ω], 1.80 [Ω] to 1.45 [Ω], 1.93 [Ω] to 1 .20 [Ω] respectively. If the electric resistance value of the parasitic resistance 602 is further increased to further reduce the peak values of these anti-resonance 1 to anti-resonance 4, the power supply impedance further increases in a frequency band higher than the frequency of anti-resonance 4.

  On the other hand, in the first embodiment in which an electric resistance value of 250 [mΩ] is applied to the resistor 622, the peak values of antiresonance 1, antiresonance 2, antiresonance 3, and antiresonance 4 are higher than those in Comparative Example 1. Reduced. Specifically, the peak values of antiresonance 1 to antiresonance 4 are 0.42 [Ω] to 0.16 [Ω], 1.87 [Ω] to 1.43 [Ω], 1.45 [Ω]. From 0.39 [Ω] and from 1.20 [Ω] to 1.03 [Ω].

  Further, in the region where the frequency is higher than that of the anti-resonance 4, that is, the frequency region where the impedance of the internal capacitor 601 of the semiconductor integrated circuit 321 is dominant, there is no difference in the power source impedance between the comparative example 1 and the first embodiment. It can be seen that the influence of the resistor 622 is small.

  For circuit simulation, a circuit simulator Hspice (H-2013.03.SP2) manufactured by Synopsys was used. The same applies to subsequent circuit simulations.

  Thus, by adding the resistance element 207 as a resistance component, the anti-resonance of the power supply impedance is reduced while suppressing the increase of the power supply impedance in the frequency region where the internal capacitance of the semiconductor integrated circuit 321 is dominant. Can do. As a result, power supply potential fluctuations can be suppressed, and signal delays can be suppressed. In particular, power supply potential fluctuations (simultaneous switching noise) when signals are simultaneously transmitted from a plurality of signal transmission units of the semiconductor integrated circuit 321 can be effectively suppressed.

  Hereinafter, the principle of reducing the anti-resonance peak of the power supply impedance and the principle of suppressing the rise of the power supply impedance between the internal capacitance of the semiconductor integrated circuit and the circuit will be described in detail.

  4A is an equivalent circuit diagram of a printed circuit board viewed from the semiconductor integrated circuit 321 side, which is the first semiconductor element, when the electrical resistance value of the connection portion is 0 [Ω] as Comparative Example 3. FIG. In order to simplify the description, an equivalent circuit is represented by one semiconductor integrated circuit, which is a parameter that is a main cause of anti-resonance. Specifically, the bypass capacitor, the parasitic resistance of the semiconductor package, and the minute wiring inductance of the printed wiring board are omitted.

  As shown in FIG. 4A, the semiconductor integrated circuit 321 is represented by an internal capacitor 801 and the package substrate 311 is represented by a parasitic inductance 802. Further, the bypass capacitor 205 is represented by a capacitor 803 and a parasitic inductance 805, the bypass capacitor 206 is represented by a capacitor 806 and a parasitic inductance 808, and the main power supply line 402 is represented by a parasitic inductance 809. The parameters of Comparative Example 3 are shown in Table 4 below.

  FIG. 4B is a graph showing the frequency characteristic of the power supply impedance in the printed circuit board of Comparative Example 3. As a result of the circuit simulation based on Table 4 shown in FIG. 4B, it can be seen that anti-resonance 1 occurs at 4.9 [MHz] and anti-resonance 2 occurs at 107.2 [MHz].

  FIG. 4C is an equivalent circuit diagram when anti-resonance 1 occurs. FIG. 4D is an equivalent circuit diagram when anti-resonance 2 occurs. Since anti-resonance occurs when an inductance and a capacitance form a parallel circuit, the equivalent circuits are the same, but the contents of each capacitance and inductance are different. Hereinafter, the generation mechanism of antiresonance 1 and antiresonance 2 will be described.

  In the case of anti-resonance 1, the internal capacitance 801 is smaller than the capacitances 803 and 806 of the bypass capacitors 205 and 206 and has a low frequency, and therefore can be regarded as open as alternating current. Furthermore, since the inductance 802 of the package substrate 311 and the parasitic inductances 805 and 808 of the bypass capacitors 205 and 206 are smaller than the parasitic inductance 809 of the main power line 402, it can be regarded as a short circuit as an alternating current.

  As a result, in the capacitor 810 constituting the parallel circuit shown in FIG. 4C, the combined capacitance of the capacitor 803 of the bypass capacitor 205 and the capacitor 806 of the bypass capacitor 206 is dominant. In addition, the inductance 811 constituting the parallel circuit shown in FIG. 4C is dominated by the inductance 809 of the main power supply line 402.

  On the other hand, in the case of anti-resonance 2, since the frequency is higher than that of anti-resonance 1, the influence of internal capacitance 801 becomes obvious. Since the capacitors 803 and 806 of the bypass capacitors 205 and 206 have low impedance, they can be regarded as a short circuit as an alternating current. Further, the effects of the inductance 802 of the package substrate 311 and the parasitic inductances 805 and 808 of the bypass capacitors 205 and 206 become obvious. Since the parasitic inductance 809 of the main power line 402 has high impedance, it can be regarded as open as alternating current.

  As a result, the capacitor 812 constituting the parallel circuit shown in FIG. 4D is dominated by the internal capacitor 801 of the semiconductor integrated circuit 321. The inductance 813 constituting the parallel circuit shown in FIG. 4 (d) is dominated by the inductance in which the combined inductance of the parasitic inductances 805 and 808 of the bypass capacitors 205 and 206 and the parasitic inductance 802 of the package substrate 311 are connected in series.

  The equivalent circuit shown in FIG. 4 (a) is described only with inductance and capacitance. Therefore, the peak of antiresonance is infinite in principle, but the antiresonance in the graph of FIG. The peak value is a finite value. This is due to the fact that the frequency sweep is a finite value in the circuit simulation.

  FIG. 5A is an equivalent circuit diagram of the printed circuit board viewed from the semiconductor integrated circuit 321 side which is the first semiconductor element in the first embodiment. As shown in FIG. 5A, a resistor 901 (Radd) is installed in parallel with the capacitor 803 and the parasitic inductance 805 and in series with the capacitor 806 and the parasitic inductance 808.

  As described above, when the anti-resonance 1 and the anti-resonance 2 occur, the parallel circuit of the inductance and the capacitance that generates the anti-resonance includes the characteristics of the bypass capacitor 205 and the bypass capacitor 206 as the combined capacitance or the combined inductance. .

  When a resistor 901 is added as shown in FIG. 5A, a resistor is added to the combined capacitance and combined inductance. That is, it is possible to insert a resistor that attenuates the antiresonance peak in the parallel circuit of the inductance and the capacitance.

  Hereinafter, this principle will be described in detail using mathematical expressions. FIG. 5B is an equivalent circuit diagram when anti-resonance 1 occurs. FIG. 5C is an equivalent circuit diagram when anti-resonance 2 occurs.

  The magnitude of the power supply impedance when anti-resonance 1 occurs, that is, the peak | Z ′ | of anti-resonance 1 uses the resistance value R ′ of resistor 903, the capacitance value C ′ of capacitor 902, and the inductance value L 3 of inductance 904. Thus, it can be expressed by Equation 2.

  In order to simplify the equation, assuming that the capacitance values of the capacitors 803 and 806 of the bypass capacitors 205 and 206 are the same value C (C1 = C2 = C), R ′ and C ′ in (Equation 2) are (Equation 3) (Expression 4).

ω ₁ is an angular frequency when anti-resonance 1 occurs. By substituting (Equation 3) and (Equation 4) into (Equation 2) and rearranging, (Equation 2) can be expressed by (Equation 5).

C in Equation (5), L3, since omega ₁ is a fixed value, | Z '| is a function whose variable is the Radd. Here, considering the case where Radd is close to zero, the value of | Z ′ |

が支配的となり、Ｒａｄｄがゼロから増加するにつれ、無限大から急激に｜Ｚ’｜が低下する。

Becomes dominant and | Z ′ | decreases rapidly from infinity as Radd increases from zero.

  On the other hand, as Radd increases, the governing term of | Z ′ |

となり、Ｒａｄｄの増加と共に｜Ｚ’｜は単調増加の傾向となるが、Ｒａｄｄが無い場合の｜Ｚ’｜は無限大である。したがって、Ｒａｄｄの付与によって反共振１のピーク｜Ｚ’｜を低減できると言える。

Thus, with increasing Radd, | Z ′ | tends to increase monotonically, but | Z ′ | in the absence of Radd is infinite. Therefore, it can be said that the peak | Z ′ | of antiresonance 1 can be reduced by applying Radd.

  Similarly, the magnitude of the power supply impedance | Z ″ | at the occurrence of anti-resonance 2 is expressed by using the resistance value R ″ of the resistor 906, the capacitance value C 0 of the capacitor 905, and the inductance value L ″ of the inductance 907 (Equation 6).

  Here, in order to simplify the equation, it is assumed that the parasitic inductance 802 of the package substrate 311 and the parasitic inductances 805 and 808 of the bypass capacitors 205 and 206 have the same inductance value L (L0 = L1 = L2 = L). R ″ and L ″ in (Expression 6) can be expressed by (Expression 7) and (Expression 8).

Note that ω ₂ is an angular frequency when anti-resonance 2 occurs.

  By substituting (Equation 7) and (Equation 8) into (Equation 6) and rearranging, (Equation 6) can be expressed by (Equation 9).

  (Equation 8)

は、反共振２が発生する周波数においてほぼゼロと見なせるから、（式９）は（式１０）に近似することができる。

Can be regarded as almost zero at the frequency at which anti-resonance 2 occurs, so (Equation 9) can be approximated to (Equation 10).

  Looking at (Equation 10), it can be seen that by adding Radd, Radd can be increased and | Z ″ | can be reduced.

  FIG. 5D is a graph showing the frequency characteristic of the power supply impedance. The graph shown in FIG. 5D is a simulation result of the power source impedance as seen from the circuit obtained by the circuit simulation based on the following Table 5 for the parameters in the circuit model of FIG.

  As shown in FIG. 5D, the peak values of antiresonance 1 and antiresonance 2 are reduced as the resistance value Radd increases.

  Next, paying attention to the site of the internal capacity 801, there is no difference between FIG. 4A and FIG. That is, even when the resistor 901 is added, the power supply impedance | Zdie | in the frequency domain where the internal capacitance 801 of the semiconductor integrated circuit 321 is dominant is the same as that in both of FIG. 4A and FIG. ) Is the same. Therefore, even if the resistor 901 is added, the increase in the power supply impedance in the frequency domain where the internal capacitance 801 of the semiconductor integrated circuit 321 is dominant does not occur in principle.

  6 shows that the resistance 622 in the first embodiment is changed to 50 [mΩ], 100 [mΩ], 250 [mΩ], 500 [mΩ], and 1000 [mΩ], and the antiresonance 2 and antiresonance 3 in FIG. It is the graph which plotted the peak value reduction rate with respect to the comparative example 1.

  Referring to FIG. 6, when 50 [mΩ] is installed, a reduction effect exceeding about 10 [%] appears, and the reduction rate tends to increase as the resistance value is increased. However, when it exceeds 500 [mΩ], the reduction rate starts to saturate.

  By the way, as shown in FIG. 2, the resistance element 207 (resistance 622) is arranged in series on the DC power supply path from the power supply circuit 208 to the semiconductor integrated circuit 322, so that the current consumption of the semiconductor integrated circuit 322 and the resistance element A DC voltage drop occurs due to the product of the electric resistance value of 207. For example, if the consumption current of the semiconductor integrated circuit 322 is 0.1 [A], a DC voltage drop of 0.1 [V] is generated only by the setting resistance unit of 1000 [mΩ].

  On the other hand, in the power supply voltage of the semiconductor device using the semiconductor process technology after 90 [nm], a case of using a voltage near 1.0 [V] is increasing. For example, when the operating voltage is 1.0 [V], a voltage drop of 0.1 [V] consumes 10 [%] of the operating voltage.

  In general, considering that the allowable voltage drop is about −5 [%] to −10 [%] of the operating voltage, it is practically difficult to use a resistance exceeding 1000 [mΩ] as the installation resistance. It is.

  From the above, the range of the electric resistance value of the resistance element 207 is preferably 50 [mΩ] or more and 1000 [mΩ] or less.

  The range of the electric resistance value of the resistance element 207 is more preferably 100 [mΩ] or more and 400 [mΩ] or less. By setting the electric resistance value of the resistance element 207 to 100 [mΩ] or more, an effect of reducing the antiresonance peak value exceeding 10 [%] with respect to Comparative Example 1 can be obtained with certainty. Moreover, since it is saturated at 500 [mΩ], the voltage drop can be more reliably suppressed by setting it to 400 [mΩ] or less.

  As described above, according to the first embodiment, in the frequency band where anti-resonance occurs, the resistance component of the resistance element 207 is added to the parallel resonance circuit including the parasitic inductances of the bypass capacitors 205 and 206 and the power supply lines 402, 410 and 420. It will be. Therefore, the anti-resonance peak in the power supply impedance can be reduced.

  Even if the resistance element 207 has an electrical resistance value higher than the electrical resistance value of the power supply line 420, the resistance element 207 does not contribute to an increase in resistance in series with the internal capacitance of the semiconductor integrated circuit 321. Therefore, it is possible to suppress an increase in power supply impedance in a frequency band higher than the frequency at which anti-resonance occurs.

[Second Embodiment]
Next, a printed circuit board according to a second embodiment of the present invention will be described. FIG. 7A is a schematic view showing a printed circuit board according to the second embodiment. FIG.7 (b) is a top view which shows the printed wiring board in Fig.7 (a).

  In the first embodiment, the resistance element is mounted on the surface layer of the printed wiring board, whereas the second embodiment is different from the first embodiment in that it is mounted on the back layer of the printed wiring board. Other configurations are the same as those of the first embodiment. Therefore, the description of the same configuration is omitted, and the points different from the first embodiment will be described.

  A printed circuit board 100A according to the second embodiment includes a printed wiring board 200A and a semiconductor package 300 mounted on the printed wiring board 200A and having the same configuration as that of the first embodiment. Further, the printed circuit board 100A includes a bypass capacitor 205 as a first capacitor and a bypass capacitor 206 as a second capacitor. The printed circuit board 100 </ b> A includes a resistance element (chip resistor) 207 that is a connection part and is a resistance component, and a power supply circuit 208. The power supply circuit 208 is mounted on the printed wiring board 200A.

  In the second embodiment, a package substrate group 350 is configured including a plurality of package substrates 311 and 312, and a substrate group 400 </ b> A is configured including the package substrate group 350 and the printed wiring board 200 </ b> A.

  The substrate group 400A includes a ground line 401, a main power supply line 402A, a power supply line 410A that is a first power supply line, and a second power supply path that supply power from the power supply circuit 208 to the semiconductor integrated circuits 321 and 322. A power supply line 420A, which is a power supply line, is formed.

  The main power supply line 402 </ b> A is connected to the power supply terminal 209 of the power supply circuit 208. The power supply line 410A branches from the main power supply line 402A and is connected to the power supply terminal 323 of the semiconductor integrated circuit 321. The power supply line 420A branches from the main power supply line 402A via the resistance element 207 and is connected to the power supply terminal 324 of the semiconductor integrated circuit 322.

  The main power line 402A is formed on the printed wiring board 200A of the board group 400A. The power supply line 410A is formed across the printed wiring board 200A and the package substrate 311 of the board group 400A. The power supply line 420A is formed across the printed wiring board 200A and the package substrates 311 and 312 of the board group 400A. Therefore, the power supply line 410A includes a power supply line 411A on the printed wiring board 200A side and a power supply line 412 on the package board group 350 side. The power line 420A includes a power line 421A on the printed wiring board 200A side and a power line 422 on the package board group 350 side. The ground lines 401 are respectively formed on the substrates 200A, 311 and 312 and are electrically connected to each other.

  FIG. 7B illustrates the ground line 401 and part of the main power supply line 402A, the power supply line 411A, and the power supply line 421A formed on the printed wiring board 200A.

  The bypass capacitor 205 is mounted on one of the boards 400A (the printed wiring board 200A in the second embodiment), and between the power line 410A (the power line 411A in the second embodiment) and the ground line 401. It is connected. Specifically, of the pair of terminals of the bypass capacitor 205, one terminal is connected to the power supply line 411A and the other terminal is connected to the ground line 401.

  The bypass capacitor 206 is mounted on one of the boards 400A (the printed wiring board 200A in the second embodiment), and between the power line 420A (the power line 421A in the second embodiment) and the ground line 401. It is connected. Specifically, of the pair of terminals of the bypass capacitor 206, one terminal is connected to the power supply line 421A and the other terminal is connected to the ground line 401.

  As shown in FIG. 7B, a plurality of connection pads 250 to which the package terminals 351 of the package substrate 311 are bonded are formed on the printed wiring board 200A. The plurality of connection pads 250 include ground connection pads 251, power connection pads 252 and 253, and other signal connection pads 254. The connection pad 252 for power supply of the semiconductor integrated circuit 321, the connection pad 253 for power supply of the semiconductor integrated circuit 322, and the connection pad 251 for ground exist on four sides.

  The power supply connection pad 252 is a part of a conductor pattern forming the power supply line 411A formed on the surface layer of the printed wiring board 200A. The connection pad 253 for power supply is a part of the conductor pattern that forms the power supply line 421A formed on the surface layer of the printed wiring board 200A. The ground connection pad 251 is a part of a conductor pattern forming the ground line 401 formed on the surface layer of the printed wiring board 200A.

  In the second embodiment, the main power supply line 402 </ b> A (power supply line 411 </ b> A) and the power supply line 421 </ b> A are connected via a connection portion 450 </ b> A having a resistance element 207. The power supply lines 411A and 421A are formed on the surface layer of the printed wiring board 200A, and the main power supply line 402A is formed on the inner layer. The resistance element 207 is mounted on the back layer of the printed wiring board 200A.

  450 A of connection parts have the conductor patterns 451A and 452A formed in the back layer of the printed wiring board 200A. One terminal of the resistance element 207 is connected to the conductor pattern 451A, and the other terminal of the resistance element 207 is connected to the conductor pattern 452A. The connecting portion 450A includes a via conductor 453A that connects the conductor pattern 451A and the power supply line 411A (conductor pattern), and a via conductor 454A that connects the conductor pattern 452A and the power supply line 421A (conductor pattern). ing. Although the main power supply line 402A is wired in the inner layer, it may be wired in the back layer.

  FIG. 8 is an equivalent circuit diagram showing the power supply wiring structure of the printed circuit board according to the second embodiment. The only difference from the equivalent circuit of the first embodiment is the parasitic inductances 723 and 724 of the wiring portion of the connection portion 450A in the printed wiring board 200A, the parasitic inductance 721 and the resistance 722 of the resistance element 207 of the connection portion 450A, and the others. This is the same as FIG. Therefore, the description of the same part as FIG. 2 is omitted.

  The parasitic inductances of the via conductors 453A and 454A in FIG. 7B are the parasitic inductances 723 and 724 in FIG. A parasitic inductance that is a combination of the conductor patterns 451A and 452A is a parasitic inductance 721. The resistance of the resistance element 207 is the resistance 722. The resistance element 207 has an internal parasitic inductance component, but can be considered to be included in the parasitic inductance 721 on an equivalent circuit.

  Tables 6 and 7 show parameters of Comparative Examples 4 and 5 and the second embodiment based on the equivalent circuit of FIG. The difference between the comparative example 4 and the second embodiment is only the resistor 722 that is a parameter of the connection portion 450A. Further, the difference between the comparative example 4 and the second embodiment is a resistor 722 which is a parameter of the connection part 450A and a parasitic resistor 602 connected in series to the internal capacitor 601 of the semiconductor integrated circuit 321.

  In Comparative Example 4, the electrical resistance value of the parasitic resistance 602 was set to 50.0 [mΩ], and in Comparative Example 5, the electrical resistance value of the parasitic resistance 602 was set to 0 [Ω]. In Comparative Examples 4 and 5, parts other than the parasitic resistance 602 were set to the same set values.

  The resistor 722 in the second embodiment represents the electrical resistance value of the resistance element 207. Further, the resistor 722 in Comparative Examples 4 and 5 does not include the resistor element 207 and represents the parasitic resistance value of the wiring.

  FIG. 9 is a graph showing the frequency characteristics of the power supply impedance as viewed from the semiconductor integrated circuit 321 side which is the first semiconductor element in the second embodiment, comparative example 4 and comparative example 5. In FIG. 9, the solid line is the simulation result of the second embodiment based on Table 7, the chain line is the simulation result of Comparative Example 4 based on Table 6, and the one-dot chain line is the simulation result of Comparative Example 5 based on Table 6. In FIG. 9, the anti-resonance of the power supply impedance is set to anti-resonance 1, anti-resonance 2, anti-resonance 3, and anti-resonance 4 in order from the lower frequency side.

  9, when Comparative Example 4 and Comparative Example 5 are compared, in Comparative Example 4, the peak values of anti-resonance 2, anti-resonance 3, and anti-resonance 4 are reduced due to parasitic resistance 722, compared to Comparative Example 5. Although the amount of reduction is small, there is no change when anti-resonance 1 is reached.

  Specifically, the antiresonance 1 peak value remains unchanged at 0.47 [Ω]. The peak values of antiresonance 2 to antiresonance 4 are 5.33 [Ω] to 4.40 [Ω], 4.05 [Ω] to 3.44 [Ω], and 0.98 [Ω] to 0. .78 [Ω] respectively. If the electric resistance value of the parasitic resistance 722 is further increased to further reduce the peak values of these anti-resonance 1 to anti-resonance 4, the power supply impedance further increases in a frequency band higher than the frequency of anti-resonance 4.

  On the other hand, in the second embodiment in which an electric resistance value of 250 [mΩ] is given to the resistor 722, the peak values of antiresonance 1, antiresonance 2, antiresonance 3, and antiresonance 4 are higher than in the case of Comparative Example 1, respectively. Reduced. Specifically, the peak values of antiresonance 1 to antiresonance 4 are 0.47 [Ω] to 0.18 [Ω], 4.40 [Ω] to 2.00 [Ω], 3.44 [Ω]. To 1.44 [Ω] and 0.78 [Ω] to 0.77 [Ω], respectively.

  Further, in the region where the frequency is higher than that of the antiresonance 4, that is, the frequency region where the impedance of the internal capacitor 601 of the semiconductor integrated circuit 321 is dominant, there is no difference in the power source impedance between the comparative example 4 and the second embodiment. It can be seen that the influence of the resistor 722 is small.

  Thus, by adding the resistance element 207 as a resistance component, the anti-resonance of the power supply impedance is reduced while suppressing the increase of the power supply impedance in the frequency region where the internal capacitance of the semiconductor integrated circuit 321 is dominant. Can do. As a result, power supply potential fluctuations can be suppressed, and signal delays can be suppressed. In particular, power supply potential fluctuations (simultaneous switching noise) when signals are simultaneously transmitted from a plurality of signal transmission units of the semiconductor integrated circuit 321 can be effectively suppressed.

  10, the resistance 722 in the second embodiment is changed to 50 [mΩ], 100 [mΩ], 250 [mΩ], 500 [mΩ], and 1000 [mΩ], and the antiresonance 2 and the antiresonance 3 in FIG. It is the graph which plotted the peak value reduction rate with respect to the comparative example 4.

  Referring to FIG. 10, when 50 [mΩ] is installed, a reduction effect exceeding about 10 [%] appears, and the reduction rate tends to increase as the resistance value is increased. However, when it exceeds 500 [mΩ], the reduction rate starts to saturate. When it is 1000 [mΩ], the reduction effect is as high as about 65 [%], but the reduction rate is lower than that at 500 [mΩ]. I understand that.

  By the way, as shown in FIG. 8, since the resistance element 207 (resistance 722) is arranged in series on the DC power supply path from the power supply circuit 208 to the semiconductor integrated circuit 322, the current consumption of the semiconductor integrated circuit 322 and the resistance element A DC voltage drop occurs due to the product of the electric resistance value of 207. For example, if the consumption current of the semiconductor integrated circuit 322 is 0.1 [A], a DC voltage drop of 0.1 [V] is generated only by the setting resistance unit of 1000 [mΩ].

  On the other hand, in the power supply voltage of the semiconductor device using the semiconductor process technology after 90 [nm], a case of using a voltage near 1.0 [V] is increasing. For example, when the operating voltage is 1.0 [V], a voltage drop of 0.1 [V] consumes 10 [%] of the operating voltage.

  In general, considering that the allowable voltage drop is about −5 [%] to −10 [%] of the operating voltage, it is practically difficult to use a resistance exceeding 1000 [mΩ] as the installation resistance. It is.

  From the above, the range of the electric resistance value of the resistance element 207 to be installed is preferably 50 [mΩ] or more and 1000 [mΩ] or less.

  The range of the electric resistance value of the resistance element 207 is more preferably 100 [mΩ] or more and 400 [mΩ] or less. By setting the electric resistance value of the resistance element 207 to 100 [mΩ] or more, an effect of reducing the antiresonance peak value exceeding 10 [%] with respect to Comparative Example 1 can be obtained with certainty. Moreover, since it is saturated at 500 [mΩ], the voltage drop can be more reliably suppressed by setting it to 400 [mΩ] or less.

  As described above, according to the second embodiment, the resistance component of the resistance element 207 is added to the parallel resonant circuit including the parasitic inductances of the bypass capacitors 205 and 206 and the power supply lines 402A, 410A, and 420A in the frequency band where anti-resonance occurs. It will be. Therefore, the anti-resonance peak in the power supply impedance can be reduced.

  Even if the resistance element 207 has an electrical resistance value higher than the electrical resistance value of the power supply line 420A, the resistance element 207 does not contribute to an increase in resistance in series with the internal capacitance of the semiconductor integrated circuit 321. Therefore, it is possible to suppress an increase in power supply impedance in a frequency band higher than the frequency at which anti-resonance occurs.

[Third Embodiment]
Next, a printed circuit board according to a third embodiment of the invention will be described. FIG. 11A is a schematic view showing a printed circuit board according to the third embodiment. FIG.11 (b) is a top view which shows the printed wiring board in Fig.11 (a). In addition, about the structure similar to 1st-2nd embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  As shown in FIG. 11A, the printed circuit board 100B includes a printed wiring board 200B and semiconductor devices 301B and 302B mounted directly on the printed wiring board 200B in a flat state. The printed circuit board 100B includes bypass capacitors 205 and 206, a resistance element 207, and a power supply circuit 208, as in the first embodiment. The power supply circuit 208 is mounted on the printed wiring board 200B.

  The semiconductor devices 301B and 302B are, for example, BGA type or LGA type semiconductor packages. The semiconductor device 301B includes a package substrate 311B that is a first package substrate, and a semiconductor integrated circuit 321 that is a first semiconductor element mounted on the package substrate 311B. The semiconductor device 302B includes a package substrate 312B that is a second package substrate, and a semiconductor integrated circuit 322 that is a second semiconductor element mounted on the package substrate 312B. Package substrates 311B and 312B are mounted (bonded) to the printed wiring board 200B.

  The package substrate group 350B is configured by including the plurality of package substrates 311B and 312B, and the substrate group 400B is configured by including the package substrate group 350B and the printed wiring board 200B.

  The substrate group 400B includes a ground line 401B, a main power supply line 402B, a power supply line 410B that is a first power supply line, and a second power supply path that supply power to the semiconductor integrated circuits 321 and 322 from the power supply circuit 208. A power supply line 420B which is a power supply line is formed.

  The main power supply line 402 </ b> B is connected to the power supply terminal 209 of the power supply circuit 208. The power supply line 410B branches from the main power supply line 402B and is connected to the power supply terminal 323 of the semiconductor integrated circuit 321. The power supply line 420B branches from the power supply line 410B via the resistance element 207 and is connected to the power supply terminal 324 of the semiconductor integrated circuit 322.

  The main power supply line 402B is formed on the printed wiring board 200B of the board group 400B. The power supply line 410B is formed across the printed wiring board 200B and the package substrate 311B of the board group 400B. The power supply line 420B is formed across the printed wiring board 200B and the package substrate 312B of the board group 400B. Accordingly, the power supply line 410B includes a power supply line 411B on the printed wiring board 200B side and a power supply line 412B on the package substrate 311B side. The power supply line 420B includes a power supply line 421B on the printed wiring board 200B side and a power supply line 422B on the package substrate 312B side. The ground line 401B is formed on each of the substrates 200B, 311B, and 312B, and is electrically connected to each other.

  The power supply line 411B on the printed wiring board 200B side and the power supply line 412B on the package substrate 311B side are connected by a package terminal (solder ball) 351B of the package substrate 311B. The power supply line 421B on the printed wiring board 200B side and the power supply line 422B on the package substrate 312B side are connected by a package terminal (solder ball) 352B of the package substrate 312B.

  FIG. 11B illustrates the ground line 401B and part of the main power supply line 402B, the power supply line 411B, and the power supply line 421B formed on the printed wiring board 200B.

  The bypass capacitor 205 is mounted on the printed wiring board 200B in the board group 400B, and is connected between the power line 410B (power line 411B in the third embodiment) and the ground line 401B. Specifically, of the pair of terminals of the bypass capacitor 205, one terminal is connected to the power supply line 411B, and the other terminal is connected to the ground line 401B. The bypass capacitor 206 is mounted on the printed wiring board 200B in the board group 400B, and is connected between the power line 420B (power line 421B in the third embodiment) and the ground line 401B. Specifically, of the pair of terminals of the bypass capacitor 206, one terminal is connected to the power supply line 421B, and the other terminal is connected to the ground line 401B.

  In the third embodiment, as shown in FIG. 11B, the power supply lines 411B and 421B are configured by a conductor pattern formed on the surface layer of the printed wiring board 200B. Further, a part of the ground line 401B is a conductor pattern formed on the surface layer of the printed wiring board 200B, and a part of the main power line 402B is a conductor pattern formed on the inner layer or the back layer of the printed wiring board 200B.

  As shown in FIG. 11B, a plurality of connection pads 251B to which the package terminals 351B of the package substrate 311B are bonded are formed on the printed wiring board 200B. The printed wiring board 200B is provided with a plurality of connection pads 252B to which the package terminals 352B of the package substrate 312B are bonded. The plurality of connection pads 251B include power connection pads 253B. The plurality of connection pads 252B include power connection pads 254B. The connection pad 253B for power supply is a part of the conductor pattern that forms the power supply line 411B formed on the surface layer of the printed wiring board 200B. The connection pad 254B for power supply is a part of the conductor pattern that forms the power supply line 421B formed on the surface layer of the printed wiring board 200B. The main power supply line 402B and the power supply line 411B are connected by a via conductor 415B.

  In the third embodiment, the power supply line 411 </ b> B and the power supply line 421 </ b> B are connected via the resistance element 207. The resistance element 207 is mounted on the surface layer of the printed wiring board 200B in the board group 400B. Also in the third embodiment, as in the first embodiment, the anti-resonance peak in the power supply impedance can be reduced, and an increase in the power supply impedance can be suppressed in a frequency band higher than the frequency at which the anti-resonance occurs.

  In the third embodiment, the case where the resistance element 207 is mounted on the surface layer of the printed wiring board 200B has been described. However, the case where the resistance element 207 is mounted on the back layer of the printed wiring board may be used. . In this case, the resistance element 207 on the back layer and the power supply lines 411B and 421B on the surface layer may be connected via via conductors.

[Fourth Embodiment]
Next, a printed circuit board according to a fourth embodiment of the invention will be described. FIG. 12A is a schematic view showing a printed circuit board according to the fourth embodiment. FIG. 12B is a plan view showing the printed wiring board and the third package substrate in FIG. In addition, about the structure similar to 1st-3rd embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  In the first to third embodiments, the case has been described in which the resistance element constituting the connection portion is mounted on the printed wiring board on which the semiconductor package is mounted. In the fourth embodiment, a case where a resistance element is mounted on a package substrate of a semiconductor package, that is, a case where the semiconductor package has a resistance element will be described.

  The printed circuit board 100C of the fourth embodiment includes a printed wiring board 200C, and a semiconductor package 300C and a power supply circuit 208 mounted on the printed wiring board 200C.

  The semiconductor package 300C includes a package substrate (interposer) 313C that is a third package substrate, and semiconductor devices 301B and 302B that are mounted on the package substrate 313C and have the same configuration as that of the third embodiment. The semiconductor package 300 </ b> C includes bypass capacitors 205 and 206 and a resistance element 207. The semiconductor devices 301B and 302B are directly mounted on the package substrate 313C in a flat state. That is, the package substrates 311B and 312B of the semiconductor devices 301B and 302B are mounted (bonded) to the package substrate 313C.

  A package substrate group 350C is configured by including the plurality of package substrates 311B, 312B, and 313C, and a substrate group 400C is configured by including the package substrate group 350C and the printed wiring board 200C.

  The substrate group 400C includes a ground line 401C, a main power supply line 402C, a power supply line 410C that is a first power supply line, and a second power supply path that supply power from the power supply circuit 208 to the semiconductor integrated circuits 321 and 322. A power supply line 420C which is a power supply line is formed.

  The main power line 402C is connected to the power terminal 209 of the power circuit 208. The power supply line 410C branches from the main power supply line 402C and is connected to the power supply terminal 323 of the semiconductor integrated circuit 321. The power supply line 420C branches from the power supply line 410C via the resistance element 207 and is connected to the power supply terminal 324 of the semiconductor integrated circuit 322.

  The main power line 402C is formed on the printed wiring board 200C of the board group 400C. The power supply line 410C is formed across the package substrate 313C and the package substrate 311B of the package substrate group 350C. The power supply line 420C is formed across the package substrate 313C and the package substrate 312B of the package substrate group 350C. Therefore, the power supply line 410C includes a power supply line 412B on the package substrate 311B side and a power supply line 411C on the package substrate 313C side. The power supply line 420C includes a power supply line 422B on the package substrate 312B side and a power supply line 421C on the package substrate 313C side. The ground line 401C is formed on each of the substrates 200C, 311B, 312B, and 313C and is electrically connected to each other.

  FIG. 12B illustrates a part of the main power supply line 402C formed on the printed wiring board 200C, a part of the ground line 401C, the power supply line 411C, and the power supply line 421C formed on the package substrate 313C. ing.

  The bypass capacitor 205 is mounted on the package substrate 313C of the package substrate group 350C in the substrate group 400C, and is connected between the power supply line 410C (power supply line 411C in the fourth embodiment) and the ground line 401C. Specifically, of the pair of terminals of the bypass capacitor 205, one terminal is connected to the power supply line 411C, and the other terminal is connected to the ground line 401C.

  The bypass capacitor 206 is mounted on the package substrate 313C of the package substrate group 350C in the substrate group 400C, and is connected between the power supply line 420C (power supply line 421C in the fourth embodiment) and the ground line 401C. Specifically, of the pair of terminals of the bypass capacitor 206, one terminal is connected to the power supply line 421C, and the other terminal is connected to the ground line 401C.

  In the fourth embodiment, as shown in FIG. 12B, the power supply lines 411C and 421C are configured by a conductor pattern formed on the surface layer of the package substrate 313C. A part of the ground line 401C is a conductor pattern formed on the surface layer of the package substrate 313C. A part of the main power supply line 402C is a conductor pattern formed on the inner layer or the back layer of the printed wiring board 200C.

  As shown in FIG. 12B, a plurality of connection pads 251C to which the package terminals 351B of the package substrate 311B are bonded are formed on the package substrate 313C. The package substrate 313C is provided with a plurality of connection pads 252C to which the package terminals 352B of the package substrate 312B are bonded. The plurality of connection pads 251C include power connection pads 253C. The plurality of connection pads 252C include connection pads 254C for power supply. The power supply connection pad 253C is a part of a conductor pattern forming the power supply line 411C formed on the surface layer of the package substrate 313C. The power supply connection pad 254C is a part of a conductor pattern constituting the power supply line 421C formed on the surface layer of the package substrate 313C. A plurality of package terminals (solder balls) are formed on the back layer of the package substrate 313C, and the plurality of package terminals are joined to a plurality of connection pads formed on the surface layer of the printed wiring board 200C. The main power supply line 402C and the power supply line 411C are connected to each other by vias 415C and 416C formed on the printed wiring board 200C and the package substrate 313C, connection pads 417C formed on the printed wiring board 200C, and the like.

  In the fourth embodiment, the power supply line 411C and the power supply line 421C are connected via the resistance element 207. The resistance element 207 is mounted on the package substrate 313C of the package substrate group 350C in the substrate group 400C. In the fourth embodiment, similarly to the first embodiment, the peak of anti-resonance in the power supply impedance can be reduced, and an increase in power supply impedance can be suppressed in a frequency band higher than the frequency at which anti-resonance occurs.

[Fifth Embodiment]
Next, a printed circuit board according to a fifth embodiment of the invention will be described. FIG. 13 is a schematic view showing a printed circuit board according to the fifth embodiment. In addition, about the structure similar to 1st-4th embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  In the fourth embodiment, the case where the resistance element is mounted on the package substrate on which the semiconductor device (semiconductor package) is mounted has been described. In the fifth embodiment, the resistance element is mounted on the package substrate of the semiconductor device. The case will be described.

  A printed circuit board 100D according to the fifth embodiment includes a printed wiring board 200D, and a semiconductor package 300D and a power supply circuit 208 mounted on the printed wiring board 200D.

  The semiconductor package 300D is a PoP-type stacked semiconductor device, and includes a semiconductor device 301D that is a first semiconductor device and a semiconductor device 302D that is a second semiconductor device mounted on the semiconductor device 301D. The semiconductor devices 301D and 302D are, for example, BGA type or LGA type semiconductor packages.

  The semiconductor device 301D includes a package substrate 311D that is a first package substrate, and a semiconductor integrated circuit 321 that is a first semiconductor element mounted on the package substrate 311D. The semiconductor device 302 includes a package substrate 312D that is a second package substrate, and a semiconductor integrated circuit 322 that is a second semiconductor element mounted on the package substrate 312D. The package substrate 311D is mounted (bonded) to the printed wiring board 200D, and the package substrate 312D is mounted (bonded) to the package substrate 311D.

  A package substrate group 350D is configured by including the plurality of package substrates 311D and 312D, and a substrate group 400D is configured by including the package substrate group 350D and the printed wiring board 200D.

  In the fifth embodiment, the bypass capacitors 205 and 206 and the resistance element 207 are mounted on the package substrate 311D of the package substrate group 350D in the substrate group 400D.

  The substrate group 400D includes a ground line 401D, a main power supply line 402D, a power supply line 410D that is a first power supply line, and a second power supply path that supply power from the power supply circuit 208 to the semiconductor integrated circuits 321 and 322. A power supply line 420D, which is a power supply line, is formed.

  The main power supply line 402D is formed on the printed wiring board 200D of the board group 400D. The power supply line 410D is formed on the package substrate 311D of the package substrate group 350D. The power supply line 420D is formed across the package substrate 311D and the package substrate 312D of the package substrate group 350D. Therefore, the power supply line 420D includes a power supply line 422D on the package substrate 312D side and a power supply line 421D on the package substrate 311D side. The ground line 401D is formed on each of the substrates 200D, 311D, and 312D, and is electrically connected to each other.

  The bypass capacitor 205 is mounted on the package substrate 311D of the package substrate group 350D in the substrate group 400D, and is connected between the power supply line 410D and the ground line 401D. Specifically, of the pair of terminals of the bypass capacitor 205, one terminal is connected to the power supply line 410D and the other terminal is connected to the ground line 401D.

  The bypass capacitor 206 is mounted on the package substrate 311D of the package substrate group 350D in the substrate group 400D, and is connected between the power supply line 420D (power supply line 421D in the fourth embodiment) and the ground line 401D. Specifically, one of the pair of terminals of the bypass capacitor 206 is connected to the power supply line 421D, and the other terminal is connected to the ground line 401D.

  In the fifth embodiment, the power supply line 410D and the power supply line 421D are connected via the resistance element 207. The resistance element 207 is mounted on the package substrate 311D of the package substrate group 350D in the substrate group 400D. Also in the fifth embodiment, as in the first embodiment, the anti-resonance peak in the power supply impedance can be reduced, and an increase in the power supply impedance can be suppressed in a frequency band higher than the frequency at which the anti-resonance occurs.

  The present invention is not limited to the embodiment described above, and many modifications are possible within the technical idea of the present invention. In addition, the effects described in the embodiments of the present invention only list the most preferable effects resulting from the present invention, and the effects of the present invention are not limited to those described in the embodiments of the present invention.

  Although the case where the resistance component in the connection portion is the resistance element 207 and the number of the resistance elements 207 is one has been described in the above embodiment, the resistance component may be configured by a plurality of resistance elements. . Further, the resistance component may be constituted by wiring, and the electric resistance value may be set by the length and width (thickness) of the wiring. However, it is preferable that the resistance component is constituted by a resistance element due to substrate restrictions.

  In the above embodiment, the semiconductor integrated circuit 321 has a signal transmission unit to transmit a signal, and the semiconductor integrated circuit 322 has a signal reception unit to receive a signal. It is not limited. The semiconductor integrated circuit 322 may include a signal transmission unit to transmit a signal, and the semiconductor integrated circuit 321 may include a signal reception unit to receive a signal. Further, the semiconductor integrated circuit 321 and the semiconductor integrated circuit 322 may operate independently of each other.

DESCRIPTION OF SYMBOLS 100 ... Printed circuit board, 200 ... Printed wiring board, 205 ... Bypass capacitor (first capacitor), 206 ... Bypass capacitor (second capacitor), 207 ... Resistance element (resistance component), 311, 312 ... Package substrate, 321 ... Semiconductor integrated circuit (first semiconductor element), 322... Semiconductor integrated circuit (second semiconductor element), 400... Substrate group, 401... Ground line, 402 ... Core power line, 410 ... Power line (first power line), 420 ... Power line (second power line)

Claims (16)

A first semiconductor element capable of simultaneously transmitting a plurality of digital signals ;
A second semiconductor element capable of receiving the plurality of digital signals ;
A first power line on which the first semiconductor element and the second semiconductor element are mounted; a ground line; a main power line; and a first power line branched from the main power line and connected to a power terminal of the first semiconductor element; A substrate group in which a second power supply line branched from the first power supply line or the main power supply line via a connection portion and connected to a power supply terminal of the second semiconductor element is formed;
A first capacitor mounted on the substrate group and connected between the first power supply line and the ground line;
A second capacitor mounted on the substrate group and connected between the second power supply line and the ground line;
A resistance element mounted on the substrate group and disposed at the connection portion, the resistance element having a higher resistance than the second power supply line;
A power supply circuit mounted on the substrate group, connected to the main power supply line and generating a DC voltage ,
Wherein the first semiconductor element, a printed circuit board, characterized in Rukoto DC voltage is applied through the basic power line and the first power supply line not through the resistive element by the power supply circuit. The printed circuit board according to claim 1, wherein an electric resistance value of the resistance element is 50 [mΩ] or more and 1000 [mΩ] or less. The printed circuit board according to claim 1, wherein an electric resistance value of the resistance element is 100 [mΩ] or more and 400 [mΩ] or less. 4. The printed circuit board according to claim 1, wherein the first semiconductor element is a controller, and the second semiconductor element is a memory . 5. The substrate group includes:
A package substrate group including a first package substrate on which the first semiconductor element is mounted and a second package substrate on which the second semiconductor element is mounted;
The printed circuit board according to claim 1, further comprising a printed wiring board on which the package substrate group is mounted. The first package substrate is mounted on the printed wiring board;
The second package substrate is mounted on the first package substrate;
The first power line is formed on the first package substrate,
The printed circuit board according to claim 5, wherein the second power supply line is formed on the first package substrate and the second package substrate.   The printed circuit board according to claim 6, wherein the first power supply line and the second power supply line are further formed on the printed wiring board. The first package substrate and the second package substrate are mounted on the printed wiring board,
The first power supply line is formed on the first package substrate and the printed wiring board,
The printed circuit board according to claim 5, wherein the second power line is formed on the second package substrate and the printed wiring board. The package substrate group further includes a third package substrate on which the first package substrate and the second package substrate are mounted,
The first power line is formed on the first package substrate and the third package substrate,
The printed circuit board according to claim 5, wherein the second power supply line is formed on the second package substrate and the third package substrate. A first semiconductor element capable of simultaneously transmitting a plurality of digital signals ;
A second semiconductor element capable of receiving the plurality of digital signals ;
The first semiconductor element and the second semiconductor element are mounted, and a ground line, a first power supply line connected to a power supply terminal of the first semiconductor element, and a branch from the first power supply line via a connection portion. A package substrate group formed with a second power supply line connected to the power supply terminal of the second semiconductor element;
A first capacitor mounted on the package substrate group and connected between the first power supply line and the ground line;
A second capacitor mounted on the package substrate group and connected between the second power supply line and the ground line;
A resistance element mounted on the package substrate group and disposed at the connection portion and having a higher resistance than the second power supply line ,
Wherein the first semiconductor element, a semiconductor package according to claim Rukoto DC voltage is applied via the first power supply line not through the resistive element by the power supply circuit connected to the first power supply line. The semiconductor package according to claim 10, wherein an electric resistance value of the resistance element is 50 [mΩ] or more and 1000 [mΩ] or less. The semiconductor package according to claim 10, wherein an electric resistance value of the resistance element is 100 [mΩ] or more and 400 [mΩ] or less. The semiconductor package according to claim 10, wherein the first semiconductor element is a controller, and the second semiconductor element is a memory . The package substrate group includes:
14. The semiconductor according to claim 10, comprising: a first package substrate on which the first semiconductor element is mounted; and a second package substrate on which the second semiconductor element is mounted. package. The second package substrate is mounted on the first package substrate;
The first power line is formed on the first package substrate,
The semiconductor package according to claim 14, wherein the second power supply line is formed on the first package substrate and the second package substrate. The package substrate group further includes a third package substrate on which the first package substrate and the second package substrate are mounted,
The first power line is formed on the first package substrate and the third package substrate,
The semiconductor package according to claim 14, wherein the second power supply line is formed on the second package substrate and the third package substrate.

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