JP6589530B2 - Method for producing semiconductor optical device, semiconductor optical device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor optical device, and a semiconductor optical device.

  Patent Documents 1 and 2 disclose Mach-Zehnder modulators.

Japanese Patent No. 4235154 JP 2010-256761 A

  A semiconductor mesa that requires electrical connection includes a semiconductor layer, eg, a contact layer, that includes a relatively high concentration of dopants for good electrical connection, which contact layer joins the metal layer. However, light absorption by the dopant in the contact layer reduces the intensity of light propagating through the semiconductor mesa. Such a semiconductor mesa structure can reduce optical loss by selectively removing the contact layer or the semiconductor layer for the contact layer. For example, Patent Document 1 discloses a complicated method of embedding a semiconductor mesa with a semiconductor and forming a waveguide from the buried region and the semiconductor mesa after removing the contact layer. Patent Document 2 discloses a waveguide in which the width of the semiconductor mesa is larger than the width of the contact layer. Alternatively, the selective removal may result in unwanted structures in the semiconductor optical device due to the etchant for contact layer removal.

  One aspect of the present invention has been made in view of the above circumstances, and provides a method for manufacturing a semiconductor optical device that enables the uppermost portion of a semiconductor mesa to be removed in a desired area. Objective. Another object of the present invention is to provide a semiconductor optical device including a semiconductor mesa that does not include a contact layer at a desired portion.

  A method of manufacturing a semiconductor optical device according to one aspect of the present invention includes a first portion, a second portion, and a third portion provided on a first area, a second area, and a third area of a semiconductor main surface, respectively. A first semiconductor mesa; a lower insulator region provided on the semiconductor main surface and covering the first semiconductor mesa; an electrode connected to the first portion of the first semiconductor mesa; and the electrode connected to the electrode A step of preparing a substrate product including a wiring electrode extending over a lower insulator region; a step of forming an upper insulator region on the substrate product; and a through hole reaching the wiring electrode in the upper portion Forming the insulator region, and forming the conductor on the upper insulator region after forming the through hole in the upper insulator region, and the lower insulator region includes the first insulator region. The first in one area A first opening reaching the upper surface of the minute and a covering provided on the third portion in the third area, the step of preparing the substrate product comprising: a semiconductor layer for a contact layer; Forming a first semiconductor mesa from the semiconductor stack, forming a structure covering a side surface and an upper surface of the semiconductor mesa, and the second portion of the first semiconductor mesa. Forming an etching opening reaching the upper surface of the structure in the structure, removing part or all of the contact layer of the second part, and leaving the contact layer in the first part and the third part And processing the second part of the first semiconductor mesa using the etching opening of the structure, wherein the conductor is on the second part or the third part of the semiconductor mesa. The To standing.

  A method for fabricating a semiconductor optical device according to another aspect of the present invention includes a first portion, a second portion, and a third portion provided on a first area, a second area, and a third area of a semiconductor main surface, respectively. Forming an insulating buried region that covers a side surface and an upper surface of the semiconductor mesa on the semiconductor mesa including the semiconductor stack and the semiconductor main surface, and the first area of the semiconductor main surface and the semiconductor Removing the insulating buried region on the first portion of the mesa to form a first opening in the insulating buried region reaching the first portion of the semiconductor mesa; and Forming an electrode on the first portion of the semiconductor mesa, removing the insulating buried region on the second area of the semiconductor main surface, and forming the first portion of the semiconductor mesa. The second opening reaching the second part is embedded in the insulation. Forming in a region, removing a part or all of a contact layer in the semiconductor stack of the semiconductor mesa by etching using the second opening, the first opening, the second opening, and the electrode Forming a conductor that crosses the semiconductor mesa in the third area of the semiconductor main surface, and the electrode passes through the first opening in the first portion of the semiconductor mesa. In contact with the contact layer.

  A method of manufacturing a semiconductor optical device according to still another aspect of the present invention includes a first portion, a second portion, and a third portion respectively provided on a first area, a second area, and a third area of a semiconductor main surface. Forming a dummy region for embedding the semiconductor mesa on a semiconductor mesa having a portion and having a semiconductor stack and on the semiconductor main surface; and removing the dummy region on the second portion of the semiconductor mesa; Forming an etching opening located on the second portion of the semiconductor mesa in the dummy region; and part or all of the contact layer of the semiconductor stack of the second portion of the semiconductor mesa in the dummy region. Removing by etching using an etching opening; removing the dummy region after performing the etching in the second portion of the semiconductor mesa; A step of producing an insulating buried region that covers the semiconductor mesa after removing the first region, and removing the insulating buried region on the first portion of the semiconductor mesa. Forming a connection opening located on one portion in the insulating buried region; and, after forming the connection opening in the insulating buried region, forming the semiconductor mesa in the connection opening in the insulating buried region. Forming an electrode on the first portion, and forming a conductor crossing the semiconductor mesa in the second area or the third area of the semiconductor main surface after forming the electrode. And the electrode contacts the contact layer in the first portion of the semiconductor mesa.

  A semiconductor optical device according to still another aspect of the present invention includes a first portion, a second portion, and a third portion provided on the first area, the second area, and the third area of the semiconductor main surface, respectively. A semiconductor mesa having an insulating film provided on the semiconductor mesa and the semiconductor main surface, and a buried region provided on the insulating film, the first being located on the first portion of the semiconductor mesa. An insulating buried region having one opening and a second opening located on the second portion of the semiconductor mesa, an insulating covering layer covering the second opening of the insulating buried region, and the insulating property An electrode in contact with the first portion of the semiconductor mesa through the first opening of the buried region, and a conductive property extending across the insulating buried region and the semiconductor mesa on the third area. And the insulating buried region is a tree. Wherein the first portion and the third portion of said semiconductor mesa includes a contact layer, said second portion of said semiconductor mesa does not include a contact layer.

  A semiconductor optical device according to yet another aspect of the present invention includes a first portion, a second portion, and a third portion provided on the first area, the second area, and the third area of the semiconductor main surface, respectively. A semiconductor mesa having an insulating film provided on the semiconductor mesa and the semiconductor main surface, and a buried region provided on the insulating film, the first being located on the first portion of the semiconductor mesa. An insulating buried region having one opening and a second opening located on the second portion of the semiconductor mesa, an insulating covering layer covering the second opening of the insulating buried region, and the insulating property An electrode in contact with the first portion of the semiconductor mesa through a first opening in the buried region; the insulating buried region; the coating layer; and an upper insulator region provided on the electrode; Provided on the upper insulator region, in front of the semiconductor main surface A conductor extending across the semiconductor mesa on the second area or the third area, the first portion and the third portion of the semiconductor mesa including a contact layer, and the semiconductor mesa The second portion does not include a contact layer, the insulating buried region includes a first resin, and the upper insulator region includes a second resin.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to one aspect of the present invention, there is provided a method of manufacturing a semiconductor optical device that enables the uppermost portion of a semiconductor mesa to be removed in a desired area. According to another aspect of the present invention, there is provided a semiconductor optical device including a semiconductor mesa that does not include a contact layer at a desired portion.

FIG. 1 is a plan view schematically showing an example of a semiconductor optical device in which a plurality of Mach-Zehnder modulators are monolithically integrated. FIG. 2 is a drawing schematically showing the arrangement of waveguide mesas and electrodes of a Mach-Zehnder modulator shown as an example of a semiconductor optical device. FIG. 3 is a drawing showing a cross section of a product in the main steps of the method for producing a semiconductor optical device according to the first embodiment. FIG. 4 is a drawing showing a cross section of a product in the main steps of the method for producing a semiconductor optical device according to the first embodiment. FIG. 5 is a drawing showing a cross section of a product in the main steps of the method for producing a semiconductor optical device according to the first embodiment. FIG. 6 is a drawing showing a cross section of a product in the main steps of the method for producing a semiconductor optical device according to the first embodiment. FIG. 7 is a drawing showing a cross-section of a product in the main steps of the method for producing a semiconductor optical device according to the first embodiment. FIG. 8 is a drawing showing a cross section of a product in the main steps of the method for producing a semiconductor optical device according to the first embodiment. FIG. 9 is a drawing showing a cross section of a product in the main steps of the method for producing a semiconductor optical device according to the first embodiment. FIG. 10 is a drawing showing a cross section of a product in the main steps of the method for producing the semiconductor optical device according to the first embodiment. FIG. 11 is a drawing showing a cross section of a product in the main steps of the method for producing a semiconductor optical device according to the first embodiment. FIG. 12 is a drawing schematically showing the semiconductor optical device according to the present embodiment. FIG. 13 is a drawing showing a cross section of a product in the main steps of the method for producing a semiconductor optical device according to the second embodiment. FIG. 14 is a drawing showing a cross section of a product in the main steps of a method for producing a semiconductor optical device according to the second embodiment. FIG. 15 is a drawing showing a cross section of a product in the main steps of a method for producing a semiconductor optical device according to the second embodiment. FIG. 16 is a drawing showing a cross section of a product in the main steps of the method for producing a semiconductor optical device according to the second embodiment. FIG. 17 is a drawing showing a cross section of a product in the main steps of a method for producing a semiconductor optical device according to the second embodiment. FIG. 18 is a drawing showing a cross section of a product in the main steps of a method for producing a semiconductor optical device according to the third embodiment. FIG. 19 is a drawing showing a cross section of a product in main steps of a method for producing a semiconductor optical device according to the third embodiment. FIG. 20 is a drawing showing a cross section of a product in the main steps of a method for producing a semiconductor optical device according to the third embodiment. FIG. 21 is a drawing showing a cross section of a product in the main steps of the method for producing a semiconductor optical device according to the third embodiment. FIG. 22 is a drawing showing a cross section of a product in the main steps of the method for producing a semiconductor optical device according to the third embodiment. FIG. 23 is a drawing schematically showing a semiconductor optical device according to the present embodiment. FIG. 24 is a drawing schematically showing a semiconductor optical device according to the present embodiment. FIG. 25 is a drawing showing a cross section of the element taken in the direction of the waveguide axis of the arm waveguide of the Mach-Zehnder modulator.

  Next, some specific examples will be described.

  A method of manufacturing a semiconductor optical device according to one aspect includes (a) a first portion, a second portion, and a third portion provided on a first area, a second area, and a third area of a semiconductor main surface, respectively. A first semiconductor mesa; a lower insulator region provided on the semiconductor main surface and covering the first semiconductor mesa; an electrode connected to the first portion of the first semiconductor mesa; and the electrode connected to the electrode Preparing a substrate product including a wiring electrode extending over the lower insulator region; (b) forming an upper insulator region on the substrate product; and (c) reaching the wiring electrode. Forming a through hole in the upper insulator region, and (d) forming a conductor on the upper insulator region after forming the through hole in the upper insulator region. The lower insulator region is the first area. The step of preparing the substrate product includes: a first opening reaching the upper surface of the first portion; and a covering portion provided on the third portion in the third area. Processing a semiconductor stack including a semiconductor layer for forming the first semiconductor mesa from the semiconductor stack, forming a structure covering a side surface and an upper surface of the semiconductor mesa, and the first semiconductor mesa Forming an etching opening in the structure that reaches the upper surface of the second portion of the structure, removing a part or all of the contact layer of the second portion, and contacting the contact with the first portion and the third portion. Processing the second portion of the first semiconductor mesa using the etching opening of the structure to leave a layer, wherein the conductor is the second portion of the semiconductor mesa or Extending the serial third portion above.

According to this method of manufacturing a semiconductor optical device, when preparing a substrate product, after forming a semiconductor mesa, a structure covering the side surface and the semiconductor main surface of the first semiconductor mesa is used to form a contact layer from the second portion. Processing to remove a part or all of. Thanks to the coating on the structure during processing, part or all of the contact layer in the second part of the first semiconductor mesa is in contact with the semiconductor layer other than the contact layer in the second part and the first part and the third part. Selectively removed. As a result of this processing step, the contact layer is left as it is in the first portion and the third portion of the first semiconductor mesa, and part or all of the contact layer is removed as a result of processing in the second portion. . Since the structure covers the semiconductor main surface during the above processing after forming the first semiconductor mesa, switching of the presence or absence of the contact layer is located on the upper surface of the first semiconductor mesa. Therefore, the above processing (contact layer processing) can be incorporated into an existing process flow including a step of forming a semiconductor mesa.
In the semiconductor optical device, light absorption caused by the dopant in the contact layer of the first semiconductor mesa is reduced in the second portion. On the other hand, the contact layer of the first portion of the first semiconductor mesa makes good electrical contact between the semiconductor stack and the electrode. Further, since the upper insulator region is formed on the insulating buried region, the electrode, and the wiring electrode, the first semiconductor mesa is formed of a conductor extending on the second portion or the third portion of the first semiconductor mesa. Separated by the upper insulator region. A conductor can extend over the upper insulator region to cross the first semiconductor mesa.

  In the method of manufacturing a semiconductor optical device according to one aspect, the step of preparing the substrate product includes forming a connection opening in the structure to reach an upper surface of the first portion of the first semiconductor mesa. The method further includes forming an insulating buried region from the structure, wherein the lower insulator region includes the insulating buried region, and the insulating buried region includes the first opening and the second area. The second opening reaching the upper surface of the second part in the first part of the first semiconductor mesa using the first opening of the insulating buried region as the connection opening. The second opening is formed as the etching opening of the structure in the step of forming an etching opening in the structure.

  According to this method of manufacturing a semiconductor optical device, the second opening of the insulating buried region for the semiconductor optical device is used to remove a part or all of the contact layer from the second portion of the first semiconductor mesa. Used. The first opening in the insulating buried region is used for connection to the contact layer in the first portion of the first semiconductor mesa.

  In the method of manufacturing a semiconductor optical device according to an aspect, the substrate product includes a second semiconductor mesa covered with the lower insulator region, and the substrate product includes the first semiconductor mesa and the second semiconductor mesa. Including a semi-insulating semiconductor substrate on which a semiconductor mesa is mounted, wherein the first semiconductor mesa and the second semiconductor mesa are provided on a conductive semiconductor region provided on a main surface of the semi-insulating semiconductor substrate, The first semiconductor mesa and the second semiconductor mesa include a conductive lower semiconductor region, a core layer, and an upper semiconductor layer connected to the conductive semiconductor region, and the contact layer is provided on the upper semiconductor layer, The insulating buried region includes a first silicon-based inorganic insulator on the first semiconductor mesa and a first resin formed on the first silicon-based inorganic insulator, and the upper insulating region is Second silicon Comprising an inorganic insulator, and a second resin formed on said second silicon-based inorganic insulation.

  According to this method for manufacturing a semiconductor optical device, the resin in the upper insulator region can provide a flat surface in the upper insulator region. In addition, the silicon-based inorganic insulator in the upper insulator region can provide the conductor with good adhesion to the base.

  A method of manufacturing a semiconductor optical device according to one aspect includes: (a) a first portion, a second portion, and a third portion provided on a first area, a second area, and a third area of a semiconductor main surface, respectively; An insulating film is grown on the semiconductor mesa including the semiconductor stack and the semiconductor main surface, and a buried region is formed on the insulating film, and the side surface of the semiconductor mesa including the insulating film and the buried region is formed. And (b) removing the insulating film and the buried region on the first area of the semiconductor main surface and the first portion of the semiconductor mesa. Forming a first opening reaching the first portion of the semiconductor mesa in the insulating buried region; and (c) after forming the first opening, on the first portion of the semiconductor mesa. Forming an electrode; (d) in front of the semiconductor main surface Removing the insulating film and the buried region on a second area to form a second opening in the insulating buried region reaching the second portion of the semiconductor mesa; and (e) the first Removing part or all of the contact layer in the semiconductor stack of the semiconductor mesa by etching using two openings, and (g) after forming the first opening, the second opening, and the electrode, Forming a conductor across the semiconductor mesa in the third area of the main semiconductor surface, the electrode being in contact with the contact layer in the first portion of the semiconductor mesa.

  According to the method for manufacturing the semiconductor optical device, the second portion of the semiconductor mesa exposed in the second opening of the insulating buried region is partially etched, so that the second portion of the semiconductor mesa is formed by the insulating buried region. A part or all of the contact layer in the semiconductor stack can be removed in the second part in the semiconductor mesa while protecting the side surface of the part. In this second portion, light absorption due to the dopant in the contact layer of the semiconductor mesa is reduced. On the other hand, the contact layer of the first portion of the semiconductor mesa makes good electrical contact between the semiconductor stack of the semiconductor mesa and the electrode. The conductor on the third area can extend over the insulating buried region and cross the semiconductor mesa in a third portion that does not have an opening in the insulating buried region.

  In the method for manufacturing a semiconductor optical device according to one aspect, the second opening is formed prior to the formation of the first opening.

  According to this method for manufacturing a semiconductor optical device, the contact layer of the second portion is removed prior to the formation of the first opening.

  A method of manufacturing a semiconductor optical device according to one aspect includes: (a) a first portion, a second portion, and a third portion provided on a first area, a second area, and a third area of a semiconductor main surface, respectively. Forming a dummy region for embedding the semiconductor mesa on the semiconductor mesa and the semiconductor main surface including the semiconductor stack; and (b) removing the dummy region on the second portion of the semiconductor mesa. Forming in the dummy region an etching opening located on the second portion of the semiconductor mesa; and (c) the semiconductor stack of the second portion of the semiconductor mesa exposed in the etching opening of the dummy region. Removing a part or all of the contact layer by etching; and (d) a step of removing the dummy region after performing the etching in the second portion of the semiconductor mesa. (E) after removing the dummy region, an insulating film is grown on the semiconductor mesa and the semiconductor main surface, and an embedded region is formed on the insulating film, and the insulating film and the embedded region are formed. Forming an insulating buried region including a region and covering the semiconductor mesa; and (f) removing the insulating film and the buried region on the first portion of the semiconductor mesa to remove the semiconductor mesa Forming a connection opening located on the first portion in the insulating buried region; and (g) forming the connection opening in the insulating buried region and then forming the connection opening in the insulating buried region. Forming an electrode on the first portion of the semiconductor mesa; and (h) a conductor crossing the semiconductor mesa in the second area or the third area of the semiconductor main surface after forming the electrode. Forming a step, before Electrode forms a contact with the contact layer in the first portion of the semiconductor mesas.

  According to this method of manufacturing a semiconductor optical device, a dummy region covering the semiconductor mesa is manufactured, and an opening located on the second portion of the semiconductor mesa is formed in the dummy region by processing the dummy region. The dummy region has an opening located on the second portion of the semiconductor mesa and covers the side surface of the semiconductor mesa. Therefore, part or all of the contact layer in the semiconductor stack can be removed from the second portion of the semiconductor mesa by etching while protecting the side surface of the semiconductor mesa from the etchant by the dummy region. In this second portion, light absorption due to the dopant in the contact layer of the semiconductor mesa is reduced. On the other hand, the contact layer of the first portion of the semiconductor mesa makes good electrical contact between the semiconductor stack and the electrode. Due to this electrical contact, the dummy region is removed after partial etching in the second portion of the semiconductor mesa and an insulating buried region is formed so as to embed the semiconductor mesa after this removal. The conductor for wiring for electrical connection can extend over the insulating buried region and cross the semiconductor mesa on the first area or the third area.

  In the method for manufacturing a semiconductor optical device according to one embodiment, the dummy region includes SOG (spin-on-glass).

  According to this method for fabricating a semiconductor optical device, a flat surface can be provided to the SOG used for embedding a semiconductor mesa.

  In the method for manufacturing a semiconductor optical device according to one aspect, the insulating film in the insulating buried region includes a silicon-based inorganic insulator, and the buried region in the insulating buried region includes a resin.

  According to this method for manufacturing a semiconductor optical device, the resin in the buried region can provide a flat surface to the insulating buried region used for filling the semiconductor mesa. In addition, the silicon-based inorganic insulator of the insulating film enables the electrode and the conductor to provide good adhesion to the base.

  A semiconductor optical device according to one aspect includes: (a) a semiconductor mesa having a first portion, a second portion, and a third portion provided on the first area, the second area, and the third area of the semiconductor main surface, respectively; (B) a first insulating layer provided on the semiconductor mesa and on the semiconductor main surface, and a buried region provided on the insulating film, the first portion located on the first portion of the semiconductor mesa; An insulating buried region having an opening and a second opening located on the second portion of the semiconductor mesa; (c) an insulating covering layer covering the second opening of the insulating buried region; d) an electrode in contact with the first portion of the semiconductor mesa through the first opening of the insulating buried region; and (e) the insulating buried region and the semiconductor mesa on the third area. And a conductor extending across the insulating embedded Band comprises a resin, said first portion and said third portion of said semiconductor mesa includes a contact layer, said second portion of said semiconductor mesa does not include a contact layer.

  According to this semiconductor optical device, a part or all of the contact layer in the semiconductor stack is removed in the first portion of the semiconductor mesa in the first opening of the insulating buried region. In this first portion, light absorption due to the dopant in the contact layer of the semiconductor mesa is reduced. On the other hand, the contact layer of the second part of the semiconductor mesa improves the electrical contact between the semiconductor stack and the electrode. The conductor can extend across the insulating buried region and the semiconductor mesa, avoiding extending over the insulating buried region and the semiconductor mesa on the second area.

  A semiconductor optical device according to one aspect includes: (a) a semiconductor mesa having a first portion, a second portion, and a third portion provided on the first area, the second area, and the third area of the semiconductor main surface, respectively; (B) a first insulating layer provided on the semiconductor mesa and on the semiconductor main surface, and a buried region provided on the insulating film, the first portion located on the first portion of the semiconductor mesa; An insulating buried region having an opening and a second opening located on the second portion of the semiconductor mesa; (c) an insulating covering layer covering the second opening of the insulating buried region; d) an electrode in contact with the first portion of the semiconductor mesa through the first opening of the insulating buried region; and (e) provided on the insulating buried region, the coating layer, and the electrode. And (f) an upper insulator region formed on the upper insulator region, A conductor extending across the semiconductor mesa on the second area or the third area of the semiconductor main surface, and the first portion and the third portion of the semiconductor mesa include a contact layer The second portion of the semiconductor mesa does not include a contact layer, the insulating buried region includes a first resin, and the upper insulator region includes a second resin.

  According to this semiconductor optical device, the conductor can extend over the upper insulator region and the insulating buried region and cross the semiconductor mesa.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, a method for producing a semiconductor optical device and the present embodiment relating to the semiconductor optical device will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

  FIG. 1 is a plan view schematically showing an example of a semiconductor optical device in which a plurality of Mach-Zehnder modulators are monolithically integrated. FIG. 2 is a drawing schematically showing the arrangement of waveguide mesas and electrodes of a Mach-Zehnder modulator shown as an example of a semiconductor optical device. Referring to FIG. 1, the semiconductor optical device 11 includes a plurality of Mach-Zehnder modulators MZ1, MZ2, MZ3, and MZ4. Mach-Zehnder-modulators MZ1, MZ2, MZ3, and MZ4 are optically coupled to the input waveguide WGIN via the first branch waveguide W1DV, the second branch waveguide W2DV, and the third branch waveguide W3DV. Input waveguide WGIN is coupled to input port LP0. Mach-Zehnder-modulators MZ1, MZ2 are optically coupled to the first output waveguide W1GT via a fourth branch waveguide W4DV, and Mach-Zehnder-modulators MZ3, MZ4 are routed via a fifth branch waveguide W5DV. And is optically coupled to the second output waveguide W2GT. The first output waveguide W1GT and the second output waveguide W2GT are coupled to the first output port LP1 and the second output port LP2, respectively. The first output port LP1 and the second output port LP2 provide an optical output (X) and an optical output (Y), respectively.

  Referring to FIG. 2, each of the Mach-Zehnder-modulators MZ1, MZ2, MZ3, and MZ4 includes an input side branch waveguide M1DV, a first arm waveguide W1ARM, a second arm waveguide W2ARM, and an output side branch waveguide M2DV. Including. In each of the Mach-Zehnder modulators MZ1, MZ2, MZ3, and MZ4, the first modulation electrode ED1M and the first phase adjustment electrode ED1P are provided on the first arm waveguide W1ARM, and the second modulation electrode ED2M and the second phase adjustment electrode ED2P is provided on the second arm waveguide W2ARM. The output of the Mach-Zehnder modulator MZ2 is combined with the output of the Mach-Zehnder modulator MZ1 via the first (π / 2) phase shifter P1SH. The output of the Mach-Zehnder modulator MZ4 is combined with the output of the Mach-Zehnder modulator MZ3 via the second (π / 2) phase shifter P2SH. The outer phase adjustment electrodes ED1PM, ED2PM, ED3PM, and ED4PM are provided on the output waveguides of the Mach-Zehnder-modulators MZ1, MZ2, MZ3, and MZ4, respectively. The modulated lights from the Mach-Zehnder modulators MZ1 and MZ2 are combined after being subjected to phase adjustment by the outer phase adjustment electrodes ED1PM and ED2PM, respectively, and the combined light propagates through the first output waveguide W1GT. The modulated lights from the Mach-Zehnder modulators MZ3 and MZ4 are combined after being subjected to phase adjustment by the outer phase adjustment electrodes ED3PM and ED4PM, respectively, and the combined light propagates through the second output waveguide W2GT.

  As shown in FIG. 1, the first transmission line EW1, the second transmission line EW2, the third transmission line EW3, and the fourth transmission line EW4 receive individual variable signals from the pad electrodes (PS1 to PS4). Are connected to the first modulation electrode EDM1 and the first phase adjustment electrode ED1P of the Mach-Zehnder-modulators MZ1, MZ2, MZ3, and MZ4, respectively. The first termination line TW1, the second termination line TW2, the third termination line TW3, and the fourth termination line TW4 are connected to pad electrodes (PT1 to PT4) for the respective terminations, and are respectively Mach-Zehnder-modulators MZ1. , MZ2, MZ3, and MZ4 are connected to the first modulation electrode ED1M. The first phase adjustment electrode ED1P and the outer phase adjustment electrode ED1PM are connected to the pad electrodes (PP1, PP2). The first transmission line EW1, the second transmission line EW2, the third transmission line EW3, the fourth transmission line EW4, the first termination line TW1, the second termination line TW2, the third termination line TW3, and the fourth termination line TW4. A part or all of the crosses the optical waveguide.

  In FIG. 2, the semiconductor optical device 11 includes a first portion 11a, a second portion 11b, and a third portion 11c. In the first portion 11a, the insulating buried region covering the semiconductor mesa for the optical waveguide has an opening on the upper surface of the semiconductor mesa. The electrode makes contact with the contact layer of the semiconductor mesa through the opening. In the second portion 11b, the semiconductor mesa for the optical waveguide does not include a contact layer in order to avoid light absorption. The third portion 11c is a region for switching from one of the first portion 11a and the second portion 11b to the other. In the third portion 11c, the semiconductor mesa includes a contact layer, but an opening for connecting electrodes. Is not provided in the insulating buried region. The third portion 11c is provided when necessary.

  A method of manufacturing the semiconductor optical device 11 according to the above embodiment will be described. In order to facilitate understanding of the relationship between the members in the manufacturing process and the counterparts of the semiconductor optical device 11, reference numerals shown in FIGS. 1 and 2 are attached to FIGS. .

  3 to 11 are drawings showing a cross section of a product in the main process of the method of manufacturing the semiconductor optical device according to the first embodiment. FIG. 3 shows a cross section taken along a line that intersects the waveguide axis of the arm waveguide in an area where a pair of arm waveguides is to be formed, which is a part of the semiconductor optical device. A substrate (for example, the substrate 13 in part (a) of FIG. 3) for preparing a semiconductor crystal is prepared. The substrate 13 can be, for example, a semi-insulating InP wafer. A plurality of semiconductor layers for the semiconductor optical device 11 (a first conductivity type semiconductor layer for the lower semiconductor layer, an i type semiconductor layer for the core layer, a second conductivity type for the upper semiconductor layer) on the substrate 13. A semiconductor layer and a highly doped semiconductor layer for the contact layer are epitaxially grown in order to form a semiconductor stack (for example, the semiconductor stack 15 of the one-dot chain line in part (a) of FIG. 3).

As shown in part (a) of FIG. 3, in step S <b> 101, a first mask 17 that defines the shape of the waveguide is formed on the semiconductor stack 15. The semiconductor stack 15 is etched using the first mask 17 to form the semiconductor mesa 19 and the first conductivity type semiconductor region 20 for the optical waveguide. The semiconductor mesa 19 is located on the first conductivity type semiconductor region 20, and the first conductivity type semiconductor region 20 is derived from the first conductivity type semiconductor layer. The semiconductor mesa 19 includes a lower semiconductor layer 21a, a core layer 21b, an upper semiconductor layer 21c, and a contact layer 21d. The first mask 17 can be, for example, SiN. The etching of the semiconductor stack 15 can be, for example, dry etching using a chlorine-based gas. After the etching, the first mask 17 is removed.
An example of the semiconductor stack 15 and the semiconductor mesa 19.
First conductive semiconductor layer for the first conductive semiconductor region 20 and the lower semiconductor layer 21a: n-type Si-doped InP.
I-type semiconductor layer for the core layer 21b: a multilayer quantum well structure comprising an AlGaInAs well layer and an AlInAs barrier layer.
Second conductivity type semiconductor layer for the upper semiconductor layer 21c: p-type Zn-doped InP.
Highly doped semiconductor layer for contact layer 21d: p-type Zn-doped GaInAs.

  After removing the first mask 17, as shown in FIG. 3B, in step S <b> 102, the second mask 23 defining the element isolation area is formed on the semiconductor mesa 19 and the first conductivity type semiconductor region 20. Form. The pattern of the second mask 23 is defined so as to separate the first conductivity type semiconductor region 20 for each Mach-Zehnder-modulator MZ1, MZ2, MZ3, MZ4, for example. The first conductive type semiconductor region 20 is etched using the second mask 23 to form element isolation mesas 25 for the Mach-Zehnder-modulators MZ1, MZ2, MZ3, and MZ4. The substrate 13 is exposed in the area. The semiconductor mesa 19 is located on the element isolation mesa 25, and the element isolation mesa 25 is derived from the first conductivity type semiconductor region 20. The second mask 23 can be, for example, SiN. The etching of the first conductive type semiconductor region 20 can be, for example, dry etching using a chlorine-based gas. After the etching, the second mask 23 is removed.

As shown in part (c) of FIG. 3, in step S103, the first insulating layer 27 is grown on the semiconductor mesa 19, the semiconductor main surface 13d (exposed area in the main surface of the substrate 13), and the element isolation mesa 25. To do. The first insulating layer 27 can be, for example, a silicon-based inorganic insulating film, and specifically is silicon oxide (for example, SiO ₂ ). A resin body 29 for the buried region of the semiconductor optical device 11 is formed on the first insulating layer 27. The formation of the resin body 29 includes, for example, a coating process and a heat treatment process after coating. The resin body 29 is provided on the upper surface and side surfaces of the semiconductor mesa 19 to embed the semiconductor mesa 19. The surface of the resin body 29 is substantially flat. The resin body 29 can be, for example, benzocyclobutene (BCB). In the present embodiment, the first insulating layer 27 and the resin body 29 constitute an insulating buried region 31. The thickness of the first insulating layer 27 is, for example, about 0.05 to 0.5 μm, and the thickness of the resin body 29 is, for example, about 3.0 to 7.5 μm on the element isolation mesa 25. The height of the semiconductor mesa 19 is, for example, about 2.0 to 3.5 μm. On the element isolation mesa 25, the thickness of the resin body 29 is larger than the height of the semiconductor mesa 19.

  Subsequent steps will be described with reference to cross sections of the first portion 19a, the second portion 19b, and the third portion 19c of the semiconductor mesa 19. The first portion 19a, the second portion 19b, and the third portion 19c of the semiconductor mesa 19 correspond to the first portion 11a, the second portion 11b, and the third portion 11c in the semiconductor optical device 11, respectively.

  In the subsequent process, the contact layer is partially removed from the second portion 19b, and an electrode in contact with the first portion 19a is formed. In this example, after the contact layer in the semiconductor mesa 9 is partially removed, the electrode that contacts the first part 19a is formed. However, the embodiment is not limited to this order.

  FIG. 4 is a drawing schematically showing a product in the step of partially removing the contact layer. Part (a), part (b) and part (c) of FIG. 4 show the processing performed in step S104 on the first part 19a, the second part 19b and the third part 19c of the semiconductor mesa 19, respectively. The first portion 19a, the second portion 19b, and the third portion 19c of the semiconductor mesa 19 are provided on the first area 13a, the second area 13b, and the third area 13c of the substrate 13, respectively. The first area 13a, the second area 13b, and the third area 13c constitute a semiconductor main surface 13d.

  In step S104, a third mask 33 for removing the contact layer of the second portion 19b of the semiconductor mesa 19 is formed. A third mask 33 is formed on the insulating buried region 31 of the product in step S103. The third mask 33 has an opening 33a on the second area 13b and the second portion 19b. The third mask 33 is provided on the first area 13a and the first portion 19a, and on the third area 13c and the third portion 19c. The resin body 29 on the first portion 19a and the third area 13c is protected. The opening 33a is provided over the second portion 19b in the extending direction of the semiconductor mesa 19, and the width MW3 of the opening 33a is preferably larger than the width W19 of the semiconductor mesa 19. The width MW3 of the opening 33a is, for example, about 1.0 to 20 μm. The width MW3 of the opening 33a and the width W19 of the semiconductor mesa 19 are defined by a method that intersects the extending method of the semiconductor mesa 19. In the method of manufacturing the semiconductor optical device 11 shown in FIG. 2, the third portion 19c is provided with the first portion 19a and the second portion 19b for switching from one of the first portion 19a and the second portion 19b to the other. Between.

Using the third mask 33, a second opening 31b reaching the upper surface of the second portion 19b is formed in the insulating buried region 31 in the second area 13b. In order to form the second opening 31 b, the pattern of the opening 33 a of the third mask 33 is transferred to the resin body 29 and the first insulating layer 27 by dry etching using the third mask 33. For the dry etching, for example, an etchant of CF ₄ / O ₂ can be used. In this step S104, the upper surface of the second portion 19b of the semiconductor mesa 19 appears in the opening 33a of the third mask 33 and the second opening 31b of the insulating buried region 31. The insulating buried region 31 having the second opening 31b covers the side surfaces of the first portion 19a, the second portion 19b, and the third portion 19c of the semiconductor mesa 19, and covers the upper surfaces of the first portion 19a and the third portion 19c. Useful as a structure. The following process is performed without removing the third mask 33.

  FIG. 5 is a drawing schematically showing a product in the process of partially removing the contact layer. Part (a), part (b) and part (c) of FIG. 5 show the processing performed in step S105 on the first part 19a, the second part 19b and the third part 19c of the semiconductor mesa 19, respectively. Second of insulating buried region 31 (a structure that covers the side surfaces of first portion 19a, second portion 19b, and third portion 19c of semiconductor mesa 19 and covers the top surfaces of first portion 19a and third portion 19c). Part or all of the contact layer 21d of the second portion 19b of the semiconductor mesa 19 is removed using the opening 31b. This removal can be performed, for example, by wet etching, and an etchant for this purpose can include, for example, a mixed aqueous solution of sulfuric acid and hydrogen peroxide (sulfuric acid / hydrogen peroxide solution / water = 3/2/40). The etching time of the 200 nm thick GaInAs layer is, for example, 7 minutes. After the wet etching for the desired etching amount (a part or all of the contact layer 21d) for the contact layer 21d is completed, the third mask 33 is removed. In this embodiment, the entire contact layer 21d of the second portion 19b is removed.

  The insulating buried region 31 (a structure that covers the side surfaces of the first portion 19a, the second portion 19b, and the third portion 19c of the semiconductor mesa 19 and covers the upper surfaces of the first portion 19a and the third portion 19c). The contact layer 21d of the first portion 19a and the third portion 19c is not etched.

  If it is necessary to ensure strict avoidance of the deterioration of the resin body that may occur during the etching of the contact layer, step S104M can be performed. In step S104M, after the pattern of the opening 33a of the third mask 33 is transferred to the resin body 29 and the first insulating layer 27 in step S104 by dry etching using the third mask 33, the contact layer 21d in step S105 is etched. It will be done in advance. FIG. 6 is a drawing schematically showing the product in step S104M. In step S104M, as shown in FIG. 6A, a protective inorganic insulating film 37 and a fourth mask 39 are formed. The inorganic insulating film 37 can include, for example, a silicon-based inorganic insulator, and is made of the same material as the first insulating layer 27 in this embodiment. After removing the first insulating layer 27 covering the upper surface of the second portion 19b, an inorganic insulating film 37 is grown to cover the upper surfaces of the resin body 29 and the second portion 19b. The fourth mask 39 has an opening 39a located on the upper surface of the second portion 19b. The width of the opening 39a (fourth width MW4) is equal to or larger than the width of the upper surface of the semiconductor mesa 19, and the edge of the opening 39a is inside the position of the outer surface of the first insulating layer 27 on the side surface of the semiconductor mesa 19. It is good to be. The inorganic insulating film 37 is etched using the fourth mask 39 to form an opening 37a in the inorganic insulating film 37 as shown in FIG. 6B. In order to facilitate accurate pattern formation for forming the fourth mask 39, the width of the opening 33a in the third mask 33 is increased, and the width of the opening 33a is preferably, for example, 1.0 μm or more. .

  After forming the inorganic insulating film 37 having the opening 37a, the contact layer 21d can be etched in the same manner as in Step S105, using the inorganic insulating film 37 as a mask.

In step S106, in order to form an electrical connection on the upper surface of the semiconductor mesa 19 (contact layer 21d of the semiconductor mesa 19), as shown in FIG. 7, the fifth mask 41 is used to form the first portion 19a. A first opening 31a reaching the upper surface is formed in the insulating buried region 31 in the first area 13a. In order to form the first opening 31a, as shown in FIG. 7B, the opening pattern 41a of the fifth mask 41 is changed to the resin body 29 and the first insulating layer by dry etching using the fifth mask 41. 27 is transferred. For the dry etching, for example, an etchant of CF ₄ / O ₂ can be used. In this step S106, the upper surface of the first portion 19a of the semiconductor mesa 19 appears in the opening pattern 41a of the fifth mask 41 and the first opening 31a of the insulating buried region 31. The insulating buried region 31 having the second opening 31b serves as a structure that covers the side surfaces of the first portion 19a, the second portion 19b, and the third portion 19c of the semiconductor mesa 19 and covers the upper surface of the third portion 19c. . In this embodiment, the order of steps in which the first opening 31a is formed after the second opening 31b is formed in the insulating buried region 31 is adopted. However, the order of production of the second opening 31b and the first opening 31a can be changed.

In the present embodiment, in order to form an electrical connection to the lower semiconductor layer 21a of the semiconductor mesa 19, the sixth mask 43 is used to form the electrical connection between the semiconductor mesas 19 as shown in FIG. A third opening 31c reaching the upper surface of the element isolation mesa 25 located at is formed in the insulating buried region 31 in the first area 13a. In order to form the third opening 31c, as shown in FIG. 8B, the pattern of the opening 43a of the sixth mask 43 is formed by the dry etching using the sixth mask 43 to form the resin body 29 and the first insulation. Transfer to layer 27. As shown in part (c) of FIG. 8, the second portion 19 b and the second area 13 b (similarly, the third portion 19 c and the third area 13 c) of the semiconductor mesa 19 are covered with the sixth mask 43. Yes. For the dry etching, for example, an etchant of CF ₄ / O ₂ can be used. The upper surface of the first conductivity type semiconductor in the element isolation mesa 25 appears in the opening 43 a of the sixth mask 43 and the third opening 31 c of the insulating buried region 31. The insulating buried region 31 is an element between the first opening 31a located in the first portion 19a of the semiconductor mesa 19, the second opening 31b located in the second portion 19b, and the semiconductor mesa 19 in the first area 13a. And a third opening 31 c located on the separation mesa 25. If possible, the first opening 31a and the third opening 31c may be formed by etching using a single mask.

FIG. 9 is a drawing schematically showing a product in a process of forming an ohmic electrode. Part (a), part (b) and part (c) of FIG. 9 show the processing performed in step S107 on the first part 19a, the second part 19b and the third part 19c of the semiconductor mesa 19, respectively. In step S107, an ohmic electrode is formed. A lift-off method is used to form the ohmic electrode. In the lift-off method, a lift-off mask having an opening pattern that defines the shape of the ohmic electrode is formed, and thereafter a metal layer for the ohmic electrode is deposited. Removing the lift-off mask leaves an ohmic electrode. In the present embodiment, the first ohmic electrode 45a is formed on the upper surface of the first portion 19a of the semiconductor mesa 19 on the first area 13a through the first opening 31a, and the semiconductor mesa on the first area 13a is formed. A second ohmic electrode 45b is formed on the upper surface of the element isolation mesa 25 between the nineteen via the third opening 31c.
First ohmic electrode 45a: TiPtAu.
Second ohmic electrode 45b: AuGeNiAu.
No ohmic electrode is formed in the second opening 31b of the second portion 19b.

  According to this method of manufacturing a semiconductor optical device, when the second portion 19 b of the semiconductor mesa 19 exposed in the second opening 31 b of the insulating buried region 31 is partially etched, the insulating buried region 31 While protecting the side surface of the second portion 19b of the semiconductor mesa 19, a part or all of the contact layer 21d in the semiconductor stack can be removed from the second portion 19b in the semiconductor mesa 19. In the second portion 19b, light absorption due to the dopant in the contact layer 21d of the semiconductor mesa 19 is reduced. The electrode (first ohmic electrode 45 a) is in contact with the contact layer 21 d of the first portion 19 a of the semiconductor mesa 19 through the first opening 31 a of the insulating buried region 31. The contact layer 21d of the first portion 19a makes good electrical contact with the electrode (first ohmic electrode 45a).

FIG. 10 is a drawing schematically showing a product in a process of forming an ohmic electrode. Part (a), part (b) and part (c) of FIG. 10 show the processing performed in step S108 on the first part 19a, the second part 19b and the third part 19c of the semiconductor mesa 19, respectively. After forming the ohmic electrode, in step S108, preparation is made for forming a conductor for the metal wiring or pad electrode. Prior to the formation of the conductor, a coating layer 47 is grown on the entire surface of the substrate, specifically, in the first area 13a, the second area 13b, and the third area 13c. The covering layer 47 can be, for example, a silicon-based inorganic insulating film, and specifically can be a silicon oxide (for example, SiO ₂ ). The covering layer 47 is provided on the second portion 19b on the second area 13b and the insulating buried region 31, and more specifically, provided on the upper surface of the second portion 19b on the second area 13b. The second opening 31b of the insertion region 31 is closed. The covering layer 47 is firmly attached to the upper surface of the second portion 19b and the inorganic insulator in the insulating embedded region 31 in the second opening 31b, thereby reducing the occurrence of film peeling of the covering layer 47 on the resin body. .

On the covering layer 47, a seventh mask 49 for defining an opening for connection to the ohmic electrode is formed. The seventh mask 49 covers the insulating buried region 31 and the coating layer 47 on the second area 13b and the third area 13c, and the first opening pattern 49a on the first ohmic electrode 45a on the first area 13a. And a second opening pattern 49b on the second ohmic electrode 45b. The covering layer 47 is etched using the seventh mask 49 to form a first connection opening 47a and a second connection opening 47c in the covering layer 47 on the first ohmic electrode 45a and the second ohmic electrode 45b, respectively. After the etching, the seventh mask 49 is removed.

  FIG. 11 is a drawing schematically showing a product in a process of forming an ohmic electrode. Part (a), part (b) and part (c) of FIG. 11 show the processing performed in step S109 on the first part 19a, the second part 19b and the third part 19c of the semiconductor mesa 19, respectively. After forming the ohmic electrode, in step S109, a conductor for the metal wiring or pad electrode is formed. An eighth mask 51 that defines the shape of the conductor, specifically, the shape of the conductor for the metal wiring or pad electrode is formed. The eighth mask 51 includes a first opening 51a for a conductor provided in the first ohmic electrode 45a on the first area 13a, a second opening 51b for a conductor provided in the second ohmic electrode 45b, and the second A third opening 51c for a conductor provided on the insulating buried region 31 on the three area 13c is provided. By the plating process using the eighth mask 51, the conductor 53 is formed in the opening defined by the eighth mask 51. In the plating step, for example, gold (Au) can be grown by plating. The conductor 53 includes a first conductor portion 53a (53) connected to the first ohmic electrode 45a on the first area 13a via the first connection opening 47a, and the second ohmic electrode 45b via the second connection opening 47c. The second conductor portion 53b (53) to be connected and the third conductor portion 53c (53) extending on the insulating buried region 31 in the third area 13c are included. After the plating process, the eighth mask 51 is removed. The conductor 53 extends on the insulating buried region 31 on the third area 13c, and can cross the semiconductor mesa 19 in the third portion 19c where the insulating buried region 31 has no opening.

  Through these steps, the semiconductor optical device 11 is manufactured. FIG. 12 shows element cross sections in the first area 13a, the second area 13b, and the third area 13c referred to in the description of the manufacturing process. The semiconductor optical device 11 includes a semiconductor mesa 19, an insulating buried region 31, a coating layer 47, electrodes (45a, 53a), and a conductor 53 (53c). The semiconductor mesa 19 includes a first portion 19a, a second portion 19b, and a third portion 19c provided on the first area 13a, the second area 13b, and the third area 13c of the semiconductor main surface 13d made of semiconductor, respectively. . The insulating buried region 31 includes a first insulating layer 27 provided on the semiconductor mesa 19 and the semiconductor main surface 13d, and a resin body 29 for the buried region provided on the first insulating layer 27. . The insulating buried region 31 has a first opening 31 a located on the first portion 19 a of the semiconductor mesa 19 and a second opening 31 b located on the second portion 19 b of the semiconductor mesa 19. The covering layer 47 has an insulating property. The second opening 31b of the insulating buried region 31 is covered. The electrodes (45a, 53a) are in contact with the contact layer 21d in the first portion 19a of the semiconductor mesa 19. The electrodes (45b, 53b) are in contact with the upper surface of the semiconductor on the element isolation mesa 25 through the third opening 31c of the insulating buried region 31. The conductor 53 (53c) extends across the insulating buried region 31 and the semiconductor mesa 19 while avoiding the insulating buried region 31 and the semiconductor mesa 19 on the second area 13b. The first portion 19a and the third portion 19c of the semiconductor mesa 19 include a contact layer 21d, and the second portion 19b of the semiconductor mesa 19 does not include a contact layer.

  According to the semiconductor optical device 11, a part or all of the contact layer 21 d in the semiconductor stack 15 is removed in the second portion 19 b of the semiconductor mesa 19 in the second opening 31 b of the insulating buried region 31. In the second portion 19b, light absorption due to the dopant in the contact layer 21d of the semiconductor mesa 19 is reduced. Further, removing the contact layer 21d in the second portion 19b contributes to increasing the electrical isolation resistance between the first portions 11a. By increasing the separation resistance, it is possible to suppress degradation of the band of the electrical response of the semiconductor optical device 11. On the other hand, the contact layer 21d of the first portion 19a of the semiconductor mesa 19 makes good electrical contact between the semiconductor stack 15 and the electrodes (45a, 53a). The conductor 53 (53c) can extend over the insulating buried region 31 so as to cross the semiconductor mesa 19 while avoiding extending over the insulating buried region 31 and the semiconductor mesa 19 on the second area 13b. .

  Another method for producing the semiconductor optical device 11 according to this embodiment will be described. In order to facilitate the understanding of the relationship between the members in the following manufacturing steps and the counterparts of the semiconductor optical device 11, the reference numerals shown in FIGS. Attached.

  13-16 is drawing which shows the cross section of the product in the main processes of the method of producing the semiconductor optical element concerning 2nd Embodiment. FIG. 13 shows a cross section along a line that intersects the waveguide axis of the arm waveguide in an area that is a part of the semiconductor optical device and is to form a pair of arm waveguides. A substrate (for example, the substrate 13 in part (a) of FIG. 13) for the growth of a semiconductor crystal is prepared. A plurality of semiconductor layers for the semiconductor optical device 11 (a first conductivity type semiconductor layer for the lower semiconductor layer, an i type semiconductor layer for the core layer, a second conductivity type for the upper semiconductor layer) on the substrate 13. A semiconductor layer and a highly doped semiconductor layer for the contact layer) are grown epitaxially in order to form a semiconductor stack.

  As shown in part (a) of FIG. 13, in step S <b> 201, from the semiconductor stack (semiconductor stack 15 in FIG. 3) to the optical waveguide using photolithography and etching (first mask 17 as in step S <b> 101). A semiconductor mesa 19 and a first conductivity type semiconductor region 20 are formed. The semiconductor mesa 19 is located on the first conductivity type semiconductor region 20, and the semiconductor mesa 19 and the first conductivity type semiconductor region 20 are derived from the first conductivity type semiconductor layer. The semiconductor mesa 19 includes a lower semiconductor layer 21a, a core layer 21b, an upper semiconductor layer 21c, and a contact layer 21d.

  In step S202, as shown in part (b) of FIG. 13, a dummy region 55 that covers the semiconductor mesa 19 is formed. The dummy region 55 is formed over the entire semiconductor main surface 13d (the first area 13a, the second area 13b, and the third area 13c). Specifically, a first dummy insulating film 57 is grown to cover the first portion 19a, the second portion 19b and the third portion 19c of the semiconductor mesa 19, and the surface of the first conductivity type semiconductor region 20. The first dummy insulating film 57 can be a silicon-based inorganic insulating film, and the silicon-based inorganic insulating film can be, for example, SiN having a thickness of 500 nm grown by chemical vapor deposition. A dummy buried region 59 is formed on the first dummy insulating film 57. The dummy buried region 59 can include, for example, spin-on-glass (SOG). The SOG can be formed by coating and heat treatment after coating, and the thickness of the heat-treated SOG is a thickness that covers the side surface and top surface of the semiconductor mesa 19. It is about 500 nm. A second dummy insulating film 61 is grown on the dummy buried region 59. The second dummy insulating film 61 can be a silicon-based inorganic insulating film, and the silicon-based inorganic insulating film can be, for example, SiON grown by chemical vapor deposition. Since the semiconductor mesa 19 is embedded using SOG formed by coating and baking, the dummy region 55 exhibits excellent flatness to which photolithography can be applied.

In step S203, as shown in FIG. 13C, a mask 62 (for example, a resist mask) for removing the dummy buried region 59 on the second portion 19b of the semiconductor mesa 19 on the dummy region 55. ). The mask 62 covers the first portion 19a and the third portion 19c of the semiconductor mesa 19, and has a first contact opening 62a located on the second portion 19b. The dummy region 55 is processed by etching using the mask 62, and an opening 55 a located on the second portion 19 b of the semiconductor mesa 19 is formed in the dummy region 55. Specifically, the insulating film stack of SiON / SOG / SiN is etched by dry etching using CF ₄ gas to expose the upper surface on the second portion 19b. The upper surface on the second portion 19b is composed of a contact layer 21d. The dummy region 55 has an opening 55a (57a, 59a, 61a) for exposing the upper surface of the second portion 19b of the semiconductor mesa 19, and covers the upper surfaces and side surfaces of the first portion 19a and the third portion 19c. The lower semiconductor layer 21a, the core layer 21b, and the upper semiconductor layer 21c in the second portion 19b of the semiconductor mesa 19 are covered with a dummy region 55. The dummy region 55 having the opening 55a serves as a structure that covers the side surfaces of the first portion 19a, the second portion 19b, and the third portion 19c of the semiconductor mesa 19 and covers the upper surfaces of the second portion 19b and the third portion 19c. . In this embodiment, the mask 62 is left after the etching.

  After the opening 55a is formed in the dummy region 55, as shown in FIG. 14A, in step S204, the contact layer 21d of the second portion 19b exposed to the opening 55a using the dummy region 55 as a mask. Remove some or all of The contact layer 21d (for example, p + type GaInAs) can be removed by, for example, wet etching, and an etchant for this purpose is, for example, a mixed aqueous solution of sulfuric acid and hydrogen peroxide (sulfuric acid / hydrogen peroxide water / water = 3 / 2/40). Since the present embodiment removes all of the contact layer 21d of the second portion 19b, the upper surface of the etched second portion 19b is composed of the upper semiconductor layer 21c.

  In step S205, after removing the contact layer 21d, as shown in FIG. 14B, after the etching, the mask 62 (resist mask) and the dummy region 55 are removed. The resist mask is peeled off by O 2 plasma treatment, and the dummy region 55 (SiON / SOG / SiN) is removed by buffered hydrofluoric acid (BHF). By removing the dummy region 55, the semiconductor mesa 19 and the first conductivity type semiconductor region 20 are exposed.

  After the dummy region 55 is removed, as shown in FIG. 14C, in step S206, the mask that defines the element isolation area (second mask 23 in step S102) is used as the semiconductor mesa 19 and the first conductivity type. It is formed on the semiconductor main surface of the semiconductor region 20. Like the second mask 23, this mask can be SiN, for example. By etching, an element isolation mesa 25 is formed for each Mach-Zehnder-modulator MZ1, MZ2, MZ3, MZ4. The substrate 13 is exposed in the area between the element isolation mesas 25 by forming the element isolation mesas 25 that isolate the first conductive type semiconductor regions 20 for each of the Mach-Zehnder modulators MZ1, MZ2, MZ3, and MZ4. The semiconductor mesa 19 is located on the element isolation mesa 25, and the element isolation mesa 25 is derived from the first conductivity type semiconductor region 20. After the element isolation mesa is formed, the second mask 23 for element isolation is removed.

  As shown in FIG. 15A, in step S207, the first insulating layer 27 is formed on the semiconductor main surface such as the semiconductor mesa 19 and the exposed area in the semiconductor main surface 13d of the substrate 13 and the element isolation mesa 25. grow up. The first insulating layer 27 can be, for example, a silicon-based inorganic insulating film, and specifically can be silicon nitride (eg, SiN). A resin body 29 for the buried region of the semiconductor optical device 11 is formed on the first insulating layer 27. The formation of the resin body 29 includes, for example, a coating process and a heat treatment process after coating. The resin body 29 is provided on the upper surface and side surfaces of the semiconductor mesa 19 to embed the semiconductor mesa 19. The surface of the resin body 29 can be substantially flat. The resin body 29 can be, for example, benzocyclobutene (BCB). In the present embodiment, the first insulating layer 27 and the resin body 29 constitute an insulating buried region 63. The insulating buried region 63 includes a first insulating layer 27 and a resin body 29 that cover the semiconductor mesa 19.

  In step S208, in order to form an electrical connection to the upper surface of the first portion 19a of the semiconductor mesa 19 (contact layer 21d of the semiconductor mesa 19), as shown in FIG. Using the fifth mask 41) in S106, a first contact opening 63a (opening like the first opening 31a) reaching the upper surface of the first portion 19a is formed in the insulating buried region 63 in the first area 13a. . In the present embodiment, in order to form an electrical connection to the lower semiconductor layer 21a of the semiconductor mesa 19, as shown in FIG. 15B, the element isolation mesa 25 positioned between the semiconductor mesas 19 A third contact opening 63c (opening like the third opening 31c) reaching the upper surface is formed in the insulating buried region 63 in the first area 13a. The first contact openings 63a and 63b are formed by dry etching using a mask (the fifth mask 41 in step S106). The insulating buried region 63 is different from the insulating buried region 31 in that the insulating buried region 31 has a second opening 31b in addition to the first opening 31a and the third opening 31c on the first portion 19a. .

  In the subsequent process, the first contact opening 63a and the third contact opening 63c of the insulating buried region 63 are respectively formed on the upper surface of the first portion 19a of the semiconductor mesa 19 on the first area 13a. A first ohmic electrode 45a that is in contact with each other through one contact opening 63a is formed, and a third contact opening 63c in the insulating buried region 63 is formed on the upper surface of the element isolation mesa 25 between the semiconductor mesas 19 on the first area 13a. A second ohmic electrode 45b is formed in contact with each other. The upper surfaces of the second portion 19 b and the third portion 19 c are covered with an insulating buried region 63. There is no electrode connection between the second portion 19b and the third portion 19c.

  According to the method of manufacturing the semiconductor optical device 11, the insulating buried region 63 covers the second portion 19 b of the semiconductor mesa 19, but the dummy region 55 is formed prior to the formation of the insulating buried region 63. While protecting the side surface of the second portion 19b of the semiconductor mesa 19 with the insulating buried region 31, a part or all of the contact layer 21d in the semiconductor stack is removed. In the second portion 19b, light absorption due to the dopant in the contact layer 21d of the semiconductor mesa 19 is reduced. On the other hand, the electrode (first ohmic electrode 45 a) is in contact with the contact layer 21 d of the first portion 19 a of the semiconductor mesa 19 through the first contact opening 63 a of the insulating buried region 63. The contact layer 21d of the first portion 19a makes good electrical contact with the electrode (first ohmic electrode 45a).

  After the formation of the ohmic electrode, preparation for forming a conductor for the metal wiring or the pad electrode is performed. As shown in FIG. 16A, in step S210, prior to the formation of the conductor, the entire surface of the substrate, specifically, the first area 13a, the second area 13b, and the third area 13c are covered. Layer 47 is grown. Since the upper surfaces of the second portion 19b and the third portion 19c are covered with the insulating buried region 63, the covering layer 47 is formed of the insulating buried region 63 and the electrodes (the first ohmic electrode 45a and the second ohmic electrode). 45b) is grown on. After this growth, an opening mask 65 is formed in the same manner as the seventh mask 49. The opening mask 65 is formed on the opening located on the first ohmic electrode 45a on the upper surface of the first portion 19a on the first area 13a and the second ohmic electrode 45b on the surface of the element isolation mesa 25 on the first area 13a. With an opening located. The covering layer 47 is etched using the opening mask 65 to form a first connection opening 47a and a second connection opening 47c reaching the first ohmic electrode 45a and the second ohmic electrode 45b, respectively, in the covering layer 47. After the etching, the mask is removed. The upper surfaces of the second portion 19 b and the third portion 19 c are covered with the covering layer 47 and the insulating buried region 63.

After forming the first ohmic electrode 45a and the second ohmic electrode 45b and the first connection opening 47a and the second connection opening 47c, in step S211, a conductor for the metal wiring or the pad electrode is formed. A plating mask 67 that defines the shape of the conductor, specifically, the shape of the conductor for the metal wiring or pad electrode is formed.
The plating mask 67 includes a first opening 67a for a conductor provided in the first ohmic electrode 45a on the first area 13a, a second opening 67b for a conductor provided in the second ohmic electrode 45b, and a third. A third opening (for example, the third opening 51c in FIG. 11) for the conductor provided on the insulating buried region 63 on the area 13c (and / or the second area 13b) is provided. Through the plating process using the plating mask 67, the conductor 53 is formed in the opening defined by the plating mask 67. In the plating step, for example, gold (Au) can be grown by plating. The conductor 53 includes a first conductor portion 53a (53) connected to the first ohmic electrode 45a on the first area 13a via the first connection opening 47a, and the second ohmic electrode 45b via the second connection opening 47c. The second conductor portion 53b (53) to be connected and the third conductor portion 53c (53) extending on the insulating buried region 31 of the third area 13c (and / or the second area 13b) are included. After the plating process, the plating mask 67 is removed. The conductor 53 extends on the insulating buried region 63 and can cross the semiconductor mesa 19 in the second portion 19b and the third portion 19c where the insulating buried region 63 does not have an opening.

  According to the method of manufacturing the semiconductor optical device 11, the dummy region 55 that covers the semiconductor mesa 19 is manufactured, and the opening 55 a located on the second portion 19 b of the semiconductor mesa 19 is formed in the dummy region by processing the dummy region 55. 55. The dummy region 55 has an opening 55 a located on the second portion 19 b of the semiconductor mesa 19 and covers the side surface of the semiconductor mesa 19. Therefore, part or all of the contact layer 21 d in the semiconductor stack can be removed from the second portion 19 b of the semiconductor mesa 19 by etching while protecting the side surface of the semiconductor mesa 19 from the etchant by the dummy region 55. In the second portion 19b, light absorption due to the dopant in the contact layer 21d of the semiconductor mesa 19 is reduced. On the other hand, the contact layer 21d in the first portion 19a of the semiconductor mesa 19 makes good electrical contact between the semiconductor stack and the electrode. Due to this electrical contact, the dummy region 55 is removed after partial etching in the second portion 19b of the semiconductor mesa 19, and the insulating buried region 63 is formed so as to bury the semiconductor mesa 19 after this removal. Is done. A conductor 53 for wiring for electrical connection can extend over the insulating buried region 63 and cross the semiconductor mesa on the second area 13b or the third area 12c.

  A further method for producing the semiconductor optical device 11 according to the embodiment will be described. 17 to 21 are drawings showing a cross section of a product in the main steps of the method for producing a semiconductor optical device according to the second embodiment. In order to facilitate the understanding of the relationship between the members in the following manufacturing steps and the counterparts of the semiconductor optical device 11, the reference numerals shown in FIGS. Attached.

  In step S301, a substrate product is prepared. As shown in FIG. 17, the substrate product includes a semiconductor mesa 19 provided on the semiconductor main surface 13d, a lower insulator region 71 provided on the semiconductor main surface 13d and covering the semiconductor mesa 19, and the semiconductor mesa 19 The first ohmic electrode 45a provided above, the second ohmic electrode 45b provided on the element isolation mesa 25, and the wiring electrode connected to electrodes such as the first ohmic electrode 45a and extending on the lower insulator region 71 (Wiring electrode 73 in FIG. 18).

  Step S301 includes, for example, a first step, a second step, a third step, and a fourth step. In the first step, as described with reference to FIG. 3 and step S101, the semiconductor stack 15 including the semiconductor layer for the contact layer 21d is processed, and the semiconductor mesa 19 is formed from the semiconductor stack 15.

  In the second step, a structure (insulating embedded region 31) that has a second opening 31 b that exposes the second portion 19 b and covers the first portion 19 a and the third portion 19 c of the semiconductor mesa 19 and the side surface of the semiconductor mesa 19. ). Specifically, as described with reference to FIG. 5 and step S105, the insulating embedded region 31 having the second opening 31b is formed by the first portion 19a, the second portion 19b, and the third portion of the semiconductor mesa 19. It serves as a structure that covers the side surfaces of 19c and covers the upper surfaces of the first portion 19a and the third portion 19c. Alternatively, as described with reference to part (c) of FIG. 13 and step S203, the dummy region 55 having the opening 55a is formed on the side surfaces of the first portion 19a, the second portion 19b, and the third portion 19c of the semiconductor mesa 19. And serves as a structure that covers the top surfaces of the first portion 19a and the third portion 19c.

  In the third step, the semiconductor mesa 19 is processed using the above structure to remove a part or all of the contact layer 21d of the second portion 19b. Specifically, as described with reference to FIG. 5 and step S105, the insulating embedded region 31 (covers the side surfaces of the first portion 19a, the second portion 19b, and the third portion 19c of the semiconductor mesa 19, Part or all of the contact layer 21d of the second portion 19b of the semiconductor mesa 19 is removed using the second opening 31b of the structure covering the upper surfaces of the first portion 19a and the third portion 19c. Alternatively, as described with reference to part (a) of FIG. 14 and step S204, a part or all of the contact layer 21d of the second portion 19b exposed to the opening 55a is removed using the dummy region 55 as a mask. To do.

In the fourth step, an electrode (first ohmic electrode 45a) is in contact with the contact layer 21d in the first portion 19a of the semiconductor mesa 19 through the first contact openings 31a and 63a of the insulating buried regions 31 and 63. Form. Specifically, as described with reference to FIG. 9 and step S107, the first ohmic electrode is in contact with the upper surface of the first portion 19a of the semiconductor mesa 19 on the first area 13a through the first opening 31a. 45a is formed, and a second ohmic electrode 45b is formed on the upper surface of the element isolation mesa 25 between the semiconductor mesas 19 on the first area 13a through the third opening 31c. Alternatively, as described with reference to part (c) of FIG. 15 and step S209 , the first contact opening 63a of the insulating buried region 63 is formed on the upper surface of the first portion 19a of the semiconductor mesa 19 on the first area 13a. The first ohmic electrode 45a is formed to be in contact with each other, and the upper surface of the element isolation mesa 25 between the semiconductor mesas 19 on the first area 13a is contacted through the third contact opening 63c of the insulating buried region 63. A second ohmic electrode 45b is formed.

As can be understood from these descriptions , the preparation process from step S101 to step S108 can be used and the preparation process from step S201 to step S209 can be used to prepare a substrate product. FIG. 17 shows a substrate product obtained from the manufacturing process of steps S101 to S108. Part (a) of FIG. 17 shows a cross section of the product in the second area 13b , and part (b) of FIG. 17 shows a cross section of the product in the first area 13a . The lower insulator region 71 includes a coating layer 47 provided on the second portion 19b in the second area, a first opening 71a reaching the upper surface of the first portion 19a in the first area 13a, and a first area 13a. And a third opening 71c reaching the upper surface of the element isolation mesa 25.

  In step S302, as shown in FIG. 18, a wiring electrode 73 extending on the lower insulator region 71 is formed so as to be connected to an electrode such as the first ohmic electrode 45a for the production of the substrate product. To do. The wiring electrode 73 is formed using a pattern mask 75 that defines a plating pattern. The pattern mask 75 has a first opening 75a for a wiring electrode connected to the first ohmic electrode 45a on the first area 13a and a second opening 75b for a wiring electrode connected to the second ohmic electrode 45b. . Through the plating process using the pattern mask 75, the wiring electrode 73 is formed in the opening defined by the pattern mask 75. In the plating step, for example, gold (Au) can be grown by plating. The wiring electrode 73 includes a first wiring electrode portion 73a (73) connected to the first ohmic electrode 45a on the first area 13a via the first opening 71a, and a second electrode 71b connected to the second ohmic electrode 45b via the second opening 71b. 2 wiring electrode part 73b (73) is included. After the plating process, the pattern mask 75 is removed. As a result of this step, the substrate product is produced.

  In the following description, a subsequent process is applied to a substrate product manufactured by applying the manufacturing process from step S101 to step S108. Referring to FIG. 18, the lower insulator region 71 includes the insulating buried region 31. A first opening 71a reaching the upper surface of the first portion 19a in the first area 13a, a second opening 71b reaching the upper surface of the second portion 19b in the second area, and an element isolation mesa 25 in the first area 13a. And a third opening 71c that reaches the upper surface of the substrate. The lower insulator region 71 covers the upper surface of the third portion 19c in the third area 13c. According to the method for manufacturing the semiconductor optical device 11, the second opening 31b of the insulating buried region 31 for the semiconductor optical device extends from the second portion 19b of the semiconductor mesa 19 to a part or all of the contact layer 21d. Used to remove. The first opening 31 a of the insulating buried region 31 is used for connection to the contact layer 21 d in the first portion 19 a of the semiconductor mesa 19.

In step S303, as shown in FIG. 19, an upper insulator region 77 is formed on the substrate product. 19A shows a cross section showing the second portion 19b of the semiconductor mesa 19, and FIG. 19B shows a cross section showing the first portion 19a of the semiconductor mesa 19. In this embodiment, the second insulating layer 79 is grown on the substrate product. The second insulating layer 79 can be, for example, a silicon-based inorganic insulating film, and specifically, can be silicon oxide (for example, SiO ₂ ). Specifically, as shown in FIG. 19B, the surface of the wiring electrode 73 is covered. A second resin body 81 for the buried region of the semiconductor optical device 11 is formed on the second insulating layer 79. The formation of the second resin body 81 includes, for example, a coating process and a heat treatment process after coating. The second resin body 81 can be, for example, benzocyclobutene (BCB). A third insulating layer 83 is grown on the second resin body 81. The third insulating layer 83 can be, for example, a silicon-based inorganic insulating film, and specifically, can be silicon oxide (for example, SiO ₂ ) or the like. In the present embodiment, the second insulating layer 79, the second resin body 81, and the third insulating layer 83 constitute the upper insulator region 77. The thickness of the second insulating layer 79 is, for example, about 0.1 to 0.5 μm, and the thickness of the third insulating layer 83 is, for example, about 0.1 to 0.5 μm. In the semiconductor optical device 11 including two layers of resin bodies, the thickness of the second resin body 81 is, for example, about 1.0 to 4.0 μm on the semiconductor mesa 19, while the thickness of the resin body 29 is On the element isolation mesa 25, for example, about 3.0 to 7.5 μm. The height of the semiconductor mesa 19 is, for example, about 2.0 to 3.5 μm. The thickness of the resin body 29 is preferably larger than the thickness of the second resin body 81.

  Since the second resin body 81 is formed over the entire substrate product and fills the third opening 71c of the lower insulator region 71, the surface of the second resin body 81 is substantially flat over the entire product. Can be. Due to the resin application twice, on the element isolation mesa 25 outside the third opening 71c, the first insulating layer 27, the resin body 29 and the covering layer 47, the second insulating layer 79, and the second resin body 81 are provided. And the 3rd insulating layer 83 is arranged in order. On the other hand, in the third opening 71c, although the resin is applied twice, the second insulating layer 79, the second resin body 81, and the third insulating layer 83 are sequentially formed on the second wiring electrode portion 73b (73). Arranged to form a simpler interlayer structure. Further, the second insulating layer 79, the second resin body 81, and the third insulating layer 83 are sequentially arranged on the first wiring electrode portion 73a (73).

In step S304, as shown in FIG. 20, a first through hole 77a and a second through hole 77b are formed in the upper insulator region 77. 20A shows a cross section showing the second portion 19b of the semiconductor mesa 19, and FIG. 20B shows a cross section showing the first portion 19a of the semiconductor mesa 19. A through-hole mask 85 is formed for forming the through-hole. The material of the through-hole mask 85 can be a resist, for example. The upper insulator region 77 is processed by dry etching using the through-hole mask 85. The first through hole 77a and the second through hole 77b reach the first wiring electrode portion 73a and the second wiring electrode portion 73b, respectively. Although the resin is applied twice, a laminated body including the second insulating layer 79, the second resin body 81, and the third insulating layer 83 is formed on the first wiring electrode portion 73a and the second wiring electrode portion 73b. The provided etching for forming the through hole is performed using dry etching using CF ₄ and O ₂ gas. After the first through hole 77a and the second through hole 77b are formed, the through hole mask 85 is removed.

  In step S305, as shown in FIGS. 21 and 22, after the first through hole 77a and the second through hole 77b are formed, a conductor 87 is formed on the upper insulator region 77. 21A shows a cross section showing the second portion 19b of the semiconductor mesa 19, and FIG. 21B shows a cross section showing the first portion 19a of the semiconductor mesa 19. FIG. 22 shows a cross section representing the third portion 19 c of the semiconductor mesa 19. In this embodiment, the conductor 87 is manufactured by a plating method using the second plating mask 89. When the conductor 87 is formed on the silicon-based inorganic insulator in the upper insulator region 77, good adhesion to the underlying layer can be provided. Specifically, the conductor 87 can comprise gold (Au). The first conductor portion 87a of the conductor 87 is formed so as to be connected to the first wiring electrode portion 73a located on the first portion 19a of the semiconductor mesa 19 and the first area 13a via the first through hole 77a. The second conductor portion 87b is formed so as to be connected to the element isolation mesa 25 and the second wiring electrode portion 73b located on the first area 13a via the second through hole 77b. Further, the third conductor portion 87c of the conductor 87 is formed so as to extend on the third portion 19c of the semiconductor mesa 19, and if necessary, extends on the second portion 19b of the semiconductor mesa 19. Formed as follows.

  According to the method of manufacturing the semiconductor optical device 11, when the substrate product is prepared, after the semiconductor mesa 19 is formed, a structure (for example, the lower insulator region 71) that covers the side surface and the semiconductor main surface of the semiconductor mesa 19 is formed. Is used to remove part or all of the contact layer 21d from the second portion 19b. Due to the covering of the structure (for example, the lower insulator region 71) during this processing, part or all of the contact layer 21d in the second portion 19b of the semiconductor mesa 19 is other than the contact layer 21d in the second portion 19b. The semiconductor layer and the first portion 19a and the third portion 19c are selectively removed. As a result of this processing step, the contact layer 21d is left as it is in the first portion 19a and the third portion 19c of the semiconductor mesa 19, and part or all of the contact layer 21d is processed as a result of processing in the second portion 19b. Has been removed. Since the structure (for example, the lower insulator region 71) covers the semiconductor main surface during the processing after the semiconductor mesa 19 is formed, the switching of the presence or absence of the contact layer 21d is located on the upper surface of the semiconductor mesa 19. Therefore, the above-described processing (processing of the contact layer 21d) can be taken into the existing process flow including the step of forming the semiconductor mesa 19.

  In the semiconductor optical device 11, light absorption due to the dopant in the contact layer 21d of the semiconductor mesa 19 is reduced in the second portion 19b. On the other hand, the contact layer 21d of the first portion 19a of the semiconductor mesa 19 makes good electrical contact between the semiconductor stack and the electrode. Further, since the upper insulator region 77 is formed on the insulating buried region 31, the first ohmic electrode 45a, and the wiring electrode 73, the semiconductor mesa 19 is formed on the second portion 19b or the third portion 19c of the semiconductor mesa 19. Is separated from the conductor 87 extending by the upper insulator region 77. A conductor 87 can extend over the upper insulator region 77 to cross the semiconductor mesa 19.

  23 and 24 are drawings schematically showing a semiconductor optical device manufactured by the above process. 23A shows a cross section of the element related to the second portion 19b of the semiconductor mesa 19, and FIG. 23B shows a cross section of the element related to the first portion 19a of the semiconductor mesa 19. FIG. 24 shows an element cross section relating to the third portion 19 c of the semiconductor mesa 19. The semiconductor optical device 11 includes a semiconductor mesa 19, an upper insulator region 77, a first ohmic electrode 45 a, and a conductor 87. The semiconductor mesa 19 includes a first portion 19a, a second portion 19b, and a third portion 19c provided on the first area 13a, the second area 13b, and the third area 13c of the semiconductor main surface 13d, respectively. The lower insulator region 71 includes an insulating buried region 31 and a covering layer 47. The insulating buried region 31 includes a first insulating layer 27 provided on the semiconductor mesa 19 and the semiconductor main surface 13d, and a buried region (for example, the resin body 29) provided on the first insulating layer 27. The insulating buried region 31 includes a first opening 31 a located on the first portion 19 a of the semiconductor mesa 19 and a second opening 31 b located on the second portion 19 b of the semiconductor mesa 19. The covering layer 47 is made of an insulating material, and is provided on the insulating embedded region 31, thereby covering the second opening 31b. The first ohmic electrode 45 a is in contact with the first portion 19 a of the semiconductor mesa 19 through the first opening 31 a of the insulating buried region 31. The upper insulator region 77 is provided on the insulating buried region 31, the coating layer 47, and the first ohmic electrode 45a. The conductor 87 is provided on the upper insulator region 77 and extends across the semiconductor mesa 19 on the second area 13b or the third area 13c. The first portion 19a and the third portion 19c of the semiconductor mesa 19 include a contact layer 21d, and the second portion 19b does not include a contact layer. The insulating buried region 31 includes a first resin such as BCB, and the upper insulator region 77 includes a second resin such as BCB. According to this semiconductor optical device 11, the conductor 87 can extend over the upper insulator region 77 and the insulating buried region 31 and cross the semiconductor mesa 19.

  FIG. 25 is a drawing showing a cross section of the element taken in the direction of the waveguide axis of the arm waveguide of the Mach-Zehnder modulator. In the embodiment shown in FIG. 25, the switching in the semiconductor mesa 19 is provided with a third portion 19c between the first portion 19a and the second portion 19b. The first ohmic electrode 45a is in contact with the first portion 19a through the first opening 31a, and terminates on the third portion 19c preceding the second portion 19b. The second opening 31b is provided on the second portion 19b and terminates at the boundary between the second portion 19b and the third portion 19c.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

  As described above, according to the present embodiment, there is provided a method for manufacturing a semiconductor optical device that makes it possible to remove the uppermost portion of the semiconductor mesa in a desired area. Further, according to the present embodiment, a semiconductor optical device including a semiconductor mesa that does not include a contact layer in a desired portion is provided.

DESCRIPTION OF SYMBOLS 11 ... Semiconductor optical element, 13 ... Board | substrate, 13a ... 1st area, 13b ... 2nd area, 13c ... 3rd area, 13d ... Semiconductor main surface, 19 ... Semiconductor mesa, 19a ... 1st part, 19b ... 2nd part 19c ... third portion, 27 ... first insulating layer, 29 ... resin body, 31 ... insulating buried region, 31a ... first opening, 31b ... second opening, 45a ... first ohmic electrode, 45b ... second Ohmic electrode, 47 ... covering layer, 53 ... conductor, 71 ... lower insulator region, 77 ... upper insulator region, 87 ... conductor.

Claims (10)

A method for producing a semiconductor optical device, comprising:
A first portion provided on a first area, a second area, and a third area of a semiconductor main surface; a first semiconductor mesa including a second portion and a third portion; and a first portion provided on the main surface of the semiconductor. 1. Substrate production including a lower insulator region covering one semiconductor mesa, an electrode connected to the first portion of the first semiconductor mesa, and a wiring electrode connected to the electrode and extending on the lower insulator region Preparing a product,
Forming an upper insulator region on the substrate product;
Forming a through-hole reaching the wiring electrode in the upper insulator region;
Forming a conductor on the upper insulator region after forming the through hole in the upper insulator region;
With
The lower insulator region includes a first opening reaching the upper surface of the first portion in the first area, and a covering portion provided on the third portion in the third area,
The step of preparing the substrate product comprises:
Processing a semiconductor stack including a semiconductor layer for a contact layer to form the first semiconductor mesa from the semiconductor stack;
Forming a structure covering a side surface and an upper surface of the semiconductor mesa;
Forming an etching opening in the structure that reaches an upper surface of the second portion of the first semiconductor mesa;
The etching opening of the structure is used to remove the contact layer in the first portion and the third portion while removing a part or all of the contact layer of the second portion, and to form the first semiconductor mesa. Processing the second portion;
Including
A method of fabricating a semiconductor optical device, wherein the conductor extends on the first portion or the third portion of the semiconductor mesa. The step of preparing the substrate product includes the step of forming a connection opening reaching the upper surface of the first portion of the first semiconductor mesa in the structure and forming an insulating buried region from the structure. Further including
The lower insulator region includes the insulating buried region, and the insulating buried region includes the first opening and a second opening reaching the upper surface of the second portion in the second area;
The electrode makes contact with the first portion of the first semiconductor mesa using the first opening of the insulating buried region as the connection opening;
The method of manufacturing a semiconductor optical device according to claim 1, wherein the second opening is formed as the etching opening of the structure in the step of forming an etching opening in the structure. The substrate product includes a second semiconductor mesa covered with the lower insulator region,
The substrate product includes a semi-insulating semiconductor substrate on which the first semiconductor mesa and the second semiconductor mesa are mounted,
The first semiconductor mesa and the second semiconductor mesa are provided on a conductive semiconductor region provided on a main surface of the semi-insulating semiconductor substrate,
The first semiconductor mesa and the second semiconductor mesa include a conductive lower semiconductor region, a core layer, and an upper semiconductor layer connected to the conductive semiconductor region, and the contact layer is provided on the upper semiconductor layer. ,
The insulating buried region includes a first silicon-based inorganic insulator on the first semiconductor mesa and a first resin formed on the first silicon-based inorganic insulator, and the upper insulating region is A method for producing a semiconductor optical device according to claim 1, comprising: a second silicon-based inorganic insulator; and a second resin formed on the second silicon-based inorganic insulator. A method for producing a semiconductor optical device, comprising:
On a semiconductor mesa having a first portion, a second portion, and a third portion provided on the first area, the second area, and the third area of the semiconductor main surface, respectively, and including the semiconductor stack, and on the semiconductor main surface Manufacturing an insulating buried region covering a side surface and an upper surface of the semiconductor mesa;
The insulating buried region on the first area of the semiconductor main surface and the first portion of the semiconductor mesa is removed, and a first opening reaching the first portion of the semiconductor mesa is formed in the insulating buried. Forming in the embedded area;
Forming an electrode on the first portion of the semiconductor mesa after forming the first opening;
Removing the insulating buried region on the second area of the semiconductor main surface to form a second opening in the insulating buried region reaching the second portion of the semiconductor mesa;
Removing part or all of the contact layer in the semiconductor stack of the semiconductor mesa by etching using the second opening;
Forming a conductor across the semiconductor mesa in the third area of the semiconductor main surface after forming the first opening, the second opening, and the electrode;
With
The method of manufacturing a semiconductor optical device, wherein the electrode is in contact with the contact layer through the first opening in the first portion of the semiconductor mesa.   The method for producing a semiconductor optical device according to claim 4, wherein the second opening is formed prior to the formation of the first opening. A method for producing a semiconductor optical device, comprising:
On the semiconductor mesa having the first portion, the second portion, and the third portion provided on the first area, the second area, and the third area of the semiconductor main surface, respectively, and including the semiconductor stack, and on the semiconductor main surface, Producing a dummy region for embedding the semiconductor mesa;
Removing the dummy region on the second portion of the semiconductor mesa to form an etching opening in the dummy region located on the second portion of the semiconductor mesa;
Removing part or all of the contact layer of the semiconductor stack of the second portion of the semiconductor mesa by etching using the etching opening of the dummy region;
Removing the dummy region after performing the etching in the second portion of the semiconductor mesa;
Producing an insulating buried region covering the semiconductor mesa after removing the dummy region;
Removing the insulating buried region on the first portion of the semiconductor mesa to form a connection opening located on the first portion of the semiconductor mesa in the insulating buried region;
Forming an electrode on the first portion of the semiconductor mesa in the connection opening of the insulating buried region after forming the connection opening in the insulating buried region;
Forming a conductor across the semiconductor mesa in the second area or the third area of the semiconductor main surface after forming the electrode;
With
A method of fabricating a semiconductor optical device, wherein the electrode makes contact with the contact layer in the first portion of the semiconductor mesa.   The method for producing a semiconductor optical device according to claim 6, wherein the dummy region comprises SOG (spin-on-glass). In the step of forming the insulating buried region, an insulating film is grown on the semiconductor mesa and the semiconductor main surface, and the buried region is formed on the insulating film,
The insulating film of the insulating embedded region includes a silicon-based inorganic insulator, and the embedded region of the insulating embedded region includes a resin. A method for producing a semiconductor optical device according to any one of the above items. A semiconductor optical device comprising:
A semiconductor mesa having a first portion, a second portion, and a third portion provided on the first area, the second area, and the third area, respectively, of the semiconductor main surface;
A first opening located on the first portion of the semiconductor mesa and the semiconductor, including an insulating film provided on the semiconductor mesa and the semiconductor main surface, and a buried region provided on the insulating film An insulating buried region having a second opening located on the second portion of the mesa;
An insulating covering layer covering the second opening of the insulating buried region;
An electrode in contact with the first portion of the semiconductor mesa through the first opening of the insulating buried region;
A conductor extending across the insulating buried region and the semiconductor mesa on the third area;
With
The insulating buried region comprises a resin;
The semiconductor optical device, wherein the first portion and the third portion of the semiconductor mesa include a contact layer, and the second portion of the semiconductor mesa does not include a contact layer. A semiconductor optical device comprising:
A semiconductor mesa having a first portion, a second portion, and a third portion provided on the first area, the second area, and the third area, respectively, of the semiconductor main surface;
A first opening located on the first portion of the semiconductor mesa and the semiconductor, including an insulating film provided on the semiconductor mesa and the semiconductor main surface, and a buried region provided on the insulating film An insulating buried region having a second opening located on the second portion of the mesa;
An insulating covering layer covering the second opening of the insulating buried region;
An electrode in contact with the first portion of the semiconductor mesa through the first opening of the insulating buried region;
An upper insulator region provided on the insulating buried region, the coating layer, and the electrode;
A conductor provided on the upper insulator region and extending across the semiconductor mesa on the second area or the third area of the semiconductor main surface;
With
The first portion and the third portion of the semiconductor mesa include a contact layer; the second portion of the semiconductor mesa does not include a contact layer;
The semiconductor optical device, wherein the insulating buried region includes a first resin and the upper insulator region includes a second resin.

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