JP6584805B2 - Information processing device - Google Patents

Description

  The present invention relates to an information processing apparatus.

  The information processing apparatus is equipped with an RTC (Real Time Clock) which is a function of keeping time even when the power is turned off, and the RTC is realized by an RTC module (for example, Patent Document 1). reference).

  The RTC module has, for example, a second counter that manages seconds and a minute counter that manages minutes. As an example, as shown in FIG. 10, the second counter updates the second count value by adding 1 to the second count value that is the count value indicating the second at the rising edge of the 1 Hz clock that is the clock of 1 Hz (Hertz). . When the second counter value of the second counter is “59”, the minute counter updates the minute count value by adding 1 to the minute count value that is the count value indicating the minute at the next rising edge of the 1 Hz clock.

  The time unit of each of hour, day, week, month, and year is managed by an hour counter, a day counter, a week counter, a month counter, and a year counter as well as seconds and minutes. At the rise of the 1 Hz clock, the hour count value, day count value, week count value, month count value, and year count value are updated.

  In this specification, for convenience of explanation, when it is not necessary to distinguish between the second counter, the minute counter, the hour counter, the day counter, the week counter, the month counter, and the year counter, they are referred to as “time counter”. Further, in this specification, for convenience of explanation, when there is no need to distinguish between the second count value, the minute count value, the hour count value, the day count value, the week count value, the month count value, and the year count value, This is referred to as “time count value”.

  By the way, the information processing apparatus is controlled by a CPU (Central Processing Unit) that operates according to a system clock. The time counter is read and written by the CPU according to the system clock. In other words, the time count value is read by the CPU according to the system clock and updated by being rewritten by the CPU according to the system clock.

JP 2006-222515 A

  However, the system clock is a frequency higher than the frequency of the 1 Hz clock (for example, several tens of kHz (kilohertz) to several GHz (gigahertz)) and asynchronous with the 1 Hz clock.

  For this reason, as shown in FIG. 11 as an example, there is a possibility that the timing of reading the second count value by the CPU overlaps with the timing of counting up the second count value, and an uncertain second count value is read by the CPU.

  As an example, as shown in FIG. 12, when the timing of rewriting the minute count value by the CPU overlaps with the timing of counting up the time count value, the 1 Hz clock is temporarily set to a low level halfway for rewriting the minute count value. Need to do. Then, the 1 Hz clock is divided, and depending on the rewrite timing, there is a possibility that the pulse width necessary for completing the count-up cannot be secured.

  An object of the present invention is to provide an information processing apparatus capable of performing time updating and reading with higher accuracy than when performing time updating and reading using only the rise of the system clock.

  In order to achieve the above object, the information processing apparatus according to claim 1 is a count value indicating a time, and is read out in synchronization with a first edge of the system clock by a central processing unit operating according to the system clock. A holding / updating unit that holds and updates the count value to be performed, and controls the holding / updating unit so that the count value is counted up in synchronization with a second edge different from the first edge of the system clock. And a control unit.

  According to the present invention, it is possible to obtain the effect that the time can be updated and read with higher accuracy than when the time is updated and read using only the rising edge of the system clock.

It is a block diagram which shows an example of the principal part structure of the information processing apparatus which concerns on 1st Embodiment. It is a schematic block diagram which shows an example of a principal part structure of RTCM contained in the information processing apparatus which concerns on 1st Embodiment. 6 is a time chart showing an example of RTCM operation timing when the time count value is updated and the time count value is read out by a CPU in the information processing apparatus according to the first embodiment. 6 is a time chart showing an example of RTCM operation timing when the time count value is updated and the time count value is rewritten by a CPU in the information processing apparatus according to the first embodiment. It is a block diagram which shows an example of the principal part structure of the information processing apparatus which concerns on 2nd Embodiment. It is a schematic block diagram which shows an example of the principal part structure of RTCM contained in the information processing apparatus which concerns on 2nd Embodiment. It is a time chart which shows an example of the operation timing of RTCM when the time count value is updated in the information processing apparatus according to the second embodiment. 9 is a time chart illustrating an example of RTCM operation timing when the time count value is updated and the time count value is read by a CPU in the information processing apparatus according to the second embodiment. 12 is a time chart illustrating an example of RTCM operation timing when the time count value is updated and the time count value is rewritten by a CPU in the information processing apparatus according to the second embodiment. It is a time chart which shows an example of the operation timing of RTCM when a time count value is updated by the conventional RTCM. It is a time chart which shows an example of the operation timing of RTCM when a time count value is updated by the conventional RTCM and a time count value is read by CPU. It is a time chart which shows an example of the operation timing of RTCM when a time count value is updated by conventional RTCM and a time count value is rewritten by CPU.

  Embodiments for carrying out the present invention will be described below in detail with reference to the drawings.

[First Embodiment]
As an example, as illustrated in FIG. 1, the information processing apparatus 10 includes a CPU 12, an RTCM (RTC module) 14, a system clock generator 18, and a 1 Hz clock generator 20. An example of the information processing apparatus 10 is a microcontroller, but is not limited thereto, and may be a personal computer or a server apparatus. In the first embodiment, the information processing apparatus 10 is a single-chip semiconductor device, but the present invention is not limited to this. For example, the CPU 12 and the RTCM 14 are separately formed into chips. It may be.

  The system clock generator 18 generates a system clock and supplies the generated system clock to the CPU 12 and the RTCM 14. The system clock is supplied not only to the CPU 12 and the RTCM 14 but also to various modules included in the information processing apparatus 10. In this embodiment, the system clock is a clock of several GHz. However, the present invention is not limited to this, and may be a clock having another frequency.

  The 1 Hz clock generator 20 generates a 1 Hz clock and supplies the generated 1 Hz clock to the RTCM 14. The 1 Hz clock is a clock asynchronous with the system clock.

  The CPU 12 controls the entire information processing apparatus 10 according to the system clock supplied from the system clock generator 18.

  The RTCM 14 measures time according to the 1 Hz clock supplied from the 1 Hz clock generator 20. That is, the RTCM 14 updates the time count value by counting up the time count value (adding 1) according to the 1 Hz clock supplied from the 1 Hz clock generator 20.

  The CPU 12 and the RTCM 14 are connected to a bus 16 including an address bus, a control bus, and a data bus. Therefore, the time count value is read from the RTCM 14 by the CPU 12 via the output data bus included in the bus 16 and rewritten by the CPU 12 via the input data bus included in the bus 16. In the present embodiment, the update of the time count value is roughly divided into an update by counting up and an update by rewriting by the CPU 12.

  The RTCM 14 has a time counter which is a BCD (Binary-coded decimal) counter for each time unit of seconds, minutes, hours, days, weeks, months, and years.

  As an example, as illustrated in FIG. 2, the time counter includes a bit time counter 14 </ b> A that is an example of a holding update unit according to the present invention. The bit time counter 14A is provided in 1-bit units, and manages the time count value for each bit.

  As an example, as shown in FIG. 2, the RTCM 14 includes a control unit 14B. The control unit 14B controls the bit time counter 14A so that the time count value is updated in synchronization with the fall of the system clock (an example of the first edge according to the present invention).

  The control unit 14B includes registers 30, 32, logical sum circuits 36, 38, and logical product circuits 40, 42, 44. The bit time counter 14 </ b> A includes a register 34, AND circuits 46, 48, 50, 52, an exclusive OR circuit 54, and selectors 56, 58. Note that the registers 30, 32, and 34 are all flip-flops. The AND circuit 52 is an example of a logic circuit according to the present invention.

  A rewrite timing signal is input from the CPU 12 to the logical sum circuit 36 via a control bus included in the bus 16. The rewrite timing signal is generated by the CPU 12 for each time unit of seconds, minutes, hours, days, weeks, months, and years, and defines the timing of rewriting the time count value of each time counter. The rewrite timing signal is a binary signal that transitions from one of the low level and the high level to the other, and the time count value is rewritten when the signal level is high.

  The rewriting timing signal is roughly classified into a second rewriting timing signal, a partial rewriting timing signal, a time rewriting timing signal, a weekly rewriting timing signal, a day rewriting timing signal, a month rewriting timing signal, and a year rewriting timing signal.

  The second rewriting timing signal is a binary signal that defines the rewriting timing of the second count value of the second counter. The minute rewriting timing signal is a binary signal that defines the timing of rewriting the minute count value of the minute counter. The time rewriting timing signal is a binary signal that defines the timing of rewriting the hour count value of the hour counter. The week rewriting timing signal is a binary signal that defines the rewriting timing of the week count value of the week counter. The month rewriting timing signal is a binary signal that defines the rewriting timing of the month count value of the month counter. The year rewriting timing signal is a binary signal that defines the rewriting timing of the year count value of the year counter.

  In the following, when there is no need to distinguish between the second rewriting timing signal, the minute rewriting timing signal, the hour rewriting timing signal, the weekly rewriting timing signal, the day rewriting timing signal, the month rewriting timing signal, and the year rewriting timing signal, This is referred to as “rewrite timing signal”.

  The logical sum circuit 36 generates a first logical sum signal indicating the logical sum of the rewrite timing signals input from the CPU 12.

  The logical product circuit 40 outputs a first logical product signal indicating the logical product of the first logical sum signal generated by the logical sum circuit 36 and the inverted system clock obtained by inverting the system clock.

  The register 30 takes in the 1 Hz clock in synchronization with the system clock, and outputs a first delay signal that is a signal obtained by delaying the fetched 1 Hz clock.

  The register 32 captures the first delay signal output from the register 30 in synchronization with the system clock, and outputs a second delay signal that is a signal obtained by delaying the captured first delay signal.

  The logical product circuit 42 outputs a second logical product signal indicating a logical product of the first delay signal output from the register 30 and the inverted delay signal obtained by inverting the second delay signal output from the register 32. .

  The logical product circuit 44 generates a third logical product signal indicating the logical product of the second logical product signal output from the logical product circuit 42 and the inverted system clock. The third AND signal is an example of a count up timing signal according to the present invention.

  The logical sum circuit 38 outputs a second logical sum signal indicating the logical sum of the first logical product signal output from the logical product circuit 40 and the third logical product signal output from the logical product circuit 44. The second logical sum signal is an example of an update signal according to the present invention.

  The register 34 stores a time count value for 1 bit. The register 34 takes in the update time count value (described later) output from the selector 58 in accordance with the second OR signal, and rewrites the currently held time count value with the fetched update time count value. To update the time count value. The time count value is read by the CPU 12 via an output data bus included in the bus 16.

  The logical product circuit 46 receives an up signal and a second logical product signal, which are binary signals that permit the count-up of the time count value stored in the register 34. The logic circuit 46 outputs a fourth logical product signal indicating the logical product of the up signal and the second logical product signal.

  The logical product circuit 48 receives a clear signal and a second logical product signal, which are binary signals for instructing to clear the time count value stored in the register 34 (return the time count value to “0”). Is done. The logical product circuit 48 outputs a fifth logical product signal indicating the logical product of the clear signal and the second logical product signal.

  The exclusive OR circuit 54 outputs an exclusive OR signal indicating the exclusive OR of the carry supplied from the bit time counter 14A of the lower digit and the time count value stored in the register 34.

  The selector 54 selectively outputs the exclusive OR signal output from the exclusive OR circuit 54 and the time count value stored in the register 34 according to the fourth AND signal.

  The logical product circuit 50 outputs a sixth logical product signal indicating the logical product of the output result of the selector 54 and the inverted logical product signal obtained by inverting the fifth logical product signal.

  The selector 58 selectively selects a sixth AND signal, which is a time count value for counting up, and a rewrite time count value input via an input data bus included in the bus 16 in accordance with a rewrite timing signal. Output as time count value for update.

  The logical product circuit 52 calculates the logical product of the carry supplied from the bit time counter 14A of the lower digit, the time count value stored in the register 34, and the inverted rewrite timing signal obtained by inverting the rewrite timing signal. A seventh logical product signal is output. The output destination of the seventh AND signal is the upper digit bit time counter 14A.

  Since the AND circuit 52 generates the seventh AND signal based on the inverted rewrite timing signal, the seventh AND signal whose signal level is high while the time count value is being rewritten. No carry is generated and the time count value is not carried.

  Next, the operation of the RTCM 14 when the time count value is read by the CPU 12 will be described with reference to FIG.

  The 1 Hz clock is taken into the register 30 in synchronization with the rising edge of the system clock, and the register 30 generates a first delay signal. The first delay signal is taken into the register 32 in synchronization with the rise of the system clock, and the register 32 generates a second delay signal that is delayed by one cycle of the system clock from the first delay signal.

  The logical product circuit 42 generates a second logical product signal indicating the logical product of the first delay signal and the inverted delay signal obtained by inverting the second delay signal. The second logical product signal generated by the logical product circuit 42 is used as a signal indicating that the rising edge of the 1 Hz clock is detected in synchronization with the system clock.

  The logical product circuit 44 generates a third logical product signal indicating a logical product (second half part of the second logical product signal) of the second logical product signal and the inverted system clock. The third AND signal generated in this way is a signal that functions in the same manner as the 1 Hz clock output in synchronization with the fall of the system clock. That is, the third logical product signal is used as a synchronization signal that defines the timing of counting up the time count value.

  In the logical product circuit 40, a first logical product signal indicating the logical product of the first logical sum signal indicating the logical sum of the rewrite timing signals and the inverted system clock is generated. The first logical product signal generated in this way is a signal that functions in the same manner as the rewrite timing signal output in synchronization with the fall of the system clock. That is, the first AND signal is used as a synchronization signal that defines the timing of rewriting the time count value by the CPU 12.

  The logical sum circuit 38 generates a second logical sum signal indicating the logical sum of the first logical product signal and the third logical product signal. Therefore, the high level period of the second logical sum signal coincides with each of the high level period of the first logical product signal (see FIG. 4) and the high level period of the third logical product signal. In the example shown in FIG. 3, since the rewrite timing signal is not supplied to the RTCM 14, the first AND signal is at the low level, and the high level period of the second OR signal is the high level of the third AND signal. It is consistent with the level period.

  Here, when reading out the second count value, the CPU 12 reads out the second count value in accordance with the second reading timing signal which is a signal for defining the reading timing. The second readout timing signal is a binary signal generated by the CPU 12, and transitions from a low level to a high level at the rising edge of the system clock (an example of the first edge according to the present invention). That is, the second readout timing signal rises ahead of the third AND signal by the half cycle of the system clock. Therefore, when the second reading timing signal rises, the second count value to be read is determined prior to counting up the second count value. When the second count value to be read is determined, the second count value is read from the register 34 by the CPU 12 during the high level period of the second read timing signal.

  The time count value is counted up in the high level period of the third AND signal that transitions from the low level to the high level at the falling edge of the system clock after the second count value to be read is determined.

  Therefore, as shown in FIG. 3, even when the high level period of the second AND signal overlaps with the high level period of the second read timing signal, the timing and second count at which the time count value to be read is determined is determined. The timing when the value is counted up does not overlap. Accordingly, it is possible to prevent the CPU 12 from reading indeterminate data that is the second count value being counted up.

  Next, the operation of the RTCM 14 when the time count value is rewritten by the CPU 12 will be described with reference to FIG. The description of the same operation as when the time count value is read by the CPU 12 is omitted.

  When rewriting the minute count value, the CPU 12 supplies a rewrite timing signal, which is a signal for defining the rewrite timing, to the RTCM 14, and supplies the rewrite minute count value to the selector 58 via the input data bus. Supply.

  Here, the rewrite timing signal changes from a low level to a high level at the rising edge of the system clock, whereas the first AND signal generated in synchronization with the third AND signal is the falling edge of the system clock. Transition from low level to high level. When the first logical product signal transitions from the low level to the high level, the CPU 12 rewrites the minute count value during the high level period of the first logical product signal in preference to counting up the minute count value.

  Similar to the example shown in FIG. 3, the time count value other than the minute count value is counted up during the high level period of the third AND signal that transitions from the low level to the high level at the falling edge of the system clock.

  Therefore, as shown in FIG. 4, even when the high level period of the second AND signal overlaps the high level period of the rewrite timing signal, the rewriting of the minute count value is completed. Further, it is avoided that the count-up of the time count value other than the minute count value becomes unstable due to the rewriting of the minute count value.

  While the minute count value is being rewritten, the AND circuit 52 of the second counter generates the seventh AND signal based on the inverted rewrite timing signal, so that the minute count value is rewritten. During this time, the signal level of the seventh AND signal does not transition to the high level. Therefore, while the minute count value is being rewritten, the carry is not supplied to the upper digit bit time counter 14A in the second counter. Note that the carry is not supplied to the upper digit bit time counter 14A, not only in the second counter but also in a time counter different from the minute counter.

  As described above, in the information processing apparatus 10, the time count value is read in synchronization with the rising edge of the system clock, and the time count value is counted up and rewritten in synchronization with the falling edge of the system clock. Therefore, the information processing apparatus 10 can update and read the time count value with higher accuracy than when updating and reading the time count value by using only the rising edge of the system clock.

  In the information processing apparatus 10, the time count value is updated by the bit time counter 14A by supplying the second logical sum signal to the bit time counter 14A in synchronization with the fall of the system clock. Therefore, the information processing apparatus 10 can realize a highly accurate update of the time count value with a simple configuration as compared with the case where the time count value is updated by the bit time counter 14A according to a signal that is not synchronized with the falling edge of the system clock. Can do.

  In the information processing apparatus 10, the time count value is rewritten according to the first logical product signal output in synchronization with the falling edge of the system clock. Further, the time count value is counted up according to the third logical product signal output in synchronization with the fall of the system clock. Therefore, the information processing apparatus 10 can realize a highly accurate update of the time count value with a simple configuration as compared with the case where the time count value is rewritten and counted up according to a signal that is not synchronized with the falling edge of the system clock. it can.

  In the information processing apparatus 10, while the minute count value is being rewritten, the carry is not supplied to the bit time counter 14A of the upper digit by the AND circuit 52 in the second counter. Therefore, the information processing apparatus 10 rewrites the minute count value as compared with the case where the carry is supplied to the bit time counter 14A of the upper digit in the second counter while the minute count value is being rewritten. It is possible to avoid a carry of the second count value in between.

  In the first embodiment, the time count value is read out in synchronization with the rising edge of the system clock, and the time count value is rewritten and counted up in synchronization with the falling edge of the system clock. The present invention is not limited to this. For example, the time count value may be read in synchronization with the falling edge of the system clock, and the time count value may be rewritten and counted up in synchronization with the rising edge of the system clock.

[Second Embodiment]
In the first embodiment, the case where the time count value is updated and read using the system clock is exemplified. However, in the second embodiment, the time count value is updated and read using the low frequency clock. Will be described. In the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  As an example, as illustrated in FIG. 5, the information processing apparatus 100 according to the second embodiment has a low-frequency clock generator 102 and the RTCM 14 compared to the information processing apparatus 10 described in the first embodiment. Instead, it has an RTCM 104.

  The low frequency clock generator 102 generates a low frequency clock that is a clock having a frequency lower than the system clock, and supplies the generated low frequency clock to the CPU 12 and the RTCM 104.

  The low frequency clock is a clock asynchronous with each of the system clock and the 1 Hz clock, and the frequency of the low frequency clock is 32768 Hz (for example, a frequency obtained by crystal oscillation). The low frequency clock of 32768 Hz is merely an example, and may be a clock having a frequency lower than the system clock and a frequency higher than 1 Hz.

  The CPU 12 controls the entire information processing apparatus 10 according to a designated clock of the system clock supplied from the system clock generator 18 and the low frequency clock supplied from the low frequency clock generator 102. The low frequency clock is a clock used by the CPU 12 when the information processing apparatus 10 shifts from the non-power saving mode to the power saving mode, for example.

  As an example, as illustrated in FIG. 6, the RTCM 104 is different from the RTCM 14 illustrated in FIG. 2 in that it includes a control unit 104B.

  The control unit 104B is different from the control unit 14B in that the logical sum circuit 36 and the logical product circuit 40 are excluded. Further, the control unit 104B has a negative OR circuit 106, a latch circuit 108 instead of the AND circuit 44, and a selector 110 instead of the OR circuit 38, as compared with the control unit 14B. Different.

  A read timing signal is input from the CPU 12 to the negative logical sum circuit 106 via a control bus included in the bus 16. The read timing signal is generated by the CPU 12 for each time unit of seconds, minutes, hours, days, weeks, months, and years, and defines the read timing of the time count value of each time counter. The read timing signal is a binary signal that transitions from one of the low level and the high level to the other. When the signal level is high, the time count value is read.

  The readout timing signal is largely the second readout timing signal, minute readout timing signal, hour readout timing signal, week readout timing signal, day readout timing signal, month readout timing signal, and year readout timing signal described in the first embodiment. Separated.

  The minute reading timing signal is a binary signal that defines the timing of reading the minute count value of the minute counter. The hour reading timing signal is a binary signal that defines the timing of reading the hour count value of the hour counter. The week read timing signal is a binary signal that defines the read timing of the week count value of the week counter. The month reading timing signal is a binary signal that defines the reading timing of the month count value of the month counter. The year reading timing signal is a binary signal that defines the reading timing of the year count value of the year counter.

  In the following, when there is no need to distinguish between the second readout timing signal, the minute readout timing signal, the hour readout timing signal, the week readout timing signal, the day readout timing signal, the month readout timing signal, and the year readout timing signal, This is referred to as “read timing signal”.

  The negative logical sum circuit 106 generates a negative logical sum signal indicating a negative logical sum of the read timing signals input from the CPU 12.

  The latch circuit 108 captures the second logical product signal in accordance with the negative logical sum signal, and outputs the captured second logical product signal to the selector 110 as a count-up clock.

  The selector 110 selectively outputs the inverted system clock and the count-up clock to the bit time counter 14A as an update timing signal that defines the timing for updating the time count value in accordance with the rewrite timing signal. That is, the selector 110 outputs the inverted system clock to the bit time counter 14A when the rewrite timing signal is input, and outputs the count-up clock to the bit time counter 14A when the rewrite timing signal is not input.

  Next, the operation of the RTCM 104 will be described with reference to FIGS.

  As an example, as shown in FIG. 7, the RTCM 104 is different from the RTCM 14 described in the first embodiment in that a second AND signal is generated according to a low-frequency clock instead of the system clock. Therefore, the second logical product signal generated by the logical product circuit 42 is used as a signal indicating that the rising edge of the 1 Hz clock is detected in synchronization with the low frequency clock.

  Here, when the second count value is read by the CPU 12, as shown in FIG. 8 as an example, a second read timing signal is input to the negative OR circuit 106. When the second readout timing signal is input to the negative OR circuit 106, the latch circuit 108 stops taking in the second logical product signal while the second count value is being read out by the CPU 12. Then, the latch circuit 108 resumes taking in the second AND signal when the CPU 12 finishes reading the second count value.

  The count-up clock generated by restarting the capture of the second AND signal by the latch circuit 108 is output to the bit time counter 14A as an update timing signal by the selector 110. The time count value is counted up by the bit time counter 14A during the high level period of the update timing signal.

  As an example, as shown in FIG. 9, when the second rewrite timing signal is input to the selector 110 while the second count value is being counted up, the selector 110 outputs the inverted system clock as the update timing signal. Is done. As a result, the update timing signal becomes low level for a half cycle of the system clock, and the second count value is rewritten during the low level period.

  As described above, in the information processing apparatus 100, the count-up clock is generated according to the low-frequency clock, so that the time count value is counted up by the bit time counter 14A at the timing defined by the low-frequency clock. . Therefore, the information processing apparatus 100 can count up the time count value even when the CPU 12 operates according to the low frequency clock.

  In the information processing apparatus 100, the time count value is counted up on condition that the reading of the time count value by the CPU 12 is completed. Therefore, even when the CPU 12 operates in accordance with the low-frequency clock, the information processing apparatus 100 can prevent the CPU 12 from reading indeterminate data that is the second count value being counted up.

  In the information processing apparatus 100, when the time count value is rewritten by the CPU 12, the time count value is rewritten according to the inverted system clock. Therefore, the information processing apparatus 100 can rewrite the time count value and count up the time count value even when the CPU 12 operates according to the low frequency clock.

  In the second embodiment, the case where only the control unit 104B controls the bit time counter 14A has been described. However, the present invention is not limited to this, and the control unit 14B and the control unit 104B are selectively connected. It may be used to control the bit time counter 14A. For example, when the RTCM 104 includes both the control unit 14B and the control unit 104B, a switch (not shown) that switches and connects the bit time counter 14A to the control unit 14B and the control unit 104B is provided, and the switch is controlled by the CPU 12. do it.

  In this case, for example, in the power saving mode, the control unit 104B is connected to the bit time counter 14A by a switch, and in the non power saving mode, the control unit 14B is connected to the bit time counter 14A by a switch. Thereby, in the power saving mode, the bit time counter 14A is controlled by the control unit 104B, and in the non power saving mode, the bit time counter 14A is controlled by the control unit 14B.

10,100 Information processing device 12 CPU
14,104 RTCM
14A bit time counters 14B and 104B Control unit 52 AND circuit

Claims (7)

A holding and updating unit that holds a count value indicating the time;
A control unit for controlling the holding update unit;
Including
The count value is a read timing signal from a central processing unit that operates according to a clock, and is read by the central processing unit according to a read timing signal that is output in synchronization with the first edge of the clock,
Wherein,
A rewrite timing signal that defines a timing of rewriting the count value of pre-Symbol central processing unit, and the rewrite timing signal output in synchronization with the different second edge and the first edge of said clock,
A count-up timing signal for defining a count-up timing of the count value, the count-up timing signal output in synchronization with the second edge;
The supplied to the holding updating unit, an information processing apparatus that performs update of the count value of the holding updater.   The holding and updating unit updates the count value by rewriting the count value according to the rewrite timing signal supplied from the control unit, and counts the count value according to the count-up timing signal supplied from the control unit The information processing apparatus according to claim 1, wherein the count value is updated by increasing the count value.   The holding / updating unit rewrites the count value in units of time according to the rewrite timing signal supplied from the control unit, and a time different from the count value to be rewritten until the count value is completely rewritten. The information processing apparatus according to claim 1, further comprising a logic circuit that prevents a carry of a unit count value. The central processing unit operates as a clock according to a designated clock of a system clock and a low frequency clock which is a clock having a frequency lower than the system clock,
The control unit controls the holding / updating unit so that the count value is counted up at a timing defined by the low frequency clock when the central processing unit operates in accordance with the low frequency clock. The information processing apparatus according to claim 3.   When the central processing unit reads out the count value, the control unit updates the holding value so that the count value is counted up on the condition that the count value is completely read out by the central processing unit. The information processing apparatus according to claim 4, which controls a unit.   When the count value is rewritten by the central processing unit, the control unit controls the holding / updating unit so that the count value is rewritten by the central processing unit at a timing defined by the system clock. The information processing apparatus according to claim 4 or 5. The first edge is a rising edge of the clock;
The information processing apparatus according to claim 1, wherein the second edge is a falling edge of the clock.

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