JP6569323B2 - Electronic apparatus thermal analysis method and thermal analysis apparatus - Google Patents

Electronic apparatus thermal analysis method and thermal analysis apparatus Download PDF

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JP6569323B2
JP6569323B2 JP2015124652A JP2015124652A JP6569323B2 JP 6569323 B2 JP6569323 B2 JP 6569323B2 JP 2015124652 A JP2015124652 A JP 2015124652A JP 2015124652 A JP2015124652 A JP 2015124652A JP 6569323 B2 JP6569323 B2 JP 6569323B2
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嘉浩 村上
嘉浩 村上
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Denso Corp
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本発明は、電子機器の熱解析方法及び熱解析装置に関する。   The present invention relates to a thermal analysis method and a thermal analysis apparatus for electronic equipment.

従来は、電子機器の放熱設計として、搭載するICのチップ全体の回路シミュレーションによりチップ全体の発熱量を見積もる、という手法を採っていた。   Conventionally, as a heat dissipation design of electronic equipment, a method of estimating the amount of heat generated by the entire chip by circuit simulation of the entire chip of the IC to be mounted has been adopted.

特開2011−237249号公報JP 2011-237249 A

IC内の熱分布も考慮した熱解析シミュレーションは正確な発熱状態を基にして熱解析を行うことができることから理想的ではあるが、その計算量が多く、現実的な時間内に完了しないため、IC内の熱分布も考慮した熱解析シミュレーションを採用することが実質的にできなかった。そのため、ICの発熱量をIC全体の最大発熱量と見積もって放熱設計を行っていた。しかし、この設計は経験に基づく設計であったため、電子機器の試作を繰り返す必要から大きなコストが発生したり、発熱量を過剰な均一温度と見積もり、放熱対策が過剰に施されたパッケージの選定を余儀なくされ、過剰な放熱経路を確保することにつながっていた。   The thermal analysis simulation considering the heat distribution in the IC is ideal because the thermal analysis can be performed based on the accurate heat generation state, but the calculation amount is large and it is not completed within a realistic time. The thermal analysis simulation considering the heat distribution in the IC could not be adopted substantially. For this reason, the heat dissipation design is performed by estimating the heat generation amount of the IC as the maximum heat generation amount of the entire IC. However, since this design was based on experience, it was necessary to repeat prototypes of electronic equipment, resulting in significant costs, estimating the amount of heat generation as excessive uniform temperature, and selecting packages with excessive heat dissipation measures. It was forced to secure an excessive heat dissipation route.

本発明は、上記課題に鑑みたものであり、その目的は、詳細な熱シミュレーションを、現実的な計算時間で実行可能とし、最適な放熱対策の設計を可能とする電子機器の熱解析方法、及び熱解析装置を提供することにある。   The present invention has been made in view of the above problems, and its purpose is to enable a detailed thermal simulation to be executed in a realistic calculation time and to design an optimum heat dissipation measure, And providing a thermal analysis apparatus.

請求項1に記載する電子機器の熱解析方法は、コンピュータにより、ICを搭載したIC搭載基板を熱解析する方法であって、IC上の回路を、前記回路の機能によるひとまとまりの回路要素ごとの複数のブロックに分割する手順と、回路シミュレーション結果から前記ブロックごとの発熱量を算出する手順と、前記IC上にレイアウトされた前記回路要素を、前記ブロックの何れかを含む複数のシート(A〜G)に分割する手順と、前記ブロックごとの発熱量を前記IC上に配置された複数の前記各シートに割り当て、前記シートごとの発熱量を算出する手順と、を備える。

The thermal analysis method for an electronic device according to claim 1 is a method for performing a thermal analysis on an IC mounting board on which an IC is mounted by a computer , wherein the circuit on the IC is divided into a group of circuit elements according to the function of the circuit. A plurality of sheets including any one of the blocks (A), a procedure for dividing the plurality of blocks, a procedure for calculating a calorific value for each block from a circuit simulation result, and the circuit elements laid out on the IC. To G), and a procedure for assigning a heat generation amount for each block to each of the plurality of sheets arranged on the IC and calculating a heat generation amount for each sheet.

請求項2に記載する熱解析装置は、ICを搭載したIC搭載基板の熱解析装置であって、前記IC上の回路を、前記回路の機能によるひとまとまりの回路要素ごとの複数のブロックに分割する手段と、回路シミュレーション結果から前記ブロックごとの発熱量を算出する手段と、前記IC上にレイアウトされた前記回路要素を、前記ブロックの何れかを含む複数のシートに分割する手段と、前記ブロックごとの発熱量を前記IC上に配置された複数の前記各シートに割り当て、前記シートごとの発熱量を算出する手段と、を備える。   The thermal analysis device according to claim 2 is a thermal analysis device for an IC mounting board on which an IC is mounted, and the circuit on the IC is divided into a plurality of blocks for each circuit element grouped by the function of the circuit. Means for calculating a heating value for each block from a circuit simulation result, means for dividing the circuit element laid out on the IC into a plurality of sheets including any of the blocks, and the block And a means for assigning a calorific value for each sheet to each of the plurality of sheets arranged on the IC and calculating a calorific value for each sheet.

この構成によれば、熱解析をIC上のすべての素子の発熱量を考慮して行わず、回路要素ごとの発熱量を基準として行う。このため、詳細な熱シミュレーションを、現実的な計算時間で実行することができ、最適な放熱対策の設計を可能とする。   According to this configuration, the thermal analysis is not performed in consideration of the heat generation amount of all the elements on the IC, but is performed based on the heat generation amount for each circuit element. For this reason, a detailed thermal simulation can be executed in a realistic calculation time, and an optimal heat dissipation measure can be designed.

ICを搭載するIC搭載基板の概略構成の一例を示す図The figure which shows an example of schematic structure of IC mounting substrate which mounts IC 回路設計の手順の一例を模式的に示したフローチャートFlow chart schematically showing an example of circuit design procedure 実施形態に係る熱解析方法の一例を示すフローチャートThe flowchart which shows an example of the thermal analysis method which concerns on embodiment 実施形態に係る熱解析方法の一例を示すフローチャートThe flowchart which shows an example of the thermal analysis method which concerns on embodiment (a)及び(b)はブロックと、シートを示すための図(A) And (b) is a figure for showing a block and a sheet | seat シートごとの発熱量を示す表Table showing calorific value for each sheet 熱解析装置の概略構成を示す図Diagram showing schematic configuration of thermal analyzer

以下、本発明を具体化した実施形態について図面を参照しながら説明する。なお、各実施形態で実質的に同一の要素には同一の符号を付し、説明を省略する。
図1に示すように、IC搭載基板100は、ボード102、ボード102上に搭載されるIC104、ボード102上に形成される配線106を備えている。IC104上には図示しない回路がレイアウトされている。本実施形態においては、IC搭載基板100の熱解析を行う。
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the substantially same element in each embodiment, and description is abbreviate | omitted.
As shown in FIG. 1, the IC mounting substrate 100 includes a board 102, an IC 104 mounted on the board 102, and a wiring 106 formed on the board 102. A circuit (not shown) is laid out on the IC 104. In the present embodiment, thermal analysis of the IC mounting substrate 100 is performed.

図2に示すように、IC設計が開始されると、まず、回路を作成し(A1)、次に、回路シミュレーションを実施し(A2)、設計した回路の動作確認を行う。その後、設計したIC回路をレイアウトする(A3)。なお、回路シミュレーション(A2)とIC回路のレイアウト(A3)の順序は入れ替えてもよい。   As shown in FIG. 2, when IC design is started, a circuit is first created (A1), then a circuit simulation is performed (A2), and the operation of the designed circuit is confirmed. Thereafter, the designed IC circuit is laid out (A3). The order of circuit simulation (A2) and IC circuit layout (A3) may be interchanged.

その後は、図示しないが、レイアウトを基にしてマスクを作成し、公知の方法により半導体チップを作成して配線、封止を行い、IC104を完成させる。次いで、IC104をボード102に搭載してIC搭載基板100を完成させる。   Thereafter, although not shown, a mask is created based on the layout, a semiconductor chip is created by a known method, wiring and sealing are performed, and the IC 104 is completed. Next, the IC 104 is mounted on the board 102 to complete the IC mounting substrate 100.

図3、及び図4は本実施形態における熱解析の手順を詳細に示したフローチャートである。図3に示すように熱解析を開始すると、まず、熱解析を行う対象である全体構成のCADデータを作成する(B1)。本実施形態においては、熱解析を行う対象は、ボード102、IC104及び配線106を含むIC搭載基板100であるため、これらを含んだ状態でのIC搭載基板100のCADデータを作成する。   3 and 4 are flowcharts showing in detail the procedure of thermal analysis in the present embodiment. When the thermal analysis is started as shown in FIG. 3, first, CAD data of the entire configuration to be subjected to the thermal analysis is created (B1). In the present embodiment, the target for thermal analysis is the IC mounting substrate 100 including the board 102, the IC 104, and the wiring 106, and therefore CAD data of the IC mounting substrate 100 including these is created.

次いで、IC部発熱量算出処理を実施する(B2)。本実施形態において発熱部はIC104であるため、IC104の発熱状況をシミュレーションにて算出する。ここでは、回路シミュレーション(A2)において行った回路動作シミュレーション結果を利用し、回路動作を行うのに必要な消費電力を算出し、これを発熱量とみなすことによりIC104の発熱量を算出する。   Next, an IC part heat generation amount calculation process is performed (B2). In this embodiment, since the heat generating part is the IC 104, the heat generation state of the IC 104 is calculated by simulation. Here, the circuit operation simulation result performed in the circuit simulation (A2) is used to calculate the power consumption necessary for performing the circuit operation, and the heat generation amount of the IC 104 is calculated by regarding this as the heat generation amount.

次いで、熱解析計算を実施する(B3)。本実施形態においては熱解析処理の内容は詳しくは説明しないが、IC104を発熱部として、ボード102、IC104及び106を搭載したIC搭載基板100全体での熱解析を実施する。   Next, thermal analysis calculation is performed (B3). Although details of the thermal analysis processing are not described in detail in the present embodiment, thermal analysis is performed on the entire IC mounting substrate 100 on which the board 102 and the ICs 104 and 106 are mounted, with the IC 104 as a heat generating portion.

図4は、IC部発熱量算出処理(B2)の内容を示したものである。図4に示すように、IC部発熱量算出処理が開始されると、まず、ICの回路を、回路のひとまとまりの機能ごと、すなわち回路要素ごとに分割し、これをそれぞれのブロックとする(C1)。これは、設計された回路を、特定の機能ごとにまとまった回路要素ごとに分けたものである。   FIG. 4 shows the contents of the IC part heat generation amount calculation process (B2). As shown in FIG. 4, when the IC unit heat generation amount calculation process is started, first, the circuit of the IC is divided into a group of functions of the circuit, that is, into each circuit element, and this is used as each block ( C1). In this method, the designed circuit is divided into circuit elements grouped according to specific functions.

次に、上記ブロックの少なくとも一つを含むようにシートを発生させる(C2)。シートは後に行う熱解析に用いる発熱量の一単位となる領域に相当し、IC104上の特定の範囲を区切る領域に相当する。次に、発生させたシートをICレイアウトの上面に配置する(C3)。続いて、各シートに、対応するブロックの発熱量を合算して割り当てる(C4)。   Next, a sheet is generated so as to include at least one of the blocks (C2). The sheet corresponds to a region serving as a unit of heat generation used for thermal analysis performed later, and corresponds to a region that delimits a specific range on the IC 104. Next, the generated sheet is placed on the upper surface of the IC layout (C3). Subsequently, the calorific value of the corresponding block is added to each sheet and assigned (C4).

図5(a)及び(b)はブロックの分割と、シートの発生を示すための図である。図5(a)に示すように、ブロックの分割は、IC104の表面にレイアウトされた回路要素のブロック11〜13、21、22、31〜34、41,42、51、52、61〜63、71〜73に分割される。次に、図5(a)及び(b)に示すように、少なくとも一つのブロックを含むように、シートA〜Gを発生させる。   FIGS. 5A and 5B are diagrams for illustrating block division and sheet generation. As shown in FIG. 5A, the division of the blocks is performed by dividing the circuit elements blocks 11 to 13, 21, 22, 31 to 34, 41, 42, 51, 52, 61 to 63, which are laid out on the surface of the IC 104. It is divided into 71-73. Next, as shown in FIGS. 5A and 5B, sheets A to G are generated so as to include at least one block.

シートは例えば一つのブロックで構成させるように発生させてもよいし、複数のブロックを含むように発生させてもよい。また、後述する熱解析装置80の計算処理能力が高い場合は、ブロックをそのままシートとみなして、ICレイアウトの上面に配置し、熱解析を行ってもよい。   For example, the sheet may be generated so as to be composed of one block, or may be generated so as to include a plurality of blocks. In addition, when the calculation processing capability of the thermal analysis device 80 described later is high, the block may be regarded as a sheet as it is and placed on the upper surface of the IC layout to perform thermal analysis.

図6は、シートの発熱量の例を示したものである。例えばシートAは、図5(a)に示すように、ブロック11〜13を包含して構成されている。シートAの発熱量はブロック11〜13の消費電力を合算したものであり、例えば1.0Wの消費電力である。また、例えばシートCは、ブロック31〜34を包含して構成されており、ブロック31〜34の消費電力の和は2.5Wである。従って、シートCの消費電力は2.5Wとする。   FIG. 6 shows an example of the heat generation amount of the sheet. For example, the sheet A includes blocks 11 to 13 as shown in FIG. The amount of heat generated by the sheet A is the sum of the power consumption of the blocks 11 to 13 and is, for example, 1.0 W of power consumption. In addition, for example, the sheet C includes blocks 31 to 34, and the sum of the power consumption of the blocks 31 to 34 is 2.5W. Accordingly, the power consumption of the sheet C is 2.5 W.

消費電力は発熱量とみなされ、本実施形態では例えばシートAの発熱量は1.0W、シートCの発熱量は2.5Wとして熱解析が実施される。他のシートB,D,E,F,Gについても同様である。   The power consumption is regarded as the heat generation amount. In this embodiment, for example, the heat analysis is performed with the heat generation amount of the sheet A being 1.0 W and the heat generation amount of the sheet C being 2.5 W. The same applies to the other sheets B, D, E, F, and G.

図7は本実施形態に係る熱解析装置80の概略構成を示しており、例えばパーソナルコンピュータにより構成されている。図7に示すように熱解析装置80は制御部82、記憶部92、操作部94及び表示部96を備えている。制御部82はCPU84、RAM86、ROM88、I/O90などを備えている。   FIG. 7 shows a schematic configuration of the thermal analysis device 80 according to the present embodiment, which is configured by a personal computer, for example. As shown in FIG. 7, the thermal analysis device 80 includes a control unit 82, a storage unit 92, an operation unit 94, and a display unit 96. The control unit 82 includes a CPU 84, a RAM 86, a ROM 88, an I / O 90, and the like.

熱解析装置80における熱解析処理は、例えばROM88に格納されたプログラムをCPU84で実行することにより実行される。熱解析装置80は、図3及び図4に示した熱解析処理を行う。すなわち、制御部82は、図3及び図4に示した各処理を実行する手段となる。   The thermal analysis process in the thermal analysis device 80 is executed by, for example, executing a program stored in the ROM 88 by the CPU 84. The thermal analysis device 80 performs the thermal analysis processing shown in FIGS. That is, the control unit 82 is a means for executing each process shown in FIGS.

なお、図2に示したIC設計も例えばパーソナルコンピュータで実現可能であるから、これをパーソナルコンピュータたる熱解析装置80に担わせることとしてもよいし、別の同様の構成を備えるコンピュータにより実現してもよい。   Since the IC design shown in FIG. 2 can also be realized by a personal computer, for example, it may be carried by the thermal analysis device 80 as a personal computer, or may be realized by a computer having another similar configuration. Also good.

以上に説明した実施形態の効果をまとめれば以下のようになる。
IC104を搭載したIC搭載基板100全体の熱解析処理において、IC104を一つの発熱体とみなして計算するのではなく、IC104に配置した複数のシートの発熱量を用いて熱解析処理を行う。このため、より実態に合致した解析結果を得ることができる。従って、必要な箇所に集中してヒートシンクなどの熱対策を施すことが可能となるなど、最適な放熱対策を設計することができるため、熱対策の無駄を回避することができる。また、本来放熱対策の必要がない箇所に過剰に放熱対策を施すなどの無駄を排除できる。
The effects of the embodiment described above are summarized as follows.
In the thermal analysis processing of the entire IC mounting substrate 100 on which the IC 104 is mounted, the thermal analysis processing is performed using the calorific values of a plurality of sheets arranged in the IC 104 instead of calculating the IC 104 as one heating element. For this reason, an analysis result more consistent with the actual situation can be obtained. Therefore, since it is possible to design an optimal heat dissipation measure, such as a heat countermeasure such as a heat sink that can be concentrated on a necessary location, waste of the heat countermeasure can be avoided. In addition, it is possible to eliminate waste such as excessive heat radiation countermeasures where no heat radiation countermeasures are originally required.

また、IC104の熱計算を、すべてのIC104上のすべての回路素子に対して行うのではなく、回路要素ごとのブロックに分割して発熱量を算出し、さらに、IC104上に設けられたシートに発熱量を割り振ったうえで、IC104を搭載するIC搭載基板100の全体で熱計算を実行する。このため、詳細な熱シミュレーションを、現実的な計算時間で実行することが可能となる。   In addition, the heat calculation of the IC 104 is not performed for all the circuit elements on all the ICs 104, but the calorific value is calculated by dividing into blocks for each circuit element, and further, on the sheet provided on the IC 104 After assigning the amount of heat generation, heat calculation is performed on the entire IC mounting substrate 100 on which the IC 104 is mounted. For this reason, it is possible to execute a detailed thermal simulation in a realistic calculation time.

本発明は、上述した実施形態に限定されるものではなく、その要旨を逸脱しない範囲で種々の実施形態に適用可能である。例えば、ボード102に一つのIC104を搭載したIC搭載基板100として説明したがこれに限定されない。ボード102上に搭載するIC104の数は任意であり、2以上の複数のIC104を搭載したIC搭載基板100に適用することができる。また、図2〜図4に示したフローチャートはその要旨を逸脱しない範囲で順序を入れ替えてもよい。   The present invention is not limited to the above-described embodiments, and can be applied to various embodiments without departing from the scope of the invention. For example, the IC mounting substrate 100 in which one IC 104 is mounted on the board 102 has been described, but the present invention is not limited to this. The number of ICs 104 mounted on the board 102 is arbitrary, and can be applied to the IC mounting substrate 100 on which two or more ICs 104 are mounted. The order of the flowcharts shown in FIGS. 2 to 4 may be changed within a range not departing from the gist thereof.

図面中、100はIC搭載基板(電子機器)、102はボード、104はIC、11〜13、21、22、31〜34、41,42、51、52、61〜63、71〜73はブロック、A,B,C,D,E,F,Gはシート、80は熱解析装置、82は制御部(各手段)を示す。     In the drawing, 100 is an IC mounting substrate (electronic device), 102 is a board, 104 is an IC, 11 to 13, 21, 22, 31 to 34, 41, 42, 51, 52, 61 to 63, and 71 to 73 are blocks. , A, B, C, D, E, F, and G are sheets, 80 is a thermal analysis device, and 82 is a control unit (each unit).

Claims (2)

コンピュータにより、IC(104)を搭載したIC搭載基板(100)を熱解析する方法であって、
IC上の回路を、前記回路の機能によるひとまとまりの回路要素ごとの複数のブロック(11〜13、21、22、31〜34、41,42、51、52、61〜63、71〜73)に分割する手順と、
回路シミュレーション結果から前記ブロックごとの発熱量を算出する手順と、
前記IC上にレイアウトされた前記回路要素を、前記ブロックの何れかを含む複数のシート(A〜G)に分割する手順と、
前記ブロックごとの発熱量を前記IC上に配置された複数の前記各シートに割り当て、前記シートごとの発熱量を算出する手順と、を備える電子機器の熱解析方法。
A method of thermally analyzing an IC mounting substrate (100) mounted with an IC (104) by a computer ,
A plurality of blocks (11-13, 21, 22, 31-34, 41, 42, 51, 52, 61-63, 71-73) for each circuit element grouped by the function of the circuit. To split it into
A procedure for calculating the amount of heat generated for each block from the circuit simulation results;
Dividing the circuit elements laid out on the IC into a plurality of sheets (A to G) including any of the blocks;
A method of assigning a heat generation amount for each block to each of the plurality of sheets arranged on the IC, and calculating a heat generation amount for each sheet.
ICを搭載したIC搭載基板の熱解析装置であって、
前記IC上の回路を、前記回路の機能によるひとまとまりの回路要素ごとの複数のブロックに分割する手段と、
回路シミュレーション結果から前記ブロックごとの発熱量を算出する手段と、
前記IC上にレイアウトされた前記回路要素を、前記ブロックの何れかを含む複数のシートに分割する手段と、
前記ブロックごとの発熱量を前記IC上に配置された複数の前記各シートに割り当て、前記シートごとの発熱量を算出する手段と、を備えることを特徴とする電子機器の熱解析装置(80)。
A thermal analysis device for an IC mounting board on which an IC is mounted,
Means for dividing a circuit on the IC into a plurality of blocks for each circuit element grouped by a function of the circuit;
Means for calculating a heating value for each block from a circuit simulation result;
Means for dividing the circuit elements laid out on the IC into a plurality of sheets including any of the blocks;
Means for assigning the amount of heat generated for each block to each of the plurality of sheets arranged on the IC, and calculating the amount of heat generated for each sheet, (80) .
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