JP6568746B2 - Distributed simulation system, simulation execution method, and control system - Google Patents

Description

  The present invention relates to a distributed simulation system, a simulation execution method, and a control system.

  A simulator used for plant operation training or the like may have a plurality of simulation models. Each simulation model repeats one cycle of simulation every time. Based on the calculation results of each simulation model over time, the simulator operator grasps the state of the plant on the simulation and performs operation control training.

  The calculation result of the simulator needs to be reproducible. That is, the simulator is required to have the same calculation result when there is the same input condition. In the case of a simulator (distributed simulation system) having a plurality of simulation models, it is important to synchronize a plurality of simulations in order to realize reproducibility. Synchronization between simulations means synchronization between elapsed times on the simulation. For example, Patent Document 1 discloses a system having a plurality of central processing units that execute simulations and a single central processing unit that includes a scheduler that controls operations of the central processing units.

JP-A-11-265297

  Here, since a plurality of simulation models execute different simulations, calculation times in one calculation cycle may be different from each other. In such a case, it is more difficult to synchronize the elapsed time on the simulation. One central processing unit of Patent Document 1 synchronizes the calculation cycles of a plurality of central processing units. However, regarding synchronization in the case where the calculation times of one central processing unit are different from each other, It is not described.

  Accordingly, the present invention provides a distributed simulation system, a simulation execution method, or a control system that appropriately synchronizes simulations in a distributed simulation system having a plurality of simulation models having different calculation times in one calculation cycle. The purpose is to do.

  In order to solve the above-described problems and achieve the object, a distributed simulation system of the present invention includes a plurality of calculation processing systems that execute simulations with different calculation times in one calculation cycle every time, and a plurality of the above-described calculation processing systems. A control processing system communicably connected to the calculation processing system, wherein the control processing system sets a processing cycle, which is a cycle in which the calculation processing system executes the simulation once, for each of the calculation processing systems. The processing cycle setting unit to be set and the calculation virtual time that is the elapsed time in one simulation are set so as to be the same as the relationship ratio between the lengths of the processing cycles for each calculation processing system. Each of the virtual time setting unit and the calculation processing system for each processing cycle set in the calculation processing system. A calculation instructing unit that transmits a calculation instruction signal and causes each of the calculation processing systems to execute a simulation for the set calculation virtual time for each of the set processing cycles. However, the processing cycle set in at least some of the calculation processing systems is different in length from the processing cycle set in other calculation processing systems.

  According to this distributed simulation system, when each processing system is operated for the same time, the elapsed time on the simulation for each calculation processing system becomes the same. Therefore, the distributed simulation system can appropriately synchronize each simulation processing system for each simulation.

  In the distributed simulation system, the calculation instruction unit transmits a calculation instruction signal at each timing for each processing cycle, so that a plurality of basic cycles each having a common multiple of the length of the processing cycle are transmitted. It is preferable that the number of simulation executions of the calculation processing system is different from each other. According to this distributed simulation system, the number of simulation processes can be set in accordance with the type of simulation and the specifications of the calculation processing system. Therefore, according to this distributed simulation system, the accuracy of simulation can be improved.

  In the distributed simulation system, the control processing system includes a calculation data acquisition unit that acquires contact data that is output data to be used as input data of the other calculation processing system among output data that is a result of the simulation. A calculation data storage unit that stores the exchange data acquired by the calculation data acquisition unit, and a plurality of the calculation processing systems are at least partially stored in the calculation data storage unit. It is preferable to acquire data and execute the simulation based on the contact data. According to this distributed simulation system, the trade data can be appropriately provided to the calculation processing system.

  In the distributed simulation system, the calculation data acquisition unit holds the acquired interaction data, and at the timing immediately before the start of the processing cycle next to the processing cycle in which the interaction data is calculated, The calculation processing system other than the calculation data storage unit that outputs to the calculation data storage unit and calculates the contact data is stored at the timing immediately before at least a part of the simulation in the processing cycle immediately after the timing immediately before. It is preferable to acquire trade data and execute the simulation based on the trade data. According to this distributed simulation system, it is possible to appropriately synchronize the acquisition of trade data.

  In the distributed simulation system, the control processing system further includes an operation information acquisition unit that acquires change request data that is information on a change request for simulation operation by an operator, and the calculation instruction unit includes the change request data. Change in the change request signal for the calculation processing system by transmitting a change request signal indicating information of the change request data to the calculation processing system at the start timing of the basic period immediately after the timing at which It is preferable to synchronize the timing of the reflection of processing with another calculation processing system. According to this distributed simulation system, since the change request by the operator is reflected in synchronization with each calculation processing system, each simulation can be appropriately synchronized.

  In the distributed simulation system, the calculation instruction unit transmits a synchronization signal to each of the calculation processing systems at a timing of each synchronization period that is a period of a common divisor of each processing period. The calculation instruction unit sets a calculation instruction flag for each of the calculation processing systems in synchronization with a synchronization signal transmitted at a timing that coincides with the processing cycle of the calculation processing system. It is preferable to set a calculation non-execution flag, which is information not to newly execute a simulation, in synchronization with a synchronization signal transmitted at a timing that does not coincide with the processing cycle. According to this distributed simulation system, since the synchronization signal is transmitted, each simulation can be appropriately synchronized.

  In the distributed simulation system, it is preferable that the control processing system includes a basic period setting unit that sets the basic period so that the period becomes a least common multiple of the lengths of the processing periods. According to this distributed simulation system, the basic period can be set as short as possible.

  In the distributed simulation system, it is preferable that the plurality of calculation processing systems are a plurality of calculation processing apparatuses each executing at least one simulation. According to this distributed simulation system, it is possible to appropriately synchronize each simulation while executing various simulations.

  In the distributed simulation system, the plurality of calculation processing systems are preferably one calculation processing device that executes the plurality of simulations. According to this distributed simulation system, control of each simulation becomes easy.

In order to solve the above-described problems and achieve the object, a simulation execution method of the present invention includes a plurality of calculation processing systems that execute simulations with different calculation times in one calculation cycle every time, and a plurality of the above-described calculation processing systems. A simulation execution method for executing a simulation using a control processing system communicably connected to a calculation processing system,
A processing cycle setting step for setting a processing cycle, which is a cycle in which the calculation processing system executes the simulation once, for each calculation processing system; and a calculation virtual time, which is an elapsed time in one simulation, For each calculation processing system, a virtual time setting step for setting the relationship ratio to be the same as the relationship ratio between the lengths of the processing cycles, and the processing set in the calculation processing system for each of the calculation processing systems A calculation instruction step of transmitting a calculation instruction signal at each timing of each cycle, and causing each of the calculation processing systems to execute the simulation for the calculation virtual time set in itself for each of the set processing cycles And in the processing cycle setting step, before being set in at least some of the calculation processing systems The processing cycle, and the processing cycle set to another computing system, varying the length. According to this simulation execution method, synchronization for each simulation can be appropriately taken.

  In order to solve the above-described problems and achieve the object, the control processing system of the present invention controls a plurality of calculation processing systems that execute simulations with different calculation times in one calculation cycle every time. A calculation cycle that is a cycle in which the calculation processing system executes the simulation once, a processing cycle setting unit that sets the processing cycle for each calculation processing system, and an elapsed time in one simulation For each of the calculation processing systems, a virtual time setting unit that sets the virtual time for each calculation processing system so as to have the same relationship ratio as the relationship ratio between the lengths of the processing cycles. A calculation instruction signal is transmitted at each timing of the set processing cycle, and set to each of the calculation processing systems. A calculation instruction unit that executes simulation for the set calculation virtual time for each of the set processing cycles, and the processing cycle set in at least some of the calculation processing systems includes other calculations. The length is different from the processing cycle set in the processing system. According to this control processing system, synchronization for each simulation can be appropriately taken.

  According to the present invention, each simulation can be appropriately synchronized.

FIG. 1 is a block diagram showing a configuration of a distributed simulation system according to the first embodiment. FIG. 2 is a time chart of a simulation executed by the calculation processing apparatus according to the first embodiment. FIG. 3 is a block diagram illustrating a configuration of the control processing device according to the first embodiment. FIG. 4 is a chart for explaining the setting of each cycle. FIG. 5 is a time chart for explaining the synchronization processing. FIG. 6 is a flowchart for explaining the synchronization processing of the control processing device. FIG. 7 is a flowchart for explaining a simulation execution process of each calculation processing apparatus. FIG. 8 is a time chart for explaining the contact synchronization processing. FIG. 9 is a flowchart for explaining the contact synchronization processing of the control processing device. FIG. 10 is a time chart for explaining the request data synchronization processing. FIG. 11 is a flowchart illustrating request data synchronization processing of the control processing device. FIG. 12 is a flowchart for explaining a simulation execution process of each calculation processing apparatus. FIG. 13 is a block diagram illustrating a configuration of a control processing device according to the second embodiment. FIG. 14 is a time chart for explaining the speed changing process.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment, Moreover, when there are two or more embodiments, what comprises a combination of each Example is also included.

(First embodiment)
First, the first embodiment will be described. FIG. 1 is a block diagram showing a configuration of a distributed simulation system according to the first embodiment. As shown in FIG. 1, the distributed simulation system 1 according to the first embodiment includes a first calculation processing device 10A, a second calculation processing device 10B, a third calculation processing device 10C, and a fourth calculation processing device 10D, and a control. It has a processing device 20 and an instructor operating device 30. Hereinafter, the first calculation processing device 10A, the second calculation processing device 10B, the third calculation processing device 10C, and the fourth calculation processing device 10D will be referred to as the calculation processing device 10 when not distinguished from each other.

  The distributed simulation system 1 is a distributed simulation system that causes each of a plurality of calculation processing devices 10 to execute a simulation under the control of the control processing device 20. The distributed simulation system 1 is used for plant operation training, particularly for nuclear power reprocessing plant operation training, but the application is not limited thereto.

(Calculation processor)
A calculation processing apparatus 10 as a calculation processing system is a processing apparatus (computer) that executes one simulation. As illustrated in FIG. 1, the calculation processing device 10 includes a communication unit 12 and a calculation processing unit 14. The communication unit 12 communicates with the control processing device 20. The communication unit 12 acquires a command for executing a simulation and input data for simulation from the control processing device 20, and outputs output data as a simulation result to the control processing device 20. The calculation processing unit 14 executes a predetermined simulation based on a command from the control processing device 20 via the communication unit 12. Note that although there are four calculation processing apparatuses 10 in the present embodiment, the number is not limited to this as long as it is plural. The calculation processing device 10 is configured by a plurality of processing devices that execute at least one type of simulation every time, but may be configured by a single processing device that executes a plurality of types of simulations. Further, the calculation processing device 10, the control processing device 20, and the instructor operation device 30 are different processing devices from each other, but may be a single processing device.

  Hereinafter, the simulation executed by the calculation processing apparatus 10 will be described. FIG. 2 is a time chart of a simulation executed by the calculation processing apparatus according to the first embodiment. As shown in FIG. 2, the simulation executed by the calculation processing device 10 includes input processing for acquiring input data from the control processing device 20, calculation processing for executing simulation (calculation) based on the input data, and results of the calculation processing. And output processing for outputting the output data to the control processing device 20. In the simulation executed by the calculation processing apparatus 10, the input process, the calculation process, and the output process are set as one calculation cycle. The simulation in the present description refers to performing the input process, the calculation process, and the output process only once. In other words, the simulation in this description has only one calculation period. The calculation processing apparatus 10 outputs the state of the plant as output data for each virtual time that is an elapsed time in the simulation by repeating this simulation a plurality of times every time.

  The calculation processing device 10 is different in the contents of the simulation to be executed. Examples of the contents of the simulation include temperature of each part in the plant, water flow of piping in the plant, valve opening, chemical reaction in the plant, control of the control device in the plant, and the like. The calculation processing apparatus 10 differs in calculation time A required for one simulation. The clock timing TA shown in FIG. 2 is a timing for explaining the length of each process, and shows the passage of time at equal intervals in the order of TA1, TA2,. In this embodiment, each clock timing TA is in increments of 0.1 seconds. That is, TA1 is the timing at the start of processing, TA2 is the timing when 0.1 second has elapsed, TA3 is the timing when 0.2 seconds have elapsed, and TA12 is the timing when 1.1 seconds have elapsed. is there.

  As illustrated in FIG. 2, when the first calculation processing device 10A receives an input processing command at the clock timing TA1, the first calculation processing device 10A executes the input processing in the time from the clock timing TA1 to TA2. Then, the first calculation processing device 10A executes the calculation process in the time from the clock timing TA2 to TA3, and executes the output process in the time from the clock timing TA3 to TA4. Clock timings TA1 to TA4 are simulation cycles of the first calculation processing apparatus 10A. That is, the calculation time AA of the first calculation processing device 10A is 0.3 seconds, which is the time from the clock timing TA1 to TA4. The first calculation processing apparatus 10A repeats this simulation every time.

  When receiving the input processing command at the clock timing TA1, the second calculation processing apparatus 10B executes the input processing in the time from the clock timing TA1 to TA2, and executes the calculation processing in the time from the clock timing TA2 to TA4. Then, output processing is executed in the time from clock timing TA4 to TA5. That is, the calculation time AB of the second calculation processing device 10B is 0.4 seconds, which is the time from the clock timing TA1 to TA5. The second calculation processing device 10B repeats this simulation every time.

  When the third processing unit 10C receives an input processing command at the clock timing TA1, the third processing unit 10C executes the input processing in the time from the clock timing TA1 to TA2, and executes the calculation processing in the time from the clock timing TA2 to TA12. Then, the output process is executed in the time from the clock timing TA12 to TA13. That is, the calculation time AC of the third calculation processing device 10C is 1.2 seconds, which is the time from the clock timing TA1 to TA13. The third calculation processing apparatus 10C repeats this simulation every time.

  When receiving the input processing command at the clock timing TA1, the fourth calculation processing device 10D executes the input processing in the time from the clock timing TA1 to TA2, and executes the calculation processing in the time from the clock timing TA2 to TA5. Then, the output process is executed in the time from the clock timing TA5 to TA6. That is, the calculation time AD of the fourth calculation processing device 10D is 0.5 seconds, which is the time from the clock timing TA1 to TA6. The fourth calculation processing device 10D repeats this simulation every time.

  Each calculation processing apparatus 10 requires the calculation time A described above to execute one simulation. However, since the calculation time A depends on the specifications of the calculation processing apparatus 10 and the contents of the simulation, the above description is an example.

  In addition, at least a part of the calculation processing device 10 uses output data (calculation result) of another calculation processing device 10 as its own input data. In the explanation example of the present embodiment, the second calculation processing device 10B uses the output data of the first calculation processing device 10A as its own input data. The second calculation processing device 10B also uses the output data of the fourth calculation processing device 10D as its own input data. Further, the third calculation processing device 10C uses the output data of the second calculation processing device 10B as its own input data.

  The simulation of the calculation processing apparatus 10 has been described above. However, these are examples, and the simulation is limited to the above description as long as simulations with different calculation times in one calculation cycle are executed every time. I can't.

(Instructor operation device)
The instructor operating device 30 is a man machine (computer) that acquires operation information from an operator (instructor). As shown in FIG. 1, the instructor operation device 30 includes an operation unit 32 and a communication unit 34. The operation unit 32 is an interface for inputting operation information from an operator, and is, for example, a computer mouse, a keyboard, a touch panel, or the like. The communication unit 34 transmits operation information from the operator to the control processing device 20. The operation information is information for setting the operation of the simulation. For example, the RUN operation for starting the simulation of all the calculation processing apparatuses 10, the FREEZE operation for stopping the simulation of all the calculation processing apparatuses 10, and the speed change for changing the simulation speed. There are operations.

(Control processing device)
The control processing device 20 as a control processing system is a processing device (computer) that is connected to the calculation processing device 10 so as to be communicable and collectively controls simulation processing of all the calculation processing devices 10. FIG. 3 is a block diagram illustrating a configuration of the control processing device according to the first embodiment. As illustrated in FIG. 3, the control processing device 20 includes a control communication unit 40, a cycle setting unit 42, a calculation instruction unit 44, a calculation data unit 46, and a change request data acquisition unit 48.

  The control communication unit 40 communicates with the communication unit 12 of the calculation processing device 10 to exchange information with the calculation processing device 10, and communicates with the communication unit 34 of the instructor operation device 30 to operate the instructor. It exchanges information with the device 30.

  The cycle setting unit 42 includes a processing cycle setting unit 52, a basic cycle setting unit 54, a synchronization cycle setting unit 56, and a virtual time setting unit 58.

  The processing cycle setting unit 52 sets the processing cycle B for each calculation processing device 10. The processing cycle B is a cycle in which each calculation processing device 10 executes the simulation once, in other words, a time from the start of the simulation to the start of the next simulation. As described above, the calculation time A, which is the time required for the calculation processing device 10 to calculate one simulation, depends on the specifications of the calculation processing device 10 and the contents of the simulation. Therefore, the calculation processing device 10 cannot repeat the simulation at a cycle shorter than the calculation time A. Therefore, the processing cycle setting unit 52 sets the processing cycle B so that each calculation processing device 10 has a length equal to or longer than the respective calculation time A. Details of the processing cycle setting method will be described later.

  The basic period setting unit 54 sets a basic period C common to all the calculation processing apparatuses 10. The basic cycle C is a cycle having a common multiple of each processing cycle B. Details of the basic period C will be described later.

  The synchronization cycle setting unit 56 sets a synchronization cycle D that is common to all the calculation processing devices 10. The synchronization period D is a period having a common divisor length of each processing period B. The synchronization period D will be described later.

  The virtual time setting unit 58 sets the calculation virtual time E for each calculation processing device 10. The calculated virtual time E is an elapsed time in the simulation. The calculation processing apparatus 10 executes the simulation for the calculation virtual time E in one simulation. That is, for example, when a temperature change simulation is performed, the calculation processing device 10 calculates a temperature change before and after the calculation virtual time E elapses. Therefore, the calculated virtual time E may be different from the actual elapsed time (here, the calculation time A or the processing cycle B). The calculation processing apparatus 10 can calculate a processing result for each virtual elapsed time in the simulation by repeating this simulation a plurality of times. Details of the setting method of the calculation virtual time E will be described later.

  As described above, the cycle setting unit 42 sets the processing cycle B, the basic cycle C, the synchronization cycle D, and the calculation virtual time E, which are set values for synchronizing the calculation processing devices 10. The cycle setting unit 42 sets these by itself based on the calculation time A of each calculation processing device 10 and the contents of the simulation to be executed, but these are set by an input operation to the cycle setting unit 42 by the operator. May be.

  Next, the calculation instruction unit 44 of the control processing device 20 will be described. As illustrated in FIG. 3, the calculation instruction unit 44 includes a synchronization signal generation unit 62, a calculation processing flag set unit 64, a calculation virtual time flag set unit 66, and an operation flag set unit 68.

  The synchronization signal generator 62 generates the synchronization signal SD for each synchronization period D. The synchronization signal generator 62 outputs the synchronization signal SD to each of the calculation processing devices 10 for each synchronization period D via the control communication unit 40. Each calculation processing device 10 that has acquired the synchronization signal SD starts a process for executing a simulation, which will be described later in detail.

  The calculation process flag setting unit 64 is for performing a synchronization process described later. The calculation processing flag setting unit 64 sets the calculation processing flag FB in its writable area in synchronization with the synchronization signal SD. The calculation processing flag setting unit 64 sets a calculation processing flag FB corresponding to each of the calculation processing devices 10. In the present embodiment, the calculation processing flag setting unit 64 sets a calculation instruction flag F1 and a calculation non-execution flag F2 corresponding to each calculation processing device 10. The calculation instruction flag F1 is a flag for issuing an instruction to cause the calculation processing apparatus 10 to perform a new simulation. The calculation non-execution flag F2 is a flag for giving an instruction not to perform a new simulation to the calculation processing apparatus 10. The calculation processing device 10 reads the calculation processing flag FB set for itself from the calculation processing flag setting unit 64 and may or may not start a new simulation based on the calculation processing flag FB.

  For example, the calculation processing flag set unit 64 is synchronized with the synchronization signal SD transmitted to the second calculation processing device 10B at a timing that coincides with the processing cycle B (second processing cycle BB) of the second calculation processing device 10B. The calculation instruction flag F1 for the second calculation processing device 10B is set. In addition, the calculation processing flag set unit 64 synchronizes with the synchronization signal SD transmitted to the second calculation processing device 10B at a timing that does not coincide with the processing cycle B (second processing cycle BB) of the second calculation processing device 10B, for example. Thus, the calculation non-execution flag F2 for the second calculation processing device 10B is set. The second calculation processing device 10B starts a new simulation when the calculation instruction flag F1 is read, and does not start a new simulation when the calculation non-execution flag F2 is read.

  The calculation virtual time flag setting unit 66 sets the calculation virtual time flag FE in its writable area in synchronization with the synchronization signal SD. The calculation virtual time flag setting unit 66 sets the calculation virtual time flag FE in correspondence with each calculation processing device 10. The calculation virtual time flag FE is a flag indicating information of the calculation virtual time E that is an elapsed time in one simulation. The calculation processing device 10 reads the calculation virtual time flag FE set for itself from the calculation virtual time flag set unit 66, and executes the simulation for the length of the calculation virtual time E in the calculation virtual time flag FE. .

  The operation flag set unit 68 is for performing request data synchronization processing described later. The operation flag setting unit 68 sets the operation flag FG in its own writable area in synchronization with the basic cycle C. The operation flag setting unit 68 sets an operation flag FG common to all the calculation processing devices 10. The operation flag FG is a flag that is set based on operation information from an operator (instructor) input to the instructor operation device 30. The operation information input to the instructor operation device 30 is input to the change request data acquisition unit 48. The change request data acquisition unit 48 is a case where the operation information is change request data which is information on a change request for a simulation operation, and when the operation information is a RUN operation or a FREEZE operation, the change request data acquisition unit 48 stores the change request data in an operation flag set unit 68. Output to. The operation flag setting unit 68 sets the operation flag FG based on the change request data. Each calculation processing device 10 reads the operation flag FG and changes the simulation operation performed by itself based on the operation flag FG. Details of the operation flag FG will be described later.

  Next, the calculation data unit 46 of the control processing device 20 will be described. As shown in FIG. 3, the calculation data unit 46 includes a calculation data acquisition unit 72 and a calculation data storage unit 74. The calculation data acquisition unit 72 acquires output data of each calculation processing device 10. The calculation data storage unit 74 stores the input data of each calculation processing device 10, and acquires and stores the output data of each calculation processing device 10 from the calculation data acquisition unit 72. Each calculation processing device 10 reads input data from the calculation data storage unit 74 and executes a simulation. Note that the calculation data storage unit 74 may store only the output data of each calculation processing device 10, and the input data of each calculation processing device 10 may be stored by the calculation processing device 10 itself.

  Moreover, the calculation data acquisition part 72 is used for the transaction data synchronization process mentioned later. The calculation data acquisition unit 72 has a function as a buffer that holds the exchange data of the output data for a predetermined time. The trade data is output data used as input data of another calculation processing device 10. Details of holding the trade data will be described later.

  The change request data acquisition unit 48 acquires operation information input to the instructor operation device 30 as described above.

  The control processing device 20 has a configuration as described above. The control processing device 20 performs cycle setting, synchronization processing, transaction data synchronization processing, and request data synchronization processing in order to synchronize simulations of the respective calculation processing devices 10. Below, each process of the control processing apparatus 20 is demonstrated.

(Cycle setting)
First, the setting of the processing cycle B, the basic cycle C, the synchronization cycle D, and the calculation virtual time E in the cycle setting unit 42 will be described. FIG. 4 is a chart for explaining the setting of each cycle. The cycle setting unit 42 first sets the processing cycle B of each calculation processing device 10 by the processing cycle setting unit 52. The processing cycle setting unit 52 sets the processing cycle B based on the calculation time A and the contents of the simulation to be executed. The processing cycle setting unit 52 sets the processing cycle B for each calculation processing device 10 so as to be longer than the calculation time A of the calculation processing device 10. Further, the processing cycle setting unit 52 may set the processing cycle B so as to be as long as the calculation time A and as short as possible. Since the frequency of simulation increases by shortening the processing cycle B, it is possible to improve the simulation accuracy. Further, the processing cycle setting unit 52 sets the processing cycle B based on the type of simulation. For example, if the processing cycle setting unit 52 is a simulation (for example, temperature control or water amount control) for a control change of a plant control device, the processing cycle setting unit 52 is longer than the calculation time A in order to increase the accuracy of the simulation, In addition, the processing cycle B is set so that the length is as short as possible. Further, in the case of a chemical reaction simulation, the processing cycle setting unit 52 is a control device in which the processing cycle B is longer than the calculation time A and has the same calculation time A because the progress of the reaction is slow. It may be set longer than the simulation for the control change. That is, when it is assumed that the calculation time A is the same, the processing cycle setting unit 52 sets the processing cycle B so that the length is as short as possible in the simulation related to the parameter that frequently needs to be checked. In a simulation related to a parameter that does not require a state check, the processing cycle B is set to be longer than that.

Further, for example, for the simulation in which the calculation time A is short and the processing cycle B can be set short, the processing cycle setting unit 52 sets the processing cycle B to the same length as the processing cycle of the actual nuclear power plant control device. Can be made the same as the actual nuclear power plant movement. Further, since the propagation speed of the pressure in the sealed pipe, the explosion event, the critical event, or the like has a high parameter change speed, the processing cycle setting unit 52 performs the processing cycle for the simulation related to the event with the high parameter changing speed. B is set to be as short as possible. That is, the processing cycle setting unit 52 shortens the length of the processing cycle B with respect to the calculation time A for an event with a higher parameter change rate. By shortening the length of the processing cycle B with respect to the calculation time A, the length of the processing cycle B can be brought close to the calculation time A, and the processing cycle B can be shortened as much as possible. In addition, the processing cycle setting unit 52 increases the length of the processing cycle B for a simulation with a large calculation load such as a fire event. Further, the processing cycle setting unit 52 sets a processing cycle B in a range that does not affect (e.g., divergence) in the simulation of the connection destination for a simulation that requires convergence calculation.

  In the example of the present embodiment, as illustrated in FIG. 4, the processing cycle setting unit 52 sets the first processing cycle BA, which is the processing cycle of the first calculation processing device 10A, to 0, which is the time from the clock timing TA1 to TA4. .3 seconds is set. The first processing cycle BA has the same length as the calculation time AA of the first calculation processing device 10A. When the start timing of the first processing cycle BA is the processing cycle timing TB and the processing cycle timing TB1 is the same timing as the clock timing TA1, the processing cycle timing TB2 is the same timing as the clock timing TA4. Similarly, the processing cycle timing TB3 is the same timing as the clock timing TA7, the processing cycle timing TB4 is the same timing as the clock timing TA10, and the processing cycle timing TB5 is the same timing as the clock timing TA13.

  As shown in FIG. 4, when the simulation is started at the processing cycle timing TB1, the first calculation processing device 10A, between the processing cycle timings TB1 and TB2, between the processing cycle timings TB2 and TB3, and between the processing cycle timings TB3 and TB4. , The simulation is executed once each between the processing cycle timings TB4 and TB5.

  In addition, the processing cycle setting unit 52 sets the second processing cycle BB, which is the processing cycle of the second calculation processing device 10B, to 0.6 seconds that is the time from the clock timing TA1 to TA7. That is, the second processing cycle BB is the time from the processing cycle timing TB1 to TB3. The second processing cycle BB is longer than the calculation time AB of the second calculation processing device 10B. The processing cycle setting unit 52 has a second processing cycle that is a multiple of the first processing cycle BA of the first processing apparatus 10A, which is equal to or longer than the calculation time AB and is shorter than itself, and is as short as possible. BB is set.

  As shown in FIG. 4, when the simulation is started at the processing cycle timing TB1, the second calculation processing device 10B performs simulation once each between the processing cycle timings TB1 and TB3 and between the processing cycle timings TB3 and TB5. Execute.

  The processing cycle setting unit 52 sets the third processing cycle BC, which is the processing cycle of the third calculation processing device 10C, to 1.2 seconds, which is the time from the clock timing TA1 to TA13. That is, the third processing cycle BC is the time from the processing cycle timing TB1 to TB5. The third processing cycle BC is longer than the calculation time AC of the third calculation processing device 10C. The processing cycle setting unit 52 has a third processing cycle that is equal to or more than a common multiple of the first processing cycle BA and the second processing cycle BB that are equal to or longer than the calculation time AC and shorter than the calculation time AC. BC is set.

  As illustrated in FIG. 4, when the simulation is started at the processing cycle timing TB1, the third calculation processing device 10C executes the simulation once between the processing cycle timings TB1 and TB5.

  The processing cycle setting unit 52 sets the fourth processing cycle BD that is the processing cycle of the fourth calculation processing device 10D to 1.2 seconds that is the time from the clock timing TA1 to TA13. That is, the fourth processing cycle BD is the time from the processing cycle timing TB1 to TB13. The fourth processing cycle BD is longer than the calculation time AD of the fourth calculation processing device 10D. The fourth processing cycle BD of the fourth calculation processing device 10D is equal to or longer than the calculation time AD and is a multiple of the first processing cycle BA and the second processing cycle BB, which are shorter than the calculation time itself, and is as short as possible. In such a case, the time is 0.6 seconds. However, since it is not necessary to increase the simulation frequency in the simulation of the fourth calculation processing device 10D, the processing cycle setting unit 52 sets the fourth processing cycle BD to 1.2 times the double.

  As shown in FIG. 4, when the simulation is started at the processing cycle timing TB1, the fourth calculation processing device 10D executes the simulation once between the processing cycle timings TB1 and TB5.

  However, the method of setting the processing cycle B by the processing cycle setting unit 52 is not limited to the method described above. The processing cycle setting unit 52 only needs to set the processing cycle B so as to be longer than the calculation time A.

  Next, the period setting unit 42 sets the basic period C common to the calculation processing devices 10 by the basic period setting unit 54. The basic period setting unit 54 sets the basic period C so as to be a common multiple of each processing period B. More specifically, it is preferable that the basic period setting unit 54 sets the basic period C so as to be the least common multiple of each processing period B. That is, in the example of FIG. 4, the basic cycle C is the first processing cycle BA, the second processing cycle BB, the third processing cycle BC, and the third processing cycle BC, which is the least common multiple of the fourth processing cycle BD, and the fourth processing. A period (1.2 seconds) having the same length as the period BD is defined as a basic period C. When the basic cycle timing TC is the same timing as the processing cycle timing TB1 when the basic cycle C start timing is the basic cycle timing TC, the basic cycle timing TC2 is the same timing as the processing cycle timing TB5.

  The basic cycle setting unit 54 sets a length equal to or longer than the longest calculation time in each calculation time A as the basic cycle C, and the processing cycle setting unit 52 is longer than the calculation time A in the calculation processing device 10. Furthermore, the processing cycle B of each calculation processing device 10 may be set so as to have a length that is a divisor of the basic cycle C. In this case, it is preferable that the processing cycle setting unit 52 sets each processing cycle B so that the length of the basic cycle C is as short as possible.

  Next, the cycle setting unit 42 sets a synchronization cycle D common to all the calculation processing devices 10 by the synchronization cycle setting unit 56. The synchronization period setting unit 56 sets the synchronization period D so as to be the length of the common divisor of each processing period B. In the example of FIG. 4, the synchronization period setting unit 56 synchronizes a period (0.3 seconds) having the same length as the first processing period BA, which is the greatest common divisor of the first processing periods BA, BB, BC, and BD. Let it be period D. When the start timing of the synchronization cycle D is the synchronization timing TD and the synchronization timing TD1 is the same timing as the processing cycle timing TB1, the synchronization timing TD2 is the same timing as the processing cycle timing TB2, and the synchronization timing TD3 is the same as the processing cycle timing TB3. The synchronization timing TD4 is the same timing as the processing cycle timing TB4, and the synchronization timing TD5 is the same timing as the processing cycle timing TB5.

  Next, the cycle setting unit 42 sets the calculation virtual time E for each calculation processing device 10 by the virtual time setting unit 58. The calculated virtual time E is an elapsed time on one simulation. That is, the calculated virtual time E is a virtual elapsed time in the simulation executed in one processing cycle. The virtual time setting unit 58 sets each calculation virtual time E so that the relationship ratio is the same as the relationship ratio between the lengths of the processing periods B. Here, the calculation virtual time E set in the first calculation processing device 10A is set as the first calculation virtual time EA, the calculation virtual time E set in the second calculation processing device 10B is set as the second calculation virtual time EB, The calculation virtual time E set in the third calculation processing device 10C is the third calculation virtual time EC, and the calculation virtual time E set in the fourth calculation processing device 10D is the fourth calculation virtual time ED. In the example of FIG. 4, the length ratio of the first processing cycle BA, the second processing cycle BB, the third processing cycle BC, and the fourth processing cycle BD is 1: 2: 4: 4. The ratio of the lengths of the time EA, the second calculation virtual time EB, the third calculation virtual time EC, and the fourth calculation virtual time ED is 1: 2: 4: 4. The first calculation virtual time EA has a length of Δ3, the second calculation virtual time EB has a length of Δ6, and the third calculation virtual time EC and the fourth calculation virtual time ED have a length of the first. 2 Δ12 which is twice the calculation virtual time EB. For example, Δ3 is 0.3 seconds, Δ6 is 0.6 seconds, and Δ12 is 1.2 seconds, but is not limited thereto.

  Here, a virtual elapsed time on simulation in the basic period C is defined as a basic virtual time CX. The length of the basic cycle C is the sum of the lengths of the processing cycles B within the basic cycle C in one calculation processing device 10. That is, the length of the basic cycle C is four times the first processing cycle BA, twice the second processing cycle BB, and equal to the third processing cycle BC and the fourth processing cycle BD. Therefore, the basic virtual time CX is four times the first calculation virtual time EA, twice the second calculation virtual time EB, and equal to the third calculation virtual time EC and the fourth calculation virtual time ED. . As described above, the ratio of the lengths of the first calculation virtual time EA, the second calculation virtual time EB, the third calculation virtual time EC, and the fourth calculation virtual time ED is 1: 2: 4: 4. Therefore, it can be said that the basic virtual time CX is the same for each calculation processing device 10.

  As described above, the cycle setting unit 42 sets the processing cycle B, the basic cycle C, the synchronization cycle D, and the calculation virtual time E. The cycle setting unit 42 sets the processing cycle B, the basic cycle C, the synchronization cycle D, and the calculation virtual time E in this order, but the processing order is not limited to this. The cycle setting unit 42 preferably calculates the processing cycle B first, and calculates the basic cycle C, the synchronization cycle D, and the calculation virtual time E based on the processing cycle B. For example, the cycle setting unit 42 may set the processing cycle B, the calculation virtual time E, the basic cycle C, and the synchronization cycle D in this order. However, the cycle setting unit 42 is not limited to calculating the processing cycle B first.

(Synchronous processing)
Next, synchronization processing of each calculation processing device 10 by the control processing device 20 will be described. FIG. 5 is a time chart for explaining the synchronization processing. In the control processing device 20, the synchronization signal generation unit 62 generates a synchronization signal SD for each synchronization cycle D, and outputs the synchronization signal SD to each of the calculation processing devices 10 for each synchronization cycle D via the control communication unit 40. To do. In the example of FIG. 5, the synchronization signal generation unit 62 outputs the synchronization signal SD to each calculation processing device 10 at each timing of the synchronization timings TD1, TD2, TD3, TD4, and TD5. The basic cycle timing TC1 matches the synchronization timing TD1, and the basic cycle timing TC2 matches the synchronization timing TD5. Further, the synchronization timings TD1, TD2, TD3, TD4, and TD5 coincide with the processing cycle timings TB1, TB2, TB3, TB4, and TB5, respectively (see FIG. 4).

  Further, the control processing device 20 sets the calculation processing flag FB corresponding to each of the calculation processing devices 10 by the calculation processing flag setting unit 64. The calculation processing flag setting unit 64 selects the calculation processing flag FB to be set from the calculation instruction flag F1 or the calculation non-execution flag F2 based on the processing cycle B of each calculation processing device 10. The calculation processing flag set unit 64 synchronizes with the synchronization signal SD transmitted to each calculation processing device 10 at a timing that coincides with the processing cycle B of the calculation processing device 10, and calculates instructions for the calculation processing device 10. Set the flag F1. In addition, the calculation processing flag set unit 64 synchronizes with the synchronization signal SD transmitted to each calculation processing device 10 at a timing that does not coincide with the processing cycle B of the calculation processing device 10, and performs calculation for the calculation processing device 10. A non-execution flag F2 is set.

  In the example of the present description, the first processing cycle BA of the first calculation processing device 10A has the same length as the synchronization cycle D. Therefore, the calculation processing flag set unit 64 synchronizes with the synchronization signal SD output at the synchronization timing TD1, TD2, TD3, TD4, TD5 as the first calculation processing flag FBA of the first calculation processing device 10A, and calculates the calculation instruction flag. Set F1.

  In the example of the present description, the second processing cycle BB of the second calculation processing device 10B is twice as long as the synchronization cycle D. Accordingly, the calculation processing flag setting unit 64 sets the calculation instruction flag F1 in synchronization with the synchronization signal SD output at the synchronization timings TD1, TD3, and TD5 as the second calculation processing flag FBB of the second calculation processing device 10B. . Then, the calculation process flag setting unit 64 sets the calculation non-execution flag F2 in synchronization with the synchronization signal SD output at the synchronization timings TD2 and TD4 as the second calculation process flag FBB.

  In the example of the present description, the third processing cycle BC of the third calculation processing device 10C is four times as long as the synchronization cycle D. Accordingly, the calculation processing flag setting unit 64 sets the calculation instruction flag F1 in synchronization with the synchronization signal SD output at the synchronization timings TD1 and TD5 as the third calculation processing flag FBC of the third calculation processing device 10C. Then, the calculation processing flag setting unit 64 sets the calculation non-execution flag F2 as the third calculation processing flag FBC in synchronization with the synchronization signal SD output at the synchronization timings TD2 and TD3TD4. The fourth processing cycle BD of the fourth calculation processing device 10D has the same length as the third processing cycle BC. Accordingly, the fourth calculation processing flag FBD of the fourth calculation processing device 10D is the same as the third calculation processing flag FBC.

  Further, the control processing device 20 sets the calculation virtual time flag FE corresponding to each calculation processing device 10 by the calculation virtual time flag setting unit 66 in synchronization with the synchronization signal SD. The calculated virtual time flag FE is a flag having information on the set calculated virtual time E.

  In the example of this description, the first calculation virtual time EA of the first calculation processing device 10A is Δ3, the second calculation virtual time EB of the second calculation processing device 10B is Δ6, and the third calculation processing device 10C. The third calculation virtual time EC is Δ12, and the fourth calculation virtual time ED of the fourth calculation processing device 10D is Δ12. Therefore, the calculation virtual time flag set unit 66 outputs the first calculation virtual time flag FEA of the first calculation processing apparatus 10A having the information of Δ3 at the synchronization timings TD1, TD2, TD3, TD4, and TD5. Set in sync with SD. The calculation virtual time flag set unit 66 outputs the second calculation virtual time flag FEB of the second calculation processing apparatus 10B having the information of Δ6 to the synchronization signal SD output at the synchronization timings TD1, TD2, TD3, TD4, and TD5. Set in sync. The calculation virtual time flag set unit 66 outputs the third calculation virtual time flag FEC of the third calculation processing device 10C having the information of Δ12 to the synchronization signal SD output at the synchronization timings TD1, TD2, TD3, TD4, and TD5. Set in sync. The calculation virtual time flag set unit 66 outputs the fourth calculation virtual time flag FED of the fourth calculation processing device 10D having the information of Δ12 to the synchronization signal SD output at the synchronization timings TD1, TD2, TD3, TD4, and TD5. Set in sync.

  Note that the calculated virtual time flag setting unit 66 may set the calculated virtual time flag FE only when the calculation instruction flag F1 is set. That is, the calculation virtual time flag setting unit 66 may set the second calculation virtual time flag FEB in synchronization with only the synchronization signal SD output at the synchronization timings TD1, TD3, and TD5, for example.

  When each calculation processing device 10 acquires the synchronization signal SD, each calculation processing device 10 reads the calculation processing flag FB and the calculation virtual time flag FE corresponding to itself from the control processing device 20. When the calculation processing flag FB is the calculation instruction flag F1, each calculation processing device 10 starts a simulation for the calculation virtual time E indicated by the calculation virtual time flag FE. Further, each calculation processing device 10 does not start the simulation when the calculation processing flag FB is the calculation non-execution flag F2.

  In the example of FIG. 5, when the first calculation processing device 10A acquires the synchronization signal SD at the synchronization timing TD1, the first calculation processing flag FBA set in the calculation processing flag setting unit 64 of the control processing device 20 and the calculation virtual The first calculation virtual time flag FEA set in the time flag setting unit 66 is read. Since the first calculation processing flag FBA at the synchronization timing TD1 is the calculation instruction flag F1, the first calculation processing device 10A newly starts a simulation for the first calculation virtual time EA (Δ3 minutes). As shown in FIG. 5, this simulation ends by the synchronization timing TD2.

  The first calculation processing flag FBA at the synchronization timings TD2, TD3, TD4, and TD5 is also the calculation instruction flag F1. Accordingly, the first calculation processing apparatus 10A similarly starts a new simulation for the first calculation virtual time EA (Δ3 minutes) at the synchronization timings TD2, TD3, TD4, and TD5.

  In the example of FIG. 5, when the second calculation processing device 10B acquires the synchronization signal SD at the synchronization timing TD1, the second calculation processing device 10B reads the second calculation processing flag FBB and the second calculation virtual time flag FEB. Since the second calculation processing flag FBB at the synchronization timing TD1 is the calculation instruction flag F1, the second calculation processing device 10B newly starts a simulation for the second calculation virtual time EB (Δ6 minutes). As shown in FIG. 5, this simulation ends by the synchronization timing TD3.

  The second calculation processing flag FBB at the synchronization timing TD2 is a calculation non-execution flag F2. Therefore, the second calculation processing device 10B does not newly start a simulation at the synchronization timing TD2. At the synchronization timing TD2, the second calculation processing device 10B is executing a simulation started at the synchronization timing TD1.

  The second calculation processing flag FBB at the synchronization timings TD3 and TD5 is the calculation instruction flag F1. Accordingly, the second calculation processing device 10B newly starts a simulation for the second calculation virtual time EB (Δ6 minutes) at the synchronization timings TD3 and TD5. Further, the second calculation processing device 10B does not newly start the simulation at the synchronization timing TD4 in which the calculation non-execution flag F2 is set.

  In the example of FIG. 5, when the third calculation processing device 10C acquires the synchronization signal SD at the synchronization timing TD1, the third calculation processing device 10C reads the third calculation processing flag FBC and the third calculation virtual time flag FEC. Since the third calculation processing flag FBC at the synchronization timing TD1 is the calculation instruction flag F1, the third calculation processing device 10C newly starts a simulation for the third calculation virtual time EC (Δ12 minutes). As shown in FIG. 5, this simulation ends by the synchronization timing TD5.

  In addition, the third calculation processing flag FBC at the synchronization timings TD2, TD3, and TD4 is the calculation non-execution flag F2. Accordingly, the third calculation processing device 10C does not newly start a simulation at the synchronization timings TD2, TD3, and TD4. Note that at the synchronization timings TD2, TD3, and TD4, the third calculation processing device 10C is executing the simulation started at the synchronization timing TD1.

  The third calculation processing flag FBC at the synchronization timing TD5 is the calculation instruction flag F1. Therefore, the third calculation processing apparatus 10C newly starts a simulation for the third calculation virtual time EC (Δ12 minutes) at the synchronization timing TD5.

  In the example of FIG. 5, when the fourth calculation processing device 10D acquires the synchronization signal SD at the synchronization timing TD1, the fourth calculation processing device 10D reads the fourth calculation processing flag FBD and the fourth calculation virtual time flag FED. Since the fourth calculation processing flag FBD at the synchronization timing TD1 is the calculation instruction flag F1, the fourth calculation processing device 10D newly starts a simulation for the fourth calculation virtual time ED (Δ12 minutes). As shown in FIG. 5, this simulation ends by the synchronization timing TD3.

  Further, the fourth calculation processing flag FBD at the synchronization timings TD2, TD3, and TD4 is the calculation non-execution flag F2. Accordingly, the fourth calculation processing device 10D does not newly start a simulation at the synchronization timings TD2, TD3, and TD4. Note that the simulation started at the synchronization timing TD1 has already ended at the synchronization timing TD3, but the fourth calculation processing apparatus 10D does not newly start the simulation at the synchronization timing TD3.

  The fourth calculation processing flag FBD at the synchronization timing TD5 is the calculation instruction flag F1. Accordingly, the fourth calculation processing device 10D newly starts a simulation for the fourth calculation virtual time ED (Δ12 minutes) at the synchronization timing TD5.

  The processing at the synchronization timing after the synchronization timing TD5 is the same as the processing at the synchronization timing TD1 to TD4. That is, the control processing device 20 and each calculation processing device 10 repeat the processing from the synchronization timing TD1 to TD4 as one cycle. In other words, the control processing device 20 and each calculation processing device 10 set the basic cycle C (basic cycle timings TC1 to TC2) as one cycle, and repeat the processing in this one cycle every time.

  In the basic cycle C (basic cycle timings TC1 to TC2), the first calculation processing device 10A executes the simulation four times, the second calculation processing device 10B executes the simulation twice, and the third calculation processing device 10C and The fourth calculation processing device 10D executes the simulation once. Since the first calculation virtual time EA, the second calculation virtual time EB, the third calculation virtual time EC, and the fourth calculation virtual time ED are Δ3, Δ6, Δ12, and Δ12, respectively, the elapsed time in the simulation for each basic period (Basic virtual time CX) is Δ12, which is the same for all the calculation processing devices 10.

  Further, as described above, each calculation processing device 10 reads the calculation instruction flag F1 and executes the simulation based on the synchronization signal SD synchronized with the calculation instruction flag F1. And each calculation processing apparatus 10 reads the calculation non-execution flag F2 based on the synchronizing signal SD synchronized with the calculation non-execution flag F2, and executes a simulation. Therefore, it can be said that the synchronization signal SD synchronized with the calculation instruction flag F1 is a calculation instruction signal for causing each calculation processing device 10 to execute a simulation. Further, it can be said that the synchronization signal SD synchronized with the calculation non-execution flag F2 is a calculation non-execution signal for preventing each calculation processing apparatus 10 from newly executing a simulation.

  The synchronization processing flow described above will be described with reference to a flowchart. FIG. 6 is a flowchart for explaining the synchronization processing of the control processing device. FIG. 7 is a flowchart for explaining a simulation execution process of each calculation processing apparatus. As shown in FIG. 6, after the processing starts, the control processing device 20 resets the elapsed time (step S12) and sets a flag (step S14) when the synchronization period D has elapsed (step S10; Yes). . In step S14, the control processing device 20 sets the calculation processing flag FB and the calculation virtual time flag FE in correspondence with each calculation processing device 10. If the synchronization period D has not elapsed (step S10; No), the control processing device 20 returns to step S10 and waits until the synchronization period D has elapsed.

  After setting the flag, the control processing device 20 outputs the synchronization signal SD to each calculation processing device 10 (step S16). Thereafter, the control processing device 20 proceeds to step S18, and ends the process when the process is terminated (step S18; Yes). If the processing is not finished (step S18; No), the control processing device 20 returns to step S10 and waits for the next synchronization period D to elapse.

  FIG. 7 is a flowchart for explaining the processing of the calculation processing device 10 that has received the synchronization signal SD output in step S16 of FIG. As illustrated in FIG. 7, when the calculation processing device 10 acquires the synchronization signal SD from the control processing device 20 (step S20), the calculation processing device 10 reads a flag from the control processing device 20 (step S21). In step S21, the calculation processing device 10 reads the calculation processing flag FB and the calculation virtual time flag FE set in association with itself. When there is the calculation instruction flag F1 in the read flag (step S22; Yes), the calculation processing device 10 acquires input data used for the simulation from the calculation data storage unit 74 of the control processing device 20 (step S24). If there is no calculation instruction flag F1 in the read flag (step S22; No), the calculation processing device 10 returns to step S20 to acquire the next synchronization signal SD without executing a new simulation.

  The calculation processing device 10 acquires the input data in step S22, and then executes a simulation (step S26), and outputs output data as a simulation result to the calculation data acquisition unit 72 of the control processing device 20 (step S28). . Thereafter, the calculation processing apparatus 10 proceeds to step S29, and ends the process when the process is terminated (step S29; Yes). If the calculation processing device 10 does not end the processing (step S29; No), the calculation processing device 10 returns to step S20 and acquires the next synchronization signal SD.

  As described above, the control processing device 20 performs the synchronization processing and controls the simulation execution processing of each calculation processing device 10. However, instead of setting the calculation processing flag FB and the calculation virtual time flag FE in its own region, the control processing device 20 outputs a signal having such information for each synchronization cycle D or each processing cycle B. You may output to the processing apparatus 10. FIG.

(Interaction synchronization processing)
Next, the process synchronization process of each calculation processing device 10 by the control processing device 20 will be described. FIG. 8 is a time chart for explaining the contact synchronization processing. The trade synchronization process is a process for synchronizing trade data. The contact data is input data of a calculation processing device 10 other than the calculation processing device 10 among the output data of the calculation processing device 10 as described above. In the present description, the second calculation processing device 10B uses the contact data of the first calculation processing device 10A and the contact data of the fourth calculation processing device 10D. Further, the third calculation processing device 10C uses the contact data of the second calculation processing device 10B.

  In the control processing device 20, the calculation data acquisition unit 72 acquires the output data of each calculation processing device 10. The calculation data acquisition unit 72 outputs the output data to the calculation data storage unit 74, and the calculation data storage unit 74 stores the output data. Further, the calculation data acquisition unit 72 temporarily holds the contact data among the output data, and outputs the contact data to the calculation data storage unit 74 at the immediately preceding timing TI. Accordingly, the calculation data storage unit 74 stores the trade data after the immediately preceding timing TI. That is, the calculation data acquisition unit 72 delays the timing for storing the trade data in the calculation data storage unit 74 until the immediately preceding timing TI.

Here, in the calculation processing unit 10 to calculate the scramble data, and the processing period B calculated the scramble data and the scramble processing cycle B _X, to the next processing cycle as follows processing cycle B _{X + 1.} Immediately before timing TI is a timing later than the synchronization timing TD just before the start time TB of the next processing cycle _{B X + 1,} and, from the next processing period _{B X + 1} of the processing cycle time TB (start timing of the next processing cycle _{B X + 1)} It is the previous timing.

In the example of FIG. 8, the second calculation processing device 10B receives the output data (interaction data) of the simulation of the first calculation processing device 10A at the synchronization timings TD2 and TD4 and the input of its own simulation at the synchronization timings TD3 and TD5. Used as data. Here, scramble processing period _{B X} in the first computing device 10A, a processing period TB beginning with synchronization timing TD2, the following processing period _{B X + 1,} will be described a processing cycle TB beginning with synchronization timing TD3. In this case, as shown in FIG. 8, the first immediately preceding timing TIA, which is the immediately preceding timing TI of the first calculation processing device 10A, is the synchronization timing TD2 immediately before the processing cycle TB (next processing cycle B _{X + 1} ) at the synchronization timing TD3. It is later and before the start timing (synchronization timing TD3) of the processing cycle TB at the synchronization timing TD3.

The first immediately preceding timing TIA is after the output timing of the simulation output data at the synchronization timing TD2, since the output data of the simulation at the synchronization timing TD2 is used as the data. The scramble processing cycle B _X in the first computing device 10A, even when a processing cycle TB in synchronous timing TD4, immediately before the timing TIA is the same timing.

In the example of FIG. 8, the second calculation processing device 10B uses the output data (interaction data) of the simulation of the fourth calculation processing device 10D at the synchronization timing TD1 as the input data of its own simulation at the synchronization timing TD5. Used. Here, the scramble processing period _{B X} in the fourth computing unit 10D, a processing period TB in synchronous timing TD1, the next processing cycle _{B X + 1,} will be described for the case where the processing cycle TB in synchronous timing TD5. In this case, as shown in FIG. 8, the fourth immediately preceding timing TID of the fourth calculation processing device 10D is a timing after the synchronization timing TD4 immediately before the processing cycle TB (next processing cycle B _{X + 1} ) at the synchronization timing TD5. Yes, and before the start timing (synchronization timing TD5) of the processing cycle TB at the synchronization timing TD5. The second calculation processing device 10B does not use the output data (interaction data) of the simulation of the fourth calculation processing device 10D at the synchronization timing TD1 as input data of its own simulation at the synchronization timing TD3.

In the example of FIG. 8, the third calculation processing device 10C uses the output data (interaction data) of the simulation of the second calculation processing device 10B at the synchronization timing TD3 as input data of its own simulation at the synchronization timing TD5. Used. Here, the scramble processing period _{B X} in the second computing device 10B, the processing cycle TB in synchronous timing TD3, the next processing cycle _{B X + 1,} will be described for the case where the processing cycle TB in synchronous timing TD5. In this case, as shown in FIG. 8, the second immediately preceding timing TIB of the second calculation processing device 10B is a timing after the synchronization timing TD4 immediately before the processing cycle TB (next processing cycle B _{X + 1} ) at the synchronization timing TD5. Yes, it is a timing before the start timing (synchronization timing TD5) of the processing cycle TB at the synchronization timing TD5.

  The calculation data acquisition unit 72 holds the contact data until the immediately preceding timing TI as described above, and outputs it to the calculation data storage unit 74 at the immediately preceding timing TI. As a result, the control processing device 20 can appropriately synchronize the exchange data when each calculation processing device 10 exchanges data. For example, when the calculation data acquisition unit 72 does not hold the contact data until the immediately preceding timing TI and immediately outputs it to the calculation data storage unit 74, the calculation processing device 10 performs a simulation based on the contact data that is not synchronized. There is a fear. In this case, the accuracy of simulation decreases.

  For example, the output data (interaction data) of the simulation of the fourth calculation processing apparatus 10D performed at the synchronization timing TD1 is calculated before the synchronization timing TD3 and is output to the calculation data acquisition unit 72. In this case, when the calculation data acquisition unit 72 does not hold until the fourth immediately preceding timing TID, the calculation data storage unit 74 stores this contact data before the synchronization timing TD3. The second calculation processing apparatus 10B that uses the trade data may read and use the trade data for the simulation performed at the synchronization timing TD3. This exchange data is output data of the fourth calculation processing apparatus 10D performed at the synchronization timing TD1, and is data calculated by Δ12 minutes (fourth calculation virtual time ED) on the simulation, that is, data after Δ12 minutes have passed. However, the simulation performed by the second calculation processing device 10B at the synchronization timing TD3 is a calculation performed immediately after Δ6 (third calculation virtual time EC). Therefore, in this case, the simulation performed by the second calculation processing apparatus 10B at the synchronization timing TD3 uses data at different times on the simulation, and the accuracy of the simulation decreases.

  However, the output data (interaction data) of the simulation of the fourth calculation processing device 10D performed at the synchronization timing TD1 is held until the fourth immediately preceding timing TID, that is, after the synchronization timing TD3. In this case, the second calculation processing device 10B uses the contact data of the fourth calculation processing device 10D performed at the synchronization timing TD1 in the calculation at the synchronization timing TD5 as described above. The simulation of the second calculation processing device 10B at the synchronization timing TD5 is a calculation performed immediately after Δ12 (two times of the third calculation virtual time EC). Therefore, this simulation uses data at the same time on the simulation. As described above, the second calculation processing device 10B according to the present embodiment does not use data at different times on the simulation, and can suppress a decrease in the accuracy of the simulation.

Note that the immediately preceding timing TI is not limited to the timing described above. Here, the processing cycle B of the calculation processing device 10 on the side using the trade data immediately before the next processing cycle B _{X + 1} of the calculation processing device 10 on the side of outputting the trade data is defined as a counterpart processing cycle _BY . Immediately before timing TI is a timing after the treatment cycle timing TB of the mating process cycle B _Y (start timing of the mating process cycle B _Y), the next processing cycle B _{X + 1} of the processing cycle time TB (next processing cycle B _Any timing may be used before ( _{X + 1} start timing). For example, at the fourth immediately preceding timing TID in the example of FIG. 8, the counterpart calculation processing device 10 that uses the trade data is the second calculation processing device 10B, and the counterpart processing cycle _BY is the synchronization timing TD3. Is the processing cycle B. In this case, the fourth immediately preceding timing TID is a timing after the synchronization timing TD3 (start timing of the other party processing cycle _BY ) and the start timing of the processing cycle TB at the synchronization timing TD5 which is the next processing cycle B _{X + 1.} It is before (synchronization timing TD5).

  The flow of the interaction synchronization process described above will be described based on the flowchart. FIG. 9 is a flowchart for explaining the contact synchronization processing of the control processing device. As shown in FIG. 9, the control processing device 20 determines whether or not the calculation data acquisition unit 72 has reached the previous timing TI for the calculation processing device 10 that has output the contact data after acquiring the contact data (step S30). Judgment is made (step S32). If the previous timing TI has not been reached (step S32; No), the calculation data acquisition unit 72 returns to step S32 and holds the acquired contact data until the previous timing TI is reached. When the immediately preceding timing TI is reached (step S32; Yes), the calculation data acquisition unit 72 outputs the acquired contact data to the calculation data storage unit 74 (step S34). The calculation data storage unit 34 stores the acquired trade data. The calculation processing apparatus 10 using the trade data reads the trade data stored in the computation data storage unit 74 as its own input data. The control processing device 20 proceeds to step S36 after step S34. If the process has not been completed (step S36; No), the process returns to step S30 to continue the process, and the process is terminated (step S36; Yes). ), And finishes these processes.

  As described above, the control processing device 20 performs the contact synchronization processing, and controls the acquisition timing of the contact data of each calculation processing device 10. The calculation data acquisition unit 72 determines whether the output data is the contact data, and holds only the contact data until the immediately preceding timing TI. However, the present invention is not limited to this, and all the acquired output data is until the immediately preceding timing TI. It may be held.

(Request data synchronization processing)
Next, request data synchronization processing of each calculation processing device 10 by the control processing device 20 will be described. FIG. 10 is a time chart for explaining the request data synchronization processing. The request data synchronization process is a process of reflecting the change request for the simulation operation from the operator indicated in the change request data in synchronization with each calculation processing device 10.

  The operation information input to the instructor operation device 30 is input to the change request data acquisition unit 48. The change request data acquisition unit 48 is a case where the operation information is change request data which is information on a change request for a simulation operation, and when the operation information is a RUN operation or a FREEZE operation, the change request data acquisition unit 48 stores the change request data in an operation flag set unit 68. Output to.

  The operation flag setting unit 68 sets the operation flag FG in synchronization with the basic period C based on the change request data. More specifically, the operation flag setting unit 68 sets the operation flag FG reflecting the change request data at the start timing of the basic period C immediately after the change request data is acquired (immediately after the basic period timing TC). The operation flag setting unit 68 sets the operation execution flag FG1 in synchronization with the basic period C when the change request data is the content to be changed to the RUN operation. The operation flag setting unit 68 sets the operation stop flag FG2 in synchronization with the basic period C when the change request data is the content to be changed to the FREEZE operation. When each calculation processing device 10 acquires the synchronization signal SD at the synchronization timing TD synchronized with the timing at which the operation flag FG is set, the calculation processing device 10 reads the operation flag FG. When the read operation flag FG is the operation execution flag FG1, each calculation processing device 10 newly starts a simulation from the synchronization timing TD. In addition, when the read operation flag FG is the operation stop flag FG2, each calculation processing device 10 does not execute the simulation after the synchronization timing TD. Note that the operation flag FG is a flag common to all the calculation processing devices 10, but a different type of flag may be set individually.

  In the example of FIG. 10, the simulation of each calculation processing device 10 is not executed in the basic cycle C immediately before the basic cycle timing TC1, and the operation is changed to the RUN operation in the basic cycle C immediately before the basic cycle timing TC1. This shows a case where change request data RU to be input is input. The change request data acquisition unit 48 outputs the change request data RU to the operation flag set unit 68. The operation flag setting unit 68 sets the operation execution flag FG1 at the synchronization timing TD1, which is the start timing of the basic period C immediately after that.

  Further, the control processing device 20 outputs the synchronization signal SD at the synchronization timing TD1 that is synchronized with the basic cycle timing TC1. Each calculation processing device 10 reads the operation flag FG set in the operation flag setting unit 68 when acquiring the synchronization signal SD. Since the operation flag FG at the synchronization timing TD1 is the operation execution flag FG1, each calculation processing device 10 starts the simulation process from the synchronization timing TD1.

  Further, in the example of FIG. 10, change request data FR to be changed to the FREEZE operation is input at a timing between the synchronization timing TD3 and the synchronization timing TD4. The change request data acquisition unit 48 outputs the change request data FR to the operation flag set unit 68. The operation flag setting unit 68 sets the operation stop flag FG2 at the synchronization timing TD5 that is the start timing of the basic period C immediately after that. In the basic cycle C of the basic cycle timing TC1, the operation execution flag FG1 remains set even at the synchronization timing TD4 after the change request data FR is input. Therefore, each calculation processing device 10 does not stop the simulation in the basic cycle C of the basic cycle timing TC1. Each calculation processing device 10 reads the operation stop flag FG2 by the synchronization signal SD at the synchronization timing TD5 in which the operation stop flag FG2 is set, and stops the simulation from the synchronization timing TD5 onward.

  As described above, the operation flag setting unit 68 sets the operation execution flag FG1 indicating the information in the change request data at the start timing of the basic cycle C immediately after the change request data is acquired. Thereby, the control processing apparatus 20 can reflect the change request by the operator in synchronization with each calculation processing apparatus 10. For example, when the change request data is set without waiting until the start timing of the immediately following basic cycle C, the elapsed time on the simulation may be different for each calculation processing device 10. In this case, the simulations are not matched and the accuracy of the simulation is lowered.

  For example, in the example of FIG. 10, a case is considered in which the change request data FR input at the timing between the synchronization timing TD3 and the synchronization timing TD4 is immediately reflected, and for example, the operation stop flag FG2 is set at the synchronization timing TD4. In this case, the first calculation processing apparatus 10A stops the simulation after executing the simulation three times from the synchronization timing TD1 to TD3. In this case, the elapsed time in the simulation until the stop in the first calculation processing apparatus 10A becomes Δ9 when Δ3 is three times. On the other hand, the second calculation processing device 10B stops the simulation after executing the simulation twice at the synchronization timings TD1 and TD3. Then, the third calculation processing device 10C and the fourth calculation processing device 10D stop the simulation after executing the simulation once at the synchronization timing TD1. In this case, the elapsed time in the simulation until the stop in the second calculation processing device 10B, the third calculation processing device 10B, and the fourth calculation processing device 10D is Δ12. Therefore, the elapsed time in simulation differs between the first calculation processing apparatus 10A and the other calculation processing apparatus 10. For example, in this case, when the simulation is resumed, the time on the simulation is different.

  On the other hand, in the present embodiment, the change request data FR input at a timing between the synchronization timing TD3 and the synchronization timing TD4 is reflected at the synchronization timing TD5. That is, the calculation processing device 10 executes the requested change process at the same timing in the elapsed time on the simulation. Therefore, the elapsed time on the simulation of each calculation processing apparatus 10 until the simulation is stopped is the same.

  Further, as described above, each calculation processing device 10 reads the operation execution flag FG1 and newly executes a simulation based on the synchronization signal SD synchronized with the operation execution flag FG1. Then, each calculation processing device 10 reads the operation stop flag FG2 based on the synchronization signal SD synchronized with the operation stop flag FG2, and stops the simulation. Therefore, it can be said that the synchronization signal SD synchronized with the operation flag FG is a change request signal indicating information of change request data to each calculation processing system.

  The flow of the request data synchronization process described above will be described with reference to a flowchart. FIG. 11 is a flowchart illustrating request data synchronization processing of the control processing device. FIG. 12 is a flowchart for explaining a simulation execution process of each calculation processing apparatus. As illustrated in FIG. 11, when the change request data acquisition unit 48 acquires the change request information (step S40), the control processing device 20 outputs information indicating that the change request information has been acquired to the instructor operation device 30. (Step S42), the obtained change request information is output to the operation flag set unit 68 (Step S43).

  When the basic period C has elapsed (step S44; Yes), in the control processing device 20, the operation flag setting unit 68 sets the operation flag FG in its own region (step S46). Specifically, the operation flag setting unit 68 sets the operation flag FG at the basic cycle timing TC immediately after the change request information is input. When the basic period has not elapsed (step S44; No), the control processing device 20 returns to step S44 and waits until the basic period has elapsed. After setting the operation flag FG, the control processing device 20 outputs the synchronization signal SD to each calculation processing device 10 (step S48). Thereafter, the control processing device 20 proceeds to step S49, and terminates the process when the process is terminated (step S49; Yes). If the processing is not finished (step S49; No), the control processing device 20 returns to step S40 and waits for a change processing request.

  FIG. 12 is a flowchart illustrating the processing of the calculation processing device 10 that has received the synchronization signal SD output in step S48 of FIG. As illustrated in FIG. 12, when the calculation processing device 10 acquires the synchronization signal SD from the control processing device 20 (step S50), the calculation processing device 10 reads the operation flag FG from the control processing device 20 and determines whether the operation flag FG has changed. (Step 52). If there is a change in the operation flag FG (step S52; Yes) and the changed operation flag FG is the operation stop flag FG2 (step S54; Yes), the computer 10 stops the subsequent simulation. (Step S56). Further, the calculation processing device 10 has a change in the operation flag FG (step S52; Yes), and the changed operation flag FG is not the operation stop flag FG2, that is, a change to the operation execution flag FG1 ( Step S54; No), the next simulation is executed (step S58).

  Further, when there is no change in the operation flag FG (step S52; No) and the current operation flag FG is the operation execution flag FG1 (step S53; Yes), the calculation processing device 10 continuously executes the next simulation. (Step S58). Further, when the operation flag FG is not changed (step S52; No) and the current operation flag FG is not the operation execution flag FG1, that is, the operation stop flag FG2 (step S53; No), the calculation processing device 10 newly Without starting simulation, the process returns to step S50 to wait for acquisition of the next synchronization signal SD.

  The calculation processing apparatus 10 proceeds to step S59 after steps S56 and S58, and terminates the process when the process ends (step S59; Yes). If the calculation processing device 10 does not end the processing (step S59; No), the calculation processing device 10 returns to step S50 and obtains the next synchronization signal SD.

  The distributed simulation system 1 described above includes a plurality of calculation processing devices 10 that execute simulations with different calculation times A in one calculation cycle every time, and a control that is communicably connected to the plurality of calculation processing devices 10. And a processing device 20. The control processing device 20 includes a processing cycle setting unit 52, a virtual time setting unit 58, and a calculation instruction unit 44. The processing cycle setting unit 52 sets a processing cycle B, which is a cycle in which the calculation processing device 10 executes the simulation once, for each calculation processing device 10. The virtual time setting unit 58 sets the calculation virtual time E, which is the elapsed time in one simulation, so as to have the same relationship ratio as the relationship ratio between the lengths of the processing cycles B for each calculation processing device 10. To do. The calculation instruction unit 44 transmits a calculation instruction signal (synchronization signal SD synchronized with the calculation instruction flag F1) to each of the calculation processing apparatuses 10 at each timing for each processing cycle B set in the calculation processing apparatus 10. Each of the calculation processing devices 10 is caused to execute a simulation for the set calculation virtual time E for each processing cycle B set in itself. The processing cycle B of at least some of the calculation processing devices 10 is different from the processing cycle B of other calculation processing devices 10.

  The distributed simulation system 1 causes a plurality of calculation processing apparatuses 10 having different calculation times A to execute the simulation to execute the simulation. The control processing device 20 sets processing periods B having different lengths in accordance with the calculation processing device 10. Further, the control processing device 20 sets a calculated virtual time E that is a virtual elapsed time on one simulation so as to have the same relationship as the ratio of the length of the processing cycle B.

  When the calculation processing devices 10 having different processing cycles B are operated for the same time, the number of simulation executions may be different. Here, when the calculation virtual time E and the processing cycle B are not matched, when the calculation processing device 10 is operated for the same time, the elapsed time on the simulation for each calculation processing device 10 cannot be synchronized. There is a case. For example, when the calculation virtual time E is the same for each calculation processing device 10, the simulation processing time of the calculation processing device 10 with a shorter processing cycle B (the number of times of simulation execution is larger) is advanced. End up. In such a case, the accuracy of simulation decreases. However, in the present embodiment, the calculation virtual time E is set to have the same relationship as the ratio of the length of the processing cycle B. Therefore, when the processing apparatus 10 is operated for the same time, the elapsed time on the simulation for each calculation processing apparatus 10 is also the same. Thus, the distributed simulation system 1 according to the present embodiment can appropriately synchronize each simulation processing device 10 for each simulation.

  In addition, the calculation instruction unit 44 transmits the calculation instruction signal at each timing for each processing cycle B, thereby differentiating the number of simulation executions of the plurality of calculation processing devices 10 in the basic cycle. The distributed simulation system 1 can set the number of simulation processes according to the type of simulation and the specifications of the calculation processing apparatus 10 by making the number of simulation executions in the basic period different from each other. Therefore, this distributed simulation system 1 can improve the accuracy of the simulation.

  In addition, the control processing device 20 includes a calculation data acquisition unit 72 and a calculation data storage unit 74. The calculation data acquisition unit 72 acquires contact data that is output data used as input data of another calculation processing system. The calculation data storage unit 74 stores the contact data acquired by the calculation data acquisition unit 72. At least a part of the plurality of calculation processing apparatuses 10 acquires the contact data stored in the calculation data storage unit 74 and executes a simulation based on the contact data. In the distributed simulation system 1, when the calculation processing device 10 uses the mutual simulation results, the shared data is stored in the common area (calculation data acquisition unit 72 and calculation data storage unit 74) of the control processing device 20. Remember. Therefore, the distributed simulation system 1 can appropriately provide the trade data to the calculation processing device 10.

  In addition, the calculation data acquisition unit 72 holds the acquired trade data, and outputs the trade data to the calculation data storage unit 74 at the immediately preceding timing TI. The calculation processing apparatus 10 other than that having calculated the contact data acquires the contact data stored at the immediately preceding timing TI when at least a part of the simulation is performed in the processing cycle B immediately after the immediately preceding timing TI. Based on the above, the simulation is executed. The immediately preceding timing TI is a timing immediately before the start of the processing cycle B next to the processing cycle B for which the trade data has been calculated. Since the calculation data acquisition unit 72 holds the contact data until the previous timing TI, the calculation processing device 10 reads the contact data after the previous timing TI. Therefore, the distributed simulation system 1 can synchronize the acquisition of the contact data when the calculation processing devices 10 use the results of the simulations.

  The control processing device 20 further includes a change request data acquisition unit 48 that acquires change request data that is information on a change request for a simulation operation by an operator. The calculation instructing unit 44 receives a change request signal (synchronization signal SD synchronized with the operation flag FG) indicating information of the change request data to the calculation processing device 10 at the start timing of the basic cycle C immediately after the timing at which the change request data is acquired. ). Accordingly, the calculation instruction unit 44 synchronizes the timing of reflecting the change process in the change request signal to the calculation processing apparatus 10 with the other calculation processing apparatus 10. Since the control processing device 20 reflects the change request by the operator in synchronization with each calculation processing device 10, the simulation processing is matched to suppress a decrease in the accuracy of the simulation.

  In addition, the control processing device 20 sets the basic cycle C so that the cycle is the least common multiple of the length of each processing cycle B. The control processing device 20 can set the basic cycle C as short as possible by setting the basic cycle C to the least common multiple of the length of the processing cycle B. Thereby, for example, the reflection timing of the change process can be performed as soon as possible while synchronizing.

  The calculation processing device 10 is a plurality of devices that execute at least one simulation. When the calculation processing apparatus 10 includes a plurality of apparatuses, various kinds of simulations can be executed. On the other hand, in such a case, since the CPUs are different from each other, it is difficult to unify the calculation time A. Even in such a case, the control processing device 20 can appropriately synchronize each calculation processing device 10 for each simulation.

  The calculation processing device 10 may be a single device that executes a plurality of simulations. When the calculation processing apparatus 10 consists of one apparatus, control of each simulation becomes easy. Even in such a case, the control processing device 20 can appropriately take synchronization for each simulation.

(Second Embodiment)
Next, a second embodiment will be described. The distributed simulation system 1a according to the second embodiment is different from the first embodiment in that the speed of simulation can be changed. In the second embodiment, the description of the same configuration as the first embodiment is omitted.

  FIG. 13 is a block diagram illustrating a configuration of a control processing device according to the second embodiment. As illustrated in FIG. 13, the control processing device 20a included in the distributed simulation system 1a according to the second embodiment includes a calculation instruction unit 44a and a change request data acquisition unit 48a. The calculation instruction unit 44a is different from the first embodiment in that the operation flag setting unit 68a sets a speed flag FH in addition to the operation flag FG.

  The operation flag setting unit 68a sets the speed flag FH in its writable area at the same timing as the operation flag FG, that is, in synchronization with the basic cycle C. The operation flag setting unit 68a sets a speed flag FH common to all the calculation processing devices 10. The speed flag FH is a flag that is set based on operation information from an operator (instructor) input to the instructor operation device 30. The operation information input to the instructor operation device 30 is input to the change request data acquisition unit 48a. The change request data acquisition unit 48a is a case where the operation information is change request data which is information on a change request for a simulation operation and a request for a speed change operation. Output to. The operation flag setting unit 68a sets the speed flag FH based on the speed change change request data. The operation flag setting unit 68a sets the speed flag FH at the start timing of the basic cycle C immediately after the timing at which the speed change change request data is input. The control processing device 20 executes a speed change process when the speed flag FH changes.

  The speed change operation is an instruction to change the speed of the simulation. When the simulation speed is changed, the control processing device 20 performs a speed change process for changing the basic virtual time CX. If the basic virtual time CX becomes longer, the elapsed time in the simulation when the calculation processing apparatus 10 is operated for the same time becomes longer, so it can be said that the speed of the simulation is increased. On the contrary, when the basic virtual time CX is shortened, the elapsed time in the simulation when the calculation processing apparatus 10 is operated for the same time is shortened, so that it can be said that the simulation speed is reduced.

  As the speed change process, the control processing device 20 sets the number of calculation instruction flags F1 to be set or the calculation virtual time E in the calculation virtual time flag FE in the basic period C immediately after the speed change change request data is acquired. At least one of the lengths is changed. When the number of calculation instruction flags F1 set within the basic period C changes, the number of times the simulation is performed changes, and thus the basic virtual time CX that is the total virtual elapsed time in the basic period C changes. Further, when the length of the calculated virtual time E changes, the total basic virtual time CX changes. More specific description will be given below.

  FIG. 14 is a time chart for explaining the speed changing process. FIG. 14 shows an example in which an instruction to double the speed is input in the basic period C immediately before the basic period timing TC1 as change request data for speed change. In this case, the operation flag setting unit 68a sets the speed flag FH2 in synchronization with the synchronization timing TD1, which is the start timing of the basic period C immediately after the change request data is input. The speed flag FH2 is a flag with contents for doubling the speed.

  The speed change process in the example of FIG. 14 changes the length of the calculation virtual time E for the first calculation processing apparatus 10A, the second calculation processing apparatus 10B, and the third calculation processing apparatus 10C, and the fourth calculation processing apparatus 10D. The number of calculation instruction flags F1 set in the basic cycle C is changed. When the speed flag FH2 is set, the calculation virtual time flag setting unit 66 sets the first calculation virtual time EA at the synchronization timings TD1, TD2, TD3, and TD4 in the same basic period C to Δ6 that is twice the conventional value. . Similarly, the calculation virtual time flag setting unit 66 sets the second calculation virtual time EB at the synchronization timings TD1, TD2, TD3, and TD4 to Δ12, which is twice the conventional value. Similarly, the calculation virtual time flag setting unit 66 sets the third calculation virtual time EC at the synchronization timings TD1, TD2, TD3, and TD4 to Δ24 that is twice the conventional value.

  On the other hand, when the speed flag FH2 is set, the calculation processing flag setting unit 64 doubles the number of calculation instruction flags F1 in the basic cycle C. Specifically, the calculation process flag setting unit 64 changes the fourth calculation process flag FBD at the synchronization timing TD3 from the calculation non-execution flag F2 to the calculation instruction flag F1. The calculation processing flag setting unit 64 may change the fourth calculation processing flag FBD at the synchronization timing other than the synchronization timing TD3 to the calculation instruction flag F1 if the simulation is not performed.

  By performing such speed change processing, as shown in FIG. 14, the first calculation processing device 10A executes the simulation of the calculation virtual time Δ6 four times, and the second calculation processing device 10B calculates the calculation virtual time Δ12. The third calculation processing device 10C executes the simulation of the calculation virtual time Δ24 once, and the fourth calculation processing device 10D executes the simulation of the calculation virtual time Δ12 twice. . Therefore, the basic virtual time CX of all the calculation processing devices 10 is Δ24, which is twice that of the conventional case.

  In the example of FIG. 14, change request data for returning the speed to 1 is input at the basic cycle C of the basic cycle timing TC1 and between the synchronization timing TD3 and the synchronization timing TD4. In this case, the operation flag setting unit 68a sets the speed flag FH1 in synchronization with the synchronization timing TD5 that is the start timing of the basic period C immediately after the change request data is input. The speed flag FH1 is a flag with contents for doubling the speed. In the basic cycle C of the synchronization timing TD5, the calculation processing flag setting unit 64 and the calculation virtual time flag setting unit 66 restore the calculation processing flag FB and the calculation virtual time flag FE.

  As described above, even when the speed change request is input as the change request data, the calculation instruction unit 44 calculates the calculation processing device 10 at the start timing of the basic cycle C immediately after the timing at which the change request data is acquired. A change request signal (synchronization signal SD synchronized with the speed flag FH) indicating the information of the change request data is transmitted. Accordingly, the calculation instruction unit 44 synchronizes the timing of reflecting the change process in the change request signal to the calculation processing apparatus 10 with the other calculation processing apparatus 10. Since the control processing device 20 reflects the change request by the operator in synchronization with each calculation processing device 10, the simulation processing is matched to suppress a decrease in the accuracy of the simulation.

  As mentioned above, although embodiment of this invention was described, embodiment is not limited by the content of this embodiment. In addition, the above-described constituent elements include those that can be easily assumed by those skilled in the art, those that are substantially the same, and those in a so-called equivalent range. Furthermore, the above-described components can be appropriately combined. Furthermore, various omissions, substitutions, or changes of the components can be made without departing from the spirit of the above-described embodiment.

DESCRIPTION OF SYMBOLS 1 Distributed simulation system 10 Calculation processing apparatus 10A 1st calculation processing apparatus 10B 2nd calculation processing apparatus 10C 3rd calculation processing apparatus 10D 4th calculation processing apparatus 20 Control processing apparatus 30 Instructor operation apparatus 44 Calculation instruction | indication part 52 Processing period setting part 54 Basic cycle setting unit 56 Synchronization cycle setting unit 58 Virtual time setting unit 62 Synchronization signal setting unit 64 Calculation processing flag set unit 66 Calculation virtual time flag set unit 68 Operation flag set unit 72 Calculation data acquisition unit 74 Calculation data storage unit A Calculation time B Processing cycle C Basic cycle D Synchronization cycle E Calculation virtual time TA Clock timing TB Processing cycle timing TC Basic cycle timing TD Synchronization timing

Claims (9)

A plurality of calculation processing systems for executing simulations with different calculation times in one calculation cycle every time;
A control processing system communicably connected to the plurality of calculation processing systems,
The control processing system includes:
A processing cycle setting unit that sets a processing cycle, which is a cycle in which the calculation processing system executes the simulation once, for each of the calculation processing systems;
A virtual time setting unit that sets a calculation virtual time, which is an elapsed time in one simulation, to be the same relationship ratio as the relationship ratio between the lengths of the processing cycles for each of the calculation processing systems;
A calculation instruction signal is transmitted to each of the calculation processing systems at each timing for each of the processing cycles set in the calculation processing system, and each of the calculation processing systems is set to its own processing cycle. A calculation instruction unit for executing simulation for the set calculation virtual time;
Have
The processing cycle set in at least some of the calculation processing systems is different in length from the processing cycle set in other calculation processing systems,
The control processing system includes:
Of the output data that is the processing result of the simulation, a calculation data acquisition unit that acquires contact data that is output data used as input data of the other calculation processing system;
A calculation data storage unit that stores the contact data acquired by the calculation data acquisition unit;
The calculation data acquisition unit holds the acquired interaction data, and stores the interaction data in the calculation data storage unit at a timing immediately before the start of a processing cycle next to a processing cycle in which the interaction data is calculated. Output,
The calculation processing system other than the calculation of the contact data obtains the contact data stored at the immediately preceding timing when at least a part of the calculation processing system performs a simulation in the processing cycle immediately after the immediately preceding timing. A distributed simulation system for executing the simulation based on the above .   The calculation instruction unit transmits the calculation instruction signal at each timing for each processing cycle, so that a plurality of the calculation processing systems in the basic cycle having a length that is a common multiple of the length of each processing cycle. The distributed simulation system according to claim 1, wherein the number of simulation executions is different from each other. The control processing system further includes an operation information acquisition unit that acquires change request data that is information on a change request for a simulation operation by an operator,
The calculation instructing unit transmits the change request signal indicating information on the change request data to the calculation processing system at a start timing of the basic period immediately after the timing at which the change request data is acquired, thereby calculating the calculation The distributed simulation system according to claim 2, wherein the timing of reflecting the change process in the change request signal to the processing system is synchronized with another calculation processing system. The calculation instruction unit transmits a synchronization signal to each of the calculation processing systems at a timing for each synchronization period that is a period of a common divisor of each processing period,
The calculation instruction unit sets a calculation instruction flag for each of the calculation processing systems in synchronization with a synchronization signal transmitted at a timing that coincides with the processing cycle of the calculation processing system. 4. The distributed simulation system according to claim 2, wherein a calculation non-execution flag, which is information not to newly execute a simulation, is set in synchronization with a synchronization signal transmitted at a timing that does not coincide with the processing cycle. Wherein the control processing system, such that the length period of the least common multiple of the length of each of the processing cycle, with a fundamental period setting unit for setting the basic period, any of claims 2 4 2. A distributed simulation system according to item 1. The distributed simulation system according to any one of claims 1 to 5 , wherein each of the plurality of calculation processing systems is a plurality of calculation processing devices that execute at least one simulation. Wherein the plurality of computing systems, which is one of the central processing unit for executing a plurality of said simulation, distributed simulation system according to any one of claims 1 to 6. The simulation is executed by using a plurality of calculation processing systems that execute simulations with different calculation times in one calculation cycle every time and a control processing system that is connected to the plurality of calculation processing systems so as to be communicable. A simulation execution method,
A processing cycle setting step for setting a processing cycle, which is a cycle in which the calculation processing system executes the simulation once, for each of the calculation processing systems;
A virtual time setting step for setting a calculation virtual time, which is an elapsed time in one simulation, to be the same relationship ratio as the relationship ratio between the lengths of the processing cycles for each of the calculation processing systems;
A calculation instruction signal is transmitted to each of the calculation processing systems at each timing of the processing cycle set in the calculation processing system, and the calculation virtual time set in the calculation processing system is transmitted to each of the calculation processing systems. A calculation instruction step for causing the simulation to be executed every set processing cycle,
In the processing cycle setting step, the processing cycle set in at least some of the calculation processing systems is different in length from the processing cycle set in other calculation processing systems.
Furthermore, among the output data that is the processing result of the simulation, further includes a calculation data acquisition step of acquiring contact data that is output data used as input data of the other calculation processing system,
In the calculation data acquisition step, the acquired contact data is held, and the contact data is stored in the immediately preceding timing which is a timing immediately before the start of the processing cycle next to the processing cycle in which the contact data is calculated. Output to the calculation data storage
When performing simulation in the processing cycle immediately after the immediately preceding timing, at least a part of the calculation processing system other than that having calculated the interaction data, the interaction data stored at the immediately preceding timing is acquired, A simulation execution method for executing the simulation based on the simulation . A control system for controlling a plurality of calculation processing systems that execute simulations with different calculation times in one calculation cycle every time,
A processing cycle setting unit that sets a processing cycle, which is a cycle in which the calculation processing system executes the simulation once, for each of the calculation processing systems;
A virtual time setting unit that sets a calculation virtual time, which is an elapsed time in one simulation, to be the same relationship ratio as the relationship ratio between the lengths of the processing cycles for each of the calculation processing systems;
A calculation instruction signal is transmitted to each of the calculation processing systems at each timing for each of the processing cycles set in the calculation processing system, and each of the calculation processing systems is set to its own processing cycle. A calculation instruction unit for executing simulation for the set calculation virtual time;
Have
The processing cycle set in at least some of the calculation processing systems is different in length from the processing cycle set in other calculation processing systems,
Of the output data that is the processing result of the simulation, a calculation data acquisition unit that acquires contact data that is output data used as input data of the other calculation processing system;
A calculation data storage unit that stores the contact data acquired by the calculation data acquisition unit;
The calculation data acquisition unit holds the acquired interaction data, and stores the interaction data in the calculation data storage unit at a timing immediately before the start of a processing cycle next to a processing cycle in which the interaction data is calculated. Output,
When performing simulation in the processing cycle immediately after the immediately preceding timing, at least a part of the calculation processing system other than that having calculated the interaction data, the interaction data stored at the immediately preceding timing is acquired, A control system for executing the simulation based on the above .

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