JP6565567B2 - Image processing apparatus, imaging apparatus, image processing method, and program - Google Patents

Description

  The present invention relates to an image processing apparatus, an imaging apparatus, an image processing method, and a program, and more specifically, an image processing apparatus that serially transfers image data with effective length specifying information indicating the effective length of the image data, and imaging The present invention relates to an apparatus, an image processing method, and a program.

  An image processing apparatus such as a digital camera has a plurality of circuit modules such as a circuit module related to image processing and a circuit module that performs communication with the outside. Circuit modules for communicating with the outside include an SPI (Serial Peripheral Interface) that communicates with an internal CPU (Central Processing Unit), a high-speed serial interface, and the like.

  An image processing apparatus transfers image data between circuit modules using a high-speed serial interface, and conventionally, a synchronization code for indicating a range of valid image data is transferred together with the image data.

  Each circuit module has a register in which operation control control information such as a synchronization code is set, and SPI is often used to access this register from an external CPU.

  Also, writing control information by single transfer using SPI takes time and affects performance. Therefore, for registers that require frequent writing, control information addresses are continuously arranged so that they can be written in bursts.

  Here, the single transfer refers to a transfer method in which the bus control right is released every time one cycle of data transfer is executed. Burst transfer refers to a transfer method in which when data transfer is started, data transfer is continuously executed until the transfer is completed a specified number of times, and the bus control right is not released.

  However, in the circuit module of the high-speed serial interface, it is necessary to set effective length information in a register that sets a range of effective image data every time the image size is changed. Therefore, since the effective length information is arranged at an address different from that of a register that frequently requires write processing, it is necessary to transfer the effective length information as a single transfer. As a result, if the effective length of the image data changes frequently, the effective length information is performed by single transfer of the SPI, and there is a problem that the transfer speed of the image data decreases.

  Conventionally, a transmission control circuit that is connected to a plurality of devices and controls information transmission between the devices, and a signal for selecting a device that performs information transmission among the plurality of devices and a type of information transmission A signal output unit that outputs a signal for identifying, a register value indicating a transmission frequency according to the type of information transmission, a register value acquisition unit that acquires from a device that performs the information transmission, and the acquired register value There has been proposed a transmission control circuit including a frequency determining unit that determines a corresponding transmission frequency and a clock generating unit that outputs a clock signal of the determined transmission frequency (see Patent Document 1).

  However, the prior art described in the above publication does not consider the single transfer of effective length information using SPI to a register that sets the range of effective image data every time the image size is changed. There was a need for.

  Therefore, an object of the present invention is to improve the transfer efficiency of image data by a high-speed serial interface based on control information transferred by a low-speed serial interface.

  In order to achieve the above object, the image processing apparatus according to claim 1 performs image processing on input image data by image processing means based on control information from the outside, and the processed image data is converted into the image data. An image processing apparatus that transfers the effective length specifying information indicating the effective length of the data to the outside by a serial transfer unit, the first storage unit storing effective length information capable of generating the effective length specifying information; Second storage means for storing control information including effective length information; storage control means for receiving the control information including the effective length information transmitted from the outside and storing the control information in the second storage means; Effective length information updating means for obtaining the effective length information from the control information of the second storage means and updating the effective length information of the first storage means. .

  According to the present invention, it is possible to improve the transfer efficiency of image data by a high-speed serial interface based on control information transferred by a low-speed serial interface.

1 is a block diagram of a main part of an imaging apparatus to which an embodiment of the present invention is applied. The principal part block diagram of image processing ASIC. The figure which shows the register space allocation for every module. The figure which shows the register write sequence and register read sequence of SPI. The figure which shows the transfer order of the byte unit of SPI. The figure which shows the overhead from the communication end of SPI to the start. The figure which shows arrangement | positioning of a LLEN setting register. The figure which shows an example of the space allocation of a LLEN setting register area. Explanatory drawing of the signal relationship of an image processing ASIC and an effective length information taking-in process. The functional block diagram of image processing ASIC. The figure which shows the timing of the main signal in image processing ASIC. The flowchart which shows a data transfer process.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The range of this invention is unduly limited by the following description. However, not all the configurations described in the present embodiment are essential constituent elements of the present invention.

  1 to 12 are diagrams illustrating an embodiment of an image processing apparatus, an imaging apparatus, an image processing method, and a program according to the present invention. FIG. 1 illustrates an image processing apparatus, an imaging apparatus, an image processing method, and an image processing apparatus according to the present invention. It is a principal part block diagram of the imaging device 1 to which one Example of the program is applied.

  In FIG. 1, an imaging apparatus 1 includes an imaging sensor 2, an image processing ASIC (Application Specific Integrated Circuit) 3, a DSP (Digital Signal Processor) 4, and the like. In the imaging apparatus 1, the imaging sensor 2 and the image processing ASIC 3 are connected by a signal line 5, and the image processing ASIC 3 and the DSP 4 are connected by a high-speed serial bus 6 and a low-speed serial bus 7. In the imaging apparatus 1 of the present embodiment, a subLVDS interface bus is used as the high-speed serial bus 6, and an SPI bus is used as the low-speed serial bus 7. Although not shown, the imaging device 1 includes an SD (Secure Digital) card, a memory card, an LCD (Liquid Crystal Display) monitor, various operation buttons, and the like.

  For example, a CCD (Charge Coupled Device) or the like is used as the imaging sensor (imaging means) 2, and an image of a subject is captured and image data of the subject is output to the image processing ASIC 3 through the signal line 5.

  The image processing ASIC 3 performs image processing on the image data sent from the image sensor 2 based on control information transferred from the DSP 4 through the low-speed serial bus 7, and transfers the image data to the DSP 4 through the high-speed serial bus 6. .

  The DSP 4 is basically composed of a signal processing unit (processor unit comprising an ALU (Arithmetic Logic Unit)) and a program storage unit (memory) for operating the signal processing unit, and has both hardware and software. ing. The DSP 4 has a plurality of ALUs, a SIMD (Single Instruction-stream Multiple Data-stream) structure in which the plurality of ALUs execute simultaneously in parallel on a series of image data, and processing such as error diffusion unsuitable for parallel processing. By using dedicated hardware, high-speed and flexible processing is performed.

  The DSP 4 is equipped with a CPU 8, and a memory in the DSP 4 stores a basic program as the imaging device 1 and a program for executing the image processing method of the present invention.

  The CPU 8 controls each part of the imaging device 1 based on the program, controls basic processing operations as the imaging device 1, and executes processing of the SD card, memory card, LCD monitor, and various operation buttons. .

  The CPU 8 is connected to the image processing ASIC 3 via the low-speed serial bus 7. Based on the program of the present invention, the CPU 8 executes an image processing method for improving the transfer efficiency of image data by the high-speed serial bus 6 of the high-speed serial interface based on the setting of control information using the low-speed serial bus 7 such as SPI. . That is, control information in the operation of the image processing ASIC 3 is transferred to the image processing ASIC 3 through the SPI low-speed serial bus 7, and the image processing ASIC 3 includes an interface of the low-speed serial bus 7, for example, SPI.

  The image processing ASIC 3 that is an image processing device performs necessary image processing on the image data sent from the imaging sensor 2 based on control information set by the CPU 8, and converts the processed image data to effective length information. Is transferred to the DSP 4 via the high-speed serial bus 6. The image processing ASIC 3 is equipped with a plurality of circuit modules in order to perform image processing necessary for the imaging device 1 on the image data. As shown in FIG. 2, the image processing ASIC 3 includes a register access unit 11, a system unit 12, an image processing unit 13, a high-speed serial interface 14 and the like as circuit modules necessary for the image processing method of the present invention. Note that the image processing ASIC 3 also includes circuit modules (not shown in FIG. 2).

  The system unit 12, the image processing unit 13, and the high-speed serial interface 14 are equipped with operation control registers 12a, 13a, and 14a, respectively, and the register access unit 11 and APB (Advanced Peripheral Bus) 15, 16, and 17 are mounted. Connected with.

  The register access unit 11 is connected to the CPU 8 mounted on the DSP 4 via a low-speed serial bus 7 of a low-speed serial interface such as SPI. The register access unit 11 transfers and writes the control information serially transferred from the CPU 8 to the registers 12a, 13a, and 14a of the units 12, 13, and 14 to which addresses are assigned in advance through the APBs 15, 16, and 17, respectively.

  The system unit 12 controls the operation of each circuit module of the image processing ASIC 3 based on the control information set in the register 12a.

  Under the control of the system unit 12, the image processing unit 13 performs necessary image processing on the image data sent from the imaging sensor 2 based on control information set in the register 13 a, and performs a high-speed serial interface 14. To pass.

  The high-speed serial interface 14 is effective length specifying information indicating the effective length information in the image data based on effective length information indicating the effective length of the image data processed by the image processing unit 13 set in the register 14a. A synchronization code is added before and after the image data and transferred.

  In general, the system unit 12 of the image processing ASIC 3, the image processing unit 13, other modules, and the registers 12 a, 13 a, and 14 a of the high-speed serial interface 14 are allocated as shown in FIG. 3. . In FIG. 3, reference numeral 18 denotes another circuit module, and 18a denotes a register of the other circuit module.

  That is, the registers 12a and 13a of the system unit 12 and the image processing unit 13 have their address values arranged in a continuous address space, but the address values of the register 14a of the high-speed serial interface 14 are in a continuous address space. Is not arranged. The registers 12a and 13a of the system unit 12 and the image processing unit 13 are registers in which control information needs to be set for each image. Accordingly, the address values of these registers 12a and 13a are arranged in a continuous address space so that the control information can be transferred at high speed by burst transfer on the low-speed serial bus 7 and set. However, since the register 14a of the high-speed serial interface 14 is set with the effective length information of the image data to be transferred, it is generally set at the time of initialization and is not frequently rewritten. Therefore, the control information of the register 14 a of the high-speed serial interface 14 is transferred from the CPU 8 by single transfer using the low-speed serial bus 7 and set in the register 14 a by the register access unit 11.

  However, the image capturing apparatus 1 often performs image capturing with zoom processing or the like, and the effective length range of the image data processed by the image processing unit 13 often changes. In such a case, if the effective length information is transferred from the CPU 8 through the low-speed serial bus 7 by single transfer and set in the register 14a of the high-speed serial interface 14, the transfer efficiency of the image data of the high-speed serial interface 14 is lowered. . In the following description, the low-speed serial bus 7 is described as using the SPI. However, the low-speed serial bus 7 is not limited to the SPI, but is a serial that switches between burst transfer and single transfer according to the address space of the data to be transferred. Any interface can be used. Here, when the low-speed serial bus 7 is SPI, four signal lines of SCK (Serial Clock), MISO (Master In Slave Out), MOSI (Master Out Slave In), and SS (Slave Select) are used. . Hereinafter, a clock flowing through SCK is referred to as an SCS signal, a signal flowing through MISO is referred to as an SDI signal, and a signal flowing through MOSI is referred to as an SDO signal.

  That is, data transfer by the low-speed serial bus 7 using SPI is performed by a register write sequence and a register read sequence as shown in FIGS. 4A and 4B, and the transfer order in units of bytes is shown in FIG. It is shown as 5. In FIG. 4A showing the register write sequence, an SDI signal surrounded by a broken line corresponds to the SDI in FIG. 5 and is a register write signal, and when the SCS signal is low (Low), The data is transferred from the CPU 8 to the register access unit 11. In FIG. 4B showing the register read sequence, the SDO signal surrounded by a broken line corresponds to the SDO in FIG. 5 and is a register read signal. When the SCS signal is low, register access is performed. The data is transferred from the unit 11 to the CPU 8.

  In burst transfer by SPI, in the case of write transfer, as shown in FIGS. 4A and 5, the CPU 8 first transfers a byte (MD, MD) indicating write, and then accesses a register. Are transferred from the first ADR3 to the last ADR0. Next, the CPU 8 considers the response preparation time on the image processing ASIC 3 side, transfers the data preparation period by 2 bytes (00, 00), and then accesses the write sequentially from the beginning of the transfer address. The CPU 8 ends the write transfer by the burst transfer when the SCS signal becomes high.

  Similarly, in the case of read transfer, as shown in FIG. 4B and FIG. 5, the byte (0, 0) indicating the read is transferred first, and the ID of the DSP 4 to be accessed next is the lower and upper IDs. Transfer in order. Next, considering the response preparation time on the image processing ASIC 3 side, the CPU 8 transfers the data preparation period by 2 bytes (00, 00), and then performs read access. The CPU 8 ends the read transfer by the burst transfer when the SCS signal becomes high.

  Then, as shown in FIG. 6, the SPI has an overhead of about 1 ms for software reasons, from “1” at the end of one transfer until the SCS signal is set to “0” for the next command. Need.

  In single transfer by SPI, it is necessary to release the bus control right every time data transfer is executed for one cycle. Therefore, the register 14a of the high-speed serial interface 14 to which the control information is transferred by single transfer needs to transfer the effective length information by single transfer every time the effective length information of the image data is changed, and the transfer efficiency is low. .

  Therefore, the image processing ASIC 3 of the present invention is provided with the LLEN setting register area 12aa in the register 12a of the system unit 12 as shown in FIG. 7 in the register space for each module shown in FIG. As shown in FIG. 8, the LLEN setting register area 12aa stores effective length information and is formed in an address area continuous with the control information register for the system unit 12. That is, the register 12a of the system unit 12 has its address value formed in a continuous address space including the LLEN setting register area 12aa.

  In the LLEN setting register area 12aa, as shown in FIG. 8, effective length information ([13: 0]) is set in bits 13 to 0, and LLEN_EN (hereinafter, acquisition availability information LLEN_EN) that is acquisition availability information is set in bit 15. "1" and "0" are set.

  Therefore, the CPU 8 can perform burst transfer of control information including effective length information through the low-speed serial bus 7 that is an SPI, and can transfer the control information at high speed and efficiently.

  Then, in the image processing ASIC 3, as shown in FIG. 9A, the system unit 12 outputs LLEN [13: 0] as effective length information and LLEN_EN as availability information to the high-speed serial interface 14. In the image processing ASIC 3, the image processing unit 13 outputs the vertical synchronization signal VD, the horizontal synchronization signal HD, and the image data DATA to the high-speed serial interface 14, and the clock CLK is further input to the high-speed serial interface 14. The

  In the high-speed serial interface 14, as shown in FIG. 9B, the acquisition permission information LLEN_EN from the system unit 12 is “1”, and the falling edge after the horizontal synchronization signal HD from the image processing unit 13 rises. At the timing, the value of the effective length information LLEN [13: 0] is acquired. Note that, as shown in FIG. 9B, the high-speed serial interface 14 has the effective length information LLEN [13: when the acquisition possibility information LLEN_EN is “0”, even if it falls after the horizontal synchronization signal HD rises. [0] value is not captured.

  The image processing ASIC 3 is stored in an internal memory (not shown) or in the memory of the imaging apparatus 1. ROM, EEPROM (Electrically Erasable and Programmable Read Only Memory), EPROM, flash memory, flexible disk, CD-ROM (Compact Disc Read) Recorded on a computer-readable recording medium, such as Only Memory), CD-RW (Compact Disc Rewritable), DVD (Digital Versatile Disk), USB (Universal Serial Bus) memory, SD card, MO (Magneto-Optical Disc), etc. Image processing that improves the transfer efficiency of image data by a high-speed serial interface based on the setting of control information transferred by a low-speed serial interface, which will be described later, by loading and introducing a program that executes the image processing method of the present invention As an image processing apparatus for executing the method It is built. And the imaging device 1 is constructed | assembled as an imaging device carrying image processing ASIC3 which is this image processing device. This program is a computer-executable program written in a legacy programming language such as assembler, C, C ++, C #, Java (registered trademark), an object-oriented programming language, or the like, and is stored in the recording medium and distributed. be able to.

  The image processing ASIC 3 that is an image processing apparatus is configured with the functional blocks shown in FIG. 10 by introducing the program. That is, the image processing ASIC 3 is installed with the above-described program, so that the high-speed serial transfer unit 23 having the first storage unit 21 and the effective length information update unit 22 and the second storage unit 24 are provided as shown in FIG. A control unit 25, an image processing unit 26, and a storage control unit 27 are constructed.

  The first storage unit 21 stores effective length information that is constructed by the register 14a and that can generate a synchronization code that is effective length specifying information. Therefore, the first storage unit 21 functions as a first storage unit.

  The second storage unit 24 is constructed by the register 12a of the system unit 12, and stores control information including the effective length information. Therefore, the second storage unit 24 functions as a second storage unit.

  The storage control unit 27 is constructed by the register access unit 11, receives control information including effective length information of processed image data transmitted from the CPU 4 of the external DSP 4 and stores it in the second storage unit 24. Let Therefore, the storage control unit 27 functions as a storage control unit.

  The effective length information update unit 22 is constructed by the high-speed serial interface 14, acquires the effective length information from the control information in the second storage unit 24, and updates the effective length information in the first storage unit 21. Therefore, the effective length information updating unit 22 functions as effective length information updating means.

  The control unit 25 is constructed by the system unit 12, and the availability information LLEN_EN indicating availability of the effective length information LLEN [13: 0] and the effective length information LLEN [13: 0] in the second storage unit 24. Is output to the high-speed serial transfer unit 23. Therefore, the control unit 25 functions as a control unit.

  The image processing unit 26 is constructed by the image processing unit 13 and performs necessary image processing on the image data from the imaging sensor 2 based on control information set in the register 13a. The image processing unit 26 outputs the processed image data and the horizontal synchronization signal HD and the vertical synchronization signal VD related to the image data to the serial transfer unit 23. Therefore, the image processing unit 26 functions as an image processing unit.

  The high-speed serial transfer unit 23 is constructed by the high-speed serial interface 14 and includes a first storage unit 21 and an effective length information update unit 22. The high-speed serial transfer unit 23 receives the effective length information LLEN [13: 0] when the effective length information updating unit 22 indicates that the acquisition permission information LLEN_EN indicates acquisition permission and the horizontal synchronization signal HD is output. get. The effective length information update unit 22 updates the effective length information LLEN [13: 0] in the first storage unit 21 with the acquired effective length information LLEN [13: 0]. Therefore, the high-speed serial transfer unit 23 functions as a serial transfer unit.

  Next, the operation of this embodiment will be described. In the image pickup apparatus 1 of the present embodiment, the image processing ASIC 3 improves the transfer efficiency of image data by the high-speed serial interface based on the setting of control information transferred by the low-speed serial interface.

  That is, the imaging apparatus 1 includes an image processing ASIC 3 that performs image processing on image data captured by the imaging sensor 2. The image processing ASIC 3 performs image processing based on control information set through the low-speed serial bus 7 from the CPU 8 of the DSP 4. Apply. The image processing ASIC 3 includes a high-speed serial interface 14 of the high-speed serial bus 6. The high-speed serial interface 14 generates a synchronization code that is effective length specifying information of image data to be transferred based on the effective length information stored in the register 14a, and adds the synchronization code to the image data. The high-speed serial interface 14 transfers the image data to which the synchronization code is added to the DSP 4 through the high-speed serial bus 6.

  That is, as shown in FIG. 11A, the image processing ASIC 3 sends an image from the image processing unit 13 to the high-speed serial interface 14 using the signals of the horizontal synchronization signal HD, the vertical synchronization signal VD, and the image data DATA [15: 0]. Data DATA is transferred. In the transfer of image data from the image processing unit 13 to the high-speed serial interface 14, the start of transfer of effective image data in units of pages is indicated by the vertical synchronization signal VD, and effective image data in units of lines is transferred by the horizontal synchronization signal HD. The start of is indicated.

  As shown in FIG. 11B, the high-speed serial interface 14 transfers the image data DATA with a serial differential signal of DATA_P and DATA_N. The high-speed serial interface 14 transfers the synchronization code HBE after the transfer period indicated by the synchronization code HBS and the effective length information LLEN [13: 0] in synchronization with the horizontal synchronization signal HD before the vertical synchronization signal VD is input. To do. After the vertical synchronization signal VD is input, the high-speed serial interface 14 is synchronized with the horizontal synchronization signal HD, and the valid image data indicated by valid during the transfer period of the synchronization code HVS and the effective length information LLEN [13: 0]. Then, after the transfer period of the valid length information LLEN [13: 0], the synchronization code HVE is transferred.

  The DSP 4 determines a period during which valid image data is transferred based on the valid image data valid of the serial differential signals DATA_P and DATA_N and the synchronization codes HVS and HVE, and takes in valid image data.

  That is, the image processing ASIC 3 performs the data transfer process shown in FIG. 12 to efficiently transfer the image data. That is, as shown in FIG. 12, the image processing ASIC 3 checks whether the storage control unit 27 has received control information including effective length information from the external CPU 8 through the low-speed serial bus 7 (step S101). When the control signal is received in step S101 (when YES in step S101), the storage control unit 27 stores the control information including the effective length information in the storage unit, particularly the second storage unit 24. (Step S102).

  At this time, the storage control unit 27 uses the LLEN setting register in which the register 12a constructing the second storage unit 24 stores effective length information serving as an address space continuous with the control information, as shown in FIG. A region 12aa is provided. Therefore, the storage control unit 27 can store the effective length information LLEN [13: 0] from the control unit 25 in a continuous address space, and is transferred from the CPU 8 by the high-speed burst transfer by the low-speed serial bus 7. come.

  Next, the valid length information update unit 22 of the high-speed serial transfer unit 23 checks whether or not the acquisition permission information LLEN_EN input from the control unit 25 is “1” indicating acquisition permission (step S103).

  In step S103, the effective length information update unit 22 waits for the horizontal synchronization signal HD to be input if the acquisition permission / inhibition information LLEN_EN is “1” (YES in step S103) (step S104).

  When the horizontal synchronization signal HD is input in step S104 (YES in step S104), the effective length information update unit 22 acquires effective length information LLEN [13: 0] (step S105). That is, when the horizontal synchronization signal HD is input when the availability information LLEN_EN is “1”, the effective length information update unit 22 receives the effective length information LLEN [13: 0] input from the control unit 25. get.

  The effective length information update unit 22 updates the effective length information LLEN [13: 0] stored in the first storage unit 21 of the high-speed serial transfer unit 23 with the acquired effective length information LLEN [13: 0]. (Step S106).

  The high-speed serial transfer unit 23 generates the synchronization codes HVS and HVE based on the updated effective length information LLEN [13: 0] in the first storage unit 21 (step S107). The high-speed serial transfer unit 21 transfers the valid image data of the serial differential signals DATA_P and DATA_N to which the synchronization codes HVS and HVE are added to the DSP 4 through the high-speed serial bus 6 (step S108).

  In step S103, if the availability information LLEN_EN is “0” (NO in step S103), the effective length information update unit 22 does not receive the effective length information LLEN [ 13: 0] is acquired, and the process proceeds to step S107. The high-speed serial transfer unit 21 generates the synchronization codes HVS and HVE based on the valid length information LLEN [13: 0] in the first storage unit 21 that has not been updated (step S107). The high-speed serial transfer unit 21 transfers the valid image data of the serial differential signals DATA_P and DATA_N to which the synchronization codes HVS and HVE are added to the DSP 4 through the high-speed serial bus 6 (step S108).

  Accordingly, the image processing ASIC 3 can efficiently receive control information including effective length information burst-transferred from the external CPU 8 through the low-speed serial bus 7 and store it in the first storage unit 21. As a result, the transfer efficiency of image data by the high-speed serial interface 14 can be improved based on the control information transferred by the low-speed serial interface.

  As described above, in the imaging apparatus 1 of this embodiment, the image processing ASIC 3 performs image processing on the input image data by the image processing unit 26 that is an image processing unit based on control information from the outside. Is an image processing apparatus that transfers the image data together with a synchronization code (effective length specifying information) indicating the effective length of the image data to the DSP 4 that is external by the high-speed serial transfer unit (serial transfer means) 23. A first storage unit (first storage means) 21 that stores effective length information LLEN [13: 0] capable of generating a code, and a first storage unit that stores control information including the effective length information LLEN [13: 0]. Two storage units (second storage means) 24 and the control information including the effective length information LLEN [13: 0] transmitted from the external CPU 8 and receiving the control information. The effective length information LLEN [13: 0] is acquired from the control information stored in the storage control unit (storage control means) 27 and the second storage unit 24, and stored in the first storage unit 21. An effective length information updating unit (effective length information updating means) 22 for updating the effective length information LLEN [13: 0].

  Therefore, the image processing ASIC 3 can efficiently receive control information transferred from the external CPU 8 through a low-speed serial interface such as SPI, particularly effective length information LLEN [13: 0]. As a result, it is possible to improve the transfer efficiency of the image data by the high-speed serial interface based on the effective length information LLEN [13: 0].

  In addition, the imaging apparatus 1 according to the present exemplary embodiment performs image processing on input image data using an image processing unit 26 that is an image processing unit based on control information from an external CPU 8, and processes processed image data. Along with the synchronization code (effective length specifying information) indicating the effective length of the image data, the image processing ASIC 3 that transfers to the external DSP 4 by the high-speed serial transfer unit 23 that is serial transfer means can generate the synchronization code. A first storage processing step of storing information LLEN [13: 0] in the first storage unit (first storage means) 21; and control information including the effective length information LLEN [13: 0] A second storage processing step stored in the storage unit (second storage means) 24 and the control length including the effective length information LLEN [13: 0] transmitted from the external CPU 8. A storage control processing step for receiving information and storing the information in the second storage unit 24; obtaining the effective length information LLEN [13: 0] from the control information in the second storage unit 24; The effective length information update processing step of updating the effective length information LLEN [13: 0] in the storage unit 21 is executed.

  Therefore, the image processing ASIC 3 can efficiently receive control information transferred from the external CPU 8 through a low-speed serial interface such as SPI, particularly effective length information LLEN [13: 0]. As a result, it is possible to improve the transfer efficiency of the image data by the high-speed serial interface based on the effective length information LLEN [13: 0].

  Further, the image pickup apparatus 1 according to the present embodiment performs image processing on input image data based on control information from the external CPU 8 by the image processing unit 26, and converts the processed image data to the validity of the image data. Along with the synchronization code indicating the length (effective length specifying information), the image processing ASIC 3 which is an image processing device that transfers to the external DSP 4 by the high-speed serial transfer unit 23 enables the control processor to generate the synchronization code. First storage processing for storing LLEN [13: 0] in the first storage unit (first storage unit) 21 and control information including the effective length information LLEN [13: 0] in the second storage unit (Second storage means) Upon receiving the control information including the second storage process stored in 24 and the effective length information LLEN [13: 0] transmitted from the external CPU 8 The effective length information LLEN [13: 0] is obtained from the storage control process to be stored in the second storage unit 24 and the control information in the second storage unit 24, and the first storage unit 21 A program for executing effective length information update processing for updating the effective length information LLEN [13: 0] is installed.

  Therefore, the image processing ASIC 3 can efficiently receive control information transferred from the external CPU 8 through a low-speed serial interface such as SPI, particularly effective length information LLEN [13: 0]. As a result, it is possible to improve the transfer efficiency of the image data by the high-speed serial interface based on the effective length information LLEN [13: 0].

  Further, in the image processing ASIC 3 of the imaging apparatus 1 according to the present embodiment, the storage control unit 27 continuously transmits the effective length information LLEN [13: 0] and the other control information to the second storage unit 24, respectively. Store it at the address you want.

  Therefore, the image processing ASIC 3 receives the control information transferred from the external CPU 8 through the low-speed serial interface such as SPI, in particular, the effective length information LLEN [13: 0] more efficiently by burst transfer. Can do. As a result, the image data transfer efficiency by the high-speed serial interface based on the effective length information LLEN [13: 0] can be further improved.

  Furthermore, in the imaging apparatus 1 of the present embodiment, the image processing ASIC 3 includes the second storage unit 24, and the effective length information LLEN [13: 0] and the effective length of the second storage unit 24 are included. The image processing unit further includes a control unit (control unit) 25 that outputs acquisition availability information LLEN_EN indicating whether the information LLEN [13: 0] can be acquired to the high-speed serial transfer unit 23 serving as the serial transfer unit. The processing unit 26 outputs the processed image data and the horizontal synchronization signal HD related to the image data to the high-speed serial transfer unit 23, and the high-speed serial transfer unit 23 includes the first storage unit 21 and the effective length information. An update unit 22, and when the effective length information update unit 22 indicates that the acquisition permission information LLEN_EN indicates acquisition permission (“1”) and the horizontal synchronization signal HD is output The effective length information LLEN [13: 0] to get the acquired the effective length information LLEN [13: 0] in the effective length information LLEN of the first storage unit 21 [13: 0] Update.

  Therefore, the image processing ASIC 3 can efficiently receive control information transferred from the external CPU 8 through a low-speed serial interface such as SPI, particularly effective length information LLEN [13: 0]. As a result, it is possible to improve the transfer efficiency of the image data by the high-speed serial interface based on the effective length information LLEN [13: 0].

  In the imaging apparatus 1 according to the present embodiment, the storage control unit 27 receives the control information including the effective length information LLEN [13: 0] from the external CPU 8 by SPI.

  Therefore, the image processing ASIC 3 can efficiently receive control information using the SPI from the external CPU 8, in particular, the effective length information LLEN [13: 0]. As a result, it is possible to improve the transfer efficiency of the image data by the high-speed serial interface based on the effective length information LLEN [13: 0].

  Furthermore, the imaging apparatus 1 according to the present embodiment is an imaging apparatus that serially transfers image data captured by the imaging sensor 2 serving as an imaging unit by performing image processing on the image processing unit 26. An image processing ASIC 3 is provided.

  Therefore, in the imaging apparatus 1, the image processing ASIC 3 efficiently receives control information transferred from the external CPU 8 through a low-speed serial interface such as SPI, particularly effective length information LLEN [13: 0]. Can do. As a result, it is possible to improve the transfer efficiency of the image data by the high-speed serial interface based on the effective length information LLEN [13: 0].

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to that described in the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Imaging device 2 Imaging sensor 3 Image processing ASIC
4 DSP
5 Signal line 6 High-speed serial bus 7 Low-speed serial bus 8 CPU
11 Register Access Unit 12 System Unit 13 Image Processing Unit 14 High-Speed Serial Interface 12a, 13a, 14a Register 12aa LLEN Setting Register Area 15, 16, 17 APB
18 Other circuit modules 18a Register 21 First storage unit 22 Effective length information update unit 23 High-speed serial transfer unit 24 Second storage unit 25 Control unit 26 Image processing unit 27 Storage control unit

JP 2012-134841 A

Claims (7)

The input image data is subjected to image processing by the image processing unit based on control information from the outside, and the processed image data is sent to the outside by the serial transfer unit together with effective length specifying information indicating the effective length of the image data. An image processing apparatus for transferring,
First storage means for storing effective length information capable of generating the effective length specifying information;
Second storage means for storing control information including the effective length information;
Storage control means for receiving the control information including the effective length information transmitted from the outside and storing it in the second storage means;
Effective length information updating means for obtaining the effective length information from the control information of the second storage means and updating the effective length information of the first storage means;
An image processing apparatus comprising: The storage control means
2. The image processing apparatus according to claim 1, wherein the effective length information and the other control information are stored in successive addresses of the second storage unit. The image processing apparatus includes:
A control unit that has the second storage unit and outputs the effective length information of the second storage unit and acquisition availability information indicating whether or not the effective length information can be acquired to the serial transfer unit;
In addition,
The image processing means includes
Output the processed image data and a horizontal synchronization signal related to the image data to the serial transfer means,
The serial transfer means includes
The effective length information update means, the effective length information update means, when the acquisition permission information indicates acquisition permission, and the horizontal synchronization signal is output, The image processing apparatus according to claim 1, wherein the effective length information is acquired, and the effective length information of the first storage unit is updated with the acquired effective length information. The storage control means
The image processing apparatus according to claim 1, wherein the control information including the effective length information is received from the outside by an SPI. An image pickup apparatus that serially transfers image data captured by an image pickup unit by performing image processing on an image processing unit,
An imaging apparatus comprising the image processing apparatus according to claim 1 as the image processing unit. The input image data is subjected to image processing by the image processing unit based on control information from the outside, and the processed image data is sent to the outside by the serial transfer unit together with effective length specifying information indicating the effective length of the image data. An image processing method by an image processing apparatus to transfer,
A first storage processing step of storing effective length information capable of generating the effective length specifying information in a first storage means;
A second storage processing step of storing control information including the effective length information in a second storage means;
A storage control processing step of receiving the control information including the effective length information transmitted from the outside and storing it in the second storage means;
An effective length information update processing step of acquiring the effective length information from the control information of the second storage means and updating the effective length information of the first storage means;
An image processing method comprising: The input image data is subjected to image processing by the image processing unit based on control information from the outside, and the processed image data is sent to the outside by the serial transfer unit together with effective length specifying information indicating the effective length of the image data. A program installed in the image processing apparatus to be transferred,
To the control processor,
A first storage process for storing effective length information capable of generating the effective length specifying information in a first storage means;
A second storage process for storing control information including the effective length information in a second storage means;
A storage control process for receiving the control information including the effective length information transmitted from the outside and storing it in the second storage means;
An effective length information update process for obtaining the effective length information from the control information of the second storage means and updating the effective length information of the first storage means;
A program characterized by having executed.

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