JP6552662B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine.

  Conventionally, a gaming machine called a pachinko gaming machine is known, and this pachinko gaming machine generally comprises a gaming area in which gaming balls launched to the gaming board can roll, and a starting area provided in the gaming area. , And a variable display control means for controlling the symbol display device. In such a gaming machine, the variable display control means controls the symbol display device when a predetermined condition such as the game ball having passed the start area (winning opening of the game ball) is established, and the symbol display device The identification information (for example, a special symbol to be described later, etc.) is variably displayed on the display area. Then, when the identification information finally derived and displayed on the display area of the symbol display device becomes a predetermined combination (specific display mode), the jackpot gaming state (so-called "big hit") in which the gaming state is advantageous to the player Move to).

  Also, conventionally, pachinko gaming machines provided with LEDs (Light Emitting Diodes) used when performing effects in accordance with the above-described game operation are known (see, for example, Patent Document 1). Patent Document 1 describes a pachinko gaming machine provided with a plurality of types of LEDs called static LEDs and dynamic LEDs whose output control modes are different from each other.

JP 2006-334179 A

  By the way, conventionally, in a gaming machine capable of displaying image data, for example, there is a demand for a technology that can speed up the processing when applying the effect calculation drawing processing to a plurality of effects.

  The present invention has been made to solve the above problems, and an object of the present invention is, for example, a gaming machine capable of speeding up processing when applying effect calculation drawing processing to a plurality of effects. Is to provide.

  In order to achieve the above object, the present invention provides a gaming machine as described below.

Production control means (for example, a display control circuit 230 described later) capable of controlling the production;
Decoding means for decoding moving image data (for example, S421 during drawing processing described later);
It is determined whether or not the moving image data decoded by the decoding unit is referred to in effect drawing, and when the moving image data is referred to in effect drawing, a transfer unit that transfers a decoding result to a texture buffer (for example, (S422, S423) during drawing processing described later,
A gaming machine, comprising: alpha conversion means (for example, alpha processing described later) that converts one of a plurality of color components into an alpha component for the decoding result transferred by the transfer means.

  According to the gaming machine of the present invention configured as described above, for example, the processing when applying the effect calculation drawing processing to a plurality of effects can be speeded up.

It is a figure showing a functional flow of a pachinko game machine concerning one embodiment of the present invention. It is an appearance perspective view of a pachinko game machine concerning one embodiment of the present invention. It is an exploded perspective view of a pachinko game machine concerning one embodiment of the present invention. It is a front view which shows the structure of the game board of the pachinko game machine which concerns on one Embodiment of this invention. It is a block diagram showing the circuit composition of the pachinko game machine concerning one embodiment of the present invention. It is a block diagram which shows the internal structure of the sub control circuit of the pachinko game machine which concerns on one Embodiment of this invention. It is a block diagram showing an internal configuration of a voice and LED control circuit of a pachinko gaming machine according to an embodiment of the present invention. It is a block diagram which shows the internal structure of the display control circuit of the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the big hit random number determination table (at the time of 1st starting opening prize winning) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the big hit random number determination table (at the time of 2nd starting opening prize winning) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the symbol determination table (at the time of a 1st starting opening winning) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the symbol determination table (at the time of 2nd starting opening prize winning) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the jackpot kind determination table (the 1) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the jackpot kind determination table (the 2) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the jackpot kind determination table (the 3) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the jackpot kind determination table (the 4) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the presentation information determination table at the time of a prize in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the fluctuation production pattern determination table in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the fluctuation production table in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the holding | maintenance effect table in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the pre-reading effect table in the pachinko game machine which concerns on one Embodiment of this invention. It is a schematic block diagram of command data in a pachinko game machine concerning one embodiment of the present invention. It is a figure which shows the content of the information contained in the structure of the demonstration display command in the pachinko gaming machine which concerns on one Embodiment of this invention, and a demonstration display command. It is a figure which shows the structure of the special symbol presentation start command in the pachinko game machine which concerns on one Embodiment of this invention, and the content of the information contained in a special symbol presentation start command. It is a figure which shows the structure of the 1st power failure return command in the pachinko game machine which concerns on one Embodiment of this invention, and the content of the information contained in a 1st power failure return command. It is a figure which shows the content of the information contained in the structure of the 2nd power failure reset command in the pachinko gaming machine which concerns on one Embodiment of this invention, and a 2nd power failure reset command. It is a figure which shows the content of the information contained in the structure of the pending | holding addition command in the pachinko gaming machine which concerns on one Embodiment of this invention, and a pending | holding addition command. In the pachinko gaming machine according to one embodiment of the present invention, it is a diagram for explaining the outline of the main-sub command control processing executed by the host control circuit (sub control circuit). It is a schematic block diagram of the ring buffer provided in the host control circuit in the pachinko gaming machine according to one embodiment of the present invention. It is a figure for demonstrating the outline | summary of the production | generation operation | movement of the various requests in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure for demonstrating the outline | summary of the animation request construction process in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure for demonstrating the outline | summary of the animation request construction process in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure for demonstrating the outline | summary of the drawing process in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure for explaining an outline of voice reproduction operation in a pachinko game machine concerning one embodiment of the present invention. It is a schematic block diagram of access data used by voice reproduction operation in a pachinko game machine concerning one embodiment of the present invention. It is a figure for demonstrating the outline | summary of the lamp | ramp (LED) lighting operation | movement in the pachinko game machine which concerns on one Embodiment of this invention. FIG. 3 is a schematic connection configuration diagram among a voice / LED control circuit, an LED driver, and LEDs in a pachinko gaming machine according to an embodiment of the present invention. It is a SPI connection block diagram between the voice / LED control circuit and the LED driver in the pachinko gaming machine according to one embodiment of the present invention. In the pachinko game machine which concerns on one Embodiment of this invention, it is a schematic block diagram of the serial data transmitted to a LED driver from a voice and LED control circuit. It is a schematic block diagram of the LED driver in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure for demonstrating the data input operation of the LED driver in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure for demonstrating the address setting operation | movement of the LED driver in the pachinko game machine which concerns on one Embodiment of this invention. In the pachinko gaming machine which relates to one execution form of this invention, it is the figure which shows the correspondence relationship between each SPI channel (physical system) and the device address and the output terminal of the LED driver which is connected to that. It is a figure which shows the format (data type) of LED data in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows the example of output control of LED data in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows the production example 1 of the LED animation in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows the production example 2 of the LED animation in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows the production example 3 of the LED animation in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows the production example 3 of the LED animation in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows the structural example of the reproduction | regeneration channel and expansion channel in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows the structural example of the reproduction | regeneration channel and expansion channel in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows the various examples of the switching reproduction | regeneration pattern of the LED animation in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows the switching reproduction | regeneration aspect (flow on a time axis) of LED animation in the switching reproduction | regeneration pattern 2 of LED animation of the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows the switching reproduction | regeneration aspect (flow on a time-axis) of LED animation in the LED animation switching reproduction | regeneration pattern 4 of the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows the LED animation switching reproduction | regeneration aspect (flow on a time axis) in the LED animation switching reproduction | regeneration pattern 6 of the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows the switching reproduction | regeneration aspect (flow on a time-axis) of LED animation in the switching reproduction | regeneration pattern 7 of LED animation of the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows the switching reproduction | regeneration aspect (flow on a time-axis) at the time of continuous reproduction | regeneration of the LED animation in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows the example of reproduction | regeneration of the LED animation at the time of not having designated "ODONLY" in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows the example of reproduction | regeneration of the LED animation at the time of "ODONLY" designation | designated in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure for demonstrating the outline | summary of the goods drive operation | movement in the pachinko game machine which concerns on one Embodiment of this invention. It is an I2C connection block diagram between a host control circuit and a motor driver in a pachinko gaming machine according to an embodiment of the present invention. The pachinko game machine which concerns on one Embodiment of this invention WHEREIN: It is a flowchart which shows an example of the main-control main process performed by main CPU. It is a flow chart which shows an example of special symbol control processing in a pachinko game machine concerning one embodiment of the present invention. It is a flow chart which shows an example of special symbol memory check processing in a pachinko game machine concerning one embodiment of the present invention. It is a flow chart which shows an example of special symbol display time management processing in a pachinko game machine concerning one embodiment of the present invention. It is a flow chart which shows an example of big hit end interval processing in a pachinko game machine concerning one embodiment of the present invention. It is a flowchart which shows an example of the normal symbol control processing in the pachinko game machine which concerns on one Embodiment of this invention. The pachinko game machine which concerns on one Embodiment of this invention WHEREIN: It is a flowchart which shows an example of the process at the time of the power activation performed by main CPU. In a pachinko gaming machine according to an embodiment of the present invention, it is a flowchart showing an example of a system timer interrupt process executed by the main CPU. It is a flowchart which shows an example of the switch input detection process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flow chart which shows an example of starting opening winning a prize detection processing in a pachinko game machine concerning one embodiment of the present invention. In the pachinko game machine which relates to one execution form of this invention, it is the flowchart which shows one example of the secondary control main processing which is executed by the host control circuit (the secondary control circuit). It is a figure for demonstrating the outline | summary of the initialization process performed by the host control circuit (sub control circuit) in the pachinko game machine which concerns on one Embodiment of this invention. In a pachinko game machine concerning one embodiment of the present invention, it is a flow chart which shows an example of initialization processing performed by a host control circuit. It is a flow chart which shows an example of backup return initialization processing in a pachinko game machine concerning one embodiment of the present invention. It is a flowchart which shows an example of the gift control initialization process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the LED registration process in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure for demonstrating the outline | summary of the process at the time of the operation input performed by the host control circuit (sub control circuit) in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the operation input timer interruption process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the operation input information acquisition process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flow chart which shows an example of command reception processing (reception interruption) in a pachinko game machine concerning one embodiment of the present invention. It is a flowchart which shows an example of the reception data storage process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flow chart which shows an example of command analysis processing in a pachinko game machine concerning one embodiment of the present invention. It is a flowchart which shows an example of the command parameter check process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flow chart which shows an example of animation request construction processing in a pachinko game machine concerning one embodiment of the present invention. It is a flow chart which shows an example of drawing control processing in a pachinko game machine concerning one embodiment of the present invention. It is a flowchart which shows an example of the moving image command creation process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flow chart which shows an example of animation data reading processing in a pachinko game machine concerning one embodiment of the present invention. It is a flowchart which shows an example of the all command list creation process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the drawing process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the drawing process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the drawing process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flow chart which shows an example of voice control processing in a pachinko game machine concerning one embodiment of the present invention. It is a flowchart which shows an example of the lamp control process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the gift control process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flow chart which shows an example of bonus article processing at the time of change start command reception in a pachinko game machine concerning one embodiment of the present invention. It is a flowchart which shows an example of a bonus product process at the time of a demonstration command reception in a pachinko game machine concerning one embodiment of the present invention. It is a flowchart which shows an example of the error process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the bonus article process at the time of change stop command reception in a pachinko game machine concerning one embodiment of the present invention. It is a flow chart which shows an example of bonus game processing at the time of big hit system command reception in a pachinko game machine concerning one embodiment of the present invention. It is a flow chart which shows an example of initial position restoration operation processing in a pachinko game machine concerning one embodiment of the present invention. In the pachinko gaming machine which concerns on one Embodiment of this invention, it is a flowchart which shows an example of the serial data output process to the LED driver via SPI performed by the audio | voice and LED control circuit. In the pachinko gaming machine according to one embodiment of the present invention, it is a flowchart showing an example of serial data output processing to the motor driver via the I2C interface executed by the host control circuit. 10 is a flowchart illustrating an example of a voice control process according to Modification 1. 10 is a flowchart illustrating an example of a lamp control process in Modification 2. 10 is a flowchart illustrating an example of a lamp control process in Modification 3. 15 is a flowchart illustrating an example of data setting processing of each port in a modification 3; It is a SPI connection block diagram between the audio | voice / LED control circuit and LED driver in the modification 4. FIG. 18 is a diagram for describing an input / output operation of serial data between the voice / LED control circuit and the LED driver in the modification 4; FIG. 18 is a diagram for describing an input / output operation of serial data between the voice / LED control circuit and the LED driver in the modification 4; In modification 4, it is a flow chart which shows an example of serial data input / output processing performed between a sound and LED control circuit and a LED driver. It is a figure which shows the output control example of the LED data in the modification 5. FIG. 18 is a schematic configuration diagram of an excitation state detection unit of a bonus according to a sixth modification. It is a flowchart which shows an example of the accessory control process in the modification 6.

  Hereinafter, the configuration and various operations of a pachinko gaming machine (game machine) according to an embodiment of the present invention will be described with reference to the drawings.

<Function flow>
First, with reference to FIG. 1, functions of the pachinko gaming machine according to the present embodiment will be described. FIG. 1 is a diagram showing a functional flow of the pachinko gaming machine according to the present embodiment.

  The pachinko game, as shown in FIG. 1, is a game in which a game ball is fired by the user's operation, and when the game ball wins various prizes, payout control processing of the game ball is performed. In addition, the pachinko game includes a special symbol game using a special symbol and an ordinary symbol game using an ordinary symbol. When a "big hit" in a special symbol game or a normal symbol game results in a "hit", the possibility that the game ball will win is relatively increased, and the game ball payout control processing is easily performed. Become.

  In addition, for various winnings, special symbol start winning which is one condition for performing variable display of special symbol in special symbol game, and one condition for performing variable display of normal symbol in normal symbol game Some regular symbol starting prizes are also included.

  In this specification, “variable display” is a concept that can be displayed in a variable manner. For example, “variable display” that is actually changed and “stop display” that is actually stopped and displayed. Is possible. In "variable display", for example, "derivative display" can be performed in which a special symbol (identification information) is displayed as a result of the special symbol game. That is, in the present specification, the operation from the start of the “variable display” to the “derivative display” is referred to as one “variable display”. Furthermore, in the present specification, "identification information" refers to "patterns" used in pachinko games such as special symbols, normal symbols, decorative symbols, identification symbols, etc., and identification symbols or decorations used in pachislot or slot games It means that it may include a symbol used when displaying or suggesting the result of a game when a player plays a game, such as a symbol, and various symbols in the embodiment and various modifications described below are also included. May be included.

  Hereinafter, an outline of the processing flow of the special symbol game and the normal symbol game will be described.

(1) Special symbol game When there is a special symbol start winning in a special symbol game, random numbers (random number for jackpot determination and random number for symbol determination) are extracted from the jackpot determination counter and the symbol determination counter, respectively. The extracted random number values are stored (see the flow of the special symbol start winning process in the special symbol game shown in FIG. 1).

  Further, as shown in FIG. 1, in the special symbol control process during the special symbol game, first, it is determined whether or not a condition for starting variable display of the special symbol is satisfied. In this determination process, it is referred to whether or not a random number value is stored by a special symbol start winning, and the condition for starting the variable symbol variable display is established with one condition that the random number value is stored. judge.

  Next, when the variable display of the special symbol is started, the jackpot determination random number value extracted from the jackpot determination counter is referred to, and the jackpot determination of whether or not to make the "big hit" is performed. Thereafter, stop symbol determination processing is performed. In this process, the special symbol to be stopped and displayed is determined by referring to the random number value for symbol determination extracted from the counter for symbol determination and the result of the jackpot determination described above.

  Next, a variation pattern determination process is performed. In this process, a random number value is extracted from the fluctuation pattern determination counter, and the random pattern value, the result of the above-described big hit determination, and the special symbol to be displayed for stop described above are referenced to determine the fluctuation pattern of the special symbol.

  Next, effect pattern determination processing is performed. In this process, random number values are extracted from the effect pattern determination counter, and the random number values, the result of the above-described big hit determination, the special symbol to be displayed in the stop mentioned above, and the variation pattern of the special symbol mentioned above are referred to. The effect pattern to be executed along with the variable display of the special symbol is determined.

  Next, a variable display control process for controlling the variable display of the special symbol with reference to the special symbol to be stopped and displayed, the variation pattern of the special symbol, and the effect pattern accompanying the variable display of the special symbol as a result of the determined big hit determination. And the effect control process which performs a predetermined effect is performed.

  Then, when the variable display control process and the effect display control process are finished, it is determined whether or not the "big hit" is to be made. In this determination process, when it is determined that the "big hit" has been made, a big hit game control process for playing a big hit game is executed. In the jackpot game, the possibility of various winnings described above increases. On the other hand, when it is determined that the "big hit" has not been made, the big hit game control process is not executed.

  If it is determined that the "big hit" has not been made, or if the big hit game control process has ended, a game state transition control process is performed to shift the game state. In this gaming state transition control process, management of the gaming state at the normal time which is different from the big hit gaming state is performed. As the gaming state at the normal time, for example, in the above-described jackpot determination, the gaming state in which the probability of being determined as a "big hit" increases (hereinafter referred to as "probability variation gaming state") or special symbol start winning is easily obtained The gaming state (hereinafter referred to as "time-saving gaming state") and the like can be mentioned. Thereafter, the process for determining whether or not to start variable symbol special display is performed again, and thereafter, the various types of special symbol control processing described above are repeated.

  In the pachinko gaming machine of the present embodiment, when the game ball starts winning while displaying the special symbol, various data (big hit determination random number value, symbol determination random number value, etc.) acquired at the start winning combination ) Is put on hold. That is, when the game ball wins a starting prize during the variation display of the special symbol, the variable display (variation display) of the special symbol corresponding to the starting prize is suspended, and after the variation display of the special symbol currently being executed is ended. The variable display of the special symbol that is put on hold is started. Hereinafter, the variable display of the special symbol that is on hold is also referred to as “holding ball”.

  In addition, in the pachinko gaming machine of this embodiment, as described later, two types of special symbol start winnings (first start opening winning and second starting opening winning) are provided, and a maximum of four for each special symbol starting winning You can get a hold ball. That is, in the present embodiment, a maximum of eight reserved balls can be acquired.

  Furthermore, although the pachinko gaming machine of the present embodiment is not shown in FIG. 1, it determines the hit of the holding ball (presence or absence of “big hit” winning) based on the information of the holding ball described above, and further determines It also has a function to perform a predetermined effect based on it, that is, a pre-reading effect function.

(2) Normal symbol game When there is a normal symbol start winning in the normal symbol game, a random number value is extracted from the counter for hit determination and the random number value is stored (the normal symbol game in the normal symbol game shown in FIG. 1). Refer to the flow of the symbol start winning process).

  As shown in FIG. 1, in the normal symbol control process during the normal symbol game, it is first determined whether or not a condition for starting variable display of the normal symbol is satisfied. In this determination process, it is referred to whether or not the random number value is stored by the normal symbol starting winning, and the condition to start the variable display of the normal symbol is established with the random number value stored as one condition. judge.

  Next, when starting normal symbol variable display, the random number value extracted from the counter for hit determination is referred to and a hit determination is made as to whether or not “win” is set. Thereafter, variation pattern determination processing is performed. In this process, the result of the hit determination is referred to, and the variation pattern of the normal symbol is determined.

  Next, the variable display control process for controlling the variable display of the normal symbol and the effect control process for performing a predetermined effect are executed with reference to the determined result of the hit determination and the variation pattern of the normal symbol.

  When the variable display control process and the effect display control process are finished, it is determined whether or not a "hit" is to be made. In this determination process, when it is determined that "hit" is to be made, a hit game control process for performing a hit game is executed. In the winning game control process, the possibility of various winnings as described above, in particular, the possibility of special symbol start winning of a game ball in a special symbol game increases. On the other hand, if it is determined that "hit" is not made, the hit game control processing is not executed. Thereafter, the process for determining whether or not to start the variable display of the normal symbol is performed again, and thereafter, the various processes of the normal symbol control process described above are repeated.

  As described above, in the pachinko game, the payout control of the game ball according to conditions such as whether or not the "big hit" in the special symbol game, the transition state of the gaming state, or the "hit" in the normal symbol game. The ease of processing changes.

  In this embodiment, as a random number extraction method, a soft random number method for generating random values by executing a program is used. However, the present invention is not limited to this, and for example, when the pachinko gaming machine includes a random number generator in which random numbers are updated at a predetermined cycle, random number values from counters (so-called ring counters) in the random number generator. A hard random number system for extracting H may be adopted as an extraction system of various random number values described above. When the hard random number method is used, it is possible to prevent extraction of the same random value in a predetermined cycle by determining the initial value of the random number at a timing different from the predetermined cycle.

<Structure of Pachinko Machine>
Next, with reference to FIG. 2 and FIG. 3, the structure of the pachinko gaming machine in the present embodiment will be described. FIG. 2 is a perspective view showing the appearance of the pachinko gaming machine. FIG. 3 is an exploded perspective view of the pachinko gaming machine.

  As shown in FIGS. 2 and 3, the pachinko gaming machine 1 is a main body 2, a base door 3 attached to the main body 2 so as to be openable and closable, and a glass door attached to the base door 3 so as to be openable and closable. 4.

[Body]
The main body 2 is formed of a frame-like member having a rectangular opening 2a (see FIG. 3). The main body 2 is formed of a material such as wood.

[Base door]
The base door 3 is formed of a plate-like member having a rectangular outer shape substantially equal to the outer shape of the main body 2. The base door 3 is disposed in front of the main body 2 (the front side of the pachinko gaming machine 1), and by rotating the base door 3 around one side edge of the main body 2, the base door 3 The opening 2a is opened and closed. As shown in FIG. 3, the base door 3 is provided with a rectangular opening 3 a. The opening 3a is formed over a region from the substantially central portion of the base door 3 to the upper side, and is formed so as to occupy most of the region.

  In addition, the speaker 11, the game board 12, the display device 13 (demonstration means, display means), the plate unit 14, the launcher 15, the payout device 16, and the substrate unit 17 are attached to the base door 3. It is done.

  The speaker 11 is disposed on the upper part (near the upper end) of the base door 3. The game board 12 is disposed in front of the base door 3 (the front side of the pachinko gaming machine 1) and is disposed so as to cover the opening 3a of the base door 3.

  The game board 12 is formed of a plate-shaped resin member having light transparency. In addition, as resin which has light transmittance, an acrylic resin, polycarbonate resin, methacryl resin etc. can be used, for example.

  Further, on the front surface of the game board 12 (the front surface of the pachinko gaming machine 1), a game area 12a is formed in which the game balls fired from the launch device 15 roll. The game area 12a is an area surrounded by a guide rail 41 (specifically, an outer rail 41a shown in FIG. 4 to be described later), and its outer peripheral shape is substantially circular. Further, a plurality of game nails (see FIG. 4 described later) are driven into the game area 12a. The configuration of the game board 12 (game area 12a) will be described in detail later with reference to FIG.

  The display device 13 is attached to the back side of the game board 12 (the side opposite to the front side of the pachinko gaming machine 1). The display device 13 has a display area 13a for displaying an image. The size of the display area 13a is set so as to occupy the whole or a part of the surface of the game board 12. In the display area 13a of the display device 13, various images such as an identification symbol for effect, an effect image, and an image for decoration (decorative pattern) are displayed. The player can visually recognize various images displayed on the display area 13 a of the display device 13 via the game board 12.

  In the present embodiment, a liquid crystal display device is used as the display device 13. However, the present invention is not limited to this, and as the display device 13, for example, a display device such as a plasma display, a rear projection display, a CRT (Cathode Ray Tube) display may be applied.

  A spacer 19 is provided on the back side of the game board 12 (the side opposite to the front side of the pachinko gaming machine 1). The spacer 19 is provided between the back surface of the game board 12 (surface on the back side of the pachinko gaming machine 1) and the front surface of the display device 13 (surface on the front side of the pachinko gaming machine 1). A space to be a flow path of the game ball rolling on the area 12a is formed. The spacer 19 is formed of a light transmitting material. In addition, this invention is not limited to this, For example, one part may be formed with the material which has light transmittance, and may be formed with the material which does not have light transmittance. .

  The tray unit 14 is disposed below the gaming board 12. The dish unit 14 includes an upper dish 21 and a lower dish 22 disposed below the upper dish 21. As shown in FIG. 2, the upper plate 21 and the lower plate 22 are respectively formed with a payout port 21a and a payout port 22a for lending out game balls and paying out game balls (prize balls). When a predetermined payout condition is satisfied, gaming balls are discharged from the payout opening 21a and the payout opening 22a, and are stored in the upper tray 21 and the lower tray 22, respectively. Further, the game balls stored in the upper plate 21 are launched into the game area 12 a by the launching device 15.

  Further, the dish unit 14 is provided with an effect button 23. The effect button 23 is mounted on the upper tray 21. A dial operation unit (jog dial) 24 is attached to the periphery of the effect button 23 so as to be rotatable with respect to the effect button 23. The pachinko gaming machine 1 of the present embodiment has a predetermined effect function performed using the effect button 23 and / or the dial operation unit 24, and when performing a predetermined effect, the display area 13 a of the display device 13 An image prompting the operation of the effect button 23 and / or the dial operation unit 24 is displayed.

  The launcher 15 is disposed in the lower right region (near the lower right corner) on the front surface of the base door 3. The launcher 15 includes a launch handle 25 operable by the player and a panel 26 engaged with the lower right portion of the tray unit 14. The firing handle 25 is disposed on the front side of the panel body 26 and is rotatably supported by the panel body 26.

  Although not shown in FIGS. 2 and 3, a solenoid actuator (driving device) for controlling the launching operation of the game ball is provided on the back side of the panel body 26. Although not shown in FIGS. 2 and 3, a touch sensor is provided at the peripheral portion of the firing handle 25, and a firing volume is provided inside the firing handle 25. The firing volume changes the resistance according to the amount of rotation of the firing handle 25 to change the power supplied to the solenoid actuator.

  In the pachinko gaming machine 1 according to the present embodiment, when the player's hand contacts the touch sensor of the launch handle 25, the touch sensor outputs a detection signal. Thereby, it is detected that the player has gripped the launch handle 25, and the game ball can be launched by the solenoid actuator. Then, when the player holds the firing handle 25 and rotates it clockwise (clockwise when viewed from the player), the resistance value of the firing volume changes in accordance with the pivot angle of the firing handle 25. Power corresponding to the resistance value is supplied to the solenoid actuator. As a result, the gaming balls stored in the upper tray 21 are sequentially fired, and the launched gaming balls are guided to the guide rails 41 (see FIG. 4 described later) and released to the gaming area 12 a of the gaming board 12.

  Also, although not shown in FIGS. 2 and 3, the side of the firing handle 25 is provided with a firing stop button. The firing stop button is a button provided to stop the firing of the game ball by the solenoid actuator. When the player presses the launch stop button, the launch of the game ball is stopped even when the launch handle 25 is gripped and rotated.

  The dispensing device 16 and the substrate unit 17 are disposed on the back side of the base door 3. A game ball is supplied to the payout device 16 from a storage unit (not shown). The payout device 16 pays out a predetermined number of gaming balls to the upper tray 21 or the lower tray 22 from the gaming balls supplied from the storage unit based on the fulfillment of the payout conditions. The board unit 17 has various control boards. The various control boards are provided with a main control circuit 70 and a sub control circuit 200 which will be described later (see FIG. 5 described later).

[Glass door]
The glass door 4 is composed of a plate-like member having a substantially square surface. The glass door 4 is disposed on the front side of the game board 12 and has a size that covers the game board 12. A speaker cover 29 is provided in an upper region facing the speaker 11 on the front surface of the glass door 4.

  In the central portion of the glass door 4, an opening 4 a having a size that exposes at least the game area 12 a is formed in an area facing the game area 12 a of the game board 12. A light transmitting protective glass 28 is attached to the opening 4a of the glass door 4, whereby the opening 4a is closed. Therefore, when the glass door 4 is closed with respect to the base door 3, the protective glass 28 is disposed so as to face at least the game area 12 a of the game board 12.

[Game board]
Next, the configuration of the game board 12 will be described with reference to FIG. FIG. 4 is a front view showing the configuration of the game board 12.

  On the front of the game board 12, as shown in FIG. 4, a guide rail 41, a ball passage detector 43, a first starting opening 44, a second starting opening 45 (starting area), and an ordinary electric role 46 And are provided. In addition, on the front surface of the game board 12, there are a plurality of general winning ports 51, 52, a first grand winning port 53 (variable winning device), a second large winning port 54 (variable winning device), and an out port 55. Game nails 56 are provided. Further, on the front surface of the game board 12, a special symbol display device 61 (special symbol display means), a normal symbol display device 62, and a normal symbol are arranged above the display area 13a of the display device 13 disposed substantially at the center. A hold display device 63, a first special symbol hold display device 64, and a second special symbol hold display device 65 are provided.

  Although not shown in FIG. 4, a 7-segment counter for effect is also provided on the front of the game board 12. The 7-segment counter for effect is composed of a display counter capable of displaying two-digit numbers and two alphabets. Moreover, in the present embodiment, a notification LED (Light Emitting Diode) which lights up when the result of the stop display of the special symbol is "big hit", a round number display LED which displays the number of rounds in the big hit game, etc. Also good.

[Various components of game area]
The guide rail 41 includes an outer rail 41a extending in an arc shape that partitions the game area 12a, and an inner rail 41b extending in an arc shape disposed on the inner side (inner peripheral side) of the outer rail 41a. Be done. The game area 12a is formed inside the outer rail 41a. The outer rail 41a and the inner rail 41b are disposed so as to face each other in the vicinity of the left end portion of the game area 12a when viewed from the player side, and thereby, between the outer rail 41a and the inner rail 41b, A guide path 41c is formed which guides the game ball fired by the camera 15 to the top of the game area 12a.

  Further, at the end of the inner rail 41b located on the upper left side of the game area 12a, a ball discharge port 41d is formed by the end of the inner rail 41b and a part of the outer rail 41a opposed thereto. A ball return prevention piece 42 is provided at the end of the inner rail 41b so as to close the ball outlet 41d. The ball return prevention piece 42 prevents the game balls discharged from the ball discharge opening 41d to the game area 12a from passing through the ball discharge opening 41d again and entering the guide path 41c.

  The game ball released from the ball discharge port 41d flows down from the upper part of the game area 12a toward the lower part. At this time, the game ball collides with various members provided in the game area 12a such as the plurality of game nails 56, the first start opening 44, the second start opening 45, etc., and changes the traveling direction of the game area 12a. Flow down from the top to the bottom.

  A display area 13a of the display device 13 is provided substantially at the center of the game area 12a. An obstacle 13 b is provided at the upper end of the display area 13 a. By providing the obstacle 13b, the gaming ball does not pass over the area overlapping the display area 13a in the gaming area 12a.

  The ball passing detector 43 is disposed near the right end of the display area 13a as viewed from the player. The ball passage detector 43 is provided with a passing ball sensor 43a (see FIG. 5 described later) for detecting a game ball passing through the ball passage detector 43. In addition, when a game ball passes through the ball passage detector 43, a lottery is performed to determine whether or not it is “winning”, and based on the result of the lottery, a normal symbol variation display is started.

  The first start port 44 is disposed below the display area 13 a, and the second start port 45 is disposed below the first start port 44. The first starting opening 44 and the second starting opening 45 are made of members capable of receiving game balls. Hereinafter, that the game ball enters or passes through the first starting opening 44 or the second starting opening 45 is referred to as "winning". When the game ball wins the first start port 44 or the second start port 45, a first predetermined number (three in this embodiment) of game balls is paid out. In addition, by the game ball entering the first starting opening 44, the lottery whether or not it is either "big hit" and "small hit" is performed, the variation of the special symbol based on the result of the lottery Display starts. Further, by the game ball entering the second starting opening 45, a lottery for "big hit" is performed, and the variation display of the special symbol is started based on the result of the lottery.

  The first starting port 44 is provided with a first starting port winning ball sensor 44a (see FIG. 5 described later) for detecting a game ball won in the first starting port 44. The second starting port 45 is provided with a second starting port winning ball sensor 45a (see FIG. 5 described later) for detecting a game ball won in the second starting port 45. In addition, the game ball which has won the first start port 44 and the second start port 45 passes through the recovery port (not shown) provided on the game board 12 and is conveyed to the recovery section (not shown) of the game ball .

  The ordinary motor-operated part 46 is provided at the second start port 45. The ordinary electric accessory 46 includes a pair of blade members rotatably attached to both sides of the second start opening 45, and an ordinary electric agent solenoid 46a (see FIG. 5 described later) for driving the pair of blade members. Have. This ordinary electric accessory 46 is driven by an ordinary electric accessory solenoid 46a, and opens the pair of blade members to make it easier to win a game ball in the second start opening 45, and closes the pair of blade members. One state of a closed state in which a game ball cannot be won is generated at the second start opening 45. In the present embodiment, when the ordinary motorized character 46 is in the closed state, the opening form of the pair of wing members is not a form that makes winning impossible, but a form that makes winning of the game ball difficult. Also good.

  The general winning opening 51 is disposed near the lower left portion of the game area 12a as viewed from the player. The general winning opening 52 is disposed below the ball passage detector 43, and is disposed near the lower right portion of the game area 12a when viewed from the player side. The general winning opening 51 and the general winning opening 52 are made of members capable of receiving game balls. Hereinafter, it is also referred to as “winning” that the game ball enters or passes through the general winning opening 51 or the general winning opening 52. When a game ball wins the general winning opening 51 or the general winning opening 52, a second predetermined number (10 in this embodiment) of gaming balls is paid out.

  The general winning opening 51 is provided with a general winning ball sensor 51 a (see FIG. 5 described later) for detecting a game ball won in the general winning opening 51. The general winning opening 52 is provided with a general winning ball sensor 52a (see FIG. 5 described later) for detecting a game ball won in the general winning opening 52.

  The first big prize opening 53 and the second big prize opening 54 are arranged below the ball passage detector 43 and between the first start opening 44 and the general prize opening 52. The first big winning opening 53 and the second big winning opening 54 are arranged vertically along the flow path of the game ball, and the first big winning opening 53 is arranged above the second big winning opening 54. The The first large winning opening 53 and the second large winning opening 54 are both so-called attacking type opening and closing devices, and can be opened and closed shutters 53a and 54a and a solenoid actuator for driving the shutters (the first in FIG. A large winning opening solenoid 53b and a second large winning opening solenoid 54b).

  Each of the first big prize opening 53 and the second big prize opening 54 receives a game ball when the corresponding shutter is open (open state), and plays when the shutter is closed (closed state). Do not accept the ball. In the following, it is also referred to as “winning” that a game ball enters or passes through the first big winning opening 53 or the second big winning opening 54. When game balls win the first big prize opening 53, a third predetermined number of balls (10 balls in the present embodiment) are paid out. On the other hand, when the game ball is won in the second big winning opening 54, the game balls of the fourth predetermined number ball (15 in the present embodiment) are paid out.

  In addition, the first grand prize opening 53 is provided with a count sensor 53c (see FIG. 5 described later) for counting the game balls won in the first big prize opening 53. Further, the second grand prize opening 54 is provided with a count sensor 54c (see FIG. 5 described later) for counting game balls won in the second big prize opening 54.

  The out port 55 is provided at the lowermost part of the game area 12a. The out port 55 is a game that has not won any of the first starting port 44, the second starting port 45, the general winning port 51, the general winning port 52, the first large winning port 53, and the second large winning port 54. I accept the ball.

  When the arrangement of various components in the game area 12a of the present embodiment is as shown in FIG. 4, when a game ball is thrown into the area on the right side of the game area 12a by the player (when it is hit right), The game ball is guided to the second starting opening 45 by the game nail 56 or the like. In this case, there is almost no possibility of winning the first starting opening 44. In this embodiment, as will be described later, the winner of the second start opening 45 is more likely to receive a “hit” lottery that is advantageous to the player than when the first start opening 44 is won. Therefore, in the "time saving game state" described later in which winning to the second starting opening 45 is relatively easy, the possibility of winning to the first starting opening 44 (convenient to the player by hitting the right) The possibility of becoming a gaming state can be reduced.

[Special symbol display device]
As shown in FIG. 4, the special symbol display device 61 is disposed in the approximate center of the upper portion of the display area 13 a of the display device 13.

  The special symbol display device 61 is a display device that variably displays special symbols (variable display and stop display) in a special symbol game. In the present embodiment, as shown in FIG. 4, a special symbol display device 61 is configured by a device that displays special symbols as symbols composed of numbers, symbols, and the like. In addition, this invention is not limited to this, You may comprise the special symbol display apparatus 61 by several LED, for example. In this case, a display pattern configured by turning on / off a plurality of LEDs is represented as a special symbol.

  The special symbol display device 61 performs variation display of the special symbol (identification information), triggered by the game ball winning in the first starting opening 44 or the second starting opening 45 (special symbol starting winning). Then, the special symbol display device 61 performs the special symbol stop display after performing the variable symbol special symbol display for a predetermined time. Hereinafter, the special symbol variably displayed on the special symbol display device 61 when the gaming ball wins the first starting opening 44 is referred to as a first special symbol. The special symbol that is variably displayed on the special symbol display device 61 when the game ball wins the second start opening 45 is referred to as a second special symbol.

  In the special symbol display device 61, when the first special symbol or the second special symbol stopped and displayed is a specific mode (a mode of "big hit"), the gaming state is advantageous to the player from the normal gaming state It shifts to the big hit game state which is a state. That is, in the special symbol display device 61, it is “big hit” that the first special symbol or the second special symbol is stopped and displayed in a state of shifting to the big hit gaming state.

  In the big hit gaming state, the first big winning port 53 or the second big winning port 54 is opened. Specifically, in the present embodiment, when the gaming ball wins the first starting opening 44 and the first special symbol is stopped and displayed in a specific mode in the special symbol display device 61, the first big winning opening 53 is open. On the other hand, when the gaming ball wins the second starting opening 45 and the second special symbol is stopped and displayed in a specific mode in the special symbol display device 61, the second big winning opening 54 is in the open state.

  The open state of each big winning opening is maintained until a predetermined number of game balls are won or until a certain period (for example, 30 sec) elapses. Then, when the elapsed period of the open state of each big winning opening satisfies any one of these conditions, the big winning opening that was in the open state is closed.

  Hereinafter, a game in which the first large winning opening 53 or the second large winning opening 54 is in a state (opened state) in which the game ball can be easily received is referred to as a round game. During the round game, the big winning opening is closed. A round game is counted as the number of rounds such as one round and two rounds. For example, the first round game is referred to as a first round, and the second round game is referred to as a second round.

  In addition, in the special symbol display device 61, when the special symbol stopped and displayed is an aspect other than the specific aspect (an aspect of “loss”), the gaming state does not shift except in the case of winning the fall lottery. That is, the special symbol game is a game in which the special symbol is variably displayed by the special symbol display device 61, and then the special symbol is stopped and displayed, and the gaming state is shifted or maintained depending on the result.

  Further, in the pachinko gaming machine 1 according to the present embodiment, when a game ball wins the first start opening 44 while the variation display of the first special symbol or the second special symbol is displayed, the variable of the first special symbol corresponding to the winning is made. The display (hold ball) is suspended. Then, when the first special symbol or the second special symbol in the variation display is stopped and displayed, the variation display of the held first special symbol is started. In the present embodiment, the number of variable displays of the first special symbol to be held (so-called “holding number (the number of holding balls)”) is defined as a maximum of four times (pieces).

  Furthermore, in the present embodiment, when the gaming ball wins the second starting opening 45 during the variable display of the first special symbol or the second special symbol, the variable display of the second special symbol corresponding to the winning (holding ball) Is put on hold. Then, when the first special symbol or the second special symbol in the variation display is stopped and displayed, the variation display of the held second special symbol is started. In the present embodiment, the number of variable displays (holding number) of the second special symbol to be held is defined as a maximum of 4 times (pieces). Therefore, in this embodiment, the total number of variable symbols to be held is 8 at the maximum.

  Moreover, in this embodiment, when the holding ball of the first special symbol and the holding ball of the second special symbol are mixed, the variable display of one of the special symbols is executed preferentially to the variable display of the other special symbol. . In addition, this invention is not limited to this, When the reservation ball | bowl of a 1st special symbol and the reservation ball | bowl of a 2nd special symbol coexist, you may make it perform the change display of a special symbol in the order kept.

[Normal symbol display device]
As shown in FIG. 4, the normal symbol display device 62 is disposed in the approximate center of the upper portion of the display area 13 a of the display device 13. And, in the present embodiment, the normal symbol display device 62 is disposed on the right side of the special symbol display device 61 as viewed from the player side.

  The normal symbol display device 62 is a display device for variably displaying normal symbols (variation display and stop display) in a normal symbol game. In the present embodiment, as shown in FIG. 4, the normal symbol display device 62 is configured by two LEDs (normal symbol display LEDs) arranged in the vertical direction. In the normal symbol display device 62, a display pattern constituted by turning on / off each normal symbol display LED is represented as a normal symbol.

  The normal symbol display device 62 alternately turns on / off the two normal symbol display LEDs in response to the game ball passing through the ball passage detector 43, and performs the variation display of the normal symbol. Then, the normal symbol display device 62 performs the normal symbol stop display after performing the normal symbol variation display for a predetermined time.

  In the normal symbol display device 62, when the normal symbol stopped and displayed is in a predetermined mode (a mode of "hit"), the normal motorized role 46 is changed from the closed state to the open state only for a predetermined period. On the other hand, when the normal symbol stopped and displayed is a mode other than the predetermined mode (a mode of “losing”), the normal motorized role 46 maintains the closed state. That is, the normal symbol game is a game in which the normal symbol is variably displayed by the normal symbol display device 62, and then the normal symbol is stopped and displayed, and the normal electric character 46 operates according to the result.

  If the game ball passes through the ball passage detector 43 during the normal symbol variation display, the normal symbol variable display is suspended. Then, when the normal symbol that is currently in the variable display is stopped and displayed, the variable display of the normal symbol that has been suspended is started. In the present embodiment, the number of variable symbols of the normal symbol to be held (that is, the “holding number”) is defined as a maximum of 4 times (pieces).

[Normal symbol hold display device]
The normal symbol hold display device 63 is disposed substantially at the center of the upper portion of the display area 13a of the display device 13, as shown in FIG. And, in the present embodiment, the normal symbol hold display device 63 is disposed below the special symbol display device 61 and the normal symbol display device 62.

  The normal symbol hold display device 63 is a device that displays the number of hold of variable display of normal symbols. In the present embodiment, as shown in FIG. 4, the normal symbol hold display device 63 is configured by four LEDs (normal symbol hold display LEDs) arranged in the left-right direction. Then, in the normal symbol holding display device 63, the number of holdings of variable symbols of normal symbols is displayed by turning on / off each normal symbol holding display LED.

  Specifically, when the number of holdings of the normal symbol variable display is 1, the normal symbol holding display LED located on the leftmost side when viewed from the player side (the first normal symbol holding display LED from the left) Lights up and the other normal symbol hold display LED goes out. In the case where the number of held variable display of the normal symbol is 2, the first and second normal symbol hold display LEDs from the left light, and the other normal symbol hold display LEDs turn off. In the case where the number of held variable display of normal symbols is 3, the first to third normal symbol hold display LEDs from the left light and the other normal symbol hold display LEDs are extinguished. When the number of normal symbol variable display hold is 4, all the normal symbol hold display LEDs are lit.

[First special symbol hold display device]
As shown in FIG. 4, the first special symbol hold display device 64 is arranged on the left side of the special symbol display device 61 when viewed from the player side in the upper part of the display area 13 a of the display device 13.

  The first special symbol hold display device 64 is a device that displays information on the variable display of the first special symbol being held (the holding ball of the first special symbol). In the present embodiment, as shown in FIG. 4, the first special symbol hold display device 64 includes a first special symbol hold number display unit 64a and a first special symbol hold information display unit 64b. The first special symbol hold information display unit 64b is arranged on the left side of the special symbol display device 61, and the first special symbol hold information display unit 64a is arranged on the left side of the first special symbol hold information display unit 64b. .

  The first special symbol reserved number display section 64a has four LEDs (first special symbol reserved display LEDs) arranged in the left-right direction. Note that the display mode of the first special symbol reservation number display unit 64 a is the same as the display mode of the normal symbol hold display device 63. That is, when the variable display of the first special symbol is on hold, the first special symbol hold display LED from the first special symbol hold display LED located on the leftmost side to the number of reserved pieces as viewed from the player side. Lights up.

  Moreover, the 1st special symbol hold information display part 64b displays the information regarding the hold ball of a 1st special symbol. For example, the first special symbol hold information display unit 64b displays information (identification information) about the hold ball of the first special symbol to be variably displayed next with a symbol made up of numbers, symbols, and the like. In addition, the configuration of the first special symbol hold display device 64 is not limited to the example shown in FIG. 4 and can be arbitrarily configured as long as it can display at least the number of pending variable displays of the first special symbol. .

[Second special symbol hold display device]
As shown in FIG. 4, the second special symbol hold display device 65 is disposed on the right side of the normal symbol display device 62 when viewed from the player side in the upper part of the display area 13 a of the display device 13.

  The second special symbol hold display device 65 is a device for displaying information on the variable display of the second special symbol being held (the holding ball of the second special symbol). In the present embodiment, as shown in FIG. 4, the second special symbol hold display device 65 includes a second special symbol hold number display unit 65a and a second special symbol hold information display unit 65b. The second special symbol hold information display unit 65b is disposed on the right side of the normal symbol display device 62, and the second special symbol hold number display unit 65a is disposed on the right side of the second special symbol hold information display unit 65b. .

  The second special symbol reserved number display unit 65a has four LEDs (second special symbol reserved display LEDs) arranged in the left-right direction. Note that the display mode of the second special symbol reservation number display unit 65 a is the same as the display mode of the normal symbol hold display device 63. That is, when the variable display of the second special symbol is being held, the second special symbol holding indication LED from the second special symbol holding indication LED located at the leftmost position to the number of holdings as seen from the player side Lights up.

  In addition, the second special symbol hold information display unit 65b displays information related to the hold ball of the second special symbol. For example, the second special symbol hold information display unit 65b displays information (identification information) related to the hold ball of the second special symbol to be variably displayed next with a symbol made up of numbers, symbols, and the like. In addition, the configuration of the second special symbol hold display device 65 is not limited to the example shown in FIG. 4 and can be arbitrarily configured as long as it can display at least the number of pending variable displays of the second special symbol. .

[Display device]
The display device 13 is configured by the liquid crystal display device as described above, and performs various image display effects in the display area 13a.

  Specifically, in the present embodiment, an effect image related to the special symbol displayed on the special symbol display device 61 is displayed in the display area 13a. Under the present circumstances, for example, when the special symbol is being variably displayed in the special symbol display device 61, a plurality of effect identification symbols (for example, decoration (decor The symbol is variably displayed in the display area 13a. When the special symbol is stopped and displayed in the special symbol display device 61, a plurality of decorative symbols (such as a jackpot symbol described later) corresponding to the special symbol are also stopped and displayed in the display area 13a.

  Then, when the special symbol stopped and displayed in the special symbol display device 61 is in a specific mode (the result of the stop display is “big hit”), the player can grasp that it is “big hit”. An effect image is displayed on the display area 13a. As an effect for causing the player to grasp that it is a “hit”, for example, first, a plurality of decorative symbols that are stopped and displayed are in a specific mode (for example, a mode in which the same decorative symbols are arranged in a predetermined direction) After that, there is an effect of displaying an image for informing the “big hit”.

  In the present embodiment, an effect image related to the display contents of the first special symbol hold display device 64 and the second special symbol hold display device 65 is displayed in the display area 13 a of the display device 13. For example, the display area 13a displays hold information (for example, the same number of holding symbols as the number of holdings) for notifying the number of holdings for variable display of special symbols. Further, for example, in the pachinko gaming machine 1 of the present embodiment, the pre-reading effect is performed based on the information of the holding ball of the special symbol, but the advance notice at this time is also displayed in the display area 13a.

  In the present embodiment, when the normal symbol stopped and displayed on the normal symbol display device 62 is in a predetermined mode, an effect image that causes the player to grasp the information is displayed on the display area 13a of the display device 13. A function may be further provided.

<Circuit configuration of pachinko machines>
Next, with reference to FIG. 5, configurations of various circuits included in the pachinko gaming machine 1 of the present embodiment will be described. FIG. 5 is a block diagram showing a circuit configuration of the pachinko gaming machine 1.

  As shown in FIG. 5, the pachinko gaming machine 1 has a main control circuit 70 (main control means) that mainly controls game operations, a payout / launch control circuit 123, and control of performance operations according to the progress of the game. And a sub-control circuit 200 (sub-control means, effect control means).

[Main control circuit]
The main control circuit 70 includes a one-chip microcomputer 77, a clock generation circuit 74, and an initial reset circuit 75. As described above, in the present embodiment, the lottery process of the special symbol is performed at the time of winning of the first starting opening 44 or the second starting opening 45, but this processing is controlled by the main control circuit 70. That is, the main control circuit 70 also serves as means (lottery means) for performing a lottery process for determining whether or not to shift the gaming state to a state advantageous to the player.

  The one-chip microcomputer 77 includes a main CPU (Central Processing Unit) 71, a main ROM (Read Only Memory) 72, a main RAM (Random Access Memory) 73, and a serial communication unit 76. The main CPU 71, the main ROM 72, the main RAM 73, and the serial communication unit 76 may be provided separately.

  In the present embodiment, a configuration in which the main ROM 72 is built in the substrate of the main control circuit 70 will be described, but the present invention is not limited to this. For example, a ROM board on which the main ROM 72 is mounted may be connected to the board of the main control circuit 70. Furthermore, in the present embodiment, the various circuits (various means) in the main control circuit 70 may be integrally formed or separately formed. Further, the main ROM 72 may not be configured to be installed in the gaming machine but may be configured to be able to communicate with the gaming machine.

  A clock generation circuit 74 and an initial reset circuit 75 are connected to the one-chip microcomputer 77. The main ROM 72 stores various programs (see FIGS. 62 to 71 described later) for controlling the operation of the pachinko gaming machine 1 by the main CPU 71, various data tables (see FIGS. 9 to 18 described later), and the like. ing.

  The main CPU 71 executes various processes according to programs stored in the main ROM 72. The main RAM 73 acts as a temporary storage area when the main CPU 71 executes various processes, and stores values of various flags and variables that the main CPU 71 needs for various processes. In the present embodiment, the main RAM 73 is used as a temporary storage area of the main CPU 71, but the present invention is not limited to this, and any recording medium can be used as a temporary storage area as long as it is a readable and writable storage medium. .

  The clock generation circuit 74 generates a clock pulse at a predetermined cycle (for example, 2 msec) in order to execute a system timer interrupt process to be described later. The initial reset circuit 75 generates a reset signal when the power is turned on. Then, the serial communication unit 76 supplies a command to the sub control circuit 200.

  Further, as shown in FIG. 5, various devices that operate according to the output signal sent from the main control circuit 70 are connected to the main control circuit 70.

  Specifically, the main control circuit 70 is connected to the special symbol display device 61, the normal symbol display device 62, the normal symbol hold display device 63, the first special symbol hold display device 64, and the second special symbol hold display device 65. Is done. Each of these devices performs a predetermined operation based on the output signal sent from the main control circuit 70. For example, when a predetermined output signal is transmitted from the main control circuit 70 to the special symbol display device 61, the special symbol display device 61 performs operation control of the variable display of the special symbol in the special symbol game based on the output signal. Do.

  The main control circuit 70 is connected to a normal electric accessory solenoid 46a, a first big prize opening solenoid 53b, and a second big prize opening solenoid 54b. Then, the main control circuit 70 drives and controls the ordinary electric accessory solenoid 46a to bring the pair of blade members of the ordinary electric accessory 46 into an open state or a closed state. Further, the main control circuit 70 drives and controls the first large winning opening solenoid 53b and the second large winning opening solenoid 54b, respectively, to make the first large winning opening 53 and the second large winning opening 54 open or closed. Do.

  Further, as shown in FIG. 5, the main control circuit 70 is connected to various sensors and receives output signals from the various sensors. Specifically, the main control circuit 70 includes count sensors 53c and 54c, general winning ball sensors 51a and 52a, a passing ball sensor 43a, a first starting port winning ball sensor 44a, a second starting port winning ball sensor 45a, and a backup. The clear switch 121 or the like is connected.

  The count sensor 53c counts the gaming balls that have won the first large winning opening 53, and outputs a predetermined output signal indicating the result to the main control circuit 70. The count sensor 54c counts the gaming balls that have won the second big winning opening 54, and outputs a predetermined output signal indicating the result to the main control circuit 70. The general winning ball sensor 51a outputs a predetermined detection signal to the main control circuit 70 when the gaming ball has won in the general winning opening 51, and the general winning ball sensor 52a has the gaming ball in the general winning opening 52 In this case, a predetermined detection signal is output to the main control circuit 70.

  The passing ball sensor 43 a outputs a predetermined detection signal to the main control circuit 70 when the game ball passes through the ball passing detector 43. The first starting hole winning ball sensor 44 a outputs a predetermined detection signal to the main control circuit 70 when the gaming ball has won the first starting hole 44. The second starting opening winning ball sensor 45 a outputs a predetermined detection signal to the main control circuit 70 when the gaming ball has won the second starting opening 45. Also, the backup clear switch 121 sends a predetermined detection signal to the main control circuit 70 and the payout / fire control circuit 123 when the backup data is cleared according to the operation of the game arcade manager or the like at the time of power interruption or the like. Output.

  Further, a payout / firing control circuit 123 is connected to the main control circuit 70. The contents of the payout / emission control circuit 123 and the various peripheral devices connected thereto will be described in detail later.

[Discharge / Launch Control Circuit and its Peripherals]
The payout / firing control circuit 123 is connected to the prize ball case unit 170, the payout state notification display device 178, the lower pan full switch 179, the firing device 15, the external terminal board 140, and the card unit 150. Further, the external terminal board 140 is connected to the data display 141, and the card unit 150 is connected to the lending operation unit 151.

  The payout / firing control circuit 123 inputs / outputs signals etc. to / from these peripheral devices based on various commands etc. transmitted from the main control circuit 70, and controls the operation of each peripheral device. For example, the payout / firing control circuit 123 receives a prize ball control command transmitted from the main control circuit 70 and a rental ball control signal to be described later transmitted from the card unit 150, and sends a predetermined value to the prize ball case unit 170. Send a signal. Thereby, the winning ball case unit 170 pays out the gaming ball.

  The prize ball case unit 170 is a device for paying out game balls, and the first 15 ball security switch 172a, the second 15 ball security switch 172b, the first counting switch 181a, the second counting switch 181b, and the payout It has a motor 174. The components included in the winning ball case unit 170 are connected to the payout / emission control circuit 123, respectively.

  Further, although not shown here, two ball supply passages are provided inside the prize ball case unit 170. The first 15-ball collateral switch 172a detects the gaming ball supplied to one of the ball supply passages, and outputs a predetermined output signal indicating the detection result to the payout / firing control circuit 123. The second 15-ball collateral switch 172b detects a game ball replenished in the other ball supply passage, and outputs a predetermined output signal indicating the detection result to the payout / launch control circuit 123.

  Furthermore, although not shown here, two payout paths are provided inside the prize ball case unit 170. Then, the first counting switch 181 a detects a game ball paid out to one payout passage, and outputs a predetermined output signal indicating the detection result to the payout / launch control circuit 123. The second counting switch 181b detects the game ball paid out to the other payout passage, and outputs a predetermined output signal indicating the detection result to the payout / launch control circuit 123.

  The payout motor 174 is composed of a stepping motor and is driven according to a control signal input from the payout / firing control circuit 123. The payout motor 174 rotationally drives a sprocket (rotating member) (not shown) provided in the winning ball case unit 170. Then, by the rotation operation of the sprocket, the game balls stored in each ball supply passage move one by one to the corresponding payout passage.

  The payout state notification display device 178 is a device for reporting the type of the abnormality when an abnormality occurs with regard to the payout of the gaming ball, and is constituted by a 7-segment display. The payout state notification display device 178 is attached at a position where only the manager of the game arcade (game arcade) can visually recognize, and is attached, for example, to a predetermined place on the back of the pachinko gaming machine 1.

  When the game ball stored in the lower plate 22 becomes full, the lower plate full tank switch 179 detects this and outputs the detection result to the payout / launch control circuit 123.

  The payout / firing control circuit 123 outputs the payout status notification display device 178 indicating that the lower tray full state is received when a signal indicating the lower tray full state is input from the lower plate full tank switch 179. A signal is output to the main control circuit 70 to indicate that it is full. Thereafter, when an effect control command is transmitted from the main control circuit 70 to the sub control circuit 200, the sub control circuit 200 uses the speaker 11, the lamp group 18, the display device 13, etc., for example, so that the lower plate 22 is full. Inform that there is.

  The launching device 15 has a launching handle 25 that can be turned by the player when the game ball stored in the upper plate 21 is launched into the game area 12a. The payout / firing control circuit 123 controls the solenoid actuator (not shown) of the launching device 15 according to the turning angle when the firing handle 25 is held by the player and turned clockwise. Supply power. Thereby, the launching device 15 launches a game ball. A motor may be used instead of the solenoid actuator as the drive unit of the launcher 15.

  The external terminal board 140 is used to transmit data to a hall computer that manages all pachinko gaming machines in the game store. The data display 141 is installed, for example, at the top of the pachinko gaming machine 1 as a subsidiary facility of a game arcade, and has a function of calling a hall clerk and a function of displaying the number of hits.

  When operated by the player, the lending operation unit 151 outputs a signal requesting the card unit 150 to lend a game ball. The card unit 150 determines the number of gaming balls to be paid out (the number of rental balls) via the prize ball case unit 170 based on the signal requesting for lending of the gaming balls output from the lending operation unit 151. Then, when the card unit 150 receives a signal requesting the game ball to be loaned from the lending operation unit 151, the card unit 150 transmits a loan ball control signal including information on the determined number of balls to the payout / firing control circuit 123.

[Sub control circuit]
The sub control circuit 200 is connected to the serial communication unit 76 of the main control circuit 70. Then, the sub control circuit 200 (host control circuit 210 described later) controls the entire sub control circuit 200 in accordance with various commands (information relating to the progress of the game) transmitted from the main control circuit 70. Then, the sub-control circuit 200 controls the sound reproduction operation by the speaker 11, the image display operation by the display device 13, and the lamp group 18 including LEDs (effects) based on various commands transmitted from the main control circuit 70. Means) controls the lamp lighting / extinguishing operation, and controls the rendering operation by the character 20 (decorative member). That is, the sub control circuit 200 controls various effect devices based on the command from the main control circuit 70, and executes various effects according to the progress of the game. In the present embodiment, a signal cannot be supplied from the sub control circuit 200 to the main control circuit 70. However, the present invention is not limited to this, and a signal can be transmitted from the sub control circuit 200 to the main control circuit 70. May be provided.

  Next, the internal configuration of the sub control circuit 200 will be described in more detail with reference to FIG. FIG. 6 is a block diagram showing a circuit configuration inside the sub-control circuit 200 and a connection relationship between the sub-control circuit 200 and its various peripheral devices.

  As shown in FIG. 6, the sub control circuit 200 includes a relay substrate 201, a sub substrate 202, a control ROM substrate 203, and a CGROM (Character Generator ROM) substrate 204. The sub substrate 202 is connected to the relay substrate 201, the control ROM substrate 203, and the CGROM substrate 204.

  The relay board 201 is a relay board for receiving a command transmitted from the main control circuit 70 and transmitting the received command to the sub board 202.

  The sub substrate 202 includes a host control circuit 210 (host control means), an audio / LED control circuit 220 (light emission control means), a display control circuit 230 (display control means), an SDRAM (Synchronous Dynamic RAM) 250, and a built-in relay board 260. Is provided.

  The host control circuit 210 is a circuit that controls the overall operation of the sub control circuit 200 based on various commands transmitted from the main control circuit 70, and is configured of a CPU processor. The host control circuit 210 is connected to the sound / LED control circuit 220, the display control circuit 230, and the built-in relay board 260 in the sub-board 202. The host control circuit 210 is connected to the control ROM board 203.

  The host control circuit 210 also includes a sub work RAM 210 a and an SRAM (Static RAM) 210 b. The subwork RAM 210a is a storage device which acts as a working temporary storage area when the host control circuit 210 executes various processes, and various flags and variables required when the host control circuit 210 executes various processes Memorize the value of. The SRAM 210 b is a storage device that backs up predetermined data in the sub work RAM 210 a. In this embodiment, a RAM is used as a temporary storage area of the host control circuit 210. However, the present invention is not limited to this, and any recording medium may be used as a temporary storage area as long as it is a readable / writable storage medium. .

  The voice / LED control circuit 220 is connected to the speaker 11 and the lamp group 18 via the built-in relay board 260, and based on control signals (a sound request and a lamp request described later) input from the host control circuit 210. It is a circuit that controls the sound reproduction operation according to the above and the light emission operation by the lamp group 18. Thus, functionally, the audio and LED control circuit 220 comprises an audio controller 220a and a lamp controller 220b. The sound controller 220 a and the lamp controller 220 b are substantially included in a sound lamp control module 226 described later. The internal configuration of the voice / LED control circuit 220 will be described in detail later with reference to the drawings.

  In this embodiment, when a control signal and data (for example, LED data described later) output from the sound / LED control circuit 220 are transmitted to the lamp group 18 via the built-in relay board 260, the sound / LED Communication between the control circuit 220 and the lamp group 18 is performed by an SPI (Serial Periperal Interface) communication method (a kind of serial communication method). In the present embodiment, the lamp group 18 includes one or more LEDs and one or more LED drivers for controlling each LED (see FIGS. 36 to 38 described later).

  The display control circuit 230 is connected to the display device 13 and displays an image (decorative symbol image, background image, effect image, etc.) related to an effect based on a control signal (drawing request) input from the host control circuit 210. It is a circuit for controlling various processing operations when displaying on the screen. The display control circuit 230 includes a display controller (a first display controller 238 and a second display controller 239 described later) and a built-in VRAM (Video RAM) 237.

  In addition, the display control circuit 230 is connected to the SDRAM 250 in the sub substrate 202. Further, the display control circuit 230 is connected to the CGROM substrate 204. Further, the display controller in the display control circuit 230 is directly connected to the display device 13 without passing through the relay substrate. The internal configuration of the display control circuit 230 will be described in detail later with reference to the drawings.

  The SDRAM 250 is configured by a DDR2 (Double-Date Rate2) SDRAM. Further, the SDRAM 250 is provided with various buffers for temporarily storing various image data in the drawing process of images (moving images and still images) displayed by the display device 13. Specifically, for example, as shown in FIGS. 90 to 92 described later, the SDRAM 250 includes a texture buffer, a move buffer, a blend buffer, two frame buffers (a first frame buffer and a second frame buffer), and a motion buffer. Etc. are provided.

  The built-in relay board 260 receives various signals and various data output from the host control circuit 210 and the sound / LED control circuit 220, and receives the received various signals and various data to the speaker 11, the lamp group 18, and the accessory 20. It is a relay board to transmit.

  The built-in relay board 260 includes an I2C (Inter-Integrated Circuit) controller 261, and the I2C controller 261 is connected to the host control circuit 210 and the motor controller 270 of the accessory 20. That is, the host control circuit 210 is connected to the accessory 20 via the I2C controller 261 and the motor controller 270. A control signal and data (for example, excitation data described later) output from the host control circuit 210 are input to the accessory 20 via the I2C controller 261 and the motor controller 270.

  In the present embodiment, communication between the I2C controller 261 and the motor controller 270 is performed by an I2C communication system (a type of serial communication system). Further, in the present embodiment, the accessory 20 includes one or more motors, and the motor controller 270 includes one or more motor drivers for driving the motors (described later). 60 and FIG. 61). Although FIG. 6 shows an example in which only one accessory 20 is provided, the present invention is not limited to this, and a plurality of accessories 20 may be provided.

  In the configuration of this embodiment, the host control circuit 210 may directly drive the motor of the accessory 20 without using the motor controller 270, or a motor control control circuit may be provided separately. Good. Furthermore, in the present embodiment, although a configuration in which a plurality of motor drivers (motors) are controlled by one control circuit will be described (see FIGS. 60 and 61 described later), the present invention is not limited thereto. In this embodiment, one or more (one or more) control circuits may control one or more (one or more) motors (motor driver), or one or more (one or more) control circuits. One motor (motor driver) may be controlled, or one control circuit may control one motor (motor driver).

  A sub main ROM 205 is provided on the control ROM board 203. In the sub main ROM 205, various programs (see FIGS. 72, 74 to 77, and 79 to 103 described later) for controlling the presentation operation of the pachinko gaming machine 1 by the host control circuit 210, and various data tables ( 19) to be described later are stored. Then, the host control circuit 210 executes various processes in accordance with the program stored in the sub main ROM 205.

  In the present embodiment, the sub main ROM 205 is applied as a storage unit for storing a program used in the host control circuit 210 and various tables, but the present invention is not limited to this. As such a storage means, a storage medium of another aspect may be used as long as it is a computer-readable storage medium provided with a control means. For example, a hard disk device, a CD-ROM and a DVD-ROM, a ROM cartridge, etc. The storage medium may be applied. Also, each of the programs may be recorded on separate storage media. Furthermore, the program may be recorded in advance in a recording medium, or may be downloaded from the outside after power on and recorded in the sub main ROM 205.

  The CGROM substrate 204 is provided with a CGROM 206. The CGROM 206 stores, for example, image data displayed on the display device 13, audio data reproduced by the speaker 11 (access data described later), and the like.

  In the present embodiment, the configuration in which various ROM boards (the control ROM board 203 and the CGROM board 204) and the sub board 202 are connected in a board-to-board manner in the sub-control circuit 200 has been described. Is not limited to this. For example, various ROMs may be directly inserted into a port such as a socket provided on the sub substrate 202, and the sub substrate 202 may be formed of a single substrate having the ROM function or the ROM itself. That is, the sub board 202 and various ROMs may be integrally configured.

[Audio / LED control circuit]
Next, the internal configuration of the voice / LED control circuit 220 will be described with reference to FIG. FIG. 7 is a block diagram showing an internal circuit configuration of the voice / LED control circuit 220 and a connection relationship between the voice / LED control circuit 220 and its various peripheral devices and peripheral circuit units. In FIG. 7, in order to simplify the description, illustration of relay boards and the like provided between the audio / LED control circuit 220 and various peripheral devices and circuit units is omitted.

  As shown in FIG. 7, the audio / LED control circuit 220 includes an LSI (Large-Scale Integration) interface 221, a memory interface 222, a digital audio interface 223, a peripheral interface 224, a command register 225, and a sound lamp. A control module 226, a main generator 227, and a multi-effector 228 are provided. The connection relationship of each part in the voice / LED control circuit 220 is as follows.

  In the audio and LED control circuit 220, the sound and lamp control module 226 is connected to the memory interface 222, the peripheral interface 224, the command register 225, the main generator 227 and the multi-effector 228. The command register 225 is connected to the LSI interface 221 in addition to the sound and lamp control module 226. The main generator 227 is connected to the memory interface 222 and the multi-effector 228 in addition to the sound / lamp control module 226. Furthermore, the multi-effector 228 is connected to the memory interface 222 and the digital audio interface 223 in addition to the sound lamp control module 226 and the main generator 227.

  Next, the configuration of each unit in the voice / LED control circuit 220 will be described.

  The LSI interface 221 is an interface circuit used when an input / output operation such as a control signal (for example, a sound request, a ramp request) is performed between the host control circuit 210 and the command register 225. That is, the command register 225 is connected to the host control circuit 210 via the LSI interface 221.

  The memory interface 222 is an interface circuit used when performing input / output operations such as audio data between the sub main ROM 205 and each of the sound / lamp control module 226, the main generator 227, and the multi-effector 228.

  The digital audio interface 223 is an interface circuit used when outputting an audio signal or the like from the multi-effector 228 to the speaker 11. The digital audio interface 223 also outputs an audio input signal to the multi-effector 228.

  The peripheral interface 224 is an interface circuit used when an input / output operation of a lamp signal or the like (LED data described later) is performed between the lamp group 18 and the sound / lamp control module 226. The peripheral interface 224 is provided with three physical systems as physical systems (SPI channels) for outputting data to the LED drivers included in the lamp group 18. In the present embodiment, two physical systems (physical system 0 (SPI channel 0) and physical system 1 (SPI channel 1)) are used as described later.

  The command register 225 includes a register group. The command register 225 sets function control for the sound / lamp control module 226, the main generator 227, and the multi-effector 228. The command register 225 also sets the operating conditions of each interface (LSI interface 221, memory interface 222, digital audio interface 223, peripheral interface 224).

  An IC (Integrated Circuit) is mounted on each of the registers constituting the command register 225, and each of the registers is constituted by a memory chip whose operation is stabilized by memory access control. When registers of such a configuration are used, the load on the signal bus to which each register is connected is reduced. Therefore, the capacity per memory module can be easily increased by increasing the number of memory chips (registers). The capacity of the command register 225 can be increased.

  The sound / lamp control module 226 controls the operation of each component (each block) in the audio / LED control circuit 220 in accordance with the setting contents of the command register 225. As shown in FIG. 7, the sound / lamp control module 226 includes a simple access control unit 226a, a sequencer unit 226b, a lamp control unit 226c, and a peripheral control unit 226d.

  The simple access control unit 226a is a circuit unit that collectively processes commands. The sequencer unit 226b includes various sequencers (automatic reproduction function units) for controlling automatic reproduction operations such as lamp lighting and sound. Then, each sequencer controls various operations in accordance with a timer and step conditions (for example, conditions set for each step processing during sequence reproduction such as LED animation and sound described later).

  The lamp control unit 226c calculates the luminance value to be set in all channels (eight channels) in which LED data to be described later can be set, and transmits the calculation result to the outside (LED driver). Also, the peripheral control unit 226d performs physical transmission control when transmitting the data of the calculation result output from the lamp control unit 226c to the LED driver.

  The main generator 227 is a circuit unit that generates an audio signal. Specifically, the main generator 227 acquires predetermined audio data stored in the CGROM 206 based on the control signal input from the sound / lamp control module 226, and acquires the acquired audio data as a predetermined audio signal. Convert to The main generator 227 also performs amplification processing of the generated audio signal.

  The multi-effector 228 has a mixer that synthesizes an audio signal input from the main generator 227 and an audio input signal input from the digital audio interface 223, and various effectors for applying various acoustic effects to audio. Then, the multi-effector 228 outputs an audio signal synthesized by the mixer, an output signal from the effector, and the like to the speaker 11 through the digital audio interface 223.

[Display control circuit]
Next, the internal configuration of the display control circuit 230 will be described with reference to FIG. FIG. 8 is a block diagram showing the circuit configuration inside the display control circuit 230 and the connection between the display control circuit 230 and its various peripheral devices and peripheral circuit units.

  The display control circuit 230, as shown in FIG. 8, includes a memory controller 231, a command memory 232, a command parser 233, a moving image decoder 234, a still image decoder 235, an SDRAM controller 236, a built-in VRAM 237, and A display controller 238, a second display controller 239, a 3D (Dimension) geometry engine 240, and a rendering engine 241 are provided. The connection relationship of each part in the display control circuit 230 and the connection relationship between the display control circuit 230 and its various peripheral devices and peripheral circuits are as follows.

  In the display control circuit 230, the memory controller 231 is connected to a command parser 233, a moving picture decoder 234 and a still picture decoder 235. The command parser 233 is connected to the command memory 232, the moving image decoder 234, the still image decoder 235 and the 3D geometry engine 240 in addition to the memory controller 231. The video decoder 234 is connected to the SDRAM controller 236 in addition to the memory controller 231 and the command parser 233. The still image decoder 235 is connected to the built-in VRAM 237 in addition to the memory controller 231 and the command parser 233.

  Further, in the display control circuit 230, the SDRAM controller 236 is connected to the built-in VRAM 237, the first display controller 238 and the second display controller 239 in addition to the moving picture decoder 234. The built-in VRAM 237 is connected to the first display controller 238, the second display controller 239, and the rendering engine 241 in addition to the still image decoder 235 and the SDRAM controller 236. Furthermore, the 3D geometry engine 240 is connected to the rendering engine 241 in addition to the command parser 233.

  The SDRAM 250 is connected to the memory controller 231 and the SDRAM controller 236 in the display control circuit 230. Further, the CGROM substrate 204 is connected to the memory controller 231 in the display control circuit 230. The host control circuit 210 is also connected to the memory controller 231 and the command memory 232 in the display control circuit 230. Furthermore, the display device 13 is connected to a first display controller 238 and a second display controller 239 in the display control circuit 230.

  Next, the configuration of each unit in the display control circuit 230 will be described.

  The memory controller 231 mainly performs communication control between various external memories (the CGROM substrate 204 and the SDRAM 250) and the display control circuit 230. For example, the memory controller 231 performs transmission / reception of an address designation signal of an external memory to be controlled, processing of memory ready, busy management, etc., and data stored in an address designated for various memories (effect data , Command data, etc.).

  The command memory 232 is a built-in memory that stores a command list. The command list may be stored in the SDRAM 250 and the CGROM substrate 204 (CGROM 206) in addition to the command memory 232.

  The command parser 233 acquires a command list from a specified memory (command memory 232, SDRAM 250 or CGROM 206). Specifically, in the present embodiment, the type (command memory 232, SDRAM 250 or CGROM 206) of the memory in which the command list is arranged in the system control register (not shown) in the display control circuit 230 by the host control circuit 210; The start address is set. Then, the command parser 233 obtains a command list by accessing the start address in the memory designated in the system control register (not shown).

  In addition, the command parser 233 generates a specific control code by analyzing the acquired command list, and outputs the control code to the moving picture decoder 234, the still picture decoder 235, and the 3D geometry engine 240. In the present embodiment, each image processing module in the display control circuit 230 operates based on the control code output by the command parser 233.

  The moving picture decoder 234 decodes (decodes) the moving picture compressed data acquired from the CGROM substrate 204 or the SDRAM 250. Then, the moving image decoder 234 outputs the decoded moving image data to the SDRAM 250 (external RAM). The moving image data (decoding result) output from the moving image decoder 234 is stored in a movie buffer provided in the SDRAM 250.

  The still image decoder 235 decodes still image compressed data acquired from the CGROM substrate 204 or the SDRAM 250. Then, the still image decoder 235 outputs the decoded still image data to the built-in VRAM 237. The still image data (decoding result) output from the still image decoder 235 is temporarily stored in a sprite buffer (described later) provided in the built-in VRAM 237.

  The SDRAM controller 236 stores the decoded moving image data and still image data in the RAM, and the built-in VRAM 237 and the CGROM substrate 204 or the SDRAM 250, as will be described later in the drawing process (see FIGS. 90 to 92 described later). And a controller that controls operations such as transfer processing of image data between them.

  The built-in VRAM 237 operates as a work RAM when executing various processes such as decoding and rendering in the later-described drawing process (see FIGS. 90 to 92 described later) by the display control circuit 230. In addition, various image data are temporarily stored in the built-in VRAM 237 in the process of transferring image data between the built-in VRAM 237 and the CGROM substrate 204 or the SDRAM 250 which is performed in each process in the drawing process described later.

  Each of the first display controller 238 and the second display controller 239 acquires the rendering result (drawing result) generated by the rendering engine 241 and outputs the rendering result to the display device 13. As a result, a predetermined image is displayed on the display screen of the display device 13. When two display controllers are provided as in the pachinko gaming machine 1 of the present embodiment, two screens are provided on the display device 13 by one display control circuit 230 (one chip), and each screen is displayed. It can be controlled independently.

  Based on the control code input from the command parser 233, the 3D geometry engine 240 converts 3D information into 2D information (projection conversion processing), and affine transformation such as figure enlargement, reduction, rotation, and movement. Perform (graphic conversion) processing. Then, the 3D geometry engine 240 outputs the result of the conversion process to the rendering engine 241.

  The rendering engine 241 performs rendering (drawing) processing on the image data with reference to the texture source (in this embodiment, the SDRAM 250) in which the decompressed still image data and moving image data are stored. Then, the rendering engine 241 writes the rendering result to the rendering target (in the present embodiment, the built-in VRAM 237 or the SDRAM 250).

  Note that “to render” as used in this specification refers to editing data decoded according to specified information (in the present embodiment, information output from the 3D geometry engine 240) such as scaling or rotation of a moving image. It is to be. The “rendering engine” here includes, for example, “rasterizer”, “pixel shader”, and the like. Therefore, in the rendering engine 241, similar to the pixel shader, the ARGB values (A: alpha value indicating transparency (opacity), R: luminance value of red component, G: green component) for image data in pixel units Calculation processing of the luminance value of B, the luminance value of the blue component) is also performed.

<Type of gaming state>
Next, the types of gaming states controlled and managed by the main CPU 71 will be described.

  In the present embodiment, as the types of gaming states controlled and managed by the main CPU 71, “big hit gaming state” (special gaming state) and “small hit gaming state” (specific gaming state) in which expectations of prize balls are different from each other There is. The “big hit game state” is a game state in which a round game occurs (for example, 30 seconds) in which the open period (that is, the period of one round) of the shutter of the first large winning opening 53 or the second large winning opening 54 is long. This is a gaming state in which a big prize ball can be expected for the player. That is, in the "big hit gaming state", the repetition mode of the open state and the closed state of the shutter of the big winning opening is advantageous by the player.

  On the other hand, "small hit gaming state" is a gaming state in which a round game occurs in which the period of one round is short (for example, 1.8 seconds etc.) compared to "big hit gaming state", and a player can not expect a big award ball It is a gaming state. That is, in the "small hit gaming state", the repetition mode of the open state and the closed state of the shutter of the big winning opening is disadvantageous to the player.

  Further, in the present embodiment, as the types of gaming states controlled and managed by the main CPU 71, “probability changing gaming states” (high probability gaming states) and “normal gaming states” (low) different in winning probability of “big hit” Stochastic gaming state).

  The “probability game state” is a game state in which the winning probability of “big hit” (1/131 in this embodiment) is high. On the other hand, the “normal gaming state” is a gaming state in which the winning probability (1/392 in this embodiment) of “big hit” is lower than the “probability changing gaming state”.

  Furthermore, in the present embodiment, as the type of gaming state controlled and managed by the main CPU 71, the “time saving game state” (high) in which the winning probability of the normal symbol (the probability that the normal symbol becomes the form of “hit”) mutually differs (Winning gaming state) and "non-time saving gaming state" (low winning gaming state).

  The "time-saving gaming state" in the present specification is a gaming state in which the probability of winning a normal symbol is high. That is, the "time saving game state" is a game state in which the normal motorized combination 46 (feather members) provided in the second start port 45 is likely to be in the open state (a game state in which the second start port winning is likely to occur) This is a game state advantageous to the player. It should be noted that the "time saving gaming state" is ended when "big hit" is determined or when variation display of a special symbol for a predetermined number of time reductions to be described later is executed. Also, in the short-time gaming state, a variation time shorter than the variation time selected during the normal gaming state can be easily selected as the variation time that is the time for performing the variation display of the special symbol executed during the state. It may be controlled. By such control, a game state that is advantageous to the player may be given by shortening the variation time in the short-time game state than in the normal game state and increasing the number of games per unit time.

  On the other hand, "non-time-saving (no time-saving) gaming state" is a gaming state in which the probability of winning a normal symbol is lower than "time-saving gaming state". Therefore, the "non-time-saving gaming state" is a gaming state (a gaming state in which it is difficult for the second start opening winning to be generated) in which the ordinary electric character 46 (feather members) are not easily opened. It is a state.

  And in this embodiment, the game state of various combinations of the above-mentioned game state other than "big hit game state" and "small hit game state" is provided. Specifically, in the present embodiment, a game state in which a “probability changing gaming state” and a “short-time gaming state” occur simultaneously (hereinafter referred to as a “high-probability time-shortening” state), and a “probability changing gaming state” A gaming state in which the “non-short-time gaming state” occurs at the same time (hereinafter referred to as a “high-precision time-short state”) is provided. It should be noted that, in the state of "high probability time short absence", it is difficult for the player to determine whether or not the gaming state is the "probability changing gaming state", so here, such a gaming state is referred to as "latency gaming state It is also called. In the present embodiment, the “normal gaming state” and the “non-short time gaming state” occur simultaneously (hereinafter referred to as “the low probability timeless” state), and the “normal gaming state” and the “short time” A game state (hereinafter referred to as a "low probability time short" state) in which the game state occurs simultaneously is also provided.

<Structure of data table stored in main ROM>
Next, the configuration of various data tables stored in the main ROM 72 of the main control circuit 70 will be described with reference to FIGS.

[Big Random Number Judgment Table (at the time of winning the first start opening)]
First, with reference to FIG. 9, the big hit random number determination table (at the time of the first starting opening winning) will be described. The big hit random number determination table (at the time of winning the first start opening) is based on the big hit determination random number value acquired when the game ball enters the first start opening 44 (winning), "big hit", "small hit" And it is a table referred when determining any of "loss" by lottery.

  In addition, the random number value for big hit judgment is a random number value for judging the lottery result performed triggered by the starting opening winning combination, more specifically, the lottery of the special symbol (the first special symbol and the second special symbol) A random value indicating the result. Moreover, in the present embodiment, the jackpot determination random number value (the random number value for lottery of the special symbol) is selected from 0 to 65535 (65,536 types).

  In the present embodiment, when the game ball is won in the first starting opening 44, one of “big hit”, “small hit” and “loss” is determined by lottery. Therefore, in the jackpot random number determination table (at the time of the first start opening winning), as shown in FIG. 9, for each value of probability change flag (“0 (= off)” or “1 (= on)”), “ The range of the jackpot judgment random number value for which the jackpot of "big hit", "small hit" and "lost" is determined, and the corresponding judgment value data ("big hit judgment value data", "small hit judgment value data") And the relationship with any one of “loss determination value data”. The probability change flag is one of the management flags stored in the main RAM 73, and is a flag for managing whether or not the game state is the “probability change game state”. When the gaming state is the "probable variation gaming state", the determination flag is "1".

  In the present embodiment, as shown in FIG. 9, when the first starting opening 44 is won, the probability change flag is “0”, and the jackpot determination random number value is any of “777” to “943”. , “Big hit” is won, and “Big hit judgment value data” is determined. In other words, the winning probability of “big hit” in this case (“selection rate” in FIG. 9) is 167/65536.

  In addition, when the probability variation flag is “0” and the big hit determination random value is any one of “1” to “300” at the time of winning the first start opening 44, “small hit” is won, The “small hit determination value data” is determined. That is, the winning probability of “small hit” in this case is 300/65536.

  Furthermore, when the first start opening 44 winning, the probability change flag is "0" and the jackpot determination random number value is neither "1" to "300" nor "777" to "943", the "loss" "Is won and" Loss determination value data "is determined.

  On the other hand, as shown in FIG. 9, when the first start opening 44 winning a prize, the probability change flag is "1" and the big hit determination random number value is any of "777" to "1277", as shown in FIG. "Is won, and" big hit judgment value data "is determined. That is, the winning probability of the “big hit” in this case (“selectivity” in FIG. 9) is 500/65536, which is higher than that in the case where the probability change flag is “0”.

  In addition, when the first start opening 44 winning a prize, the probability change flag is "1" and the big hit judgment random number value is any of "1" to "300", "small hit" is won, and " The “small hit determination value data” is determined. That is, the winning probability of "small hit" in this case is 300/65536, which is the same as that when the probability change flag is "0".

  Furthermore, when the first start opening 44 winning, the probability change flag is "1" and the big hit determination random number value is neither "1" to "300" nor "777" to "1277" "Is won and" Loss determination value data "is determined.

  As described above, in the present embodiment, when the game ball is won in the first starting opening 44, the selection rate (big hit probability) depends on whether or not the gaming state at the time of winning is "probable change gaming state". fluctuate. Specifically, the jackpot probability when the game ball is won in the first starting opening 44 when the gaming state is the "probability gaming state" is about three times that of the gaming state not being the "probability gaming state" Get higher.

[Big Random Number Judgment Table (at the time of winning the second starting opening)]
Next, with reference to FIG. 10, the big hit random number determination table (at the time of second starting opening winning) will be described. The big hit random number determination table (at the time of the second start opening winning) is a lottery to determine whether or not it is a “big hit” based on the random number for determining the big hit when the game ball enters (wins) the second starting opening 45 Is a table that is referred to when

  In the present embodiment, when the game ball is won in the second starting opening 45, either "big hit" or "loss" is determined by lottery. When the game ball is won in the second starting opening 45, the "small hit" is not won. Therefore, in the jackpot random number determination table (at the time of the second start opening winning), as shown in FIG. 10, for each value of probability change flag (“0 (= off)” or “1 (= on)”), “ The relationship between the range of the jackpot judgment random number values for which the jackpot of "big hit" and "loss" is determined, and the corresponding judgment value data (either "big hit judgment value data" or "loss judgment value data") Is defined.

  In the present embodiment, as shown in FIG. 10, when the second starting opening 45 is a prize, the probability change flag is “0”, and the jackpot determination random number value is any of “777” to “943”. , “Big hit” is won, and “Big hit judgment value data” is determined. In other words, the winning probability of “big hit” in this case (“selection rate” in FIG. 10) is 167/65536.

  Also, when the second start opening 45 winning, the probability change flag is "0" and the big hit determination random number value is neither "777"-"943", "loss" is won and "loss determination" Value data is determined.

  On the other hand, if the probability change flag is "1" and the jackpot determination random number value is any of "777" to "1277" at the time of the second start opening 45 winning, as shown in FIG. "Is won, and" big hit judgment value data "is determined. In other words, the winning probability (hit probability) of “big hit” in this case is 500/65536, which is higher than that when the probability variation flag is “0”.

  In addition, when the second start opening 45 winning a prize, the probability change flag is "1" and the big hit judgment random number value is neither "777" nor "1277", it becomes "loss" and "loss judgment value data" "Is determined.

  As described above, in the present embodiment, the selection rate (big hit probability) also depends on whether or not the gaming state at the time of winning is the "probability changing gaming state", even when the game ball is won in the second starting opening 45. Changes. Specifically, similarly to the first start opening 44 winning, also when the second start opening 45 winning, when the gaming state is "probability game state" when the game ball wins in the second start opening 45 The jackpot probability is about three times higher than that when the gaming state is not "probable gaming state".

[Symbol determination table (at the time of winning the first start opening)]
Next, with reference to FIG. 11, the symbol determination table (at the time of winning at the first starting opening) will be described.

  In this embodiment, the winning types (“big hit”, “small hit” or “missing”) of the lottery based on the jackpot determination random number value performed when the game ball is won in the first starting opening 44, and the first start A special symbol is selected based on the symbol random number value (random symbol value for symbol determination) acquired at the time of winning the mouth. The symbol determination table (at the time of winning at the first starting opening) is a table to be referred to when selecting the special symbol. The symbol random number value is a random number value for determining a special symbol, and is selected from 0 to 99 (100 types) regardless of the winning classification of the lottery based on the jackpot determination random number value.

  As shown in FIG. 11, a symbol designating command for designating a special symbol in each of the determination value data indicating the winning classification of the lottery based on the big hit determination random number value, as shown in FIG. The relationship between (“zA1” to “zA3”) and the symbol random value for which the symbol designation command is selected is defined.

  In addition, when the winning classification of the lottery based on the big hit judgment random number value is “small hit” (small hit judgment value data), the symbol designation command to be selected is one type (zA2), and the symbol designation is sure The command (zA2) is determined. In addition, even when the winning classification of the lottery based on the jackpot determination random number value is "loss" (loss determination value data), the symbol designation command to be selected is one type (zA3), and the symbol designation command (always) zA3) is determined.

  On the other hand, when the winning classification of the lottery based on the big hit determination random number value is "big hit" (big hit determination value data), as shown in FIG. 11, there are a plurality of types of special symbols selected, and "big hit" A plurality of kinds ("z0" to "z4") of symbol designation commands (big hit selection symbol command in FIG. 11) are also prepared. At the time of “big hit”, the big hit selection symbol command to be determined also changes according to the acquired symbol random number value. For example, when the symbol random number value acquired at the time of "big hit" is any of "40" to "59", the big hit selection symbol command "z2" is selected, and the selection rate is 20/100 Become.

[Pattern determination table (at the time of winning the 2nd starting opening)]
Next, with reference to FIG. 12, the symbol determination table (at the time of second starting opening winning) will be described.

  In this embodiment, the winning type (“big hit” or “loss”) of the lottery based on the jackpot determination random number value performed when the game ball is won in the second starting opening 45 and the second starting opening winning is obtained The special symbol is selected based on the symbol random number value (random number value for symbol determination). The symbol determination table (at the time of second start opening winning) is a table to be referred to when selecting the special symbol.

  As shown in FIG. 12, a symbol designation command for designating a special symbol for each determination value data indicating the winning classification of the lottery based on the random number value for big hit determination as shown in FIG. The relationship between ("zA1" and "zA3") and the symbol random number for which the symbol designation command is selected is defined.

  In addition, even when the winning classification of the lottery based on the jackpot determination random number value is "loss" (loss determination value data), the symbol designation command to be selected is one type (zA3), and the symbol designation command (be sure to be selected) zA3) is determined.

  On the other hand, when the winning classification of the lottery based on the big hit judgment random number value is "big hit" (big hit judgment value data), as shown in FIG. 12, there are a plurality of types of special symbols to be selected, and "big hit" A plurality of kinds ("z0" and "z4") of symbol designation commands (big hit selection symbol command in FIG. 12) are also prepared. At the time of “big hit”, the big hit selection symbol command to be determined also changes according to the acquired symbol random number value. For example, when the symbol random number value acquired at the time of "big hit" is any of "29" to "99", the big hit selection symbol command "z4" is selected, and the selection rate is 80/100 Become.

[Big hit type decision table]
Next, the jackpot type determination table will be described with reference to FIGS. In the present embodiment, when the big hit time selection symbol command (any of “z0” to “z4”) is determined with reference to the symbol determination table (see FIGS. 11 and 12), the determined big hit time selection is performed. Based on the symbol command, the type of "big hit" (content of the big hit game) is determined. The jackpot type determination table is a table that is referred to when determining the type of “hit” (the contents of the jackpot game) based on the jackpot selection symbol command.

  Further, in the present embodiment, a big hit type determination table is provided for each gaming state at the time of the “big hit” winning. FIG. 13 is a big hit type determination table (part 1) to be referred to when the “big hit” is won when the gaming state is “no low probability time short”, and FIG. 14 is the “low probability time short” It is a jackpot type determination table (part 2) to be referred to when the "big hit" is won when "yes". FIG. 15 is a big hit type determination table (part 3) that is referred to when “big hit” is won when the gaming state is “no high accuracy time,” and FIG. This is a big hit type determination table (part 4) that is referred to when “big hit” is won when “there is a short time”.

  In each big hit type determination table, the relationship between a big hit time selection symbol command ("z0" to "z4") and various parameters for determining the type of "big hit" is defined. As various parameters for determining the type of "big hit" (content of the big hit game), the value of the time reduction flag, the number of time reductions, the value of the probability change flag, and the number of rounds in the big hit game are defined.

  For example, in the case of winning the "big hit" in the "high probability time low" state, and when "z1" is determined as the big hit time selection symbol command, as shown in FIG. As various parameters for determining the content of the jackpot game, a time saving flag “1”, a time saving count “100”, a probability change flag “0”, and a round number “10” are set.

  The “number of rounds” defined in each jackpot type determination table is the number of rounds in which the opening time of the big prize opening is relatively long in the jackpot game. The "time saving flag" is one of the management flags stored in the main RAM 73, and is a flag for managing whether or not the gaming state is the "time saving gaming state". When the gaming state is “time saving gaming state”, the time saving flag is “1 (ON)”. In addition, "time reduction number" is the number of times of variation display of the special symbol given in "time reduction gaming state".

[Prize presentation information decision table]
Next, with reference to FIG. 17, the winning effect information determination table will be described.

  In the present embodiment, the main control circuit 70 (main CPU 71) selects the winning type ("big hit", "small hit" or "lost") determined at the time of winning (when starting opening) and symbol designation command or big hit. Based on the time selection symbol command, the sub control circuit 200 determines information to be used when determining the content of the effect. For example, in the sub-control circuit 200, information used when determining the contents relating to the color change effect of the holding symbol indicating the reserved ball of the special symbol, the contents relating to the pre-reading effect, and the like is determined. The winning effect information determination table is referred to when determining the outline of the effect contents executed by the sub control circuit 200 based on the information acquired by the main control circuit 70 at the time of winning (at the start opening winning). It is a table.

  In the winning effect information determination table, “winning effect information 1” and “winning effect information 1” indicating the combination of various types of information determined at the time of winning (at the start opening winning time) and the effect contents executed by the sub-control circuit 200 are displayed. The relationship with “winning effect information 2” is defined. In this embodiment, the type of starting opening, the type of determination value data, the type of big hit selection symbol command, and the type of symbol designation command are various types of information determined at the time of winning (at starting opening). It is defined in the hour performance information determination table.

  In the sub-control circuit 200, the effect data 1 for winning (“1A” to “1D”) defined in the effect information determining table for winning is mainly a color change effect of a holding symbol indicating a holding ball of a special symbol. It is the production information used when determining the content regarding. When the sub control circuit 200 receives the prize effect information 1 determined based on the prize effect information determination table, the sub control circuit 200 changes the effect of the color change effect of the holding symbol included in the category of the prize effect information 1. One production pattern is selected from a plurality of types of production patterns.

  In addition, the prize effect information 2 ("2A" to "2D") specified in the prize effect information determination table is a pre-reading effect (pre-reading continuous on the basis of the holding ball of the special symbol in the sub control circuit 200) This is the production information used when determining the content related to the production. When the sub control circuit 200 receives the prize effect information 2 determined on the basis of the prize effect information determination table, the sub control circuit 200 generates a plurality of types of pre-read effects included in the category of the prize effect information 2. One production pattern is selected from the patterns.

  When the winning effect information determination table of this embodiment is referred to, for example, when “big hit” is won at the time of the first starting opening winning, “1A” as winning effect information 1 regardless of the type of big hit selection symbol command Is determined, and "2A" is determined as effect information 2 at the time of winning.

[Variation production pattern determination table]
Next, the variation effect pattern determination table will be described with reference to FIG.

  In the present embodiment, the main control circuit 70 (main CPU 71) selects a win type ("big hit", "small hit" or "lost"), a symbol designation command, a big hit selection symbol command, when the variation display of the special symbol starts. Based on the information such as the change time, the change effect pattern of the special symbol is determined. The variation presentation pattern determination table is a table referred to when determining the variation presentation pattern of this special symbol.

  In addition, the change effect pattern (information included in the special symbol effect start command described later) determined based on the change effect pattern determination table is transmitted from the main control circuit 70 to the sub control circuit 200 (host control circuit 210) . When the sub control circuit 200 receives the information on the change effect pattern, the sub control circuit 200 determines the type of effect based on the received information such as the change effect pattern and the game state.

  As shown in FIG. 18, in the fluctuation effect pattern determination table, the combination of the symbol designating command determined at the time of winning (starting opening winning), the combination of the big hit selection symbol command and the variation time of the special symbol, and the variation display of the special symbol A relationship with the type of effect (variation effect pattern) executed by the sub control circuit 200 is defined therein.

  In the present embodiment, the variation effect pattern is represented by a two-digit number, and the “upper” (first digit) parameter and the “lower” (second digit) parameter described in the variation effect pattern column in FIG. It is expressed in combination with parameters. For example, when the symbol designating command determined at the time of winning (when starting opening winning) is “zA1”, the big hit selection symbol command is “z0”, and the variation time of the special symbol is “15000 msec”. The parameter is “C1” (a combination of the upper “C” and the lower “1”).

  In addition, in this embodiment, the information of a fluctuation production parameter is contained in the below-mentioned special symbol production start command. At this time, the “upper” parameter and the “lower” parameter defined in the variation effect pattern column are stored in different parameter areas. Therefore, in the variation presentation pattern determination table, the “upper” parameter and the “lower” parameter of the variation presentation pattern are separately defined.

<Configuration of data table stored in sub-main ROM>
Next, the configuration of various data tables stored in the sub main ROM 205 of the sub control circuit 200 will be described with reference to FIGS.

[Change production table]
First, the variation effect table will be described with reference to FIG.

  In the pachinko gaming machine 1 according to the present embodiment, as described above, various effects are executed during the special symbol variation display under the control of the sub-control circuit 200 (host control circuit 210). The content (effect pattern) of the effect performed at this time is the change effect of the special symbol included in the special symbol effect start command (described later) transmitted from the main control circuit 70 to the sub-control circuit 200 at the start of the change display of the special symbol. It is determined based on pattern information and the like. The variation effect table is referred to when determining the effect content (effect pattern) based on information such as the variation effect pattern and the gaming state.

  In the variation effect table, as shown in FIG. 19, a combination of various information (including information on the variation effect pattern) determined at the time of winning (at the time of winning the start opening) and an effect pattern (“EN00” determined by lottery). ”To“ EN44 ”) and the contents of the effects, and the correspondence between the random values for selecting (determining) each effect pattern and the selection rate (winning probability) are defined. In the present embodiment, as the various information determined at the time of winning (when starting opening winning), the types (“A0” to “A4”, “B1” to “B3” and “C1”) of the variation effect pattern of the special symbol "-" CF "), variation time of special symbol, winning classification (" big hit "," small hit "or" loss "), symbol designation command and big hit selection symbol command are defined in the variation effect table.

  In this embodiment, it is assumed that the fluctuation time of the special symbol specified in the fluctuation presentation table is substantially the same as the presentation time of the corresponding presentation pattern. In addition, the random number values specified in the fluctuation presentation table are random number values acquired in the process of S319 (sub-lottery process) during the command analysis process shown in FIG. 83 described later, and “0” to “999” ( 1000 types).

  When determining an effect pattern with reference to the change effect table of the present embodiment, for example, when the change pattern of the special symbol determined at the start of the special symbol change display is “C1” and selecting the effect pattern When the random number value acquired in step S is any one of “0” to “499”, “EN 15” is selected as the effect pattern. In this case, an effect called "normal reach effect A" is performed in the variable symbol display period (15000 msec) of the special symbol. And with the completion | finish of "normal reach production A", the display of a "big hit" aspect is performed on the display area 13a of the display apparatus 13, and a special symbol changes and stops.

[Hold effect table]
Next, the hold effect table will be described with reference to FIG.

  In the pachinko gaming machine 1 of the present embodiment, various effects relating to the color change of the holding symbol indicating the holding ball of the special symbol are executed under the control of the sub-control circuit 200 (host control circuit 210). The content (effect pattern) of the color change effect of the holding symbol performed at this time is a prize included in a holding addition command to be described later transmitted from the main control circuit 70 to the sub control circuit 200 at the start of the special symbol variation display. It is determined based on hour performance information 1 ("1A" to "1D"). The on-hold effect table is referred to when the content (effect pattern) of the color change effect on the on-hold symbol is determined based on the information such as the effect information 1 at the time of winning.

  On the hold effect table, as shown in FIG. 20, a combination of various information (including winning effect information 1) determined at the time of winning (when starting opening), and the color of the symbol for holding determined by lottery A correspondence relationship between effect patterns (“HE00” to “HE19”) and effect contents of the change effect, random number values for selecting (determining) each effect pattern, and a selection rate (wining probability) is defined. In the present embodiment, as various information determined at the time of winning (when starting opening), information at the time of winning 1 (“1A” to “1D”), winning type (“big hit”, “small hit” or "Loss"), a symbol designation command and a jackpot selection symbol command are defined in the hold effect table. Further, the random number values defined in the hold effect table are random number values acquired in the process of S319 (sub-lottery process) in the command analysis process shown in FIG. 83 described later, and “0” to “999” ( 1000 types).

  When determining the effect pattern of the color change effect of the symbol for suspension with reference to the suspension effect table of this embodiment, for example, the effect information 1 at the time of winning determined at the start of the variation display of the special symbol is "1A", If the jackpot selection symbol command is “z0” and the random number value acquired when selecting the effect pattern is any of “0” to “499”, the color of the symbol for holding “HE00” is selected as the effect pattern of the change effect. In this case, an effect referred to as “holding effect A” is performed as the color change effect of the reserved symbol.

[Pre-reading effect table]
Next, the prefetch effect table will be described with reference to FIG.

  In the pachinko gaming machine 1 of the present embodiment, when the variable display of the special symbol is suspended, the sub control circuit 200 (host control circuit 210) displays the content of the variable display of the suspended special symbol (holding ball Depending on the content, a predetermined pre-reading effect is performed. The contents (effect pattern) of the pre-reading effect performed at this time are the winning effect information 2 (included in a hold addition command, which will be described later) transmitted from the main control circuit 70 to the sub-control circuit 200 at the start of variable symbol display. “2A” to “2D”) and the like. The look-ahead effect table is referred to when the contents of the look-ahead effect (render pattern) are determined based on information such as the effect information 2 at the time of winning.

  As shown in FIG. 21, the pre-read effect table has a combination of various information (including in-time effect information 2) determined at the time of winning (when starting opening) and an effect pattern of pre-selected effect determined by lottery. A correspondence relationship between (“SE00” to “SE19”) and the contents of effects, random number values for selecting (determining) each effect pattern, and selection rate (wining probability) is defined. In the present embodiment, as various information determined at the time of winning (when starting opening), information at the time of winning 2 ("2A"-"2D"), winning classification ("big hit", "small hit" or "Loss"), a symbol designation command and a jackpot selection symbol command are defined in the prefetch effect table. The random number values specified in the pre-reading effect table are random number values acquired in the process of S319 (sub-lottery process) during the command analysis process shown in FIG. 83 described later, and “0” to “999” ( 1000 types).

  When determining the effect pattern of the pre-reading effect with reference to the pre-reading effect table of this embodiment, for example, the effect information 2 at the time of winning determined at the start of the variation display of the special symbol is "2A", and the big hit selection symbol command Is “z0”, and when the random number value acquired when selecting the effect pattern is any value of “0” to “499”, “SE00” is the effect pattern of the pre-reading effect It is selected. In this case, as pre-reading effect, an effect called “pre-reading effect A” is performed.

<Configuration of various commands>
Here, configurations of various commands transmitted from the main control circuit 70 to the sub control circuit 200 will be described. In the present embodiment, the main control circuit 70 also serves as means (command transmission means, game information transmission means) for generating a command including information relating to the progress of the game and transmitting the command data to the sub-control circuit 200. .

[Basic configuration]
First, the basic structure of a command will be described with reference to FIG. FIG. 22 is a diagram showing a basic configuration (basic format) of command data.

  In the present embodiment, the command transmitted from the main control circuit 70 to the sub control circuit 200 is composed of a command type section in which command type information is stored, and a parameter field section in which various information relating to games and effects are stored. Be done. In the present embodiment, the information of the parameter field section is analyzed by command analysis processing described later executed in the sub control circuit 200, and various types of information regarding the game and the effect are acquired.

  The command type part is provided at the head part of the command and is composed of 8 bits (1 byte: fixed length). On the other hand, in the parameter field section, information on game and effect is defined in bit units, and the bit length (length) of the parameter field section changes according to the command type.

  In this embodiment, since the command transmission / reception operation is repeatedly performed in units of 8 bits, the parameter field part is also managed in units of 8 bits. Here, the area in units of 8 bits is referred to as a “parameter”. Also, the names of the parameters arranged in the parameter field part are referred to as “first parameter”, “second parameter”, “third parameter”,... From the head side of the command (command type part side).

  Below, as an example of the command, the configuration of the demo display command, special symbol effect start command, power interruption return command and hold addition command, and the contents of various information included in these commands will be specifically described with reference to the drawings. explain.

[Demo display command]
First, the configuration of the demo display command and the contents of various information included in the command will be described with reference to FIG. FIG. 23 is a diagram showing a bit-by-bit configuration of the demo display command and the contents of various information stored in each bit.

  The demonstration display command is composed of a command type part and a parameter field part consisting of one parameter (first parameter). That is, the number of bytes (command length) of the whole demo display command is 2 bytes (16 bits), and the number of bytes of the parameter field portion is 1 byte (8 bits).

  The command type portion of the demo display command stores a value “80H” indicating the type of the demo display command.

  In the bit 0 (b0) to the bit 2 (b2) of the first parameter of the demonstration display command, the "state number" (one of 0 to 7) corresponding to the gaming state is stored. For example, if the value of the probability variation flag is “0” and the value of the time reduction flag is “0”, the “state number” is any one of “0” to “2” among “0” to “7”. Is set to bit 0 (b0) to bit 2 (b2). Bit 4 (b4) and bit 5 (b5) of the first parameter store the value of the time reduction flag (“0” or “1”) and the value of the probability change flag (“0” or “1”), respectively. . Also, data "0" is always stored in each of bit 3 (b3), bit 6 (b6) and bit 7 (b7) of the first parameter. In the following, a bit in which data "0" is always stored is also referred to as "always 0 area".

  In the sub-control circuit 200, when a command analysis process described later is performed on the demo display command having the above-described configuration, the game state information (game status) at the time of displaying the demo screen is acquired from the first parameter as the analysis result.

[Special symbol production start command]
Next, the configuration of the special symbol effect start command and the contents of various information included in the command will be described with reference to FIG. In addition, FIG. 24 is a figure which shows a structure of the bit unit of a special symbol presentation start command, and the content of the various information stored in each bit.

  The special symbol effect start command is composed of a command type part and a parameter field part composed of five parameters (first parameter to fifth parameter). That is, the number of bytes of the entire special symbol rendering start command is 6 bytes (48 bits), and the number of bytes of the parameter field portion is 5 bytes (40 bits).

  In the command type portion of the special symbol effect start command, a value “81H” indicating the type of the special symbol effect start command is stored.

  A "state number" (one of 0 to 7) corresponding to the game state is stored in bit 0 to bit 2 of the first parameter of the special symbol effect start command. The value ("0" or "1") of the time saving flag and the value ("0" or "1") of the probability variation flag are stored in bit 4 and bit 5 of the first parameter, respectively.

  Bit 6 of the first parameter stores information on winning / non-winning of the falling lottery (“falling lottery winning / refusal information”). In the case where the fall lottery is not won, “0” is stored in the bit 6 of the first parameter as “fall lottery success / failure information”, and in the case of the fall lottery, “fall lottery success / failure information” is 1 "is stored in bit 6 of the first parameter. Also, bit 3 and bit 7 of the first parameter are always 0 area.

  In bit 0 to bit 6 of the second parameter of the special symbol effect start command, symbol designation commands (“zA1” to “zA3”) determined by lottery using the symbol determination table (see FIGS. 11 and 12). A value corresponding to is stored. Note that bit 7 of the second parameter is always 0 area.

  In the third parameter bit 0 to bit 3 of the special symbol effect start command, the information “upper” of the change effect pattern determined by the lottery using the change effect pattern determination table (see FIG. 18) (“A” To “C”) are stored. Note that bits 4 to 7 of the third parameter are "always 0 region".

  In the bit 0 to bit 3 of the fourth parameter of the special symbol effect start command, information “lower” of the change effect pattern determined by lottery using the above-mentioned change effect pattern determination table (see FIG. 18) (“0” Values corresponding to “9” and “A” to “F” are stored. Note that bits 4 to 7 of the fourth parameter are "always 0 region".

  In addition, in bits 0 to 6 of the fifth parameter of the special symbol effect start command, a value corresponding to the remaining short time variation number is stored. Note that bit 7 of the fifth parameter is always 0 area.

  When a command analysis process described later is performed on the special symbol effect start command of the above configuration in the sub control circuit 200, the game state information (game status) at the start of the special symbol effect start is acquired from the first parameter as an analysis result. The special symbol stop symbol designation information is obtained from the second parameter, the variation effect pattern number designation information is obtained from the third parameter and the fourth parameter, and the remaining short time variation number designation information is obtained from the fifth parameter. Ru.

[Disruptive recovery command]
Next, the structure of the power interruption return command and the contents of various information included in the command will be described with reference to FIGS. In the present embodiment, the power failure recovery command is configured of a set of two commands (a first power failure recovery command and a second power failure recovery command). And FIG. 25 is a figure which shows the structure of the bit unit of a 1st power failure return command, and the content of the various information stored in each bit. FIG. 26 is a diagram showing the configuration in bit units of the second power failure recovery command and the contents of various information stored in each bit.

(1) First power failure recovery command As shown in FIG. 25, the first power failure recovery command is composed of a command type portion and a parameter field portion including three parameters (first parameter to third parameter). Ru. That is, the number of bytes of the entire first power failure recovery command is 4 bytes (32 bits), and the number of bytes of the parameter field portion is 3 bytes (24 bits).

  The command type portion of the first power failure recovery command stores a value “D1H” indicating the type of the first power failure recovery command.

  A "state number" (one of 0 to 7) corresponding to the gaming state is stored in bit 0 to bit 2 of the first parameter of the first power failure return command. The value ("0" or "1") of the time saving flag and the value ("0" or "1") of the probability variation flag are stored in bit 4 and bit 5 of the first parameter, respectively. In the bit 6 of the first parameter, “fall lottery success / failure information” is stored. Note that bit 3 and bit 7 of the first parameter are always 0 regions.

  The stop symbol specification information ("special stop symbol specification information") of the special symbol is stored in bit 0 to bit 5 of the second parameter of the first power failure return command. Further, bit 6 of the second parameter has a value (“0” or “1”) corresponding to the stop state of the first special symbol at the time of detection of power interruption (“first special stop symbol selection state”). Is stored. In addition, in the most recent special symbol variation display (the variation display executed at the time of power interruption detection and before the power interruption detection is the latest one performed), the stop symbol of the first special symbol is selected. For example, the value of the “first special symbol selection state” is “1”, and if the symbol of the first special symbol is not selected, the value of the “first special symbol selection state” is “0”. Also, bit 7 of the second parameter is always 0 area.

  "Special stop symbol designation information" is stored in bit 0 to bit 5 of the third parameter of the first power failure return command. In addition, in bit 6 of the third parameter, a value (“0” or “1”) corresponding to the selection state of the stop symbol of the second special symbol (“second special stop symbol selection state”) at the time of detecting power interruption. Is stored. In addition, in the latest special symbol variation display (the variation display executed at the time of power interruption detection and before the power interruption detection, the latest executed variation display), the stop symbol of the second special symbol is selected. For example, the value of “second special stop symbol selection state” is “1”, and if the stop symbol of the second special symbol is not selected, the value of “second special symbol selection state” is “0”. Also, bit 7 of the third parameter is always 0 area.

  In the sub-control circuit 200, when a command analysis process described later is performed on the first power failure recovery command having the above-described configuration, game state information (game status) at the time of power failure recovery is acquired from the first parameter as an analysis result. The information of the stop symbol of the first special symbol at the time of power failure recovery is acquired from the second parameter, and the information of the stop symbol of the second special symbol at the time of power failure recovery is acquired from the third parameter.

(2) Second power failure recovery command As shown in FIG. 26, the second power failure recovery command is composed of a command type portion and a parameter field portion including three parameters (first parameter to third parameter). Ru. That is, the number of bytes of the entire second power failure recovery command is 4 bytes (32 bits), and the number of bytes of the parameter field portion is 3 bytes (24 bits).

  The command type portion of the second power failure recovery command stores a value “D2H” indicating the type of the second power failure recovery command.

  A value corresponding to the number of pending variable displays of the second special symbol is stored in bit 0 to bit 2 of the first parameter of the second power failure recovery command. In bits 4 to 6 of the first parameter, a value corresponding to the number of holdings of variable display of the first special symbol is stored. Also, bit 3 and bit 7 of the first parameter are always 0 areas.

  In the case where the number of reservations is 0, “000” is stored in bit 0 to bit 2 or bits 4 to 6 of the first parameter of the second power failure recovery command, and the number of reservations is one. “001” is stored, “010” is stored when the number of holdings is two, “011” is stored when the number of holdings is three, and when the number of holdings is four, “100” is stored.

  The “internal control state number” is stored in bit 0 to bit 2 of the second parameter of the second power failure recovery command. Also, bits 3 to 7 of the second parameter are always 0 area.

  When the internal control state is the demo screen display state, “000” is stored as “internal control state number” in bits 0 to 2 of the second parameter of the second power failure recovery command, and internal control is performed. “001” is stored as “internal control state number” when the state is the special symbol variation state (the state during special symbol variation), and “010” is stored when the internal control state is the special symbol determination state. It is stored as an "internal control state number", and "011" is stored as an "internal control state number" when the internal control state is the start state per special symbol. Further, in the second parameter bit 0 to bit 2 of the second power failure recovery command, “100” is stored as the “internal control state number” when the internal control state is the big prize opening open state. When the control state is an inter-round interval state, “101” is stored as the “internal control state number”, and when the internal control state is the end state per special symbol, “110” is the “internal control state number”. Stored as

  Further, “the number of remaining short state fluctuation times” (“0” to “99”) is stored in bit 0 to bit 6 of the third parameter of the second power failure recovery command. Also, bit 7 of the third parameter is always 0 area.

  When a command analysis process described later is performed for the second power failure recovery command of the above configuration in the sub control circuit 200, the analysis result indicates that the number of pending variable displays of the special symbol at the time of power failure recovery from the first parameter. The information is acquired, the information on the internal state at the time of power failure recovery is acquired from the second parameter, and the information on the remaining number of times of short fluctuation at the time of power failure recovery is acquired from the third parameter.

[Pending addition command]
Next, the configuration of the hold addition command and the contents of various information included in the command will be described with reference to FIG. FIG. 27 is a diagram showing a bit-by-bit configuration of the pending addition command and the contents of various information stored in each bit.

  The pending addition command is composed of a command type part and a parameter field part composed of three parameters (first parameter to third parameter). That is, the total number of bytes of the pending addition command is 4 bytes (32 bits), and the number of bytes in the parameter field portion is 3 bytes (24 bits).

  The command type portion of the hold addition command stores a value “85H” indicating the type of the hold addition command.

  In bit 0 to bit 2 of the first parameter of the hold addition command, a value corresponding to the hold number of variable displays of the second special symbol is stored. In bits 4 to 6 of the first parameter, a value corresponding to the number of holdings of variable display of the first special symbol is stored. Also, bit 3 and bit 7 of the first parameter are always 0 areas.

  In the bit 0 to bit 2 of the second parameter of the hold addition command, “big hit selection symbol information” is stored. Note that "big hit selection symbol information" is information corresponding to a big hit selection symbol command ("z0" to "z4") determined by lottery using the above-mentioned symbol determination table (see FIGS. 11 and 12). is there.

  Bit 3 of the second parameter stores “Large probability big hit / fail information”. In the case of winning a "big hit" at low confidence, "1" is stored in bit 3 as "low probability when big hit success / failure information", and if winning a "lost" at low confidence, "low probability" “0” is stored in bit 3 as “time big hit success / failure information”. Further, in the bit 4 of the second parameter, “high probability big hit success / failure information” is stored. In the case of winning the “big hit” at high confidence, “1” is stored in the bit 4 as “high probability when big hit success or failure information”, and when winning “losing” at high confidence, “high probability” “0” is stored in bit 4 as “time big hit success / failure information”. These pieces of information are determined based on the result of the lottery used in the jackpot type determination table (see FIGS. 13 to 16).

  In bits 5 and 6 of the second parameter, “first winning effect information” is stored. “First winning effect information” is information corresponding to winning effect information 1 (“1A” to “1D”) determined by lottery using the winning effect information determination table (see FIG. 17). It is. For example, when the winning effect information 1 is “1A”, “00” is stored in bits 5 and 6 as the “first winning effect information”, and the winning effect information 1 is “1B”. In the case, “01” is stored in bit 5 and bit 6 as “first winning effect presentation information”. Further, for example, when the winning effect information 1 is “1C”, “10” is stored in the bits 5 and 6 as the “first winning effect information”, and the winning effect information 1 is “1D”. In this case, “11” is stored in bit 5 and bit 6 as “first winning effect presentation information”. Also, bit 7 of the second parameter is always 0 area.

  The “second prize effect information” is stored in bit 4 and bit 5 of the third parameter of the hold addition command. The “second winning effect information” is information corresponding to winning effect information 2 (“2A” to “2D”) determined by lottery using the winning effect information determination table (see FIG. 17). It is. For example, when the winning effect information 2 is “2A”, “00” is stored in bits 4 and 5 as the “second winning effect information”, and the winning effect information 2 is “2B”. In the case, “01” is stored in bit 4 and bit 5 as “second winning effect presentation information”. Further, for example, when the winning effect information 2 is “2C”, “10” is stored in the bits 4 and 5 as the “second winning effect information”, and the winning effect information 2 is “2D”. In this case, “11” is stored in bit 4 and bit 5 as “second winning effect presentation information”.

  In addition, the values of the "first prize effect information" and the "second prize effect information" are executed based on the pre-reading information (information regarding the pending before the change) at the time of the pending addition command generation (at the pending addition). It may be changed (updated) according to the number of effects (the number of pending effects for which pre-reading effects are executed).

  Bit 6 of the third parameter stores “falling lottery information”. When there is no fall, "0" is stored in the bit 6 as "fall lottery information", and when there is a fall, "1" is stored in the bit 6 as "fall lottery information". In addition, each of bit 0 to bit 3 and bit 7 of the third parameter always becomes a zero area.

  In the sub-control circuit 200, when a command analysis process to be described later is performed on the pending addition command having the above-described configuration, information on the number of suspended display of the special symbol variable display at the time of winning is acquired as the analysis result, The designated information of the hold effect is acquired from the second parameter, and the designated information of the prefetch effect is acquired from the third parameter.

[Other command]
Next, the configuration of commands other than the various commands described above and the contents of various information included in the commands will be described. In addition, illustration of the structure of other various commands is abbreviate | omitted, and only the structure of the parameter field part in each command and the outline | summary of the various information contained in this command are demonstrated.

(1) Special Effect Stop Command The parameter field portion of the special effect stop command is composed of two parameters (a first parameter and a second parameter).

  As a first parameter of the special effect stop command, for example, gaming state information (game status) such as a falling lottery, a probability change flag, a time saving flag, and a state number is stored. Moreover, the information of the stop symbol of a special symbol is stored in a 2nd parameter.

  In the sub-control circuit 200, when a command analysis process to be described later is performed on the special effect stop command having the above-described configuration, as the analysis result, when the effect at the time of special symbol variation display from the first parameter and the second parameter is ended. The various game information is acquired.

(2) Special symbol start display command The parameter field part of the special symbol start display command is composed of two parameters (first parameter and second parameter).

  The first parameter of the special symbol start display command stores, for example, game state information (game status) such as a state number. Moreover, the information of the stop symbol of a special symbol is stored in a 2nd parameter.

  In the sub-control circuit 200, when a command analysis process to be described later is performed on the special symbol start display command having the above-described configuration, the analysis result includes information on the special symbol hit state (for example, from the first parameter and the second parameter). Information such as whether or not the jackpot is in progress, or whether or not the small hit is in progress is acquired.

(3) Large winning opening open display command The parameter field portion of the large winning opening open display command is configured of three parameters (first to third parameters).

  For example, game state information (game status) such as a state number is stored in the first parameter of the display command for opening the big winning opening. The second parameter stores information on a special symbol stop symbol. Also, information on the number of rounds (“0” to “15”) is stored in the third parameter.

  In the sub-control circuit 200, when a command analysis process described later is performed on the display command for opening the special winning opening having the above-described configuration, information on a special symbol hit state is acquired from the first parameter and the second parameter as an analysis result. Then, information on the number of rounds is acquired from the third parameter.

(4) Inter-Round Display Command The parameter field portion of the inter-round display command is composed of three parameters (first to third parameters).

  For example, game state information (game status) such as a state number is stored in the first parameter of the inter-round display command. The second parameter stores information on a special symbol stop symbol. In addition, information on the number of rounds (“0” to “14”) is stored in the third parameter.

  In the sub-control circuit 200, when a command analysis process to be described later is performed on the inter-round display command having the above-described configuration, the information about the special symbol hit state is acquired from the first parameter and the second parameter as the analysis result. Information on the number of rounds is acquired from the three parameters.

(5) Special symbol end display command The parameter field portion of the special symbol end display command is composed of two parameters (a first parameter and a second parameter).

  For example, game status information (game status) such as a status number is stored in the first parameter of the special symbol end display command. Moreover, the information of the stop symbol of a special symbol is stored in a 2nd parameter.

  In the sub control circuit 200, when the command analysis processing described later is performed on the display command per special symbol per configuration described above, information on the hit state of the special symbol is acquired from the first parameter and the second parameter as an analysis result. Ru.

(6) Hold Subtraction Command The parameter field part of the hold subtraction command is composed of three parameters (first parameter to third parameter).

  For example, game state information (game status) such as a fall lottery, a probability change flag, a time saving flag, and a state number is stored in the first parameter of the hold subtraction command. The second parameter stores information on the number of pending variable displays of special symbols. The third parameter stores information on the number of remaining short games.

  In the sub-control circuit 200, when a command analysis process described later is performed on the pending subtraction command having the above-described configuration, the game state information at the start of the change is acquired from the first parameter as the analysis result, and the change is performed from the second parameter. Information on the number of pending pieces at the start is acquired, and information on the number of remaining short game times is acquired from the third parameter.

(7) Winning Information Command The parameter field portion of the winning information command is composed of one parameter (first parameter).

  For example, winning detection information such as detection results of the count sensors 53c and 54c is stored in the first parameter of the winning information command.

  When a command analysis process described later is performed on the winning information command of the above configuration in the sub control circuit 200, winning detection information of the special winning opening is acquired from the first parameter as an analysis result.

(8) Fraud detection related command The parameter field part of the fraud detection related command includes two parameters (a first parameter and a second parameter).

  The first parameter of the fraud detection related command includes, for example, door open detection (open / close not detected, closed detection, open detection), first prize winning fraud detection, second prize winning fraud detection, ordinary electric Stores information such as detection of illegal winnings of a prize. Further, information such as, for example, induced magnetic field detection, magnetic detection, and sensor abnormality detection is stored in the second parameter.

  In the sub control circuit 200, when a command analysis process described later is performed on the fraud detection related command of the above configuration, fraud detection information is acquired from the first parameter and the second parameter as an analysis result.

(9) Dispensing abnormality related command The parameter field part of the dispensing abnormality related command is configured of one parameter (first parameter).

  The first parameter of the payout abnormality-related command stores, for example, information such as payout error information and lower pan full information.

  In the sub control circuit 200, when the command analysis processing described later is performed on the payout abnormality related command of the above configuration, the payout abnormality information is acquired from the first parameter as an analysis result.

(10) Initialization Command The parameter field portion of the initialization command is configured of one parameter (first parameter).

  In the first parameter of the initialization command, for example, information on an initialization factor at the time of power-on such as checksum abnormality, power failure recovery when power failure is not detected, or backup clear is pressed is stored.

  When command analysis processing described later is performed on the initialization command of the above configuration in the sub control circuit 200, designation information of initialization factor is acquired from the first parameter as an analysis result.

<Overview of command reception processing and command analysis processing>
Next, an outline of command reception processing and command analysis processing performed when the host control circuit 210 receives the above-described various commands will be described with reference to FIG. FIG. 28 is a diagram showing an overview of command reception processing in this embodiment. The command reception process is performed as a reception interrupt process in a main-sub command control process (see FIG. 72 described later) to be described later which is executed by the host control circuit 210.

  In the present embodiment, as shown in FIG. 28, when the above-described command is transmitted from the main control circuit 70 (main CPU 71) to the host control circuit 210 and the host control circuit 210 receives the command, first, the host control circuit 210 is received. , Writes the data of the received command into a ring buffer provided in the host control circuit 210. If an error occurs during command reception, the set information of the received command data and error information is written to the ring buffer.

  Here, FIG. 29 shows a schematic configuration of the ring buffer. In the present embodiment, the ring buffer is composed of a buffer area for storing received command data and a buffer area for storing corresponding error information. The size of each buffer area is 2048 bytes, and addresses (“0” to “2047”) are assigned to each 1-byte storage area.

  In the buffer area for storing command data, command data is stored for each storage area of 1 byte, and command data is stored from the area of the head address of the buffer area in the order of command reception. Also in the buffer area for storing error information, error information is stored for each storage area of 1 byte, and is stored in order of command reception from the top address side of the buffer area. At this time, the error information is stored in the storage area of the error information address associated one-to-one with the address of the corresponding command data storage area.

  When command data is received after the command data is stored at the last address “2047” of the ring buffer, the command data is stored in the storage area of the top address “0” of the ring buffer.

  Next, after the command data is stored in the above-described ring buffer, the host control circuit 210 transfers the command data stored in the ring buffer to the sub work RAM 210a and stores it.

  Then, the host control circuit 210 analyzes the contents of the command stored in the sub work RAM 210 a to acquire various information. Specifically, the host control circuit 210 determines the command type based on the information stored in the command type part of the command, and acquires various information relating to the game and the effect stored in the parameter field part of the command.

  When the above-described command analysis processing is performed, the following effects can be obtained based on the structural features of the command.

  As described above, among commands such as the demo display command, special symbol effect start command, first power interruption return command, special effect stop command, special symbol start display command, etc. Game status information (game state information) is stored in the first parameter arranged at the head (second byte from the head of the command). Therefore, when these commands are received and the command analysis processing is performed for each byte, the command analysis processing in the second byte from the start of command reception is always the game status regardless of the command type. Since the analysis process is performed, the analysis process of the second byte can be standardized in the analysis process of these commands. That is, when command analysis processing is performed on these commands, the timing of analysis processing of the game status based on the start time of the command analysis processing becomes the same regardless of which command, and Analysis processing can also be standardized. In this case, the efficiency of command analysis processing in the host control circuit 210 can be improved, and more advanced presentation control can be performed.

  Further, in the command analysis processing for the command having the above configuration, the check of the always 0 area provided in the predetermined bit area in each parameter, the check of the effective range of each data stored in the parameter, and the stored data By checking the combination of, it is possible to determine the presence or absence of the validity of the command. In this case, since the number of check items in the determination process increases, the presence or absence of the validity of the received command can be determined more accurately, and a safer game can be provided to the player.

<Animation request construction method>
In the pachinko gaming machine 1 of the present embodiment, the host control circuit 210 in the sub control circuit 200 controls various operations of effects using the display device 13 based on various commands received from the main control circuit 70. A process (hereinafter referred to as animation request construction process) of generating a command signal (request) for operating the rendering device (including the display device 13) is performed.

[Overview of animation request construction process]
First, the outline of the animation request construction process will be described with reference to FIG. FIG. 30 is a diagram showing an outline of the operation when an animation request is constructed.

  When the host control circuit 210 receives various commands from the main control circuit 70, as shown in FIG. 30, first, based on the received command, an object for generating a request called animation request including designation information of effect contents (Hereinafter referred to as an animation object).

  Note that “object” (processing information) in the present specification is a concept that abstracts the target of a procedure of a program in a broad sense, and in the present embodiment, is a set of one or more types of processing. Specifically, the “object” in the present embodiment is a set of commands for calling a process (specifying a name serving as an execution trigger, a call, an execution start process), and a structure has one or more variables. Register the call ID (such as the name for specifying the process) of the process to be included and executed for each variable. Then, in the "object", the processing registered in each variable is executed by executing such a structure. In addition, since the “object” is the name of the structure, the ID that can specify the structure, or the structure itself, the “object” is not limited to the structure, but by grouping one or a plurality of processes. It is a meaning that includes a name, an ID, a process, storage information, and the like that can manage the execution order of the process.

  In recent years, software construction is managed in object units, and software is constructed by combining a plurality of objects. In this case, when using an object that already exists, it is not necessary to know the details of its internal configuration and operation principle, and the function of the object is activated if a message (identification command, arguments, etc.) is sent to the object from the outside. Can be made to.

  The host control circuit 210 then generates an animation request based on the animation object (using the animation object). Then, the host control circuit 210 also generates various requests (reproduction start request) such as a drawing request, a sound request, a lamp request, and a feature request based on the generated animation request.

  Thereafter, the host control circuit 210 outputs the generated requests to the control circuit (controller) of the corresponding rendering device. Specifically, the host control circuit 210 outputs the sound request and the lamp request to the voice / LED control circuit 220, and outputs the drawing request to the display control circuit 230. Although not shown in FIG. 30, the accessory request generated by the host control circuit 210 is passed between the processes related to accessory control performed in the host control circuit 210.

  Then, the audio / LED control circuit 220 controls the audio reproduction operation by the speaker 11 based on the input sound request. Further, the voice / LED control circuit 220 controls a light emission effect (LED animation) operation by the lamp (LED) group 18 based on the input lamp request. The display control circuit 230 controls the image display effect operation by the display device 13 based on the input drawing request. Also, the host control circuit 210 controls the rendering operation by the accessory 20 based on the generated accessory request.

[Type of animation object]
Here, various animation objects generated (used) in the animation request construction process will be described. In the animation request construction process of the present embodiment, basically, an animation object called an effect object and an animation object called a holding object are generated, and an animation request is generated using these two animation objects.

  The effect object is an animation object generated according to the received command. For example, an animation object (object name "Demo", identification command "80H": hereinafter referred to as "demo object") generated when a demo display command is received, or an animation object (object name "Hendo Tz 01) generated when a special symbol presentation start command is received. ", Identification command" 81H ": hereinafter referred to as a variable object), and the like are examples of effect objects.

  Note that after the lottery process, only one effect object described above is generated as a second-come-first priority basis for each command reception. That is, a plurality of effect objects described above are not generated simultaneously, and the effect object is overwritten each time a command is received. It should be noted that since the reception command is called one by one, when the object is generated based on the arrival command after arrival while the objects are generated on a first-come-first-served basis, the object is generated based on the arrival command after arrival. The generated object overwrites the object generated based on the first received command. Therefore, it is referred to herein as “late arrival priority”. In the present embodiment, when an object is generated based on a late arrival reception command, the object generated based on the first arrival reception command may be discarded.

  The hold object (object name “Horyu”) is an animation object generated at the time of activation. In the hold object, processing for displaying the current hold state on the screen is performed. In addition, a pending object is basically an object (one of resident objects) that is not destroyed during startup. However, when a simple mode object described later is generated, the suspended object is also discarded.

  Further, in the present embodiment, in addition to the above animation objects, for example, an animation object with an object name “SimpleMode” (hereinafter referred to as a simple mode object), an animation object with an object name “InitAnm”, etc. are generated in the animation request construction process. Be used (used). The simple mode object will be described in detail later.

  The animation object with the object name “InitAnm” is a command generated in the sub-board 202 at the time of start-up or when an RTC (Real Time Clock) error occurs (for example, a time setting screen call command, a time change is executed on the time setting screen) And the time setting screen display process. When the host control circuit 210 receives a command from the main control circuit 70 and another effect object is generated, the animation object with the object name “InitAnm” is discarded.

[Various processing performed on animation object]
Next, an outline of various processes performed in the animation object described above will be described. The animation object basically includes an initialization process, a main process, and an end process. Further, in the effect object generated in response to the reception command, the command reception process is further included in the animation object. Then, depending on the game situation, a predetermined process is called and executed from among these various processes included in the animation object.

  The initialization process is a process executed only once at the start of object generation. In the initialization processing, for example, processing such as initialization of an object and acquisition of a lottery result is performed. The main process is a process that is executed every frame (in a frame per second (FPS) cycle) during object generation. In the main process, processing such as generation and setting of an animation request is performed. When object generation is started, initialization processing and main processing are executed in the same frame. The termination process is a process that is executed only once when the object is discarded. In the end processing, processing such as the end of reproduction of unnecessary effects is performed. Also, command reception logic is processing that is executed only once when a command is received. This command reception process is used, for example, when performing animation control based on a hold addition command or a hold subtraction command.

  Here, an example of the flow of the animation request construction process using the animation object described above will be described with reference to FIGS. 31 and 32. FIG. 31 is a diagram showing a process flow of an animation object during an animation request construction process performed when a demonstration display command is received. Further, FIG. 32 is a diagram showing a processing flow of an animation object in the animation request construction processing which is performed when the special symbol rendering start command is received after the demonstration display command. 31 and 32, in order to simplify the description, main-sub command control processing, command analysis processing, and animation request construction processing in the flow of main processing performed by the host control circuit 210 (see FIG. 72 described later). Shows only the flow part that performs loop processing for the number of received commands.

  In the animation request construction process at the time of receiving a demo display command, a demo object initialization process, a demo object command reception process, a pending object command reception process, and a demo object main process are executed in this order. The demo object is generated in the initialization process of the demo object. Also, the command reception process of the demo object and the command reception process of the hold object are called and executed with the identification command “80H” as an argument. In the main process of the demo object, an animation request is generated.

  Next, when a special symbol effect start command is received after the demo display command, a demo object end process, a variable object initialization process, a variable object command reception process, a pending object command reception process, and a variable object main process Are executed in this order. Note that in the demo object end process, the demo object generated at this point is discarded. In the initialization process of the variable object, a variable object is generated. The variable object command reception process and the pending object command reception process are called and executed with the identification command “81H” as an argument. In the main process of the variable object, an animation request is generated. This main process is performed until the next command is received.

  The pending object command reception process is executed regardless of the command type, but the processing content (processing result) differs depending on the number of pending objects, the game status, and the like when the pending object is executed.

Simple mode object
The simple mode object (specific processing information) is an object generated in the simple screen state, and in the simple mode object, the display process of the simple screen is performed. The simple mode object is basically when the power interruption return command (identification command “D1H”) is received, and the internal control state (the variation of the identification symbol) included in the received power interruption recovery command (see FIG. 25). It is generated only when the information on the display) is in the special symbol variation state. That is, the simple mode object is generated when a power failure occurs during the fluctuation display of the special symbol and then the power failure is restored. However, in this embodiment, since the presence / absence of the simple screen state is checked every frame, if the simple screen state occurs, a simple mode object is generated.

  In this embodiment, when a simple mode object is generated, all objects (including resident objects such as a hold object) generated at that time are terminated (discarded).

  Then, when the power failure recovery command is received (when activated), and the internal control state is the special symbol fluctuation state, the host control circuit 210 generates an animation request based on the simple mode object, Various requests described above are generated based on the animation request. In this embodiment, when the drawing request generated based on the simple mode object is output from the host control circuit 210 to the display control circuit 230, the display control circuit 230 returns to the power interruption based on the drawing request. An animation (including a moving image and a still image) for notifying of information related to is created, and the animation is displayed on the display device 13.

  Further, in the present embodiment, when a simple mode object is generated, a new object is not generated until the simple mode object ends. That is, in the simple screen state, other effect objects other than the simple mode object are not generated. Then, the simple mode object ends when a command related to fluctuation stop (a fluctuation stop command, a command indicating a big hit, etc.) is transmitted from the main control circuit 70.

  As described above, in the present embodiment, only the simple mode object is generated in the power failure recovery process executed when the internal control state is the special symbol variation state (the identification information variation display state). , Power interruption recovery can be performed quickly.

  In the present embodiment, when the simple mode object is generated, it is determined whether or not the received power interruption return command includes information indicating that the internal control state (information regarding the variation display of the identification symbol) is the special symbol variation state. Do. Therefore, in the present embodiment, the power failure recovery process can be performed in consideration of the consistency of the gaming state between before the power failure detection and after the power failure recovery.

  Furthermore, in the present embodiment, as described above, only one object is generated with late arrival priority (object is overwritten) each time the host control circuit 210 receives a command, but there is a simple mode object. When new, no new object is created. Therefore, the consistency of the object generated by the host control circuit 210 based on the received command is also ensured.

  Further, in the present embodiment, at the time of power failure recovery, information indicating that power failure recovery is in progress is notified by the display device 13 based on the animation request generated by the simple mode object. Even in the case of a gaming machine that does not have the function of playing from the middle according to the situation, it is possible to perform the power-off return without giving a sense of discomfort to the player.

  Furthermore, in the present embodiment, as described above, the termination trigger of the simple mode object is the case where a command regarding fluctuation stop is transmitted from the main control circuit 70 to the host control circuit 210. Therefore, for example, even when a power interruption is detected during a change and then the power is restored, for example, the display type 13 at the end of the simple mode object indicates that the animation type after the power interruption is a power interruption. An unnatural effect is suppressed such that an effect different from the type of animation during the change before detection is performed, or the same effect as the effect before the power failure return is performed again from the beginning. As a result, even in an abnormal state such as when power is restored, it is possible to suppress the generation of effects that give the player a sense of incongruity, and the game can proceed smoothly.

<Overview of drawing control method>
Next, an outline of a drawing process executed by the display control circuit 230 when a drawing request is output from the host control circuit 210 to the display control circuit 230 will be described with reference to FIG. FIG. 33 is a diagram showing a flow of image data (moving image data and still image data) at the time of drawing processing.

  In this embodiment, data (compressed data) of an image (moving image and / or still image) displayed on the liquid crystal screen of the display device 13 is stored in the CGROM 206 in the CGROM substrate 204. Then, when the drawing request is input to the display control circuit 230, the display control circuit 230 first reads out the compressed image data from the CGROM 206 and decodes (expands). At this time, when the moving picture compressed data is read, the moving picture compressed data is decoded by the moving picture decoder 234 in the display control circuit 230, and when the still picture compressed data is read, the inside of the display control circuit 230 is The still image decoder 235 decodes still image compressed data.

  Next, the display control circuit 230 writes the decoding result (image decompression data) of the image data in a predetermined buffer designated as the texture source. In the present embodiment, a movie buffer, a texture buffer, and a sprite buffer in the built-in VRAM 237 provided in the SDRAM 250 (external RAM) are specified as texture sources. For example, when one moving image is displayed, the expanded moving image data (decoding result) is written out to the movie buffer in the SDRAM 250. Also, for example, when displaying one still image, the expanded still image data is written out to the sprite buffer in the built-in VRAM 237.

  Next, the display control circuit 230 specifies a rendering target to which the rendering (drawing) result of the image data is written. As the rendering target, for example, a frame buffer provided in the SDRAM 250 (external RAM), a frame buffer provided in the built-in VRAM 237, or the like can be designated.

  Next, the display control circuit 230 operates the rendering engine 241 to perform rendering processing on the decoding result of the image data written to the texture source, and writes the rendering result to the rendering target. Note that in this processing, rendering processing is performed according to specification information (various pieces of information input from the 3D geometry engine 240) such as scaling or rotation of a moving image.

  Next, the display control circuit 230 displays the rendering result (display output data) written to the rendering target on the display screen of the display device 13.

  In the present embodiment, two frame buffers are prepared as rendering targets (see FIGS. 90 to 92 described later). Then, when the rendering result is written from the rendering engine 241 to the frame buffer, the frame buffer to which the rendering result is written is switched for each frame. For example, when rendering results are written to one frame buffer in a predetermined frame, rendering results are written to the other frame buffer in the next frame, and rendering results are written to one frame buffer in the next frame. That is, in the present embodiment, the process of writing rendering results to one frame buffer and the process of writing rendering results to the other frame buffer are alternately switched frame by frame and executed.

  In the rendering result writing process and display process described above, the rendering result written in one frame buffer in a predetermined frame is displayed on the display screen of the display device 13 in the next frame (one side). The function of the frame buffer is switched from the drawing function to the display function). Also, the rendering result written out to the other frame buffer in the next frame is displayed on the display screen of the display device 13 in the next frame (the function of the other frame buffer is switched from the drawing function to the display function). That is, in the present embodiment, the display processing of the rendering result in one frame buffer and the display processing of the rendering result in the other frame buffer are alternately switched and executed for each frame.

<Overview of voice reproduction control method>
Next, when the sound request is output from the host control circuit 210 to the audio / LED control circuit 220, an outline of the audio reproduction process executed by the audio / LED control circuit 220 will be described with reference to FIG. FIG. 34 is a diagram showing an operation outline of the audio / LED control circuit 220 at the time of audio reproduction processing.

  In the present embodiment, sound data to be output to the speaker 11 is stored in the CGROM 206. Then, when a sound request is input to the voice / LED control circuit 220, the voice / LED control circuit 220 specifies an access number based on the sound request, and reads out access data associated with the access number from the CGROM 206.

  In the present embodiment, the sound request includes not only the access number but also various sequence playback control commands (for example, start, stop, loop, etc. of audio playback) necessary for the audio playback processing generated in the sub-board 202. Command).

  Then, the voice / LED control circuit 220 performs voice reproduction processing based on the read access data. At this time, in the present embodiment, the reproduction control of the sound is performed by the simple access control. Here, “simple access control” refers to a plurality of command register trains registered in the CGROM 206 (external ROM) by the voice / LED control circuit 220 based on the sound request transmitted from the host control circuit 210. It is a control method to be set collectively. Further, the number of simple access controls that can be executed simultaneously by the voice / LED control circuit 220 depends on the number of execution systems (four in the present embodiment).

  FIG. 35 shows a schematic configuration of access data. As shown in FIG. 35, the access data includes a plurality of set information of setting data and addresses arranged in a predetermined order. A simple access end code (code indicating the end of audio reproduction) is placed at the end of the access data. ) Is stored. As shown in FIG. 34, when a plurality of access data are associated with one access number, a simple access end code is provided only for the last access data.

  When setting data is set to a corresponding address for access data having such a configuration, a reproduction code corresponding to the setting data is executed, and audio reproduction is performed. Then, this playback code execution process is sequentially performed from the setting data on the head side in the access data to the end, and when the simple access end code is finally set, the audio playback operation based on the read access data is completed. Do.

<Various drive control methods for lamps (LEDs)>
Next, when a lamp request is output from the host control circuit 210 to the sound / LED control circuit 220, the contents of various drive control processes of the plurality of LEDs included in the lamp group 18 executed by the sound / LED control circuit 220 Will be explained. In the lamp control method of the present embodiment described below, an LED is described as an example of a light emitting element, but the present invention is not limited to this, and the present embodiment is applicable to any other light emitting element. The lamp control method can be similarly applied.

[Overview of LED Control]
First, with reference to FIG. 36, an outline of a control method when driving (turning on / off) an LED provided in the pachinko gaming machine 1 will be described. FIG. 36 is a signal flow diagram at the time of LED driving (lighting on / off).

  When the LED is driven (turned on / off), first, a lamp request (LED control request) is output from the host control circuit 210 in the sub control circuit 200 to the voice / LED control circuit 220. In the present embodiment, the effect control process (sub control main process shown in FIG. 72 described later) of the host control circuit 210 is performed in a predetermined FPS cycle (for example, about 16.7 msec, about 33.3 msec, etc.) Therefore, the transmission process of the lamp request to the voice / LED control circuit 220 is also performed in a predetermined FPS cycle.

  Next, when a lamp request is input to the audio / LED control circuit 220, the audio / LED control circuit 220 sets LED data (drive data) for setting the lighting pattern (LED animation) of the LED based on the lamp request. ) Are sent to each of the LED drivers 280 (light emission drive means, effect drive means) in the lamp group 18. At this time, transmission of LED data from the audio / LED control circuit 220 to the LED driver 280 is performed by the SPI communication method. Further, transmission processing of LED data from the audio / LED control circuit 220 to the LED driver 280 is performed in a cycle of about 4 msec.

  Then, the LED driver 280 turns on / off the connected LED 281 (light emitting means) in a predetermined pattern based on the received LED data. As a result, an effect operation based on LED animation is executed.

  In addition, the light emission aspect based on LED data is controlled from the signal (control signal) transmitted based on LED data which can be controlled from the light emission aspect transmitted from the LED driver 280 to the LED 281. Specifically, according to the electrical waveform parameters (voltage value, current value, duty ratio of pulse width, etc.) of the signal transmitted from the LED driver 280 to the LED 281, light emission modes such as lighting, extinguishing, blinking, and luminance of the LED 281 Is controlled.

  Further, in the present embodiment, an example has been described in which a signal generated based on LED data is used as a “control signal based on drive data” for driving the LED 281, but the present invention is not limited to this. The “control signal based on drive data” when driving the LED 281 may be a transfer mode of LED data (drive data) or data generated based on the LED data. Here, "data generated based on LED data" includes a signal, command, and voltage change, and in this case, the control means that has received the LED data drives the other control means. A control signal based on data or drive data is transmitted.

[Voice / LED control circuit and connection configuration between LEDs]
Next, the connection configuration between the audio / LED control circuit 220 and each LED 281 will be described with reference to FIG. FIG. 37 is a schematic connection configuration diagram between the voice / LED control circuit 220 and the LED 281.

  In the present embodiment, as shown in FIG. 37, the audio / LED control circuit 220 uses a physical system 0 (SPI channel 0) and a physical system 1 (SPI channel 1) as LED data output systems (SPI channels). use. A plurality of LED drivers (devices) 280 are connected in parallel to each physical system via an SPI bus. In the example shown in FIG. 37, sixteen LED drivers 280 (device 0 to device 15) are connected in parallel to each physical system.

  Each LED driver 280 is provided with a plurality of output ports (hereinafter simply referred to as "ports") in which LED data are set, and one LED 281 is connected to each port (connection unit). That is, in this embodiment, the LED 281 is an LED 281 that is statically controlled. In the present specification, the statically controlled LED 281 is referred to as a static LED 281.

  In the example shown in FIG. 37, each LED driver 280 (each device) is provided with 16 ports (port 0 to port 15). That is, 16 LEDs 281 are connected to each LED driver 280 (each device). In the present embodiment, sixteen LEDs 281 are connected to each LED driver 280, but the present invention is not limited to this, and each LED driver may be selected according to the function and specification of the LED driver 280 (device). Eight, thirty-two, sixty-four, etc. LEDs 281 may be connected to 280.

  In the pachinko gaming machine 1 configured as shown in FIG. 37, at startup, the voice / LED control circuit 220 sets various parameters related to the connection configuration of the LED 281 for each SPI channel. Specifically, the audio / LED control circuit 220 starts the operation using the number of devices used in each SPI (the number of LED drivers 280 connected to each SPI channel), the start port of the LED 281, the end port of the LED 281, and the LED driver A start address of 280 is set. For example, in the example shown in FIG. 37, “16” is set as the number of used devices of SPI, “0” as the start port, “15” as the end port, and “0” as the start address. The start address of the LED driver 280 is not limited to “0” because it is appropriately set for each SPI channel.

  When various parameters related to the connection configuration of the LED 281 are set as described above, for example, the address of the LED 281 connected to the port 15 of the device 15 (LED driver) connected to the SPI channel 0 in FIG. , Device number = 15 and port number = 15.

  Here, the connection configuration between the audio / LED control circuit 220 and the LED driver 280 will be described in more detail with reference to FIG. FIG. 38 is a connection configuration diagram between the audio / LED control circuit 220 and the LED driver 280.

  Since the voice / LED control circuit 220 and the LED driver 280 are connected by the SPI bus (signal wiring means) as described above, the signal lines (SCL) of serial clock (SCL) are connected in each physical system (SPI channel). Timing signal lines) and signal lines (data signal lines) for serial data (SDO, SDI) are provided separately. And in each physical system (SPI channel) of the audio / LED control circuit 220 (master), the output terminal (SCL_P *, SCL_N *: “*” of serial clock signal (timing signal) of the audio / LED control circuit 220 is 1 or 2) are connected to the serial clock signal input terminals (SCL_P, SCL_N) of each LED driver 280 (slave). Also, the output terminals (SDO_P *, SDO_N *) of the serial data (transmission data including drive data) of the audio / LED control circuit 220 are connected to the serial data input terminals (SDI_P, SDI_N) of each LED driver 280 Be done.

  In the present embodiment, basically, the voice / LED control circuit 220 (master) continues to transmit data between the voice / LED control circuit 220 and the LED driver 280, and each LED driver 280 (slave) is sent. Received data unilaterally. At this time, each LED driver 280 detects the rising edge of the serial data and starts input of the serial data to the internal shift register.

[Serial data configuration]
FIG. 39 shows the configuration (format) of serial data transmitted from the sound / LED control circuit 220 to the LED driver 280.

  In this embodiment, as shown in FIG. 39, “1” (specific data) is continuously stored in the area of 16 bits or more at the beginning of the serial data. Therefore, when the LED driver 280 detects reception of “1” continuously 16 times or more, the state of the LED driver 280 is in a state of waiting for input of serial data.

  After the 16-bit or more “1” storage area (first data section) in the serial data, the storage area of the device address (the address of the LED driver 280) and the storage area of the register address are arranged in this order . The storage area (second data portion) of the device address (output destination information) and the storage area of the register address are each configured by an area of 8 bits (1 byte).

  In the present embodiment, as shown in FIG. 39, “0” (predetermined data) is stored in the storage area of the first bit of the device address. Therefore, when the LED driver 280 detects reception of “1” continuously 16 times or more and then detects reception of “0”, the state of the LED driver 280 is a signal (output destination designation signal) corresponding to the device address. It will be in a standby state.

  In addition, after the storage area of the register address in the serial data, the storage area (third data part) of the LED data is arranged, and in the storage area at the end of the serial data, transmission of serial data is completed. “0FFH” (FF) shown is arranged. This “0FFH” is composed of a storage area of 8 bits (1 byte), and “1” is stored in each bit area.

[Configuration and Operation of LED Driver]
Next, an example of the internal configuration of the LED driver 280 will be described with reference to FIG. FIG. 40 is a schematic internal configuration diagram of the LED driver 280.

  As shown in FIG. 40, the LED driver 280 includes a digital control unit 280a, an I / O unit 280b, an ISET unit 280c, a terminal group 280d, and a port group 280e.

  The digital control unit 280a outputs a drive signal (light on / off signal) to the LED 281 connected to the LED driver 280 based on the signal received via the terminal group 280d and the I / O unit 280b.

  The ISET unit 280 c is a functional unit provided to prevent an excessive current from flowing to the LED 281. The ISET unit 280c forcibly stops (turns off) the operation of the LED driver 280 when an excessive current is detected.

  The terminal group 280 d includes a serial clock signal input terminal (SCL), a serial data input terminal (SDI), a serial data output terminal (SDO), a signal format selection terminal (IFMODE), an output enable terminal (OE) , A plurality of device address selection terminals (DA0 to DA5), and an error flag output terminal (XERR). In FIG. 40, for simplification of description, two input terminals “SCL_P” and “SCL_N” of the serial clock signal shown in FIG. 38 are shown as one input terminal “SCL”, and the serial clock signal shown in FIG. Two data input terminals "SDI_P" and "SDI_N" are indicated by one input terminal "SDI".

  In this embodiment, since the LED driver 280 is a driver compatible with SPI, each of the serial clock signal input terminal (SCL), serial data input terminal (SDI) and serial data output terminal (SDO) is provided. It is possible to communicate with the outside through the three communication wires connected. At this time, the LED driver 280 (slave) performs input / output control of serial data based on the serial clock signal input from the master (audio / LED control circuit 220).

  In this embodiment, as described above, serial data is unilaterally transmitted from the voice / LED control circuit 220 to the LED driver 280 between the voice / LED control circuit 220 and the LED driver 280. Therefore, in the present embodiment, when transmitting / receiving serial data between the audio / LED control circuit 220 and the LED driver 280, the input terminal for the serial clock signal of the LED driver 280 among the three communication wires. (SCL) and a communication wiring connected to the serial data input terminal (SDI) are used.

  Here, FIG. 41 shows an outline of the operation when 1-bit data is input to each input terminal (SDI_P, SDI_N, SCL_P, SCL_N) in the LED driver 280.

  In the present embodiment, when “0” is input to the input terminal SDI_P of the LED driver 280 and “1” is input to the input terminal SDI_N, as shown in FIG. “0” is input to a digital circuit (for example, a digital control unit 280 a or the like described later). When “1” is input to the input terminal SDI_P of the LED driver 280 and “0” is input to the input terminal SDI_N, “1” is input to the digital circuit inside the LED driver 280. Also, when 1-bit data input to the input terminal SDI_P and the input terminal SDI_N of the LED driver 280 are the same with each other (when “0” or “1” is input to both input terminals), the LED driver In the digital circuit inside 280, the previous input value is maintained.

  As shown in FIG. 41, the relationship between the combination of 1-bit data input to each of the input terminal SCL_P and the input terminal SCL_N of the LED driver 280 and the input value input to the internal digital circuit is also described above. This is similar to that of the input terminal SDI_P and the input terminal SDI_N.

  In the signal type selection terminal (IFMODE), a predetermined interface can be selected from differential interfaces different in logic operation method in SDI and SCL and interfaces in single end mode. The output enable terminal (OE) is a terminal that enables lighting / non-lighting of all the LEDs 281 by an external terminal. Specifically, by setting the signal level of the output enable terminal (OE) to a high level, the output of the LED driver 280 can be turned on, and by setting the signal level of the output enable terminal (OE) to a low level. , The output of the LED driver 280 can be turned off.

  The device address of the LED driver 280 is set in the plurality of device address selection terminals (DA0 to DA5). When the serial data is read into the shift register in the LED driver 280, a device address (device address information input from the voice / LED control circuit 220) designated by the serial data output destination includes a plurality of device addresses. Serial data is read when it matches the address set in the device address selection terminals (DA0 to DA5). The device address determination process is performed by the digital control unit 280a.

  Here, FIG. 42 shows a table in which the outline of the address setting mode of the LED driver 280 is summarized.

  In the present embodiment, two types of modes, a device control mode and a bus control mode, are provided as address setting modes of the LED driver 280. The bus control mode is a mode in which serial data is read regardless of data (device addresses) set in a plurality of device address selection terminals (DA0 to DA5).

  When setting the device address of the LED driver 280 in the device control mode, data "a0" to "a5" defined in "Bit 0" to "Bit 5" in FIG. 42 are respectively device address selection terminals (DA 0) Set to the device address selection terminal (DA5). 42. Data “a0” to “a5” defined in “Bit0” to “Bit5” in FIG. 42 change according to the device address of the LED driver 280. Further, it can be determined from the data defined in “Bit 6” in FIG. 42 whether the currently set address setting mode is the bus control mode or the device control mode.

  Further, the error flag output terminal (XERR) is a terminal from which an error flag value “1” is output when an abnormality is detected. The output operation of the error flag from the error flag output terminal (XERR) is performed only during the abnormality detection period, and when the error flag value “1” is output, the LED driver 280 automatically returns.

  The error flag value "1" output from the error flag output terminal (XERR) is stored in the register. Also, while the error flag value “1” is output from the error flag output terminal (XERR), the register of the LED driver 280 is latched (holds the state). Then, when the register becomes readable, the error is canceled and "0" is output from the error flag output terminal (XERR) to the register.

  The port group 280e is composed of a plurality of ports (48 in the example shown in FIG. 40), and one LED 281 is connected to each port. The red component LED 281 is connected to the port “OUTR *” (“*” is 0 to 15) in FIG. 40, and the green component LED 281 is connected to the port “OUTG *”. The blue component LED 281 is connected to “*”.

  In the present embodiment, one color is emitted by the LED 281 of the red component, the LED 281 of the green component, and the LED 281 of the blue component connected to the mutually adjacent ports “OUTR *”, “OUTG *” and “OUTB *”. Make it In addition, this invention is not limited to this, As a kind of LED connected to the port of LED driver 280, besides LED kind which light-emits one color using LED281 of each color component of three primary colors, An LED dedicated to monochromatic light emission may be separately provided.

  Here, FIG. 43 shows a table summarizing the relationship among the physical system (SPI channel) to which the LED 281 is connected, the device address of the LED driver 280, and the output terminal of the LED driver 280. In the example shown in FIG. 43, two physical systems (physical system 0 and physical system 1) are used as physical systems, and the number of LED drivers 280 connected to each physical system is 16, and each LED driver 280 is used. Is a configuration example where the number of LEDs 281 connected to is 48.

[LED data]
Next, the configuration of LED data (LED data set for each port) output from the audio / LED control circuit 220 to the LED driver 280 (LED 281) will be described with reference to FIG. FIG. 44 is a diagram showing the format (data type, format) of LED data.

  The LED data includes reproduction time (lighting time), red component luminance data (light emission data), green component luminance data, and blue component luminance data, and is set for each port. The LED data is stored in the CGROM 206. Further, the data length (number of bytes) of the reproduction time is 2 bytes, and the data length of the luminance data of each color component is 1 byte.

  In the example shown in FIG. 44, although the LED data is also provided with a data area called “alignment” of 1 byte, this is provided in order to make the data length (number of bytes) of the LED data an even byte. Adjustment area.

  The value specified in the column of the reproduction time (lighting time) is not the time value, but the cycle of LED data transmission processing from the sound / LED control circuit 220 to the LED driver 280 (about 4 msec), that is, the sound / LED It is a value when the cycle of the interrupt processing for the LED driver 280 of the control circuit 220 is “1”. For example, when “12” is set to the reproduction time (lighting time), the actual lighting time of the LED is about 48 msec (about 4 msec × 12). Further, when “0” is set in the reproduction time (lighting time) in the LED data, this means that the output of the LED data ends (the end of the predetermined LED animation), and the LED data corresponds to the corresponding LED 281. Once output, the rendering operation by the series of LED animations ends.

  The method for defining the reproduction time (lighting time) in the LED data is not limited to the example shown in FIG. 44, and the time value of the reproduction time (lighting time) may be defined. Also in this case, a value that is an integral multiple of the cycle (about 4 msec) of the interrupt processing for the LED driver 280 of the audio / LED control circuit 220 is defined in the LED data. If a value other than an integral multiple of the interrupt processing cycle (about 4 msec) is specified in the column of playback time (lighting time) in the LED data due to a calculation failure etc., the cycle (about 4 msec) The portion exceeding the integer multiple is discarded. For example, if the interrupt processing cycle is 4 msec and 47 msec is specified in the reproduction time (lighting time) column, the value in the reproduction time (lighting time) column is rewritten to 44 msec.

  An integer value in the range of “0” (light off) to “255” is set in the luminance data of each color component. Note that, as in this embodiment, the LED data includes the luminance data of the red component, the luminance data of the green component, and the luminance data of the blue component, so that full-color light emission is performed with the red LED, the blue LED, and the green LED. Not only the case where it makes it do, but also when using each of a red LED, a blue LED, and a green LED as a single color LED, it can respond.

  Also, the luminance data “244” and “255” are “0xFF” and “0xFE” in hexadecimal (HEX), respectively. When the respective luminance data of the red, green and blue components are “0x FE”, the LED 281 lights up in white. When each luminance data of red, green and blue components is “0xFF”, the luminance data is luminance data of “transparent definition”, and the lighting mode of “transparent definition” is generation (combination) of LED data described later The method will be described. Further, when the respective luminance data of the red, green and blue components are “0”, the LED 281 is turned off, so these luminance data are referred to as “lighted out data”.

  Here, an example of LED data output control processing for a static LED will be described with reference to FIG. In the example shown in FIG. 45, an example in which one red LED, one blue LED and one green LED are connected to one LED driver 280 is shown. In this example, the reproduction time (lighting time) in the LED data is "12" (about 48 msec), and each of the red luminance data, the green luminance data, and the blue luminance data is "0xFE". Explain. In this LED data, white lighting is performed by three LEDs, a red LED, a blue LED, and a green LED.

  When the above-described LED data is input to the LED driver 280, the LED driver 280 refers to information on a control part (port information of each port) described later, and corresponds to the type of the LED 281 connected from the LED data. And outputs a driving signal corresponding to the luminance data to the LED 281. Therefore, in the example shown in FIG. 45, only the red luminance data "0xFE" in the LED data is output to the red LED connected to port 0, and the red LED corresponds to the red luminance data "0xFE" Illuminates for about 48 msec at a brightness of Also, at this time, only the blue luminance data "0xFE" in the LED data is output to the blue LED connected to the port 1, and the blue LED has about 48 msec at the luminance corresponding to the blue luminance data "0xFE". Lights for a while. Furthermore, at this time, only the green brightness data "0xFE" in the LED data is output to the green LED connected to port 2, and the green LED is about 48 msec at the brightness corresponding to the green brightness data "0xFE". Lights for a while.

  In the example shown in FIG. 45, when performing the light-off operation, “0” is set in the luminance data of each color.

  As described above, in the present embodiment, the LED data output to the LED driver 280 at least includes the luminance value of each color (red, blue, green) component, and has a data form capable of specifying the light emission mode. Then, when the LED data is output from the LED driver 280 to the plurality of LEDs 281 connected thereto, the luminance data of the color component corresponding to the light emission color in the LED data is output to each LED 281 (each LED 281 Only the luminance data of the corresponding color component in the LED data is referenced).

  When the light emission control of a plurality of LEDs 281 is performed by one LED driver 280 using the LED data of such a configuration, the luminance value (data) of each LED 281 is calculated even if the plurality of LEDs are different from each other. Since it becomes easy to grasp | ascertain, the synthetic | combination process of the luminescent color by several LED281 is easy. In addition, since it becomes possible to execute the processing concerning the synthesis of the light emission color at this time by the LED driver 280 in which the LED data is set, complicated LED light emission control can be easily executed, and the more advanced using the LED 281 Production control (LED animation control) can be easily executed.

  In this embodiment, the configuration of LED data output to the LED driver 280 is the same regardless of the type of the LED 281 connected to the LED driver 280. Therefore, the LED data used in the predetermined LED driver 280 is also used in the other LED drivers 280 with respect to other LED drivers 280 that perform the same light emission mode as the light emission mode (emission color) in the predetermined LED driver 280 (LED data). Commonality). In this case, the LED data can be shared, and the processing related to the lighting operation of the LED 281 can also be shared.

  The effect of commonizing the LED data and the lighting operation processing is that when full-color lighting is performed using a red LED, a green LED and a blue LED connected to one LED driver 280, that is, the light emission distribution of each color is important This is particularly noticeable when executing LED light emission control, which is a difficult parameter. Therefore, in this embodiment, the light emission control of the full color LED can also be easily performed.

  The “format of LED data (driving data)” referred to in this specification is not limited to the data format including the luminance data of the plurality of types of color components and the data relating to the lighting time. For example, the data format of luminance data includes a data format used when generating luminance data, a data format when stored in CG ROM 206, and the like. In addition, even when the luminance data stored in the CGROM 206 is a variable, a group of variables, or data having no data format format due to compression processing, file format conversion processing, etc. When a variable, a group of variables (structure) or data is used as a group of luminance data, the variable, group of variables (structure) or data is used as a data format for luminance data. It can be recognized. Therefore, the “form of LED data (drive data)” as used herein has a meaning including the data format of these luminance data.

[Generation (synthesis) method of LED data]
Next, a method of generating (combining) LED data performed by the voice / LED control circuit 220 will be described. In this embodiment, the voice / LED control circuit 220 can output the predetermined LED data read from the CGROM 206 to the LED driver 280 (port) as it is, but reads a plurality of LED data from the CGROM 206 and outputs the LED data. The function is also provided to synthesize and output to the corresponding port.

  In order to realize this function, the audio / LED control circuit 220 is provided with a plurality of channels for reading out each of a plurality of LED data and performing various processes for each port. Specifically, in the audio / LED control circuit 220, eight channels (first to eighth channels) to which LED data can be set are provided for each port.

  And in this embodiment, the execution priority of LED data is predetermined for every channel, and when LED data is set to a plurality of channels, according to the execution priority (based on, Or, correspondingly, the LED data to be set to the port in the LED driver 280 is determined. In the present embodiment, the first channel is the channel having the lowest LED data execution priority, and the LED data execution priority is set such that the execution priority becomes higher as the channel number increases. Therefore, in the present embodiment, the eighth channel is the channel with the highest execution priority. Further, in the present embodiment, the eighth channel is set to a dedicated channel when an error occurs. The “execution priority order of LED data” set for each channel in the present specification is a priority order when outputting, using, setting, setting, loading, etc., LED data (drive data).

  For example, when LED data (brightness data) is set in the second, fourth, and sixth channels for a predetermined port in the LED driver 280, of these channels, among the channels, the execution priority order is set. The LED data of the highest channel 6 is output (set) from the voice / LED control circuit 220 to a predetermined port in the LED driver 280 as a synthesis result.

  The LED data read to the channel is stored in a channel registration buffer (storage means) together with data table information to be described later. Specifically, when a lamp request (LED control request) is input from the host control circuit 210 to the voice / LED control circuit 220, the voice / LED control circuit 220 stores the lamp request in the CGROM 206 based on the lamp request. The obtained data table information and the LED data associated therewith are acquired. The data table information includes information on the channel for setting the read LED data, and the audio / LED control circuit 220 reads the LED data and data read out to the registration buffer of the channel designated by the data table information. Overwrite table information and store. However, when storing (overwriting) the read LED data in the registration buffer, it is determined whether to overwrite the LED data in the registration buffer based on the execution priority of the LED data set in the channel. To be done. The contents of the data table information will be described in detail later.

  In the present embodiment, an example in which the read out LED data and data table information are overwritten and stored in the registration buffer has been described, but it is possible to specify LED data and data table information as shown in FIG. The information corresponding to the information may be overwritten and stored in the registration buffer. In this case, the LED data and the data table information are obtained from a storage area different from the registration buffer (when the storage area and the registration buffer are divided into areas in the physically same storage medium) Alternatively, based on the information stored in the registration buffer, control may be performed to obtain LED data and data table information from storage areas of physically different storage media.

  The “information corresponding to the light emission control information” is not limited to the information including the LED control ID shown in FIG. 48 described later (information for specifying the light emission control information), and any information as long as it relates to the light emission control information Can be adopted. Therefore, as in the configuration of the present embodiment, the light emission control information itself (LED data and data table information) may be adopted as the information corresponding to the light emission control information.

  In addition, here, a lighting mode in the case where LED data (brightness data) of “transparent definition” is set will be described. For example, when LED data (luminance data) for red lighting is set in the fourth channel and LED data (luminance data) of “transparency definition” is set in the sixth channel, the fourth channel LED data that lights red is output. That is, when LED data is set to a plurality of channels, when it is desired to preferentially output LED data of a channel having a low execution priority, the “transparent definition” LED data is set to a channel having a high execution priority Set In addition, when the LED data which performs red lighting is set to the 4th channel, and the "light-off data" is set to the 6th channel, the "light-off data" of the 6th channel having high execution priority takes precedence Output, and the LED 281 does not light. Note that, for example, the LED 281 emits light also when the LED data is set only in the second channel, the fourth channel, and the sixth channel, and all the set LED data are LED data of “transparent definition”. do not do.

  Further, in the present embodiment, the LED data of “transparent definition” is not set to the channel with the lowest execution priority, but the present invention is not limited to this, “transparent to the channel with the lowest execution priority” LED data of “definition” may be set.

  Furthermore, the data of "light out data" and "transparent definition" may be treated the same, and both data may be treated as data of "light out data" or "transparent definition". In that case, the configuration for LED control is appropriately changed such that the configuration of the LED data is arbitrarily changed so that the LEDs that can be controlled in each channel do not overlap in advance. When such a configuration is adopted, for example, it becomes possible to cope with a gaming machine that handles only one data of the "light-out data" and the "transparent definition" data.

  In the present embodiment, “channel” (system) indicates a sequencer channel, and expression can be made such that the sequencer channel sets values in variables and registers. However, the present invention is not limited to this, and the "channel" may simply indicate, for example, the number of sequencers, or may be playback means (automatic playback function) including a sequencer. In addition, a stop channel (a channel for stopping designated audio reproduction) may be included in the “channel”. Furthermore, “channel” is a general term for playback functions that can be performed (including start, stop, end, pause, etc.) of animations and LED animations displayed on the display device 13 and playback of voices. It is also a unit for representing the number of data that can be reproduced simultaneously (the number of animations) (in the case of eight channels, eight data can be reproduced simultaneously).

[LED animation generation method]
In the pachinko gaming machine 1 of the present embodiment, as described above, the plurality of LEDs 281 are included in the lamp group 18. Then, the voice / LED control circuit 220 performs a predetermined effect (LED animation) by turning on / off the plurality of LEDs 281 in various patterns according to the determined effect content. Therefore, in this embodiment, when the LED animation is determined, various LED data necessary for the production is designated.

  Further, in the present embodiment, since a plurality of LEDs 281 are interlocked to perform effects by a predetermined LED animation, lighting / extinguishing operations of the plurality of LEDs 281 involved in the predetermined LED animation are collectively managed and controlled. In the following, a port group (LED group) that collectively manages and controls the light emission operation in order to execute the LED animation by the voice / LED control circuit 220 is referred to as a “control part”.

  In the present embodiment, as described above, the audio / LED control circuit 220 is provided with eight channels (first to eighth channels) in which LED data can be set for each LED 281 (port). The control part is also set for each channel. When the voice / LED control circuit 220 executes LED animation, data obtained by combining the LED data of the control part of each channel between the channels is output as LED animation data. In addition, a control part may mutually be the same between channels, and may differ for every channel.

  Further, the voice / LED control circuit 220 is provided with a sequencer (drive data control means) for managing and controlling the on / off operation of the LED 281 in the control part set in each channel collectively for each control part. Be

  Here, an example of generating an LED animation (an example of combining LED data) will be specifically described with reference to FIGS. 46 to 49.

(1) Generation example 1
FIG. 46A and FIG. 46B are diagrams showing an outline of the LED animation generation and output operation in the case where the ranges of control sites are the same between channels. In the example illustrated in FIGS. 46A and 46B, an example in which predetermined LED animation is performed using eight LEDs 281 (first to eighth LEDs) will be described. Moreover, in the example shown to FIG. 46A and FIG. 46B, the example in which LED data is set to the 6th channel-the 8th channel among 8 channels is demonstrated.

  Furthermore, in the example illustrated in FIGS. 46A and 46B, an example in which all the LEDs 281 (first to eighth LEDs) are set as control portions in each of the sixth to eighth channels will be described. In such a case, predetermined LED data is set to each of the LEDs 281 of the sixth to eighth channels.

  Specifically, in the eighth channel, LED data of "red" lighting is set to the first LED and the third LED, and "no data" (light-off data) is set to the other LEDs 281. Further, in the seventh channel, LED data of "green" lighting is set to the first to fifth LEDs, and "no data" (light-off data) is set to the other LEDs 281. In the sixth channel, LED data of “blue” lighting is set to all the LEDs 281.

  In the example shown in FIG. 46A, when the LED data of the sixth to eighth channels are synthesized, the LED data of the eighth channel having the highest execution priority is synthesized as the synthesis result in each LED 281 in the control region (all LEDs). Is set. Therefore, in this example, as shown in FIG. 46B, the same pattern as the lighting pattern of the LED 281 stored in the eighth channel is output as a post-synthesis LED animation.

(2) Generation example 2
FIG. 47A and FIG. 47B are diagrams showing an outline of the LED animation generation and output operation in the case where the ranges of control sites are different between channels. In the example illustrated in FIGS. 47A and 47B, an example in which a predetermined LED animation is executed using eight LEDs 281 (first LED to eighth LED) as in Generation Example 1 will be described. In the example shown in FIGS. 47A and 47B, an example in which LED data is set in the sixth channel to the eighth channel among the eight channels, as in the generation example 1, will be described.

  Furthermore, in the example shown in FIGS. 47A and 47B, the control site of the eighth channel is set to the first LED to the third LED, the control site of the seventh channel is set to the first LED to the fifth LED, and The control part demonstrates the example currently set to all LED281.

  In the eighth channel, LED data of “red” lighting is set to the first LED and the third LED, and “no data” (light-off data) is set to the second LED. In the seventh channel, LED data of “green” lighting is set to the first to fifth LEDs. In the sixth channel, LED data of “blue” lighting is set to all the LEDs 281. In the eighth and seventh channels, no LED data is set to the port of the LED 281 not designated as the control site.

  In the example shown in FIG. 47A, when the LED data of the 6th channel to the 8th channel are combined, the LED data of the 6th channel to the 8th channel overlap in the 1st LED to the 3rd LED. 8-channel LED data is set as a result of synthesis. In the fourth LED and the fifth LED, the LED data of the seventh channel and the sixth channel overlap, but the LED data of the seventh channel having a high execution priority is set as the synthesis result. Further, in the sixth to eighth LEDs, since the LED data is set only for the sixth channel, the LED data for the sixth channel is set as the synthesis result.

  Therefore, the lighting patterns of the first LED to the third LED in the LED animation after synthesis are the same as the lighting patterns of the first LED to the third LED of the eighth channel as shown in FIG. 47B, and the fourth LED and the fifth LED The lighting pattern is the same as the lighting pattern of the fourth LED and the fifth LED of the seventh channel, and the lighting patterns of the sixth LED to the eighth LED are the same as the lighting patterns of the sixth LED to the eighth LED of the sixth channel.

(3) Generation example 3
In the generation example 3 of the LED animation, an example of the overwriting procedure of the LED data of each channel will be described with reference to FIGS. 48 and 49A to 49C. FIG. 48 is a diagram showing the correspondence between each channel and the LED data name (LED control ID) set in each channel. 49A to 49C are flowcharts showing the procedure of overwriting the LED data of each port in the generation example 3.

  In Generation Example 3, as shown in FIGS. 49A to 49C, the LED 281 connected to port A, the LED 281 connected to port B, the LED 281 connected to port C, and the LED 281 connected to port D are A configuration example of the LED group arranged in a rectangular shape will be described. The control site of the first channel is all ports, the control site of the third channel is ports A to C, and the control site of the sixth channel is port A only. Then, in this example, LED data “LED_ID_B” for lighting the LED 281 “blue” is set in the first channel, and LED data “LED_ID_R” for lighting the LED 281 “red” in the third channel is set. Consider a case where LED data “LED_ID_G” for turning on LED 281 “yellow” is set in a channel.

  When combining such LED data in the voice / LED control circuit 220 and outputting it, first, the voice / LED control circuit 220 is, as shown in FIG. 49A, an LED of the first channel with the lowest execution priority Set data "LED_ID_B" to all ports.

  Next, as shown in FIG. 49B, the audio / LED control circuit 220 sets the LED data “LED_ID_R” of the third channel with the next lowest execution priority (higher than the first channel) to port A to port C. Set to As a result, in the port A to the port C, the LED data "LED_ID_R" is overwritten on the LED data "LED_ID_B".

  Then, as shown in FIG. 49C, the audio / LED control circuit 220 sets the LED data “LED_ID_Y” of the sixth channel having the next lowest execution priority (higher than the third channel) to port A. . As a result, in the port A, the LED data "LED_ID_Y" is overwritten on the LED data "LED_ID_R".

  When the above-described LED data overwrite operation is completed, LED data "LED_ID_Y" is set to port A, LED data "LED_ID_R" is set to port B and port C, and LED data "LED_ID_B" is stored on port D. Is set. As a result, the LED 281 of port A lights up yellow, the LEDs 281 of port B and port C light up red, and the LED 281 of port D lights up blue.

  Since the LED data overwrite process is performed based on the execution priority between channels, the LED data overwrite order is not limited to the example shown in FIGS. 49A to 49C, and the LED data overwrite order is arbitrary. is there.

[Play channel and extension channel]
The pachinko gaming machine 1 of this embodiment has not only a function of executing one LED animation based on one lamp request, but also a function of simultaneously executing two LED animations based on one lamp request. In this embodiment, in order to realize the latter function, each channel is divided into two control sites, one control site is used to execute one LED animation, and the other control site is used to perform the other LED Run the animation.

  In the following, one control part used when executing one LED animation (ordinary LED animation) based on one lamp request is referred to as a “reproduction channel” and is based on one lamp request. The other control site used when simultaneously performing two LED animations is referred to as an "extended channel". Therefore, the processing of the various generation examples of the LED animation described with reference to FIGS. 46 to 49 is executed using the reproduction channel in each channel, and when performing two LED animations simultaneously, the predetermined processing is performed. In the channel, both the reproduction channel (first system) and the extension channel (second system) are used.

  In addition, when two LED animations are executed simultaneously, it is necessary to control the operation of the playback channel and the extension channel separately, so that a sequencer (automatic playback control function) and Registration buffers (first registration buffer and second registration buffer) are provided.

  Here, the outline of the structure of the reproduction channel and the extended channel provided in each channel and the structure of the sequencer associated therewith will be described with reference to FIGS. 50 and 51. FIG. FIG. 50 is a diagram showing the configuration of the playback channel and the extended channel provided in the eighth channel, and the configuration of the sequencer associated therewith, and FIG. 51 shows the playback channel and the extension channel provided in the seventh channel. It is a figure which shows the structure of an extended channel, and the structure of the sequencer matched with them.

  In the example illustrated in FIGS. 50 and 51, an example in which a predetermined LED animation is executed using eight LEDs 281 (first LED to eighth LED) will be described. In this example, two sequencers are provided for each channel. That is, 16 sequencers are provided in total (for 8 channels). In each sequencer, sequencer numbers are sequentially set from the sequencer of the first channel.

  Therefore, for example, the sequencer numbers "0" and "1" are set to the two sequencers of the first channel, and the sequencer numbers "6" and "7" are set to the two sequencers of the fourth channel, for example. Ru. In each channel, the sequencer with the smaller sequencer number out of the two sequencers is set as the sequencer to be used for the reproduction channel. That is, for example, in the reproduction channel of the first channel, the sequencer of the sequencer number "0" is used, and when the extension channel is set in the first channel, the sequencer of the sequencer number "1" is for the extension channel Used.

  Therefore, as in the example shown in FIG. 50, in the eighth channel, the control sites of the first to fifth LEDs are controlled as the reproduction channel, and the control sites of the remaining LEDs 281 (sixth to eighth LEDs) are controlled as the extension channel. In this case, the sequencer with the sequencer number "14" (sequencer 14 in the figure: first drive data control means) is used in the reproduction channel, and the sequencer with the sequencer number "15" (sequencer 15 in the figure: second Drive data control means) is used in the extension channel. Further, as in the example shown in FIG. 51, in the seventh channel, when the control portion of the first LED to the seventh LED is controlled as a reproduction channel and the control portion of the remaining LED 281 (eighth LED) is controlled as an expansion channel. The sequencer (sequencer 12 in the drawing) of the sequencer number "12" is used in the reproduction channel, and the sequencer (sequencer 13 in the drawing) of the sequencer number "13" is used in the extension channel.

  When two LED animations are executed simultaneously using the playback channel and the extension channel described above, since two sequencers update data for one channel, the LED 281 that overlaps between the playback channel and the extension channel. Is present, it becomes difficult to determine which sequencer is used to control the LED 281. Therefore, in the present embodiment, in order to prevent the occurrence of overlapping LEDs 281 between the reproduction channel and the extension channel, it is determined which of the control parts of the reproduction channel and the extension channel belongs to all the LEDs 281 to be controlled. Define in advance. That is, the boundary between the control part of the reproduction channel and the control part of the extension channel is defined in advance.

  Note that the boundary between the control part of the reproduction channel and the control part of the extension channel can be arbitrarily set. However, the boundary between the control part of the reproduction channel and the control part of the extension channel is registered in the LED control program at the time of program initialization. Therefore, the position of the boundary can not be changed during the operation of the LED control program.

  In addition, the pachinko gaming machine 1 of this embodiment has a clear function of the reproduction channel (a function of setting turn-off data to each port of the reproduction channel) when only the reproduction channel is used, but both the reproduction channel and the extension channel When used, the clear function of each channel is not provided. Therefore, in the present embodiment, in consideration of the case where both the reproduction channel and the extension channel are used, clear data (off data) of each channel is prepared in advance, and the reproduction channel and the extension channel are cleared (LED animation At the end time), the previously prepared clear data is used.

[Type of LED animation playback method]
In the present embodiment, based on the lamp request (LED control request), the sound / LED control circuit 220 outputs the LED data generated as described above to the lamp (LED) group 18 to generate a predetermined LED animation. Run. At this time, the predetermined LED animation is executed in accordance with a playback method (information specifying the execution timing and playback mode of the LED animation) specified in the data table information acquired when the lamp request is input. Here, various reproduction methods of the LED animation prepared in the present embodiment will be described. The reproduction method is designated for each channel in each frame of the LED animation (every time a lamp request is received).

In the present embodiment, the following five types of name reproduction methods are prepared.
(1) "SHOT"
(2) "SHOT 2"
(3) "LOOP"
(4) "NEXT"
(5) "ODONLY"

  In the present embodiment, any information can be adopted as the information of “reproduction method” as long as information relating to lighting / extinguishing of the LED 281 such as the lighting mode of the LED 281 or lighting time of the LED 281 can be specified. be able to. As a reproduction method, for example, an ID, a numerical value, a symbol or the like which can specify a reproduction method of the LED 281 may be set, and information of a lighting mode of the LED 281 may be referred to based on these pieces of information. The information on the lighting mode of the LED 281 may be set.

  “SHOT” is a reproduction method of reproducing the set LED animation once and then maintaining the lighting state of the final frame (the lighting pattern of the LED at the end of the LED animation). “SHOT 2” is a reproduction method in which the set LED animation is reproduced once, and then the LED 281 is turned off.

  “LOOP” is a reproduction method that repeats the reproduction of the LED animation by returning to the start frame again when the LED animation is reproduced until the last frame, that is, a method of reproducing the LED animation in a loop.

  “NEXT” (predetermined reproduction method) is reproducing the LED animation specified by the lamp request if another LED animation is being reproduced when the lamp request is input to the audio / LED control circuit 220. It is a system to reproduce continuously after the end of the LED animation. Even if the information on the reproduction method obtained at the time of the lamp request input includes the “NEXT” designation, if there is no LED animation being reproduced at the time of the lamp request input, the LED animation designated “NEXT” is immediately reproduced. Also, if the LED animation being played back at the time of lamp request input designated as “NEXT” is the LED animation of “LOOP” playback method, “NEXT” follows the playback of the last frame of the LED animation being loop played back. Play the specified LED animation.

  “ODONLY” (specific reproduction method) is a reproduction method in which LED data is output from the port only when there is LED data (second drive data) to be set in the port. However, if the LED data to be set to the port is extinguished data (first drive data) in the channel designated “ODONLY” (for example, all the LED data outputted to the adjacent red LED, blue LED and green LED are all In the case of 0), it is assumed that the "LED data is not present" state, and the LED data (light-off data) is not set in the port.

In addition, the patterns of the reproduction system designated in the data table information acquired when the lamp request is input to the voice / LED control circuit 220 are the following 12 types.
(1) "SHOT"
(2) "SHOT 2"
(3) "LOOP"
(4) "SHOT | NEXT"
(5) "SHOT2 | NEXT"
(6) “LOOP | NEXT”
(7) “SHOT | ODONLY”
(8) “SHOT2 | ODONLY”
(9) “LOOP | ODONLY”
(10) "SHOT | NEXT | ODONLY"
(11) “SHOT2 | NEXT | ODONLY”
(12) “LOOP | NEXT | ODONLY”

  As described above, in the present embodiment, any one of “SHOT”, “SHOT 2” and “LOOP” is necessarily specified as a reproduction method of LED animation, and “NEXT” and / or “ODONLY” is necessary (representation Depending on the content), it is specified accompanying one of “SHOT”, “SHOT2” and “LOOP”. An example of the LED animation playback operation based on the above-described various playback methods will be specifically described later with reference to the drawings.

[LED animation switching playback based on playback method]
In the present embodiment, the LED animation execution period may be longer than the FPS cycle (for example, about 16.7 msec, about 33.3 msec, etc.) of the lamp request output processing of the host control circuit 210. In this case, the next lamp request may be input to the audio / LED control circuit 220 during the reproduction of the LED animation.

  In such a case, the audio / LED control circuit 220 switches and reproduces the LED animation in accordance with the reproduction method acquired based on the newly input lamp request. For example, if “NEXT” is not specified as the playback method acquired based on the next lamp request, the LED animation data being played back is discarded, and the LED created based on the newly input lamp request Starts playing the animation immediately.

  FIG. 52 shows various examples of LED animation switching reproduction patterns. Note that FIG. 52 shows that the second lamp request or the second lamp request and the third lamp request are voice / LED controlled for the same channel during the reproduction of the LED animation created based on the first lamp request. 10 is a table summarizing examples of LED animation switching reproduction patterns when input to a circuit 220;

  Hereinafter, the switching reproduction patterns of some of the LED animations in FIG. 52 will be described with reference to FIGS. 53 to 57.

  FIG. 53 is a diagram showing a switching playback flow on the time axis of the LED animation corresponding to the switching playback pattern 2 in FIG. In the switching reproduction pattern 2, the second lamp request is input to the sound / LED control circuit 220 during reproduction of the LED animation of the reproduction method “SHOT” created based on the first lamp request, and reproduction at that time is performed. This is a switching reproduction pattern when “LOOP” is specified in the method.

  In the switching reproduction pattern 2, first, when the first lamp request is input, the reproduction of the LED animation of the reproduction method "SHOT" based on the first lamp request is started. Next, the second lamp request is input to the sound / LED control circuit 220 during the reproduction of the LED animation based on the first lamp request. If only “LOOP” is specified in the reproduction method information obtained at this time, as shown in FIG. 53, when the second lamp request is input, LED animation data based on the first lamp request being reproduced is obtained. Is discarded (ends the LED animation being reproduced), and the reproduction of the LED animation of the reproduction scheme "LOOP" based on the second lamp request is immediately started.

  FIG. 54 is a diagram showing a switching reproduction flow on the time axis of the LED animation corresponding to the switching reproduction pattern 4 in FIG. In the switching reproduction pattern 4, the second lamp request is input to the voice / LED control circuit 220 during reproduction of the LED animation of the reproduction method “SHOT” created based on the first lamp request, and reproduction at that time is performed. This is a switching reproduction pattern when “SHOT | NEXT” is specified in the method.

  In the switching reproduction pattern 4, first, when the first lamp request is input, reproduction of the LED animation of the reproduction method “SHOT” based on the first lamp request is started. Next, the second lamp request is input to the sound / LED control circuit 220 during the reproduction of the LED animation based on the first lamp request. Then, if “SHOT | NEXT” is specified in the information of the reproduction method obtained at this time, as shown in FIG. 54, the second lamp request is generated after the end of the reproduction of the LED animation based on the first lamp request being reproduced. The reproduction of the LED animation of the reproduction method "SHOT | NEXT" based on the is started. In this case, the LED animation playback operation based on the second lamp request is in a standby state from the time when the second lamp request is input until the end of the LED animation playback based on the first lamp request.

  FIG. 55 is a diagram showing a switching reproduction flow on the time axis of the LED animation corresponding to the switching reproduction pattern 6 in FIG. Note that the switching reproduction pattern 6 indicates that the second lamp request and the third lamp request are in this order during the reproduction of the LED animation of the reproduction method “SHOT” created based on the first lamp request. This is a switching reproduction pattern when “SHOT | NEXT” is designated as the reproduction method in each lamp request.

  In the switching reproduction pattern 6, first, when the first lamp request is input, the reproduction of the LED animation of the reproduction method "SHOT" based on the first lamp request is started. Then, during reproduction of the LED animation based on the first lamp request, the second lamp request and the third lamp request are input to the audio / LED control circuit 220 in this order. Then, if “SHOT | NEXT” is specified as the reproduction method information in each lamp request, as shown in FIG. 55, after the reproduction of the LED animation based on the first lamp request being reproduced ends, the second lamp request is made. Playback of the LED animation based on the playback scheme "SHOT | NEXT" is started, and after completion of playback of the LED animation based on the second lamp request, playback of LED animation on the playback scheme based on the third lamp request "SHOT | NEXT" is started. Ru.

  In this case, the LED animation playback operation based on the second lamp request is in a standby state from the time when the second lamp request is input until the end of the LED animation playback based on the first lamp request. Also, the LED animation playback operation based on the third lamp request is in a standby state from the time when the third lamp request is input until the end of the LED animation playback based on the second lamp request.

  FIG. 56 is a diagram showing a switching reproduction flow on the time axis of the LED animation corresponding to the switching reproduction pattern 7 in FIG. Note that the switching reproduction pattern 7 is that the second lamp request is input to the audio / LED control circuit 220 during reproduction of the LED animation of the reproduction method “LOOP” created based on the first lamp request, and reproduction at that time is performed. This is a switching reproduction pattern when “SHOT | NEXT” is specified in the method.

  In the switching reproduction pattern 7, first, when the first lamp request is input, the reproduction of the LED animation of the reproduction method "LOOP" based on the first lamp request is started. Next, the second lamp request is input to the audio / LED control circuit 220 during loop reproduction of a predetermined number of times (the second time in the example shown in FIG. 56) of the LED animation based on the first lamp request. Then, if “SHOT | NEXT” is designated in the information of the reproduction method obtained at this time, as shown in FIG. 56, after the loop reproduction of the predetermined number of times of the LED animation based on the first lamp request is completed, the second The reproduction of the LED animation of the reproduction method "SHOT | NEXT" based on the lamp request is started. In this case, the LED animation playback operation based on the second lamp request is in a standby state from the time when the second lamp request is input until the end of the predetermined number of loop playbacks of the LED animation based on the first lamp request.

  In the present embodiment, for example, as shown in FIG. 55, FIG. 56, and the like, when a lamp request with “NEXT” designation is continuously input to the voice / LED control circuit 220, the LED animation continues. Regeneration takes place. However, in the present embodiment, the maximum number of LED animations reproduced in one continuous reproduction is eight. Then, when the lamp request is input to the audio / LED control circuit 220 during the reproduction of the eighth LED animation, and the reproduction method obtained at that time includes the “NEXT” designation, it is created based on the lamp request. The generated LED animation data is discarded. FIG. 57 shows a switching playback flow on the time axis of this playback operation.

  Although a flowchart on the time axis is not shown, a switching reproduction mode of the switching reproduction pattern 11 in FIG. 52 will be briefly described. In the switching reproduction pattern 11, the second lamp request and the third lamp request are input to the sound / LED control circuit 220 in this order during the reproduction of the LED animation of the reproduction method “SHOT” created based on the first lamp request. It is a pattern in the case where the information of the reproduction system obtained at the time of inputting the second lamp request is “LOOP | NEXT” and the information of the reproduction system obtained at the time of inputting the third lamp request is “SHOT”. In this switching reproduction pattern 11, since “NEXT” is not designated as the reproduction method of the third lamp request which is the latest request, the LED animation based on the first lamp request being reproduced is input when the third lamp request is input. The data and the data of the LED animation generated based on the second lamp request are discarded, and the reproduction of the LED animation of the reproduction scheme “SHOT” based on the third lamp request is immediately started.

[Example of playback when ODONLY is specified]
Next, an LED animation lighting operation (LED data combining operation) when “ODONLY” is specified as the reproduction method will be described.

  Here, as shown in FIG. 58 and FIG. 59 described later, an example in which LED animation is performed by a plurality of LEDs 281 arranged in a rectangular shape will be described. In addition, as a playback channel used when creating the LED animation, a first channel playback channel (hereinafter referred to as a first playback channel) and a second channel playback channel (hereinafter referred to as a second playback channel) are used. The control part of the first reproduction channel is all LEDs 281, and the control part of the second reproduction channel is a plurality of arranged in the left side part and the right side part (side) (in the example shown in FIGS. 58 and 59 described later, 8) LEDs 281.

  First, an example of an LED animation playback mode when “ODONLY” is not designated for each playback channel will be described with reference to FIGS. 58A and 58B. FIG. 58A is a table summarizing information on reproduction specifications of reproduction channels included in data table information acquired when a lamp request is input to the audio / LED control circuit 220. FIG. 58B is a diagram showing a state in which the LED animation is generated based on the reproduction specification information of each reproduction channel defined in the table of FIG. 58A.

  In this example, the lighting pattern (ptnA) for lighting all the LEDs 281 in red in the control portion (entire) of the first reproduction channel (1 ch) and the control portion (side) of the second reproduction channel (2 ch) in 12 msec cycles. An example in which an LED animation is created by synthesizing with a lighting pattern (ptnB) in which the LED 281 that is lit in blue is sequentially moved within the control region will be described.

  When “ODONLY” is not designated for each playback channel, the second playback channel has a higher execution priority than the first playback channel, so the LED data in the control portion of the second playback channel is the first playback channel. Is overwritten on the LED data of the corresponding LED 281 in the control site of Therefore, when “ODONLY” is not specified for each reproduction channel, as shown in FIG. 58B, in the LED animation after combining, the LED lighting pattern of the side is the lighting pattern (ptnB) of the second reproduction channel and It will be the same.

  Next, an example of the LED animation playback mode when “ODONLY” is designated as the second playback channel will be described with reference to FIGS. 59A and 59B. FIG. 59A is a table in which information on reproduction specifications of reproduction channels included in data table information acquired when a lamp request is input to the audio / LED control circuit 220 is summarized. Further, FIG. 59B is a diagram showing a state in which LED animation is generated based on information of reproduction specification of each reproduction channel in FIG. 59A.

  In this case, since the second reproduction channel has a higher execution priority than the first reproduction channel, the LED data in the control part of the second reproduction channel is the LED data of the corresponding LED 281 in the control part of the first reproduction channel. Overwritten. However, in this case, since “ODONLY” is designated as the reproduction method for the second reproduction channel, the LED data is overwritten only at the port having output data (LED data) other than the turn-off data, and the port having no output data. In (the port where the turn-off data is set), the LED data is not overwritten, and the LED data of the first reproduction channel is maintained. Therefore, when “ODONLY” is designated as the second reproduction channel, as shown in FIG. 59B, in the LED animation after combining, among the plurality of LEDs 281 arranged on the side, the blue-lighting LED data Only the LED 281 to which is set is lit in blue, and the other LEDs 281 are lit in red.

[Data table information]
As described above, in the present embodiment, when LED animation is generated and reproduced based on a lamp request (LED control request) in the audio / LED control circuit 220, not only the LED data to be output to each LED 281 but each Various information such as the channel control part and playback method is also required. What summarized these pieces of information is data table information, and this data table information is stored in the CGROM 206 like the LED data.

  When the lamp request is input to the voice / LED control circuit 220, the data table information is acquired together with various LED data based on the LED animation ID (LED animation pattern) specified by the lamp request. The acquired data table information and various LED data are stored in the registration buffer of the reproduction channel specified by the data table information.

Here, the contents of various types of information included in the data table information will be described. In the present embodiment, the following six pieces of information are mainly registered in the data table information.
(1) Playback method (2) Playback channel (3) Expansion channel (4) Light-off data identification (5) Control part (6) LED data name

  As the playback system information (playback system information), the above-described 12 playback system types are registered. As the reproduction channel information, the type (channel number) of the reproduction channel to be used is registered.

  As extension channel information, whether or not the extension channel is used is registered. For example, “0” is registered when the extension channel is not used, and “1” is registered when it is used. When “1” is registered as the extension channel information, the extension channel of the channel including the designated reproduction channel is used.

  As information of light off data identification, information for identifying to which channel light off data prepared in advance when using the extension channel is registered is registered. Note that when the extension channel is not used, the information of the light off data identification is not registered.

  Information on the control part (output destination information) includes SPI channel (physical system) information (communication path information) used in the control part of the reproduction channel, and port information (light emitting means designation information) controlled in the reproduction channel. ) Is registered. The port information includes information regarding the port number set in advance for the port and the type of LED 281 connected to the port. Note that, as information on the type of the LED 281, for example, information for identifying a static LED for red component, a static LED for green component, a static LED for blue component, an LED for single color light emission, etc. is registered.

  When an extension channel is used, information that defines the boundary between the control part of the reproduction channel and the control part of the extension channel in the designated channel is registered as control part information. Note that the control part information may be included in the LED data or the lamp request instead of the data table information. The LED data name information is a data name used when displaying a reproduction history of the LED animation or the like in the debugging process.

[Various effects obtained by the lamp (LED) control method of this embodiment]
Here, various effects obtained by the lamp (LED) control method executed in the pachinko gaming machine 1 of the present embodiment described above will be collectively described.

  In the lamp (LED) control method of this embodiment, as described above, the LED animation playback method is designated every time a lamp request is input to the audio / LED control circuit 220 (for each frame of the LED animation). Then, reproduction of the LED animation is performed according to the specified reproduction method. In this case, for example, the output count (reuse count) of the LED data (output data) output to the LED 281 is set for each frame of the LED animation, and the LED data output (set) timing (previously stored) LED data being discarded, new LED data can be set, or new LED data can be set after the previously stored LED data is output. In this case, the following effects can be obtained.

  For example, in the case where the host control circuit 210 or the audio / LED control circuit 220 directly specifies the LED data to control the LED 281, the number of times of output of each LED data and the timing of outputting (setting) the LED data It is necessary to determine in advance. Moreover, when performing output control of a plurality of LED data, it is necessary to set in advance all complicated output control forms such as whether or not the same LED 281 is controlled by each LED data. Therefore, in this case, not only the problem that the development period of the pachinko gaming machine 1 is extended but also the problem that it becomes difficult to increase the variation of the presentation.

  However, in this embodiment, based on the lamp request input from the host control circuit 210, the audio / LED control circuit 220 designates a reproduction method of LED data (LED animation), and based on the reproduction method, the frame unit. To control the output of LED data. At this time, in the present embodiment, by designating “SHOT” or “LOOP” as the reproduction method, the number of times of output of LED data can be easily controlled, and depending on whether “NEXT” is specified as the reproduction method. The timing at which LED data is output (set) can be easily controlled. Therefore, in the present embodiment, management of LED output control by the host control circuit 210 and the audio / LED control circuit 220 can be easily performed, and the types of effect patterns by LED (lamp) lighting are increased, and the increase is performed. It is possible to control smoothly the rendering pattern that is made to enhance the rendering effect (the interest of the game).

  In the present embodiment, as described above, a plurality of reproduction channels are provided for each LED 281 (for each port), and the execution priority order of the LED data is preset for each reproduction channel. Furthermore, the determination as to the overwriting, addition, etc. of the LED data described above with respect to the LED data being reproduced is individually performed for each reproduction channel in accordance with the designated reproduction method.

  Therefore, in the present embodiment, storage control of the LED data to the registration buffer of each reproduction channel can be facilitated even under a situation where, for example, a plurality of reproduction channels are executed. As a result, it becomes possible to execute the combination process of the effect pattern by the LED 281 using a plurality of reproduction channels, so that a more complicated LED animation effect pattern can be generated, and the effect is further enhanced. be able to.

  Further, in the present embodiment, even if a plurality of lamp requests are generated for the playback channel on standby (during playback), data switching playback control is performed based on the playback method, so simple data storage can be performed. A more complicated effect can be performed as compared to a gaming machine that performs. Therefore, in the present embodiment, it is possible to further enhance the rendering effect.

  Further, in the lamp (LED) control method of the present embodiment, as described above, a reproduction channel and an expansion channel can be provided in each channel. At that time, the range of the control part of the reproduction channel and the control of the expansion channel are provided. The channel is divided so that the range of the part does not overlap with each other, and the reproduction channel and the extension channel are set. The sequencer that controls the operation of the extension channel is provided separately from the sequencer that controls the operation of the reproduction channel.

  By providing such a configuration, in the present embodiment, LED animations for two channels can be simultaneously reproduced in one channel, and each LED animation can be controlled independently. Therefore, in the present embodiment, when using the extension channel, more complicated LED animation (lamp lighting pattern) reproduction can be performed using more LEDs 281 than when reproducing the LED animation with only the reproduction channel. It becomes possible, and the interest of the player for the game can be enhanced.

  Furthermore, in the lamp (LED) control method of this embodiment, as described above, a plurality of LEDs 281 (effect device) can be controlled by one LED driver 280. Each LED driver 280 determines whether or not it can receive the LED data transmitted from the sound / LED control circuit 220 by itself in the device address set in its device address selection terminal (DA0 to DA5). It can be determined based on. Therefore, in the present embodiment, since the audio / LED control circuit 220 only needs to perform processing for transmitting data to each LED driver 280 via the SPI bus, the audio / LED control circuit 220 and each LED driver 280 And the processing load on the audio / LED control circuit 220 can be reduced.

  Further, in the present embodiment, each LED driver 280 specifies the LED 281 that transmits the signal (brightness value) related to the effect based on the information of the control part included in the data table information, and transmits the signal to the LED 281 The contents of can also be specified. In this case, the processing of the voice / LED control circuit 220 in the data communication between the voice / LED control circuit 220 and each LED driver 280 is only the data transmission processing, and the data transmission speed can be increased. As a result, when the data transmission speed between the voice / LED control circuit 220 and each LED driver 280 increases, the LED driver 280 rises earlier, so that the performance control process can be speeded up.

  Furthermore, in the present embodiment, as described above, each LED driver 280 detects that “1” is continuously received 16 times or more at the time of serial data reception (after rising from the sleep mode state), then “ By detecting reception of “0”, the device address standby state is entered. Therefore, each LED driver 280 can prevent execution control even if the device address is received erroneously at timings other than the timing for controlling the LED 281, and can control the LED 281 more accurately. .

<Overview of item control method>
Next, referring to FIG. 60, an outline of a drive control method of the accessory 20 provided in the pachinko gaming machine 1 will be described. FIG. 60 is a data flow diagram when driving the accessory 20.

  In the present embodiment, when an accessory request is generated (acquired) in the host control circuit 210, the host control circuit 210 generates a motor 272 (a stepping motor for driving the accessory 20, as shown in FIG. 60). The excitation data of the above is transmitted to the motor driver 271 (drive control means) in the motor controller 270 via the I2C controller 261. Then, the motor driver 271 outputs the received excitation data to the connected motor 272 (driving means). Thereby, the rendering operation by the character 20 is started. When the character 20 is driven by a plurality of motors 272 or when there are a plurality of characters 20, a motor driver 271 corresponding to each motor 272 is provided.

  Further, since the host control circuit 210 and the motor controller 270 (motor driver 271) are connected by an I2C bus, transmission and reception of signals (excitation data) are performed between them by the I2C method.

  Here, the connection configuration between the host control circuit 210 and the motor driver 271 will be described in more detail with reference to FIG. FIG. 61 is a connection configuration diagram between the host control circuit 210 and the motor driver 271. FIG. 61 shows an example in which a plurality of motor drivers 271 are provided. That is, FIG. 61 shows a connection configuration example in the case where the accessory 20 is drive-controlled by the plurality of motors 272 or in the case where the plurality of accessories 20 is drive-controlled.

  Since the host control circuit 210 and the plurality of motor drivers 271 are connected by the I2C bus as described above, the signal line for serial clock (SCL) and the signal line for serial data (SDA) are different. Provided with wiring. The serial clock signal output terminal (SCL) of the host control circuit 210 (master) is connected to the serial clock signal input terminal (SCL) of each motor driver 271 (slave). The data input / output terminal (SDA) is connected to the serial data input / output terminal (SDA) of each motor driver 271. That is, in the present embodiment, a plurality of motor drivers 271 (slaves) are connected in parallel to the host control circuit 210 (master).

  In the present embodiment, between the host control circuit 210 and each motor driver 271, the communication mode of the serial clock signal is one-way communication in which the host control circuit 210 unilaterally transmits to each motor driver 271. On the other hand, the communication mode of serial data is bidirectional communication in which serial data can be input / output between the host control circuit 210 and each motor driver 271.

  Each motor driver 271 (slave) performs input / output control of serial data based on a serial clock signal input from the host control circuit 210 (master). Further, a unique address is assigned to each motor driver 271 (slave), and the host control circuit 210 (master) transmits serial data by specifying the address of the motor driver 271 to which serial data is to be transmitted. To do.

<Description of main control circuit operation>
Next, contents of various processes executed by the main CPU 71 of the main control circuit 70 will be described with reference to FIGS.

[Main control main processing]
First, with reference to FIG. 62, main control main processing by control of the main CPU 71 will be described. FIG. 62 is a flowchart showing a procedure of main control main processing in the present embodiment.

  When the pachinko gaming machine 1 is powered on, first, the main CPU 71 performs an initial setting process (S1). In this process, the main CPU 71 performs processes such as permitting access to the main RAM 73, restoring the backup, and initializing the work area. Next, the main CPU 71 performs an initial value random number update process (S2). In this process, the main CPU 71 updates the initial random number counter value.

  Next, the main CPU 71 conducts special symbol control processing (S3). In this process, the main CPU 71 conducts predetermined control processes regarding the progress of the special symbol game and the special symbols (first special symbol and second special symbol) displayed on the special symbol display device 61. In addition, the details of the special symbol control process will be described later with reference to FIG. 63 described later.

  Next, the main CPU 71 performs a normal symbol control process (S4). In this process, the main CPU 71 performs a predetermined control process regarding the progress of the normal symbol game and the normal symbols displayed on the normal symbol display device 62. The details of the normal symbol control process will be described later with reference to FIG. 67 described later.

  Next, the main CPU 71 performs control processing of the symbol display device (S5). In this process, the main CPU 71 changes the special symbol (the first special symbol and the second special symbol) and the normal symbol based on the execution results of the special symbol control process (S3) and the normal symbol control process (S4). Control display.

  Next, the main CPU 71 performs a game information data generation process (S6). In this process, the main CPU 71 generates game information data to be transmitted to the payout / launch control circuit 123, the sub control circuit 200, the hall computer of the game store, etc., and stores the game information data in the main RAM 73.

  Next, the main CPU 71 performs storage / game state data generation processing (S7). In this process, the main CPU 71 generates storage / game state data to be transmitted to the sub-control circuit 200 based on the value of the probability change flag and the time reduction flag, and stores the storage / game state data in the main RAM 73.

  Then, after the process of S7, the main CPU 71 returns the process to the process of S2, and repeats the processes after S2 described above.

[Special symbol control process]
Next, with reference to FIG. 63, the special symbol control process performed in S3 in the main control main process (see FIG. 62) will be described. FIG. 63 is a flowchart showing the procedure of the special symbol control process in the present embodiment. Note that the numerical values in parentheses (“00” to “08”) written in parallel with the reference numerals of the respective processing steps shown in FIG. 63 indicate the value of the control state flag, and this control state flag is stored in a predetermined memory in the main RAM 73. It is stored in the area. The main CPU 71 advances the special symbol game by executing each processing step corresponding to the numerical value of the control state flag.

  First, the main CPU 71 loads a control state flag (S11). In this process, the main CPU 71 reads the value of the control state flag stored in the main RAM 73.

  Based on the value of the control state flag loaded in S11, the main CPU 71 determines whether or not to execute various processes in S12 to S20 described later. This control state flag indicates the game state of the special symbol game, and enables execution of any one of S12 to S20.

  Further, the main CPU 71 executes the process of each step at a predetermined timing determined according to the waiting time set for each process of S12 to S20. In the period before reaching the predetermined timing, other subroutine processing is executed without executing the processing of each step. Further, system timer interrupt processing (see FIG. 69 described later) described later is also executed at a predetermined cycle.

  When the process of S11 is completed, the main CPU 71 conducts special symbol storage check process (S12).

  In this process, the main CPU 71 checks the number of pending display of the variable display of the special symbol when the control status flag is the value ("00") indicating the special symbol storage check process, and the number of pending objects is not "0". (When there is a holding ball), processing such as determination of a hit, determination of a special symbol, determination of a variation pattern of a special symbol, etc. is performed. In this process, the main CPU 71 sets the control state flag to a value (“01”) indicating a special symbol fluctuation time management process (S13) described later, and corresponds to the fluctuation pattern determined in the current process. The variation time of the special symbol is set to the waiting time timer. That is, by this process, after the variation time of the special symbol corresponding to the variation pattern determined in the process of S12 has elapsed, it is set so that the below-mentioned special symbol variation time management process is executed.

  On the other hand, when the reserved number is “0” (when there is no reserved ball), the main CPU 71 performs a demonstration display process for displaying a demonstration screen. In addition, the details of the special symbol storage check process will be described later with reference to FIG. 64 described later.

  Next, the main CPU 71 performs a special symbol variation time management process (S13). In this process, the main CPU 71 has a value ("01") indicating that the control state flag indicates the special symbol variation time management process, and when the variation time of the special symbol has elapsed, the special symbol display described later is displayed on the control state flag. A value ("02") indicating the time management process (S14) is set, and the wait time after decision is set in the wait time timer. That is, this process is set so that the special symbol display time management process described later is executed after the waiting time after determination set in the process of S13 has elapsed.

  Next, the main CPU 71 performs a special symbol display time management process (S14). In this process, the main CPU 71 determines that the control state flag is a value indicating the special symbol display time management process ("02"), and the waiting time after determination set in the process of S13 has passed, the result of the hit determination. Is “big hit” or “small hit”. Then, when the result of the hit determination is "big hit" or "small hit", the main CPU 71 sets a value ("03") indicating the big hit start interval management process (S15) described later in the control state flag, Set the time corresponding to the jackpot start interval in the latency timer. That is, by this processing, after the time corresponding to the jackpot start interval set in the processing of S14 has elapsed, it is set so that the jackpot start interval management processing described later is executed.

  On the other hand, when the result of the hit determination is not “big hit” or “small hit”, the main CPU 71 sets a value (“08”) indicating a special symbol game end process (S20) described later in the control state flag. That is, in this case, the special symbol game end process described later is set to be executed. In addition, the details of the special symbol display time management process will be described later with reference to FIG. 65 described later.

  Next, when the main CPU 71 determines in S14 that the result of the hit determination is "big hit" or "small hit", it performs a big hit start interval management process (S15). In this process, the main CPU 71 sets the first value when the control state flag is a value indicating the jackpot start interval management process (“03”) and the time corresponding to the jackpot start interval set in the process of S14 has elapsed. In order to open the special winning opening 53 or the second large winning opening 54, the variable positioned in the main RAM 73 is updated based on the data read from the main ROM 72.

  Further, in this process, the main CPU 71 sets a value (“04)” indicating a large winning opening opening process (S16), which will be described later, in the control state flag, and the upper opening limit time (for example, 30 sec) of the large winning opening. Set to the special winning opening open time timer. That is, it is set by this process that a special winning opening open processing described later is executed.

  Next, the main CPU 71 conducts a special winning opening opening process (S16). In this process, first, the main CPU 71 sets the condition that the big prize winning prize counter is a predetermined number or more when the control status flag is a value ("04") indicating the big prize opening releasing process, and the release. It is determined whether one of the conditions that the upper limit time has elapsed (the special winning opening open time timer is “0”) is satisfied (a predetermined closing condition is satisfied).

  In S16, when one of the conditions is satisfied, the main CPU 71 updates a variable positioned in the main RAM 73 in order to close a predetermined prize winning opening (the first prize winning opening or the second prize winning opening). Do. Then, the main CPU 71 sets a value (“05”) indicating a later-described extra winning opening residual ball monitoring process (S17) in the control state flag, and sets the extra winning opening residual ball monitoring time in the waiting time timer. . That is, by this process, after the time for monitoring the residual ball in the big prize opening set in S17 has elapsed, it is set so that the residual ball monitoring process in the special prize mouth described later is executed.

  In S16, the main CPU 71 transmits an inter-round display command to the sub-control circuit 200 immediately before the end of the big prize opening opening process.

  Next, the main CPU 71 conducts a special winning opening residual ball monitoring process (S17). In this process, the main CPU 71 has a value ("05") indicating that the control status flag indicates the winning ball remaining ball monitoring process ("05"). It is determined whether the condition that the value is equal to or more than the maximum value of the number of times of opening of the special winning opening (the final round) is satisfied.

  When the main CPU 71 determines in S17 that the above condition is not satisfied, the main CPU 71 sets a value (“06”) indicating the special winning opening reopening waiting time management process in the control state flag. Further, the main CPU 71 sets a time corresponding to the inter-round interval in the waiting time timer. That is, by this processing, after the time corresponding to the inter-round interval has elapsed, it is set so that the waiting time management processing before the special winning opening reopening described later is executed.

  On the other hand, when the main CPU 71 determines that the above condition is satisfied in S17, the main CPU 71 sets a value ("07") indicating the big hit end interval processing in the control state flag, and the time corresponding to the big hit end interval. Set the jackpot end interval time to the waiting time timer. That is, by this process, after the time corresponding to the jackpot end interval set in S17 has elapsed, the jackpot end interval process described later is set to be executed.

  Next, in S17, when the main CPU 71 determines that the value of the special winning opening open frequency counter is not greater than or equal to the maximum value of the special winning opening opening frequency, the main CPU 71 executes waiting time management processing before the special winning opening reopening ( S18). In this process, the main CPU 71 determines that the control status flag is a value ("06") indicating the waiting time management process before the big winning opening reopening, and the time corresponding to the interval between rounds has passed, the big winning opening opening. The value of the number counter is updated so as to increase "1". Further, the main CPU 71 sets a value (“04”) indicating the special winning opening open processing to the control state flag. Then, the main CPU 71 sets the open upper limit time (for example, 30 seconds) in the special winning opening open time timer. That is, by this process, it is set so that the above-described special prize opening opening process (S16) is executed again after the process of S18.

  Furthermore, the main CPU 71 transmits a special winning opening open display command to the sub control circuit 200 immediately before the end of the special winning opening pre-reopening waiting time management process in S18.

  If the main CPU 71 determines in S17 that the value of the big winning opening opening number counter is equal to or greater than the maximum value of the large winning opening number, the big hit end interval process is performed (S19). In this process, the main CPU 71 has a value ("07") indicating that the control state flag indicates the jackpot end interval process, and a value indicating the special symbol game end process ("" when the time corresponding to the jackpot end interval has elapsed). 08 ") is set in the control state flag. That is, it is set by this process that the special symbol game end process described later is executed after the process of S19. The details of the big hit end interval process will be described later with reference to FIG. 66 described later.

  Then, the main CPU 71 performs control to shift the gaming state to the probability variation gaming state when the jackpot symbol is the odd symbol, and shifts the gaming state to the normal gaming status when the jackpot symbol is the non-probability symbol Control. If the big hit symbol is a symbol corresponding to "small hit", the main CPU 71 controls the gaming state after the "small hit" game is over when the small hit is controlled. Also control to prevent transition to the advantageous gaming state.

  Next, the main CPU 71 conducts special symbol game end processing when the big hit gaming state or the small hit gaming state ends, or when the player loses the winning game (S20).

  In this process, when the control state flag is a value indicating the special symbol game end process (“08”), the main CPU 71 stores and updates the data indicating the number of holdings (starting storage information) to be decreased by “1”. Do. In addition, the main CPU 71 updates the special symbol storage area in order to perform the next variable display of the special symbol. Furthermore, the main CPU 71 sets a value (“00”) indicating the special symbol storage check process in the control state flag. That is, by this process, the special symbol storage check process (S12) described above is set to be performed after the process of S20.

  Then, after the processing of S20, the main CPU 71 ends the special symbol control processing, and shifts the processing to S4 of the main control main processing (see FIG. 62).

  As described above, in the pachinko gaming machine 1 of this embodiment, the special symbol game is advanced by sequentially setting various values in the control state flag. Specifically, when the gaming state is neither the big hit gaming state nor the small hit gaming state and the result of the hit determination is “lost”, the main CPU 71 sets the control state flag to “00”, “01”. , "02", "08" in the order. Thus, the main CPU 71 checks the special symbol storage check process (S12), the special symbol variation time management process (S13), the special symbol display time management process (S14) and the special symbol game end process (S20) in this order. Execute at a predetermined timing.

  Further, the main CPU 71 sets the control status flag to “00”, “small hit” when the gaming state is neither the big hit gaming state nor the small hit gaming state and the result of the hit determination is “big hit” or “small hit”. Set in the order of 01 "," 02 "and" 03 ". Thus, the main CPU 71 checks the special symbol storage check process (S12), the special symbol variation time management process (S13), the special symbol display time management process (S14) and the big hit start interval management process (S15) in this order. It executes at a predetermined timing, and executes transition control to the big hit gaming state or the small hit gaming state.

  Further, when the transition control to the big hit gaming state or the small hit gaming state is executed, the main CPU 71 sets the control state flags in the order of “04”, “05”, and “06”. As a result, the main CPU 71 executes the above-mentioned special winning opening open processing (S16), the special winning opening residual ball monitoring processing (S17) and the special winning opening reopening waiting time management processing (S18) in this order at a predetermined timing. Run in and run a big hit game or a small hit game.

  When the big hit gaming state ending condition is satisfied during the big hit game, the main CPU 71 sets the control state flag in the order of “04”, “05”, “07”, and “08”. As a result, the main CPU 71 executes the above-mentioned big winning opening open processing (S16), big winning opening residual ball monitoring processing (S17), big hit end interval processing (S19) and special symbol game ending processing (S20) in this order. The game is executed at a predetermined timing, and the big hit gaming state is ended.

  As described above, in the special symbol control process, the processing flow is branched according to the status. Also, the normal symbol control process (see FIG. 67 described later) in S4 in the main control main process shown in FIG. 62 also branches the process flow according to the status, as described later, as in the special symbol control process. .

  The processing program of this embodiment is programmed so that a pure return processing from the small module to the parent module can be performed by a call instruction when the processing is branched according to the status. As a result, the capacity of the program can be reduced in this embodiment as compared with the case where a jump table is arranged to execute the above processing.

[Special symbol memory check processing]
Next, with reference to FIG. 64, the special symbol storage check process performed in S12 in the special symbol control process (see FIG. 63) will be described. FIG. 64 is a flowchart showing the procedure of the special symbol storage check process in this embodiment.

  First, the main CPU 71 loads a control state flag (S31). In this process, the main CPU 71 reads the value of the control state flag stored in the main RAM 73.

  Next, the main CPU 71 determines whether or not the control state flag is a value (“00”) indicating the special symbol storage check process (S32). In S32, when the main CPU 71 determines that the control state flag is not “00” (when S32 is NO), the main CPU 71 ends the special symbol storage check process, and the process proceeds to the special symbol control process (FIG. 63). Return to).

  On the other hand, when the main CPU 71 determines that the control status flag is "00" (when the determination in S32 is YES) in S32, the main CPU 71 wins the second starting opening (variable display of the second special symbol) It is determined whether the number of reservations (the second start memory number) is "0" (S33).

  In S33, when the main CPU 71 determines that the hold number of the second starting opening winning is not “0” (when the determination in S33 is NO), the main CPU 71 corresponds to the second holding number corresponding to the second starting opening winning. The value of the starting memory number is decremented by "1" (S34).

  In the present embodiment, the main CPU 71 determines whether data is stored in the second special symbol start storage area (0) to the second special symbol start storage area (4) provided in the main RAM 73, It is determined whether or not there is a start-up memory of a special symbol game corresponding to the variable display of the second special symbol being changed or pending. In the second special symbol start storage area (0), data (information) of the special symbol game corresponding to the variable display of the changing second special symbol is stored as the start memory. And, in the second special symbol starting memory area (1) ~ the second special symbol starting memory area (4), a special symbol game corresponding to the variable display (holding ball) of the second special symbol for 4 times being held Data (information) is stored as a starting memory. The data contained in the start memory stored in each second special symbol start storage area is, for example, data such as a jackpot determination random number value and a jackpot symbol random number value acquired at the time of winning of the second start port 45 .

  After the processing of S34, the main CPU 71 conducts special symbol storage transfer processing based on the second start hole winning (S35). In this process, the main CPU 71 transfers (stores) data of the second special symbol start storage areas (1) to (4) to the second special symbol start storage areas (0) to (3), respectively. Then, after the process of S35, the main CPU 71 performs a process of S40 described later.

  Here, if the main CPU 71 determines that the number of held second starting hole wins is "0" (S33 is YES), the main CPU 71 returns to the process of S33 again. It is determined whether or not the reserved number (first start memorized number) of the first start opening prize (variable display of the first special symbol) is “0” (S36).

  In S36, when the main CPU 71 determines that the number of held first starting hole wins is “0” (when the determination in S36 is YES), the main CPU 71 performs a demonstration display process (S37). Then, after the process of S37, the main CPU 71 ends the special symbol storage check process, and returns the process to the special symbol control process (see FIG. 63).

  In the demonstration display process of S37, the main CPU 71 sets a demonstration display permission value in the main RAM 73. That is, the main CPU 71 causes a state in which the number of reserved first start hole wins and the number of reserved second start hole wins is “0” (state in which the special symbol game start memory is “0”) is a predetermined time (for example, 30 sec), the predetermined value is set as the demonstration display permission value. When the demonstration display permission value is a predetermined value in the demonstration display process of S37, the main CPU 71 sets the demonstration display command data in the main RAM 73. Then, the demonstration display command data is transmitted from the main CPU 71 of the main control circuit 70 to the host control circuit 210 in the sub control circuit 200. When receiving the demonstration display command data, the sub control circuit 200 causes the display area 13a of the display device 13 to display a demonstration screen.

  On the other hand, when the main CPU 71 determines in S36 that the number of pending positions for the first starting hole winning is not "0" (when the determination in S36 is NO), the main CPU 71 corresponds to the number of pending first starting holes for winning. The value of the first start memory number is subtracted by “1” (S38).

  In the present embodiment, the main CPU 71 determines whether data is stored in the first special symbol start storage area (0) to the first special symbol start storage area (4) provided in the main RAM 73, and It is determined whether or not there is a start-up memory of a special symbol game corresponding to the variable display of the first special symbol being changed or suspended. In the first special symbol start storage area (0), data (information) of the special symbol game corresponding to the variable display of the first special symbol being changed is stored as the start memory. And, in the first special symbol starting memory area (1) ~ the first special symbol starting memory area (4), a special symbol game corresponding to the variable display (holding ball) of the first special symbol for 4 times being held Data (information) is stored as a starting memory. The data contained in the start memory stored in each first special symbol start storage area is, for example, data such as a jackpot determination random number value and a jackpot symbol random number value acquired at the time of winning of the first start port 44 .

  After the processing of S38, the main CPU 71 conducts special symbol storage transfer processing based on the first start hole winning (S39). In this process, the main CPU 71 transfers (stores) data of the first special symbol start storage areas (1) to (4) to the first special symbol start storage areas (0) to (3), respectively. Then, after the process of S39, the main CPU 71 performs a process of S40 described later.

  Next, after the processing of S35 or S39, the main CPU 71 determines whether or not the value of the time-short state variation frequency counter is “0” (S40).

  In S40, when the main CPU 71 determines that the value of the hour reduction state fluctuation number counter is “0” (when the determination in S40 is YES), the main CPU 71 performs the processing of S44 described later. On the other hand, when the main CPU 71 determines in S40 that the value of the short-time state variation number counter is not “0” (when S40 is NO), the main CPU 71 decrements the value of the short-time state variation number counter by “1”. To do (S41).

  After the process of S41, the main CPU 71 determines whether or not the value of the short-time state variation number counter is “0” (S42).

  In S42, when the main CPU 71 determines that the value of the time saving state fluctuation number counter is not “0” (when the determination in S42 is NO), the main CPU 71 performs the processing of S44 described later. On the other hand, when the main CPU 71 determines that the value of the time saving state variation counter is “0” in S42 (when the determination in S42 is YES), the main CPU 71 sets “0” in the time saving flag (S43). ).

  After S43, if S40 is YES or S42 is NO, the main CPU 71 sets a value ("01") indicating the special symbol variation time management process in the control state flag (S44). Further, in this process, the main CPU 71 transmits the hold subtraction command and the special symbol effect start command to the sub control circuit 200.

  Next, the main CPU 71 conducts jackpot determination processing (S45). In this process, the main CPU 71 determines (determines) which of “big hit”, “small hit”, and “losing” has been won by lottery based on the jackpot determination random number value acquired at the starting opening winning combination.

  Next, the main CPU 71 clears information (data) of the storage area used for the previous variable display (S46). Next, the main CPU 71 sets the variation time corresponding to the determined variation pattern of the special symbol in the waiting time timer (S47). Then, after the process of S47, the main CPU 71 ends the special symbol storage check process, and returns the process to the special symbol control process (see FIG. 63).

[Special symbol display time management process]
Next, with reference to FIG. 65, the special symbol display time management process performed in S14 in the special symbol control process (see FIG. 63) will be described. In addition, FIG. 65 is a flowchart which shows the procedure of the special symbol display time management process in this embodiment.

  First, the main CPU 71 determines whether or not the control state flag is a value ("02") indicating a special symbol display time management process (S51). In S51, when the main CPU 71 determines that the control status flag is not the value ("02") indicating the special symbol display time management process (when the determination of S51 is NO), the main CPU 71 conducts special symbol display time management process The process is returned to the special symbol control process (see FIG. 63).

  On the other hand, when the main CPU 71 determines that the control status flag is the value indicating the special symbol display time management process ("02") in S51 (when the determination of S51 is YES), the main CPU 71 determines that the waiting time timer is It is determined whether or not the value (waiting time) is “0” (S52). In this process, the main CPU 71 determines whether or not the waiting time (variation start waiting time) set in the waiting time timer has been settled.

  When the main CPU 71 determines in S52 that the value of the waiting time timer is not “0” (when S52 is NO), the main CPU 71 ends the special symbol display time management process, and performs the special symbol control process. Return to (see FIG. 63). On the other hand, when the main CPU 71 determines in S52 that the value of the waiting time timer is “0” (when S52 is YES), the main CPU 71 determines whether or not the special symbol game is “big hit”. A determination is made (S53). Also, in this process, the main CPU 71 simultaneously transmits a special effect stop command to the sub control circuit 200.

  In S53, when the main CPU 71 determines that the special symbol game is not “big hit” (when S53 is NO), the main CPU 71 sets a value (“08”) indicating the special symbol game end process in the control state flag. Set (S54). After the process of S54, the main CPU 71 ends the special symbol display time management process, and returns the process to the special symbol control process (see FIG. 63).

  On the other hand, when the main CPU 71 determines in S53 that the special symbol game is a "big hit" (when the determination in S53 is YES), the main CPU 71 sets a big hit flag to an on state (S55). The jackpot flag is a flag indicating whether or not to play a jackpot game.

  Next, the main CPU 71 clears the value of the time saving state change frequency counter, the value of the time saving flag, and the value of the probability change flag (S56). Next, the main CPU 71 sets a value (“03”) indicating a big hit start interval management process in the control state flag (S57).

  Next, the main CPU 71 sets the jackpot start interval time (for example, 5000 msec) corresponding to the special symbol (first special symbol or second special symbol) in the waiting time timer (S58). Next, the main CPU 71 sets a big hit start command (special symbol start display command) corresponding to the special symbol in the main RAM 73 (S59). Further, in this process, the main CPU 71 simultaneously transmits a special symbol hit start display command to the sub control circuit 200.

  Next, the main CPU 71 sets the round number display LED pattern flag to the on state (S60). The number-of-rounds display LED pattern flag is a flag indicating whether or not to display the number of remaining rounds in a predetermined pattern. Then, after the process of S60, the main CPU 71 ends the special symbol display time management process, and returns the process to the special symbol control process (see FIG. 63).

[Big hit end interval processing]
Next, with reference to FIG. 66, the big hit end interval process performed in S19 in the special symbol control process (see FIG. 63) will be described. FIG. 66 is a flowchart showing the procedure of the big hit end interval process according to the present embodiment.

  First, the main CPU 71 determines whether or not the control state flag is a value (“07”) indicating the big hit end interval process (S71).

  When the main CPU 71 determines in S71 that the control state flag is not a value indicating the jackpot end interval process (“07”) (when S71 is NO), the main CPU 71 ends the jackpot end interval process and performs the process. Is returned to the special symbol control process (see FIG. 63). On the other hand, when the main CPU 71 determines in S71 that the control state flag is a value indicating the jackpot end interval process ("07") (when S71 is YES), the main CPU 71 determines that the value of the waiting time timer is It is determined whether it is "0" (S72). In this process, the main CPU 71 determines whether or not the big hit end interval time set in the waiting time timer has been consumed.

  In S72, when the main CPU 71 determines that the value of the waiting time timer is not “0” (when S72 is NO), the main CPU 71 ends the big hit end interval process, and the process is a special symbol control process (FIG. 63). On the other hand, when the main CPU 71 determines in S72 that the value of the waiting time timer is “0” (when S72 is YES), the main CPU 71 clears the special winning opening opening number display LED pattern flag ( S73).

  Next, the main CPU 71 clears the round number distribution flag (sets it to "0") (S74).

  Next, the main CPU 71 sets a value (“08”) indicating the special symbol game end process in the control state flag (S75). Further, in this processing, the main CPU 71 simultaneously transmits a special symbol hit end display command to the sub control circuit 200. Next, the main CPU 71 clears the big hit flag (S76).

  Next, the main CPU 71 refers to the jackpot type determination table (see FIG. 13 to FIG. 16), and sets the value of the probability change flag based on the gaming state at the time of jackpot winning and the type of the jackpot selection symbol command (S77). . Next, the main CPU 71 refers to the big hit type determination table (see FIGS. 13 to 16), and sets the value of the short time flag based on the gaming state at the time of the big win and the type of the big hit selection symbol command (S78). .

  Next, the main CPU 71 determines whether the value of the time saving flag is “1” (the time saving flag is in the on state) (S79). In S79, when the main CPU 71 determines that the value of the time saving flag is not “1” (when the determination in S 79 is NO), the main CPU 71 ends the big hit end interval processing, and the processing is a special symbol control processing (FIG. 63) Return to).

  On the other hand, when the main CPU 71 determines that the value of the time reduction flag is “1” in S79 (when S79 is YES), the main CPU 71 refers to the big hit type determination table (see FIGS. 13 to 16). Then, based on the gaming state at the time of big hit winning and the type of big hit selection symbol command, the value of the corresponding time saving number is set in the time saving state variation number counter (S80). Then, after the processing of S80, the main CPU 71 ends the jackpot end interval processing and returns the processing to the special symbol control processing (see FIG. 63).

[Normal symbol control process]
Next, with reference to FIG. 67, the normal symbol control process performed in S4 in the main control main process (see FIG. 62) will be described. FIG. 67 is a flowchart showing the procedure of the normal symbol control process in the present embodiment.

  67, the numerical values in parentheses (“00” to “04”) written in parallel with the reference numerals of the respective processing steps in the flowchart shown in FIG. 67 indicate the normal symbol control state flag, and this normal symbol control state flag is the main RAM 73. Stored in a predetermined storage area. The main CPU 71 advances the normal symbol game by executing each processing step corresponding to the value of the normal symbol control state flag.

  First, the main CPU 71 loads a normal symbol control state flag (S91). In this process, the main CPU 71 reads the normal symbol control state flag stored in the main RAM 73. The main CPU 71 determines whether or not to execute various processes of S92 to S96 described later based on the value of the normal symbol control state flag loaded in S91. The normal control state flag indicates the game state of the normal symbol game, and enables execution of any one of the processes of S92 to S96.

  Further, the main CPU 71 executes the processing of each step at a predetermined timing determined according to the waiting time or the like set for each processing of S92 to S96. In the period before reaching the predetermined timing, other subroutine processing is executed without executing the processing of each step. Further, system timer interrupt processing (see FIG. 69 described later) described later is also executed at a predetermined cycle.

  Then, when the process of S91 ends, the main CPU 71 conducts a normal symbol storage check process (S92).

  In this process, when the normal symbol control state flag is a value (“00”) indicating the normal symbol storage check process, the main CPU 71 checks the number of holdings of the variable symbol variable display, and the number of holdings is “0”. If not, processing such as hit determination is performed. Further, in this process, the main CPU 71 sets a value (“01”) indicating a normal symbol fluctuation time monitoring process (S93) described later in the normal symbol control state flag, and sets the fluctuation time determined in the current process. Set to the wait timer. That is, by this processing, after the variation time of the normal symbol determined in the processing of S92 has elapsed, it is set so that the below-mentioned normal symbol variation time monitoring processing is executed.

  Next, the main CPU 71 conducts normal symbol fluctuation time monitoring processing (S93). In this process, the main CPU 71 indicates that the normal symbol control state flag is a value (“01”) indicating the normal symbol variation time monitoring process. The value ("02") indicating the normal symbol display time monitoring process (S94) is set, and the wait time after decision (for example, 0.5 sec) is set in the wait time timer. That is, by this process, after the waiting time after the determination set in the process of S93 has elapsed, it is set so that the below-mentioned normal symbol display time monitoring process is executed.

  Next, the main CPU 71 conducts normal symbol display time monitoring processing (S94). In this process, the main CPU 71 determines a hit when the normal symbol control state flag is a value ("02") indicating the normal symbol display time monitoring process and the waiting time after determination set in the process of S93 has elapsed. It is determined whether the result of is a hit. If the result of the hit determination is “hit”, the main CPU 71 conducts a normal electric accessory release setting process, and the normal symbol control state flag indicates a value indicating a normal electric accessory release process (S95) described later (S95). “03”) is set. That is, by this processing, it is set so that the below-mentioned normal motor-operated combination release processing is executed.

  On the other hand, when the result of the hit determination is not “hit”, the main CPU 71 sets a value (“04”) indicating a normal symbol game end process (S96) described later in the normal symbol control state flag. That is, in this case, it is set such that a normal symbol game end process described later is executed.

  Next, when the main CPU 71 determines in S94 that the result of the hit determination is "hit", the main CPU 71 conducts a normal electric combination release process (S95). In this process, the main CPU 71 has received a predetermined number of start prizes during the opening of the ordinary electric accessory 46 when the ordinary symbol control state flag is a value ("03") indicating the ordinary electric accessory release process. It is determined whether or not one of the following conditions and the condition that the opening upper limit time of the normal motorized symbol 46 has passed (the normal electric power releasing timer is “0”) is satisfied.

  In S95, when the above one condition is satisfied, the main CPU 71 updates the variable positioned in the main RAM 73 in order to close the blade member, which is the normal motorized product 46. Then, the main CPU 71 sets a value (“04”) indicating a normal symbol game end process (S96) described later to the normal symbol control state flag. That is, by this processing, it is set so that the below-mentioned normal symbol game end processing is executed.

  Next, the main CPU 71 conducts normal symbol game end processing (S96). In this process, when the normal symbol control state flag is a value indicating the normal symbol game end process (“04”), the main CPU 71 decreases the data indicating the number of hold of the variable symbol variable display by “1”. Update the memory. Further, the main CPU 71 updates the normal symbol storage area in order to perform variable display of the next normal symbol. Further, the main CPU 71 sets a value ("00") indicating the normal symbol storage check process in the normal symbol control state flag. That is, by this processing, after the processing of S96, the above-described normal symbol storage check processing (S92) is set to be executed.

  Then, after the processing of S96, the main CPU 71 ends the normal symbol control processing, and shifts the processing to S5 of the main control main processing (see FIG. 62).

[Power-on processing]
Next, power-on processing executed by the main CPU 71 will be described with reference to FIG. FIG. 68 is a flowchart showing the procedure of the power-on process in this embodiment.

  First, the main CPU 71 sets a predetermined initial value in the stack pointer (S101). Next, the main CPU 71 determines whether the power failure detection signal is in the OFF state (LOW level) (S102). In this determination process, when the power failure detection signal is in the OFF state, this corresponds to the case where the power failure detection process can not be performed. That is, in the state in which the interruption can be detected, the interruption detection signal is turned on.

  In S102, when the main CPU 71 determines that the power interruption detection signal is in the OFF state (LOW level) (when S102 is YES), the main CPU 71 sets the power interruption detection signal in the ON state (HIGH level). Until the determination process of S102 is repeated. On the other hand, when the main CPU 71 determines in S102 that the power interruption detection signal is not in the OFF state (LOW level) (when S102 is NO), the main CPU 71 determines that the built-in RWM (Read Write Memory), that is, the main An access permission process to the RAM 73 is performed (S103). Further, in this process, the main CPU 71 performs various initial setting processes such as an initialization process of the work area of the main RAM 73, for example.

  Next, the main CPU 71 executes a sub control reception acceptance wait process (S104). In this process, the main CPU 71 waits until the operation state of the sub control circuit 200 becomes ready to receive data such as command data, for example. Next, the main CPU 71 executes initialization processing of a device incorporating the CPU (S105).

  Next, the main CPU 71 determines whether or not the backup clear signal is in the on state (HIGH level) (S106). Specifically, the main CPU 71 determines whether the backup clear switch 121 (see FIG. 5) is on.

  In S106, when the main CPU 71 determines that the backup clear signal is in the on state (when the determination in S106 is YES), the main CPU 71 performs the processing of S113 described later. On the other hand, when the main CPU 71 determines that the backup clear signal is not in the on state in S106 (when the determination in S106 is NO), the main CPU 71 sets the power failure detection flag (the power failure detection flag is It is determined whether or not it is "1" (S107).

  In S107, when the main CPU 71 determines that the power failure detection flag is not set (when the determination in S107 is NO), the main CPU 71 performs the processing of S113 described later. On the other hand, when the main CPU 71 determines that the power failure detection flag is set in S107 (when the determination in S107 is YES), the main CPU 71 performs a damage check process on the work area (S108). In this process, the main CPU 71 checks whether the work area is damaged or not based on a checksum value or the like.

  After the process of S108, the main CPU 71 determines whether the work area is normal based on the result of the damage check process of the work area of S108 (S109). In S109, when the main CPU 71 determines that the work area is not normal (when the determination in S109 is NO), the main CPU 71 performs the processing of S113 described later.

  On the other hand, when the main CPU 71 determines in S109 that the work area is normal (when the determination in S109 is YES), the main CPU 71 initializes the work area where the initial value needs to be set at the time of power failure recovery. (S110). Next, the main CPU 71 conducts notification setting processing of the high probability gaming state at the time of power failure recovery (S111).

  After the processing of S111, the main CPU 71 transmits a power failure recovery command to the sub control circuit 200 (S112). In this process, the main CPU 71 transmits the first power failure recovery command and the second power failure recovery command (see FIGS. 25 and 26) described above to the sub control circuit 200. Then, after the process of S112, the main CPU 71 ends the power-on process.

  Here, it returns to the process of S106, S107, or S109 again, and when S106 is YES determination or when S107 or S109 is NO determination, that is, the pachinko gaming machine 1 is returned to the state before the power failure detection. If not, the main CPU 71 clears all the work areas (S113).

  Next, the main CPU 71 conducts an initial setting process of a work area that requires setting of initial values when initializing the main RAM 73 (S114). Next, the main CPU 71 transmits an initialization command for the main RAM 73 to the sub control circuit 200 (S115). Then, after the process of S115, the main CPU 71 ends the power-on process.

[System timer interrupt processing]
In the pachinko gaming machine 1 of the present embodiment, the main CPU 71 interrupts the main processing at a predetermined cycle and executes the system timer interrupt processing even while the main processing is being performed. Specifically, the main CPU 71 executes system timer interrupt processing in response to a clock pulse generated from the clock generation circuit 74 in a predetermined cycle (for example, 2 msec). Here, a system timer interrupt process executed by the main CPU 71 will be described with reference to FIG. FIG. 69 is a flowchart showing the procedure of the system timer interrupt process in this embodiment.

  First, the main CPU 71 saves data (information) of each register (S121). Next, the main CPU 71 performs random number update processing (S122). In this process, the main CPU 71 updates various random numbers extracted from a big hit determination counter, a symbol determination counter, a hit determination counter, a fall determination counter, a variation pattern determination counter, an effect pattern determination counter, and the like. . The jackpot determination counter and the symbol determination counter lack fairness when the update timing of the counter value is indefinite. Therefore, the jackpot determination counter and the symbol determination counter are updated at a timing determined in a cycle of 2 msec in order to secure fairness.

  Next, the main CPU 71 performs switch input detection processing (S123). In this process, the main CPU 71 detects winning or passing to the various starting openings, various winning openings, and the ball passing detector 43. The details of the switch input detection process will be described later with reference to FIG. 70 described later.

  Next, the main CPU 71 conducts timer update processing (S124). Specifically, the main CPU 71 controls various timers such as a waiting time timer for synchronizing the main control circuit 70 and the sub control circuit 200, and a special winning opening opening time timer for measuring the opening time of the special winning opening. Update processing is performed.

  Next, the main CPU 71 executes command output processing (S125). In this process, the main CPU 71 outputs various commands such as a winning command and a fluctuation command to the host control circuit 210 of the sub control circuit 200.

  Next, the main CPU 71 conducts game information output processing (S126). In this process, the main CPU 71 outputs various information relating to the game processed by the main control circuit 70, the sub control circuit 200, the payout / fire control circuit 123 and the like to the hall computer of the game arcade.

  Next, the main CPU 71 restores the data of each register saved in S121 (S127). After the process of S127, the main CPU 71 ends the system timer interrupt process.

[Switch input detection processing]
Next, with reference to FIG. 70, the switch input detection process performed in S123 in the system timer interrupt process (see FIG. 69) will be described. FIG. 70 is a flowchart showing the procedure of the switch input detection process according to this embodiment.

  First, the main CPU 71 performs a start opening winning detection process (S131). In this process, the main CPU 71 determines whether the gaming ball has entered (passed) the first starting opening 44 or the second starting opening 45. That is, the main CPU 71 detects whether or not the winning of the gaming ball has been detected by the first starting opening winning ball sensor 44a or the second starting opening winning ball sensor 45a. The details of the start opening winning detection process will be described later with reference to FIG. 71 described later.

  Next, the main CPU 71 conducts a general winning opening detection process (S132). In this process, the main CPU 71 determines whether the game ball has entered the general winning opening 51 or 52. That is, the main CPU 71 detects whether or not the winning of the gaming ball has been detected by the general winning ball sensor 51a or 52a. Then, when a winning of the gaming ball to the general winning opening 51 or 52 is detected, the main CPU 71 performs various predetermined processing corresponding to the winning.

  Next, the main CPU 71 performs a special winning opening passing detection process (S133). In this process, the main CPU 71 determines whether the game ball has entered the first large winning opening 53 or the second large winning opening 54. That is, the main CPU 71 detects whether or not the winning of the game ball has been detected by the first large winning opening solenoid 53b or the second large winning opening solenoid 54b. Then, when a winning of the gaming ball to the first big winning opening 53 or the second big winning opening 54 is detected, the main CPU 71 performs various predetermined processing corresponding to the winning.

  Next, the main CPU 71 conducts gate passage detection processing (S134). In this process, the main CPU 71 determines whether the gaming ball has passed the ball passage detector 43 or not. That is, the main CPU 71 detects whether or not passage of the game ball is detected by the passage ball sensor 43a. Next, when it is detected that the gaming ball has passed the ball passage detector 43, the main CPU 71 executes various predetermined processes corresponding to the passage. Then, after the process of S134, the main CPU 71 ends the switch input detection process, and shifts the process to S124 of the system timer interrupt process (see FIG. 69).

[Starting mouth winning detection process]
Next, with reference to FIG. 71, the starting opening winning combination detection process performed in S131 in the switch input detection process (see FIG. 70) will be described. FIG. 70 is a flowchart showing the procedure of the starting opening winning detection process in the present embodiment.

  First, the main CPU 71 determines whether or not the winning of the game ball to the first starting opening 44 has been detected based on the output signal of the first starting opening winning ball sensor 44a (S141).

  In S141, when the main CPU 71 determines that the winning of the gaming ball to the first starting opening 44 is not detected (when the determination of S141 is NO), the main CPU 71 performs the processing of S149 described later. On the other hand, when the main CPU 71 determines that the winning of the game ball to the first starting opening 44 has been detected in S141 (when the determination of S141 is YES), the main CPU 71 pays out information corresponding to the first starting opening winning Are set in the main RAM 73 (S142). In the present embodiment, when the gaming ball wins the first starting opening 44, a predetermined number of gaming balls are paid out. Therefore, in the process of S142, payout information of a predetermined number of gaming balls is set.

  After the processing of S142, the main CPU 71 determines whether or not the number of reserved first winning opening winnings (variable display of the first special symbol) (number of holding balls) is less than "4" (S143).

  In S143, when the main CPU 71 determines that the number of held first starting hole wins is not less than “4” (when the determination of S 143 is NO), the main CPU 71 performs the processing of S 149 described later. On the other hand, when the main CPU 71 determines in S143 that the number of first start hole winnings held is less than "4" (when S143 is YES), the main CPU 71 determines the number of first starting holes winnings. A process of adding "1" is performed (S144).

  After the processing of S144, the main CPU 71 acquires various random values used for the lottery, and stores the acquired various random values in a predetermined area of the main RAM 73 (S145). Specifically, the main CPU 71 acquires various random values such as a jackpot determination random number value, a design random number value, a fall determination random number value, and the like.

  Next, the main CPU 71 performs a first special stop symbol determination process (S146). In this process, the main CPU 71 refers to the big hit random number determination table (first start port) (see FIG. 9) and the symbol determination table (first start port) (see FIG. 11), and determines the big hit determination obtained in S145. Based on the numerical value and the symbol random number value, it is determined whether or not "big hit", and in the case of "big hit", the big hit symbol (identification symbol for effect) to be displayed on the display screen of the display device 13. Make a selection (judgment).

  Next, the main CPU 71 performs a process for determining whether or not there is a fall (S147). In this process, the main CPU 71 conducts a fall lottery based on the fall determination random number value acquired in S145, and determines whether or not there is a fall. As a result, the main CPU 71 acquires the falling lottery information (“0”: no fall or “1”: with fall).

  Next, the main CPU 71 sets the pending addition command data at the time of winning the first start opening in the main RAM 73 (S148).

  In this process, the main CPU 71 determines the big hit random number determination table (first start port) (see FIG. 9), the symbol determination table (first start port) (see FIG. 11), and the big hit type determination table (see FIGS. 13 to 16). ) And the winning time effect information determination table (see FIG. 17), the gaming state (“normal”, “certain change”, “time reduction”), winning classification (“big hit”, “small hit”, “loss”) "), Number of starting memory (number of first special symbol held), symbol designation command, jackpot selection symbol command, winning presentation effect information, jackpot determination result information, information such as fall lottery information, hold addition command Determine the information (transmission content) to be included in.

  In this case, the gaming state is obtained by referring to the values of the probability change flag and the time saving flag, and the winning type is obtained by referring to the big hit random number determination table (first start port) (see FIG. 9). The symbol designation command and the big hit selection symbol command are acquired by referring to the symbol determination table (first start port) (see FIG. 11), and the winning effect information is the winning effect information determination table (see FIG. 17). It is acquired by referring to. Further, the result information of the jackpot determination is acquired in the process of S146, and the falling lottery information is acquired in the process of S147.

  In the present embodiment, in the process of S148, a hold addition command at the time of winning the first start opening is transmitted from the main CPU 71 to the sub control circuit 200 (host control circuit 210). Then, based on the hold addition command at the time of the first start hole winning, the sub control circuit 200 selects the effect pattern of the hold effect and the prefetch effect.

  After the processing of S148, or if S141 or S143 is NO, the main CPU 71 detects a winning of the gaming ball to the second starting opening 45 based on the output signal of the second starting opening winning ball sensor 45a It is determined whether or not it is (S149).

  In S149, when the main CPU 71 determines that the winning of the game ball to the second starting opening 45 is not detected (when the S149 is NO determination), the main CPU 71 ends the starting opening winning detection processing, and processing Is shifted to S132 of the switch input detection process (see FIG. 70). On the other hand, when the main CPU 71 determines in S149 that the game ball has been detected to win the second starting opening 45 (when the determination in S149 is YES), the main CPU 71 pays out information corresponding to the second starting opening winning Are set in the main RAM 73 (S150). In the present embodiment, when the gaming ball wins the second starting opening 45, a predetermined number of gaming balls are paid out. Therefore, in the process of S150, payout information for a predetermined number of game balls is set.

  After the processing of S150, the main CPU 71 determines whether or not the reserved number (the number of reserved balls) of the second start opening winning (variable display of the second special symbol) is less than “4” (S151).

  In S151, when the main CPU 71 determines that the number of held second starting hole winnings is not less than “4” (when S151 is NO), the main CPU 71 ends the starting opening winning detection process and switches the processing. The process proceeds to S132 of the input detection process (see FIG. 70). On the other hand, when the main CPU 71 determines in S151 that the number of reserved second start hole winnings is less than “4” (when the determination of S151 is “YES”), the main CPU 71 determines the number of reserved second starting port winnings. A process of adding "1" is performed (S152). After the processing of S152, the main CPU 71 acquires various random number values used for the lottery, and stores the acquired various random number values in a predetermined area of the main RAM 73 (S153). Specifically, the main CPU 71 acquires various random values such as a jackpot determination random number value, a design random number value, a fall determination random number value, and the like.

  Next, the main CPU 71 performs a second special stop symbol determination process (S154). In this process, the main CPU 71 refers to the big hit random number determination table (second start opening) (see FIG. 10) and the symbol determination table (second start opening) (see FIG. 12), and the big hit determination randomness obtained in S153. Based on the numerical value and the symbol random number value, it is determined whether or not "big hit", and in the case of big hit, selection of the big hit symbol (identification symbol for effect) to be displayed on the display screen of the display device 13 Make a judgment).

  Next, the main CPU 71 performs a process for determining whether or not there is a fall (S155). In this process, the main CPU 71 conducts a fall lottery based on the fall determination random number value acquired in S153, and determines whether or not a fall occurs. As a result, the main CPU 71 acquires the falling lottery information (“0”: no fall or “1”: with fall).

  Next, the main CPU 71 sets the pending addition command data at the time of the second start opening winning in the main RAM 73 (S156).

  In this process, the main CPU 71 determines the big hit random number determination table (second start opening) (see FIG. 10), the symbol determination table (second start opening) (see FIG. 12), and the big hit type determination table (see FIGS. 13 to 16). ) And the winning time effect information determination table (see FIG. 17), gaming state (“normal”, “certain change”, “time reduction”), winning classification (“big hit”, “missing”), start memory Information to be included in the pending addition command based on information such as number (second special symbol pending number), symbol specifying command, jackpot selection symbol command, winning presentation information, jackpot determination result information, falling lottery information and so on Determine the transmission content).

  In this case, the gaming state is acquired by referring to the values of the probability change flag and the time saving flag, and the winning type is acquired by referring to the big hit random number determination table (second starting port) (see FIG. 10). The symbol designation command and the jackpot selection symbol command are obtained by referring to the symbol determination table (second starting opening) (see FIG. 12), and the prize effect information is a prize effect information determination table (see FIG. 17). It is acquired by referring to. Moreover, the result information of the jackpot determination is acquired in the process of S154, and the falling lottery information is acquired in the process of S155.

  Further, in the present embodiment, in the process of S156, the hold addition command at the time of the second start opening winning is transmitted from the main CPU 71 to the sub control circuit 200 (host control circuit 210). The sub control circuit 200 selects the effect pattern of the on-hold effect and the pre-read effect on the basis of the on-hold addition command at the time of winning at the second starting opening. Then, after the processing of S156, the main CPU 71 ends the starting hole winning detection processing, and shifts the processing to S132 of the switch input detection processing (see FIG. 70).

<Description of operation of sub control circuit>
Next, contents of various processes executed by various control circuits in the sub-board 202 of the sub-control circuit 200 will be described with reference to FIGS. The sub control circuit 200 receives various commands transmitted from the main control circuit 70 and performs various processes based on the various commands.

[Sub control main processing]
First, sub-control main processing executed by host control circuit 210 will be described with reference to FIG. FIG. 72 is a flowchart showing the procedure of the sub control main process in the present embodiment. The sub control main process is a process that is started when the power is turned on.

  First, the host control circuit 210 performs an initialization process (S201). In this process, the host control circuit 210 performs various initial setting processes such as hardware initialization, device initialization, application (various processing) initialization, backup data restoration initialization, and the like. Details of the initialization process will be described later with reference to FIGS. 73 and 74 described later.

  Next, the host control circuit 210 clears the counter of the watchdog timer (S202). At the time of start-up, the reset time (for example, 200 msec) of the watchdog timer is set, and thereafter, when the service pulse is not written (at time-out), the power-off process is started. Also, the timing to clear the watchdog timer counter is at the start of main loop processing (processing of S202 to S212) in the sub control main processing, at the start of device initialization processing, at the start of application initialization processing, and at power failure It is at the start of the process.

  Next, the host control circuit 210 performs operation means input processing (S203). In this process, the host control circuit 210 performs a process for determining whether or not an operation has been performed on an operation means such as a button or a jog dial by the player, and an operation content information acquisition process. Details of the operation means input process will be described later with reference to FIGS. 78 to 80 described later.

  Next, the host control circuit 210 performs a main / sub-command control process (S204). In this processing, the host control circuit 210 performs command data reading processing (command reception processing) when command data is received from the main CPU 71 and command data storage processing (reception data storage processing) in the sub work RAM 210a. The details of the main-sub command control process will be described later with reference to FIGS. 81 and 82 described later.

  Next, the host control circuit 210 performs command analysis processing (S205). In this process, the host control circuit 210 analyzes the contents of the command stored in the sub work RAM 210a and acquires various types of information included in the command. Details of the command analysis processing will be described later with reference to FIG. 83 described later.

  Next, the host control circuit 210 performs animation request construction processing (S206). In this process, the host control circuit 210 generates an animation request necessary for effect control using the display device 13, and based on the animation request (corresponding to the animation request, the animation request is And various requests (sound request, lamp request and feature) for operating various rendering devices that can be expressed in correspondence with rendering control (display) on the display device 13 executed based on the animation request Generate a request). Details of the animation request construction process will be described later with reference to FIG.

  In the present embodiment, as described above, the number of command packets (number of bytes) differs depending on the type of command. When the host control circuit 210 receives a plurality of command data, if the total number of packets of all the command data is equal to or less than the predetermined maximum number of packets, the above-described command analysis process (S205) and animation are performed. The request construction process (S206) is performed on the received plurality of command data in the same frame. However, when the total number of packets of the plurality of received command data exceeds the predetermined maximum number of packets, the command for the predetermined maximum number of packets among the plurality of received command data is commanded in the same frame Analysis processing (S205) and animation request construction processing (S206) are performed, and command analysis processing (S205) and animation request construction processing (S206) on command data for the remaining number of packets are performed in the next frame.

  Next, the host control circuit 210 determines whether or not the processes of S204 to S206 have been performed for the number of received commands (S207).

  In S207, when the host control circuit 210 determines that the processes in S204 to S206 have not been performed for the number of received commands (when S207 is NO), the host control circuit 210 returns the process to S204. Repeat the subsequent processing.

  On the other hand, if the host control circuit 210 determines in S207 that the processing of S204 to S206 has been performed for the number of received commands (if YES in S207), the host control circuit 210 performs drawing control processing (S208). ). In this process, the host control circuit 210 generates a moving image command and a drawing request based on the animation request, and transmits the generated moving image command and the drawing request generated in the previous frame to the display control circuit 230. At this time, the display control circuit 230 performs various processes for displaying (drawing) the effect image on the display device 13 based on the received moving image command and the drawing request. The details of the drawing control process will be described later with reference to FIGS. 86A and 86B described later.

  Next, the host control circuit 210 performs voice control processing (S209). In this process, the host control circuit 210 transmits a sound request (command) to the voice / LED control circuit 220. At this time, the sound / LED control circuit 220 performs sound reproduction control processing by the speaker 11 based on the received sound request. Details of the voice control process will be described later with reference to FIGS. 93A and 93B described later.

  Next, the host control circuit 210 performs lamp control processing (S210). In this process, the host control circuit 210 transmits a lamp request (command) to the voice / LED control circuit 220. At this time, the sound / LED control circuit 220 performs light emission control of the lamp group 18 based on the received lamp request. The details of the lamp control process will be described later with reference to FIGS. 94A and 94B described later.

  Next, the host control circuit 210 performs an accessory control process (S211). In this process, the host control circuit 210 transmits excitation data for driving the accessory 20 to the motor controller 270 (motor driver 271) via the I2C controller 261 based on the generated accessory request. Further, the motor driver 271 outputs the received excitation data to the corresponding motor 272 to drive the accessory 20. The details of the accessory control process will be described later with reference to FIG. 95 described later.

  Next, the host control circuit 210 determines whether or not the elapsed time from the start of the process of S202 described above is equal to or longer than a predetermined FPS cycle time (S212). In the present embodiment, the host control circuit 210 executes the series of processing (main loop processing) of S202 to S211 described above in a predetermined FPS cycle. For example, the FPS cycle is set to about 16.7 msec (60 FPS), about 33.3 msec (30 FPS), or the like.

  In S212, when the host control circuit 210 determines that the elapsed time from the start of the process of S202 is not equal to or longer than a predetermined FPS cycle time (when S212 is NO), the host control circuit 210 performs the determination process of S212. repeat. On the other hand, when the host control circuit 210 determines in S212 that the elapsed time from the start of the process of S202 is equal to or longer than the predetermined FPS cycle time (when S212 is YES), the host control circuit 210 performs the process. It returns to S202 and repeats the process after S202.

[Initialization process]
Next, with reference to FIGS. 73 and 74, the initialization process performed in S201 in the sub control main process (see FIG. 72) will be described. FIG. 73 is a diagram showing an outline of the operation of the initialization process in this embodiment, and FIG. 74 is a flowchart showing the procedure of the initialization process in this embodiment.

  When the pachinko gaming machine 1 is powered on, in the initialization process, as shown in FIG. 73, the host control circuit 210 not only itself but also various control circuits connected to the host control circuit 210 and the hardware of the controller. Initialize the hardware. Next, each control circuit or controller performs an initialization process for the corresponding device (the lamp group 18, the speaker 11, the display device 13, and the accessory 20). A specific procedure of this initialization process will be described below with reference to the flowchart of FIG.

  First, the host control circuit 210 determines whether or not power-on is detected (S221). If the host control circuit 210 determines in S221 that the power-on is not detected (S221 is NO), the host control circuit 210 repeats the determination process of S221. In the power on detection process, it is determined whether or not the power supply voltage supplied to the host control circuit 210 is stable. Therefore, when the power on is not detected, the power is actually turned on. Even if it exists, it represents that the power supply voltage supplied to the host control circuit 210 is not stable. Therefore, the power-on state detection process repeatedly performed in S221 is a standby process until the power supply voltage supplied to the host control circuit 210 is stabilized.

  On the other hand, when the host control circuit 210 determines that power on has been detected in S221 (when the determination in S221 is YES), the host control circuit 210 performs hardware initialization processing (S222). In this process, the host control circuit 210 is connected to the various control circuits (the circuit itself, the audio / LED control circuit 220 and the display control circuit 230) provided in the sub substrate 202, and the motor connected to the host control circuit 210. Initialize the hardware of the controller 270. Specifically, initialization processing of a register, setting processing of a control ROM, and the like in each control circuit and motor controller 270 are performed.

  Next, the host control circuit 210 clears the counter of the watchdog timer (S223).

  Next, various control circuits provided in the sub substrate 202, and the motor controller 270 perform initialization processing of the corresponding devices (S224). In this processing, the audio / LED control circuit 220 performs initialization / setting processing (including ROM access setting processing) of the driver (control program) of the lamp group 18 and the speaker 11. The display control circuit 230 also performs initialization / setting processing (including ROM access setting processing) of the driver of the display device 13. The motor controller 270 also performs initialization / setting processing (including ROM access setting processing) of the motor driver 271 for driving the accessory 20. Furthermore, in this embodiment, in this processing, the host control circuit 210 also performs initialization / setting processing (including ROM access setting processing) of a driver of an operation means (not shown).

  Next, the host control circuit 210 clears the counter of the watchdog timer (S225).

  Next, the host control circuit 210 performs application initialization processing (S226). In this process, the host control circuit 210 initializes various setting values used in various processes performed in the main loop process in the sub control main process described with reference to FIG. Specifically, the host control circuit 210 performs operation means input processing (S203), main / sub command control processing (S204), animation request construction processing (S206), drawing control processing (S208), voice control processing (S209). ) And initialization processing of various setting values used in each of the lamp control processing (S210).

  Next, the host control circuit 210 performs other various initialization processes (S227). In this process, the host control circuit 210 performs a backup recovery initialization process, an accessory control initialization process and an LED registration process. Details of the backup recovery initialization process will be described later with reference to FIG. 75 to be described later, and details of the accessory control initialization process will be described later with reference to FIG. 76 to be described later. Details of the registration process will be described later with reference to FIG. 77 described later.

  Then, after the processing of S227, the host control circuit 210 ends the initialization processing, and shifts the processing to S202 of the sub control main processing (see FIG. 72).

[Backup recovery initialization process]
Next, with reference to FIG. 75, backup restoration initialization processing performed in S227 in the initialization processing (see FIG. 74) will be described. FIG. 75 is a flow chart showing the procedure of backup restoration initialization processing in the present embodiment.

  First, the host control circuit 210 performs a process of checking the consistency of game data stored in the backup area of the SRAM 210b (S231). In the game data integrity check process, processes such as game data sum value determination, program version and magic code (generally called a magic number) check, and thumb check are performed. Note that “game data” includes information of parameters in the command, etc., and is a structure (a storage area or a variable) of data to be referred to in various lottery processes performed in the host control circuit 210 or animation request construction process. Aggregate)). Further, as described later, information on lottery results of various lottery processes (for example, effect patterns and the like) is also registered in the “game data”.

  Next, the host control circuit 210 determines whether or not the game data stored in the backup area of the SRAM 210b is consistent (S232). In this process, the host control circuit 210 determines whether or not game data is damaged.

  In S232, when the host control circuit 210 determines that the game data is consistent (when S232 is YES), the host control circuit 210 performs a process of S236 described later.

  On the other hand, when the host control circuit 210 determines in S232 that the game data is not consistent (when S232 is NO), the host control circuit 210 matches the game data stored in the mirroring area in the SRAM 210b. A sex check process is performed (S233). Next, the host control circuit 210 determines whether or not the game data stored in the mirroring area in the SRAM 210b is consistent (S234).

  In S234, when the host control circuit 210 determines that the game data is consistent (when S234 is YES), the host control circuit 210 performs the process of S236 described later.

  On the other hand, when the host control circuit 210 determines that the game data is not consistent (S234 is NO), the host control circuit 210 performs a game data initialization process (when the RAM is cleared) (S234). S235). In this process, the host control circuit 210 performs an initialization process when clearing the RAM area in which the game data is stored. Specifically, the host control circuit 210 initializes variables and the like to return the game data to the initial value (completely initializes the game data).

  After the process of S235, or when S232 or S234 is YES, the host control circuit 210 performs a game data initialization process (when the power is turned on) (S236).

  At this time, if the process of S236 is performed after the process of S232, the host control circuit 210 performs a process of restoring the game data stored in the backup area of the SRAM 210b. When the process of S236 is performed after the process of S234, the host control circuit 210 performs a restoration process of the game data stored in the mirroring area in the SRAM 210b. When the process of S236 is performed after the process of S235, the host control circuit 210 performs a process of restoring the completely initialized game data (initial value).

  Next, the host control circuit 210 backs up the game data restored by the process of S236 to the SRAM 210b (S237). After the process of S237, the host control circuit 210 ends the backup restoration initialization process.

[Function control initialization process]
Next, referring to FIG. 76, the item control initialization process performed in S227 in the initialization process (see FIG. 74) will be described. FIG. 76 is a flowchart showing the procedure of the item control initialization process in the present embodiment. In this process, initialization processing of various settings used in the accessory control process (S211) in the sub-control main process described with reference to FIG. 72 is performed.

  First, the host control circuit 210 sets “0” to the number of operations of the accessory 20 (S241). Next, the host control circuit 210 determines whether the motor 272 for driving the accessory 20 is at the initial position (S242). This determination process is performed based on the detection result of a sensor (not shown) provided to determine whether or not the motor 272 is in the initial position.

  In S242, when the host control circuit 210 determines that the motor 272 is in the initial position (when the determination in S242 is YES), the host control circuit 210 performs the determination process of S242 for all the motors 272 used. It is determined whether or not it has been received (S243).

  In S243, when the host control circuit 210 determines that the determination process of S242 has not been performed for all the motors 272 to be used (when S243 is NO), the host control circuit 210 moves the process to S241. The process returns to S241 and the subsequent steps are repeated.

  On the other hand, when the host control circuit 210 determines in S243 that the determination process of S242 has been performed on all the motors 272 to be used (when S243 is YES), the host control circuit 210 performs the power-on process. (S244). In the process of S244, the host control circuit 210 performs an operation confirmation process of the accessory 20 when the power is turned on. Specifically, the host control circuit 210 moves the accessory 20 to the maximum movable range or a predetermined movable range, and then returns the accessory 20 to the initial position. Then, after the process of S244, the host control circuit 210 performs a process of S249 described later.

  Here, returning to the processing of S242 again, in S242, when the host control circuit 210 determines that the motor 272 is not in the initial position (when S242 is NO), the host control circuit 210 has the number of operations. It is determined whether or not it is 10 times or more (S245). In this process, it is determined whether or not an abnormality (error) has occurred so as to cause the motor 272 to be inspected to stop operation, but the number of operations serving as a threshold for this error determination is not limited to ten times. It can be set arbitrarily.

  In S245, when the host control circuit 210 determines that the number of operations is 10 or more (when S245 is YES), the host control circuit 210 stops the operation of the motor 272 (error motor) in which the error occurs. It sets (S246). After the process of S246, the host control circuit 210 performs a process of S249 described later.

  On the other hand, when the host control circuit 210 determines in S245 that the number of operations is not 10 or more (when S245 is NO), the host control circuit 210 drives the motor 272 to be inspected to move to the initial position. (S247). Next, the host control circuit 210 adds “1” to the number of operations (S248). Then, after the processing of S248, the host control circuit 210 returns the processing to S242 and repeats the processing of S242 and subsequent steps.

  After the process of S244 or S246, the host control circuit 210 determines whether or not the operation stop of the error motor has been detected (S249).

  In S249, when the host control circuit 210 determines that the operation stop of the error motor is not detected (when S249 is NO), the host control circuit 210 shifts the operation state to the command reception standby state (S250). ). Then, after the process of S250, the host control circuit 210 ends the accessory control initialization process.

  On the other hand, when it is determined in S249 that the host control circuit 210 has detected the operation stop of the error motor (when S249 is YES), the host control circuit 210 sets a state in which an accessory request cannot be passed ( S251). In the present embodiment, the feature request is delivered between the processes related to feature control executed by the host control circuit 210.

  Next, the host control circuit 210 sets a state in which the motor is stopped until the power is turned on again and initialization of the accessory 20 is performed (S252). After the process of S252, the host control circuit 210 ends the accessory control initialization process.

[LED registration process]
Next, with reference to FIG. 77, the LED registration process performed in S227 in the initialization process (see FIG. 74) will be described. FIG. 77 is a flowchart showing the procedure of the LED registration process in the present embodiment.

  First, the host control circuit 210 registers hardware information of the channel of the LED 281 to be used (S261). Specifically, the host control circuit 210 sets the channel start port number, channel end port number, and channel start address of each SPI used.

  Next, the host control circuit 210 performs information setting of the LED driver 280 to be used (S262). Specifically, the host control circuit 210 registers a data table (the total number of lighting patterns of the LED 281, an information table corresponding to the luminance value output to the LED driver 280, etc.) in the LED driver 280. Then, after the process of S262, the host control circuit 210 ends the LED registration process.

[Operation means input processing]
Next, with reference to FIGS. 78 to 80, the operation means input process performed in S203 in the sub control main process (see FIG. 72) will be described. FIG. 78 is a diagram showing an operation outline of the operation means input process in the present embodiment. FIG. 79 is a flowchart showing a procedure of an operation input timer interrupt process performed in the operation means input process of this embodiment. FIG. 80 shows an operation input information acquisition process performed in the operation means input process. It is a flowchart which shows a procedure.

  In the operation means input process according to the present embodiment, when a player performs a predetermined operation related to performance on various operation means (not shown) provided in the pachinko gaming machine 1 (for example, buttons, jog dial, etc.), FIG. As shown, a signal corresponding to the predetermined operation (input signal in FIG. 78) is output from the driver of the operation means to the host control circuit 210. Then, the host control circuit 210 acquires information on an input state by a predetermined operation of the player based on the input signal.

  In the operation means input process, an operation input timer interrupt process performed as a timer interrupt process (measurement timer update process) with a period of 1 msec and a preset FPS period (for example, 16.7 msec or 33.3 msec) Operation input information acquisition processing to be performed is performed. Hereinafter, specific procedures of the operation input timer interrupt process and the operation input information acquisition process will be described with reference to the flowcharts of FIGS. 79 and 80, respectively.

(1) Operation Input Timer Interrupt Process In the operation input timer interrupt process, first, as shown in FIG. 79, the host control circuit 210 determines whether or not there is an operation input signal input from the driver of the operation means. (S271).

  When the host control circuit 210 determines in S271 that there is no input of the operation input signal (when the determination in S271 is NO), the host control circuit 210 ends the operation input timer interrupt process.

  On the other hand, when the host control circuit 210 determines in S271 that there is an input of the operation input signal (when the determination in S271 is YES), the host control circuit 210 determines the operation input state based on the operation input signal. The operation input state information is stored in the sub work RAM 210a (S272). Then, after the process of S272, the host control circuit 210 ends the operation input timer interrupt process.

(2) Operation Input Information Acquisition Processing In the operation input information acquisition processing, the host control circuit 210 refers to the sub work RAM 210a as shown in FIG. 80, and if the operation input status information is stored in the sub work RAM 210a. The information of the operation input state is acquired (S281). Then, after the process of S281, the host control circuit 210 ends the operation input information acquisition process.

  In the process of S281, for example, when the operation input is an operation input to the button, information such as the type of the operated button and the number of times of pressing is acquired as the information of the operation input state. Further, for example, when the operation input is an operation input to the jog dial, information such as the rotation direction, rotation angle, and rotation speed of the jog dial is acquired as the information of the operation input state. The information on the operation input state acquired in S281 is used when determining (setting) the contents of an effect (such as an effect of the effect) executed based on the player's operation input to the operation means.

[Main / Sub command control processing]
Next, with reference to FIGS. 81 and 82, the main / sub-command control process performed in S204 in the sub-control main process (see FIG. 72) will be described. FIG. 81 is a flowchart showing a procedure of command reception processing performed in the main / sub-command control processing of this embodiment, and FIG. 82 shows received data storage performed in the main / sub-command control processing. It is a flowchart which shows the procedure of a process.

  In the present embodiment, when a command is transmitted from the main control circuit 70 (main CPU 71) to the sub control circuit 200 (host control circuit 210) and the host control circuit 210 receives the command, the host control circuit 210 Inter-command control processing is performed as interrupt processing. Then, in the main-sub command control process, a command reception process performed as an interrupt process at the time of command reception and a reception data storage process performed after the command reception process are performed. Hereinafter, specific procedures of the command reception process and the reception data storage process will be described with reference to the flowcharts of FIGS. 81 and 82, respectively.

(1) Command reception processing (reception interrupt processing)
In the command reception process, first, when receiving a command transmitted from the main control circuit 70, the host control circuit 210 determines whether or not a command reception error has occurred as shown in FIG. 81 (S291).

  In S291, when the host control circuit 210 determines that a command reception error has not occurred (when S291 is NO), the host control circuit 210 performs the process of S293 described later. On the other hand, if the host control circuit 210 determines that a command reception error has occurred in S291 (if YES in S291), the host control circuit 210 performs error information setting processing (S292).

  After the processing of S292 or when S291 is NO, the host control circuit 210 performs command data reception processing (S293). In this processing, the host control circuit 210 writes the received command data in a ring buffer (see FIG. 29) in the host control circuit 210. If a command reception error occurs and error information is set in S292, set information of the received command data and error information is written to the ring buffer. Then, after the processing of S293, the host control circuit 210 ends the command reception processing.

(2) Received Data Storage Process In the received data storage process, as shown in FIG. 81, the host control circuit 210 stores the received command data written in the ring buffer by the above-described command receiving process in the sub work RAM 210a (S301). ). With this processing, the received command is stored in the sub work RAM 210a. In this process, the received command data is transferred byte by byte from the ring buffer to the sub work RAM 210a.

  Then, after the process of S301, the host control circuit 210 ends the received data storage process.

Command analysis processing
Next, with reference to FIG. 83, the command analysis processing performed in S205 in the sub control main processing (see FIG. 72) will be described. FIG. 83 is a flow chart showing the procedure of command analysis processing in the present embodiment. The command analysis processing described below is controlled by the host control circuit 210 (sub control circuit 200). That is, the host control circuit 210 (sub control circuit 200) doubles as means (command analysis means) for performing command analysis processing.

  First, the host control circuit 210 acquires the received command data stored in the sub work RAM 210a (S311). At this time, if there is error information associated with the received command data, the host control circuit 210 discards the received command data.

  Next, the host control circuit 210 specifies the type of the received command (S312). Further, in this process, the host control circuit 210 stores the information of the specified command type in the sub work RAM 210a. The command type is specified based on the information (preset value) stored in the command type portion (head byte area) of each command as described above (see FIGS. 22 to 27). For example, if the received command is a demonstration display command, the command type “80H” is stored in the sub work RAM 210a in the process of S312.

  Next, when the host control circuit 210 determines that there is no command type corresponding to the command received in the command type specifying process of S312, the host control circuit 210 discards the received command data (S313). Next, the host control circuit 210 checks the number of parameters included in the received command data, and discards the received command data if the number of parameters is different from the number of parameters corresponding to the specified command type (S314) .

  Next, the host control circuit 210 performs command parameter check processing (S315). In this processing, the host control circuit 210 checks the contents of information (hereinafter referred to as command parameters) in various parameters (see FIGS. 23 to 27) set for each command. Specifically, the host control circuit 210 checks, for example, the check of the always 0 area provided in the predetermined bit area in the parameter, the check of the effective range of each data stored in the parameter, and the stored data. Check the combination. The details of the command parameter check process will be described later with reference to FIG. 84 described later.

  Next, the host control circuit 210 determines whether the command parameter included in the received command is normal (S316). In this determination process, the host control circuit 210 determines whether the command parameter is normal (whether or not the command is valid) based on the result of the command parameter check process of S315.

  In S316, when the host control circuit 210 determines that the command parameter included in the received command is not normal (when S316 is NO), the host control circuit 210 discards the data of the received command (S317). Then, after the processing of S317, the host control circuit 210 ends the command analysis processing, and moves the processing to S206 of the sub control main processing (see FIG. 72).

  On the other hand, when the host control circuit 210 determines in S316 that the command parameter included in the received command is normal (when the determination in S316 is YES), the host control circuit 210 determines the command parameter (information such as game status). Is reflected (registered) in the game data (S318). In this process, the game data reflecting the command parameters is stored in a predetermined area in the sub work RAM 210a.

  Next, the host control circuit 210 performs a sub lottery process (S319). In this process, the host control circuit 210 acquires various random number values for effect, and performs a lottery process related to the determination of the effect contents corresponding to the command type of the received command.

  For example, when the received command is a special symbol effect start command, the host control circuit 210 performs a variable effect pattern (“EN00” to “EN44”) by a lottery process using the variable effect table (see FIG. 19). To decide. In addition, for example, when the received command is the hold addition command, the host control circuit 210 performs the lottery process using the hold effect table (see FIG. 20), the effect pattern relating to the color change effect of the hold symbol While "HE00" to "HE19" are determined, the effect pattern ("SE00" to "SE19") relating to the pre-reading effect is determined by the lottery process using the pre-reading effect table (see FIG. 21).

  Further, in the process of S319, the host control circuit 210 stores the lottery result of the sub lottery process (for example, information of the various effect patterns described above) in a predetermined area in the sub work RAM 210a.

  Next, the host control circuit 210 reflects (registers) the lottery result obtained by the sub lottery process of S319 in the game data stored in the sub work RAM 210a (S320).

  Next, the host control circuit 210 performs backup processing of the game data stored in the sub work RAM 210a (S321). By this processing, game data is stored in a predetermined area in the SRAM 210b and its mirroring area. The game data backed up in this process is referred to when the game data is damaged in the above-described backup recovery initialization process (see FIG. 75). Then, after the process of S321, the host control circuit 210 ends the command analysis process and moves the process to S206 of the sub-control main process (see FIG. 72).

  In the present embodiment, as described above, in the command analysis process, the received command may be discarded. However, the command is completely transmitted from the main CPU 71 to the host control circuit 210 before the discarded received command. If not, no animation request is generated, and a black image is displayed on the display screen of the display device 13. On the other hand, when a command is sent from the main CPU 71 to the host control circuit 210 before the discarded reception command, an animation request based on the discarded reception command is not generated, and the display screen of the display device 13 is discarded. The image generated by the animation request based on the previous command of the received command is maintained and displayed.

[Command parameter check processing]
Next, with reference to FIG. 84, the command parameter check process performed in S315 in the command analysis process (see FIG. 83) will be described. FIG. 84 is a flowchart showing the procedure of the command parameter check process in the present embodiment.

  First, the host control circuit 210 acquires the command type stored in the sub work RAM 210a, and sets a check item (masking) corresponding to the command type of the received command (S331).

  Next, the host control circuit 210 checks information of all the always zero areas included in the reception command (S332). In this process, when the host control circuit 210 detects that information other than “0” is stored in one or more constant 0 areas, the host control circuit 210 discards the received command. Further, when the zero region is not always provided in the received command to be analyzed, the process of S332 is not performed.

  Next, the host control circuit 210 checks whether the value of each piece of information included in the received command is within the corresponding predetermined range (S333). In the present embodiment, the value of the information stored in the parameter field portion of the received command is previously defined to be a value within a predetermined range (effective range). For example, special stop symbol designating information is stored in the second parameter storage area (8-bit area “b0” to “b7”) of the first power failure recovery command (see FIG. 25). The valid range of the value of the special stop symbol designation information is set to “0x00” to “0x20”. Then, in this process, when the host control circuit 210 determines that the value is not within the corresponding predetermined range in one or more pieces of information included in the reception command, the host control circuit 210 receives the reception. Discard the command.

  Next, the host control circuit 210 checks a combination of various information included in the received command (S334). In the present embodiment, even if the value of each information included in the received command is a value within the corresponding effective range, if a contradiction occurs in the combination of various information included in the command, the host control circuit 210 Discard the received command. For example, when the received command is a special symbol effect start command, the game status information included in the received command indicates “small hit”, and when the symbol designation command information is a big hit symbol, a combination of information in the command The host control circuit 210 discards the received special symbol presentation start command.

  After the process of S334, the host control circuit 210 ends the command parameter check process, and moves the process to S316 of the command analysis process (see FIG. 83).

  In the present embodiment, as described above, the command parameter check process is controlled by the host control circuit 210 (sub control circuit 200). That is, the host control circuit 210 (sub-control circuit 200) is a means (first command determination means) that performs a zero area check process in S332, and a validity check process for each information value included in the received command in S333. (Second command determination means), and also serve as a means (third command determination means) for checking the combination of various information included in the received command in S334.

[Animation request construction process]
Next, with reference to FIG. 85, the animation request construction process performed in S206 in the sub control main process (see FIG. 72) will be described. FIG. 85 is a flowchart showing the procedure of the animation request construction process in the present embodiment.

  First, the host control circuit 210 determines whether a command has been received from the main control circuit 70 (S341).

  In S341, when the host control circuit 210 determines that the command is not received from the main control circuit 70 (when the determination in S341 is NO), the host control circuit 210 performs the process of S352 described later. On the other hand, when the host control circuit 210 determines in S341 that the command has been received from the main control circuit 70 (when the determination in S341 is YES), the host control circuit 210 generates a power failure recovery command (first power failure recovery command). And determines whether or not the second power failure recovery command has been received (S342).

  In S342, when the host control circuit 210 determines that the power interruption return command has not been received (when S342 is NO), the host control circuit 210 performs the process of S346 described later. On the other hand, when it is determined in S342 that the host control circuit 210 has received the power failure recovery command (when S342 is YES), the host control circuit 210 determines that the power failure recovery command (second power failure recovery command). It is determined whether or not the status (internal control state) information included is in a fluctuating state (S343). Specifically, the host control circuit 210 determines whether "001" (special symbol fluctuation state) is set in the storage area of the internal control state number included in the second parameter in the second power failure recovery command. Determine. If the state at the time of detecting the power interruption is in the special symbol variation display, “001” is stored in the storage area of the internal control state number in the second parameter of the second power interruption recovery command at the time of the process of S343. "(Special symbol variation state) is set.

  In S343, when the host control circuit 210 determines that the status information included in the power interruption return command is not in a fluctuating state (when S343 is NO), the host control circuit 210 performs the process of S346 described later.

  On the other hand, if the host control circuit 210 determines in S343 that the status information included in the power failure recovery command is in a fluctuating state (if S343 is YES), the host control circuit 210 generates a simple mode object. A process is reserved (S344). Next, the host control circuit 210 performs termination processing for all objects (including resident objects) other than the simple mode object (S345). Then, after the process of S345, the host control circuit 210 performs the process of S350 described later.

  Here, returning to the processing of S342 or S343 again, if S342 or S343 is NO, the host control circuit 210 determines whether or not an object exists (S346).

  In S346, when the host control circuit 210 determines that the object does not exist (when S346 is NO), the host control circuit 210 performs the process of S350 described later. On the other hand, if the host control circuit 210 determines in S346 that the object exists (YES in S346), the host control circuit 210 determines whether or not the simple mode object exists (S347).

  In S347, when the host control circuit 210 determines that the simple mode object does not exist (S347 is NO), the host control circuit 210 performs the process of S349 described later. On the other hand, when the host control circuit 210 determines that the simple mode object exists in S347 (when S347 is YES), the host control circuit 210 uses a command (for example, a command indicating that the special symbol variation display ends) It is determined whether or not a special effect stop command, a special symbol end display command, etc.) have been received (S348).

  In S348, when it is determined that the host control circuit 210 has not received a command indicating that the special symbol variation display ends (when S348 is NO), the host control circuit 210 performs the process of S352 described later. Do. On the other hand, if it is determined in S348 that the host control circuit 210 has received a command indicating that the special symbol variation display is terminated (S348 is YES), that is, if the simple mode object is terminated, the host The control circuit 210 performs the process of S349 described later.

  When S347 is NO determination or S348 is YES determination, the host control circuit 210 performs an end process of the object already generated (S349). As a result of this process, unnecessary rendering operation (generation of a command indicating effect image reproduction, feature moving, sound reproduction, etc.) is ended. If the already generated object is a simple mode object, the rendering operation by the simple mode object is terminated by this process.

  After the processing of S349 or S345, or if S346 is NO, the host control circuit 210 generates an object corresponding to the command type based on the information of the command type stored in the sub work RAM 210a (S350). When this process is performed after the process of S345, the host control circuit 210 generates a simple mode object in the process of S350. In addition, at the time of initial power-on or at the end of the simple mode object, the host control circuit 210 also generates a resident object in the process of S350.

  Next, the host control circuit 210 performs object initialization processing (S351). In this process, the host control circuit 210 initializes a storage area used by the object.

  After the processing of S351, or if S341 or S348 is NO, the host control circuit 210 refers to the information of the game data stored in the sub work RAM 210a, and an object (for example, effect object, hold object, simple mode object Etc.), and the animation request is set in a predetermined area of the sub work RAM 210a (S352). By this processing, an animation request corresponding to command reception is generated.

  Next, based on the animation request, the host control circuit 210 generates a sound request, a lamp request, and an accessory request corresponding to the effect specified by the animation request (S353). Further, in this process, the host control circuit 210 sends the generated sound request, lamp request, and accessory request to the host in order to synchronize the video display operation with the sound reproduction operation, the light emission operation, and the accessory driving operation. It temporarily stores in the request buffer provided in the control circuit 210. In the present embodiment, the request buffer is provided in, for example, the sub work RAM 210a, the SDRAM 210b, etc., but the location where the request buffer is formed is not particularly limited.

  Then, after the processing of S353, the host control circuit 210 ends the animation request construction processing, and shifts the processing to S207 of the sub control main processing (see FIG. 72).

  In the present embodiment, as described above, the animation request construction process is controlled by the host control circuit 210 (sub control circuit 200). That is, the host control circuit 210 (sub control circuit 200) doubles as a means (process information generation means) for performing the object generation process of S350, and a means (production start request creation means) for performing the animation request generation process of S352. .

[Draw control process]
Next, the drawing control process performed in S208 in the sub control main process (see FIG. 72) will be described with reference to FIGS. 86A and 86B. FIG. 86A is a flowchart showing the procedure of the drawing control process executed by the host control circuit 210. FIG. 86B is a flowchart showing a procedure of processing executed by the display control circuit 230 when a drawing request is output from the host control circuit 210 to the display control circuit 230 in the drawing control processing.

(1) Drawing Control Process Performed by Host Control Circuit First, the host control circuit 210 performs a moving image command creation process as shown in FIG. 86A (S361). The details of the moving image command creation process will be described later with reference to FIG. 87 described later.

  Next, the host control circuit 210 performs management processing of the moving image reproduction state (S362). Next, the host control circuit 210 issues (outputs) a moving image command (moving image decoding start command) to the display control circuit 230 (S363). The processing of the display control circuit 230 is started by this processing.

  Next, the host control circuit 210 issues (outputs) to the display control circuit 230 a drawing request generated in the previous frame (previous drawing control process), which is stored in the subwork RAM 210a (S364). The display control circuit 230 performs a rendering process based on the transmitted previous frame rendering request.

  Next, the host control circuit 210 performs all command list creation processing (S365). With this process, a drawing request used in a drawing process executed by the display control circuit 230 is generated in the next frame, and the drawing request is stored in the sub work RAM 210a. The details of the all command list creation process will be described later with reference to FIG. 89 described later.

  Next, the host control circuit 210 confirms that the rendering result display process has started based on the display start command output from the display control circuit 230 (S366). Then, after the process of S366, the host control circuit 210 ends the drawing control process and moves the process to S209 of the sub-control main process (see FIG. 72).

(2) Processing of Display Control Circuit Performed During Drawing Control Process First, when a moving image command (moving image decoding start command) output from the host control circuit 210 is input to the display control circuit 230, the display control circuit 230 , Decoding of the moving image is started (S371). In the present embodiment, the decoding process and the drawing process described later are performed over a period of two frames.

  Next, when the drawing request (drawing request generated in the previous frame) output from the host control circuit 210 is input to the display control circuit 230, the display control circuit 230 performs drawing processing based on the drawing request. (S372). The details of the drawing process will be described later with reference to FIGS. 90 to 92 described later.

  Next, the display control circuit 230 starts display processing of the rendering result (drawing result) obtained in the drawing processing of S372 (S373). In this process, the display control circuit 230 switches the function of one frame buffer in the SDRAM 250 in which the rendering result is stored from the drawing function to the display function, and starts the rendering result display process.

  Next, the display control circuit 230 outputs a display start command indicating that display processing of the rendering result (drawing result) has been started to the host control circuit 210 (S374). Then, after the process of S374, the display control circuit 230 ends the series of processes performed during the drawing control process. In this way, since the drawing process is executed based on the drawing request generated in the previous frame, the function (use area) of the frame buffer executed after the drawing process ends is displayed from the drawing function (drawing storage area). At the timing of switching to the function (display storage area), the sound request and the feature request are transmitted to the corresponding control circuits. Therefore, the sound request and the feature request are transmitted to the corresponding control circuit two frames after each request is generated.

[Video command creation process]
Next, with reference to FIG. 87, the moving image command creation process performed in S361 in the drawing control process (see FIG. 86A) will be described. FIG. 87 is a flowchart of the procedure of the moving image command creation process according to the present embodiment.

  First, the host control circuit 210 refers to the animation request stored in the sub work RAM 210a, and acquires information for setting a route composition of drawing data (S381). The root composition is the main drawing data to be displayed at the time of presentation, and in the present embodiment, the maximum number of settable root compositions is eight. Therefore, in this embodiment, up to eight drawing data set in the root composition can be reproduced simultaneously.

  Next, the host control circuit 210 refers to the animation request stored in the sub work RAM 210 a and acquires information for setting the sub composition of the drawing data (S 382). The sub composition is drawing data that gives a visual effect (such as an effect) that is secondary to the root composition.

  Next, the host control circuit 210 determines whether or not the processing of S384 to S387, which will be described later, has been executed in accordance with all layers corresponding to the drawing data specified by the animation request or all layers specified by the animation request. (S383). As used herein, “executed according to all layers” includes all layers, performed a number of times corresponding to all layers, or executed based on all layers, and the like. The processes in S384 to S387 described later may be performed a number of times corresponding to the number of layers corresponding to the request or drawing data. Moreover, you may perform the process of below-mentioned S384-S387 under various preconditions, such as performing selection with respect to each layer even if it is not all layers.

  In S383, the host control circuit 210 determines that the processing of S384 to S387 described later is not executed according to all layers corresponding to drawing data specified by the animation request or all layers specified by the animation request. In the case where the determination is NO (S383: NO), the host control circuit 210 performs an animation data reading process stored in the sub main ROM 205 (S384). The details of the animation data reading process will be described later with reference to FIGS. 88A and 88B described later.

  After the process of S384, the host control circuit 210 acquires information related to the drawing data from the animation data (S385). Next, the host control circuit 210 rewrites the information related to the drawing data in accordance with the effect content specified by the animation request (S386). In this process, for example, information related to footage, effects, and motion is rewritten according to the contents of the effect.

  Next, the host control circuit 210 performs processing for creating a moving image command (a command for starting decoding processing of image data) (S387). After the process of S387, the host control circuit 210 returns the process to S383, and repeats the processes after S383.

  Here, returning to the processing of S383 again, in S383, the processing of S384 to S387 by the host control circuit 210 is all layers corresponding to the drawing data specified by the animation request or all layers specified by the animation request. When the host control circuit 210 determines that the process is executed in accordance with the determination (YES in S383), the host control circuit 210 performs the above-described processes in S381 to S387 according to the drawing data in which the route composition specified by the animation request is set. It is determined whether or not it has been executed (S388).

  In S388, when the host control circuit 210 determines that the processes in S381 to S387 described above are not executed according to the drawing data in which the route composition specified by the animation request is set (S388 is NO). ), The host control circuit 210 returns the process to S381, and repeats the processes after S381. On the other hand, when the host control circuit 210 determines in S388 that the processes in S381 to S387 described above have been executed in accordance with the drawing data in which the route composition specified by the animation request is set (YES in S388) ), The host control circuit 210 ends the moving image command creation process, and moves the process to S362 of the drawing control process (see FIG. 86A).

[Animation data reading process]
Next, with reference to FIG. 88A and FIG. 88B, the animation data reading process performed in S384 during the moving image command creation process (see FIG. 87) will be described. FIG. 88A is a flowchart showing the procedure of the animation data reading process in the present embodiment. FIG. 88B is a diagram showing the configuration of various data included in the animation data stored in the sub main ROM 205 and the storage area of those data.

  First, the host control circuit 210 refers to the configuration specification table in the sub main ROM 205, and confirms the configuration data of the animation specified by the object (S391). Next, the host control circuit 210 acquires the address of the designated configuration data (S392).

  Next, the host control circuit 210 refers to the storage area for the designated configuration data in the sub main ROM 205 (S393). Next, the host control circuit 210 refers to the configuration information included in the configuration data, and acquires drawing target information (S394). The configuration information mainly includes information such as the position, width, height, number of layers, start frame, end frame, number of data updates (every frame, 2 frames, etc.) of the frame. Next, the host control circuit 210 refers to the storage area for the configuration data and acquires the address of the layer data to be referred to (S395).

  Next, the host control circuit 210 refers to the storage area of the layer data at the address acquired in S395 (S396). Then, the host control circuit 210 acquires layer information included in the layer data (S397). The layer information includes, for example, information such as a footage ID / composition ID, a start frame, an end frame, and the number of parameters. Next, the host control circuit 210 acquires various data addresses (for example, parameter address, effect table address, etc.) to be referred to when acquiring various parameters of the layer (S 398).

  Next, the host control circuit 210 refers to the parameter data storage area of the parameter address acquired in the process of S398 (S399). Next, the host control circuit 210 acquires layer parameter information and various layer parameters included in the parameter data (S400). The layer parameter information includes, for example, information such as the number of frames and the data type. Also, various parameters of the layer are configured by parameters set for each frame, and each time the sub control main processing is executed in frame units, parameters of the corresponding frame are requested.

  Next, the host control circuit 210 refers to the footage table corresponding to the footage ID included in the layer information acquired in the process of S397 (S401). Next, the host control circuit 210 acquires the footage information and the information for each footage type stored in the footage table (S402). The footage information includes, for example, information such as a footage type, an image width, and a height. Also, the information for each footage type includes, for example, information such as a decoding rate.

  Next, the host control circuit 210 refers to the effect table specified by the layer data, that is, the effect table of the effect table address acquired in the process of S398 (S403). Next, the host control circuit 210 acquires an address of effect data to be referred to (S404).

  Next, the host control circuit 210 refers to the effect data storage area at the address acquired in the process of S404 (S405). Then, the host control circuit 210 acquires effect information included in the effect data (S406). The effect information includes, for example, information such as the effect type and the number of parameters. Next, the host control circuit 210 acquires the address of parameter data included in the effect data (S407).

  Next, the host control circuit 210 refers to the parameter data storage area of the parameter address acquired in the process of S407 (S408). Next, the host control circuit 210 obtains effect parameter information and various effect parameters included in the parameter data (S409). The parameter information of the effect includes, for example, information such as the number of frames and data type.

  After the process of S409, the host control circuit 210 ends the animation data reading process, and moves the process to S385 of the moving image command creation process (see FIG. 87).

[All command list creation processing (drawing request generation processing)]
Next, with reference to FIG. 89, the all command list creation process performed in S365 in the drawing control process (see FIG. 86A) is described. FIG. 89 is a flowchart showing the procedure of all command list creation processing in this embodiment.

  First, the host control circuit 210 determines whether or not the processes of S412 to S418, which will be described later, have been executed for all the root compositions of the drawing data (S411).

  In S411, when the host control circuit 210 determines that the processing of S412 to S418, which will be described later, has not been executed for all the root compositions of the drawing data (when S411 is NO), the host control circuit 210 During processing of S413 to S418 described later for the second and subsequent route compositions, still image decoding processing and various commands (still image decoding, drawing commands, etc.) described later in the processing for the first route composition The process waits until the generation process and the like are completed (S412).

  Next, the host control circuit 210 creates a sprite buffer 0 command (S413). For the sprite buffer 0 command, for example, when the sprite buffer 0 is provided in the built-in VRAM 237 and a still image (sprite) is read from the CGROM substrate 204 to the sprite buffer 0 and decoded in the drawing process described later. This command is used for.

  Next, the host control circuit 210 acquires texture information (S414). In this process, the host control circuit 210 acquires information of the designated texture source (SDRAM 250).

  Next, the host control circuit 210 creates an effect command (S415). The effect command is a command used when, for example, an effect buffer is provided in the built-in VRAM 237 and various processes are executed on the effect data using the effect buffer in a drawing process described later.

  Next, the host control circuit 210 creates a drawing command (S416). The drawing command is a command used when, for example, rendering (drawing) processing is performed on various decoding results read into the built-in VRAM 237 in the drawing processing described later.

  Next, the host control circuit 210 creates a still image decoding command (S417). For still image decoding commands, for example, the sprite buffer 1 is provided in a half area of the built-in VRAM 237 in the drawing process described later, and the still image (sprite) is read from the CGROM substrate 204 into the sprite buffer 1 and decoded. It is a command used when executing processing.

  Next, the host control circuit 210 creates a frame end command (S418). It is to be noted that the command for end of frame is a frame buffer in the SDRAM 250 designated as a rendering target, for example, the rendering result finally stored in the composition drawing buffer provided in the built-in VRAM 237 in the drawing processing described later. It is a command used when executing the process of writing in the 1 frame buffer or the 2nd frame buffer). After the process of S418, the host control circuit 210 returns the process to S411, and repeats the processes after S411.

  Here, if the process returns to S411 and the host control circuit 210 determines that the processes of S412 to S418 have been executed for all the route composition of drawing data (S411 is YES). And the host control circuit 210 generates a drawing request including all the commands generated by the loop processing of S412 to S418 described above (S419). Then, after the process of S419, the host control circuit 210 ends the all command list creation process, and moves the process to S366 of the drawing control process (see FIG. 86A). In the present embodiment, the host control circuit 210 in the drawing control process (FIG. 86A), the moving image command creation process (FIG. 87), the animation data reading process (FIG. 88A) and the all command list creation process (FIG. 89) described above. The display control circuit 230 may execute the processing that is executed. In this case, an animation request is sent from the host control circuit 210 to the display control circuit 230, and the display control circuit 230 performs these various processes based on the received animation request.

[Drawing process]
Next, the drawing process executed by the display control circuit 230 in S372 during the drawing control process (see FIG. 86B) will be described with reference to FIGS. 90A, FIG. 91A, and FIG. 92A are flowcharts showing the procedure of the drawing process in the present embodiment. FIGS. 90B, 91B and 92B are diagrams showing input / output operations and storage operations of various data among the CGROM substrate 204 (CGROM 206), the built-in VRAM 237, and the SDRAM 250, which are performed in each processing step of drawing processing. is there.

  First, the display control circuit 230 decodes predetermined moving image data stored on the CGROM substrate 204 and stores it in a movie buffer provided in the SDRAM 250 (S421: see arrow T1 in FIG. 90B). The movie buffer is a buffer for storing the decoding result of the moving image data. The size of the movie buffer secured in the SDRAM 250 changes according to the size (capacity) of the moving image data to be used, the number of streams, and the like.

  Next, the display control circuit 230 determines whether or not the decoded moving image data is referred to in the effect drawing operation (S422).

  When the display control circuit 230 determines in S422 that the moving image data is not referred to in the effect drawing operation (when the determination in S422 is NO), the display control circuit 230 performs the process of S424 described later. On the other hand, when the display control circuit 230 determines in S422 that the moving image data is referred to in the effect drawing operation (when S422 is YES), the display control circuit 230 decodes the moving image data stored in the movie buffer. The result is transferred to the texture buffer in the SDRAM 250 (S423).

  In the process of S423, first, the display control circuit 230 expands the decoding result of the moving image data stored in the movie buffer in the SDRAM 250 in the movie blend buffer generated in the built-in VRAM 237 (arrow in FIG. 90B). T2). In this process, the entire area of the built-in VRAM 237 is used as a movie blend buffer. Next, the display control circuit 230 transfers the decoding result of the moving image data expanded in the movie blend buffer to the texture buffer in the SDRAM 250 and performs an alpha process on the decoding result using the alpha table (FIG. 90B). (See arrow T3 in the middle).

  The alpha table is a table that defines alpha values (opacity) independent of color data (RGB), and one alpha value is assigned to each dot of pattern data. This alpha table is stored in the CGROM 206. In addition, in the process of converting the luminance of the R (red) component to the value of the A (alpha) component (alpha value), the image data is subjected to alpha conversion in the process of converting the result of the conversion to alpha. In this embodiment, an alpha value which is a value of transparency (opacity) is provided as information other than RGB, and when dynamically changing the transparency (opacity) of a moving image, the alpha value is an RGB component. Of these, the luminance value of a predetermined color component is set (converted). A moving image subjected to such an alpha conversion process is used when the moving image is not expressed in three primary colors (RGB) (when expressed in black and white or the like).

  After the process of S423 or when S422 is NO, the display control circuit 230 reads the sprite data stored in the CGROM board 204 and used in each route composition to the sprite buffer 0 in the built-in VRAM 237 (in FIG. 90B). (See arrow T4 in FIG. 9), and the decoded result is transferred to the texture buffer in the SDRAM 250 (S424: see arrow T5 in FIG. 90B). The “sprite data” here is image data obtained by expanding still image data. However, the present invention is not limited to this, and for example, reduction, enlargement, curvature, brightness change, etc. for still image data. May be processed. Sprite data decoded in the process of S424 is image data drawn a plurality of times, image data used in an effect, and image data of a size that can not be stored in the sprite buffer 1. Further, in this process, the entire area of the built-in VRAM 237 is used as the sprite buffer 0.

  Next, the display control circuit 230 determines whether or not the buffer size (effect buffer size) used in the effect data rendering process is less than or equal to half the size of the built-in VRAM 237 (S425). Note that the effect buffer in the built-in VRAM 237 is the effect data (image data used in the effect) included in the sprite data transferred to the texture buffer in S424 in the decoding results of various images stored in the texture buffer in the SDRAM 250. Is a buffer for applying.

  In S425, when the display control circuit 230 determines that the buffer size used in the effect data drawing process is not less than half the size of the built-in VRAM 237 (when S425 is NO), the display control circuit 230 is stored in the SDRAM 250. Drawing processing (effect calculation drawing processing) for applying effect data to the decoding results of various images stored in the texture buffer is performed (S426).

  Specifically, in the process of S426, first, the display control circuit 230 reads the decoding results of various images and effect data stored in the texture buffer into the effect buffer provided in the built-in VRAM 237 (arrow in FIG. 91B). (See T6). At this time, the entire area of the built-in VRAM 237 is used as an effect buffer. Next, the display control circuit 230 performs drawing processing (effect calculation drawing processing) for applying the effect data to the decoding results of various images. Then, the display control circuit 230 transfers the result of the effect calculation drawing process (effect result) from the effect buffer in the built-in VRAM 237 to the texture buffer in the SDRAM 250 (see arrow T7 in FIG. 91B).

  On the other hand, when the display control circuit 230 determines in S425 that the buffer size used in the rendering process of the effect data is equal to or less than half the size of the built-in VRAM 237 (if YES in S425), the display control circuit 230 A half area of the built-in VRAM 237 is operated as an effect buffer, and the remaining half area is operated as a copy buffer (S427). Next, the display control circuit 230 reads the decoding result of various images and effect data stored in the texture buffer from the effect buffer provided in the built-in VRAM 237, and performs effect calculation drawing processing (S428).

  At this time, when the decoding result (effect source image of the effect) of the effect data has already been transferred to the copy buffer, the display control circuit 230 does not read out the source image of the effect from the texture buffer of the SDRAM 250. The effect source image is directly read into the effect buffer (see arrow T8 in FIG. 91B), and effect calculation drawing processing is performed. On the other hand, when the source image of the effect has not been transferred to the copy buffer, the display control circuit 230 reads the source image of the effect from the texture buffer of the SDRAM 250 to the copy buffer (see arrow T9 in FIG. 91B). The effect source image is read from the copy buffer to the effect buffer and effect calculation drawing processing is performed. Then, the display control circuit 230 saves the result of the effect calculation drawing process (effect result) in the copy buffer (see arrow T10 in FIG. 91B), and transfers the effect result saved in the copy buffer to the texture buffer of the SDRAM 250. (See arrow T11 in FIG. 91B). When a plurality of effects are applied and the buffer usage of each effect is less than half the size of the built-in VRAM 237, the display control circuit 230 copies the result (effect result) for each effect calculation drawing process. After the drawing results of the plurality of effects have been completed, the effect results are transferred from the copy buffer to the texture buffer of the SDRAM 250.

  As described above, in the present embodiment, drawing processing is performed on all effects applied to layers used in each composition before the composition drawing processing described later. Further, in the present embodiment, when the buffer capacity used in the effect is equal to or less than half the capacity of the built-in VRAM 237, a half area in the built-in VRAM 237 is used as a copy buffer, and the buffer capacity used in the effect is the built-in VRAM 237. If it is not less than half the capacity, the entire area of the built-in VRAM 237 is used as an effect buffer. That is, the area in the built-in VRAM 237 used as an effect buffer is appropriately changed according to the buffer capacity used in the effect. By performing such processing, it is possible to speed up processing when effect calculation drawing processing is applied to a plurality of effects.

  After the processing of S426 or S428, the display control circuit 230 reads the sprite data not decoded in S424 (not stored in the texture buffer) into the composition drawing buffer provided in the built-in VRAM 237 and draws it (S429). . Specifically, first, the display control circuit 230 reads the sprite data not decoded in S424 from the CGROM board 204 into the sprite buffer 1 provided in the half area in the built-in VRAM 237 and decodes it (in FIG. 92B). (See arrow T12). Note that “to read out sprite data to the sprite buffer 1 and decode it” has a meaning including an aspect of reading out sprite data while decoding to the sprite buffer 1. Therefore, in this process, the sprite data read process and the decode process may be performed at the same timing, or the sprite data decode process may be performed before the read process. That is, the process of “reading and decoding the sprite data into the sprite buffer 1” may include both processes regardless of the processing order of the sprite data read process and the decode process. It should be noted that the processing of “read to sprite buffer 1 and decoded” may be processing including only the read processing and decoding processing of sprite data.

  Next, the display control circuit 230 transfers the sprite data decoding result stored in the sprite buffer 1 to the composition drawing buffer and performs drawing processing (see arrow T13 in FIG. 92B).

  After the process of S429, the display control circuit 230 reads out the result of decoding the moving image data stored in the movie buffer in the SDRAM 250 to the composition drawing buffer in the built-in VRAM 237 and draws it (S430). Specifically, first, the display control circuit 230 transfers the color component of the decoding result of the moving image data stored in the movie buffer in the SDRAM 250 to the movie blend buffer provided in the remaining half area in the built-in VRAM 237. At the same time, the decoding result is subjected to an alpha process (see arrow T14 in FIG. 92B). Next, the display control circuit 230 transfers the decoded result of the moving image data transferred to the movie blend buffer and subjected to the alpha conversion processing to the composition drawing buffer to perform the drawing processing (see arrow T15 in FIG. 92B).

  Next, the display control circuit 230 performs composition drawing processing (S431). In this process, the following various processes are performed.

  First, the display control circuit 230 stores various source images (moving image / still image decoding result, effect result, composition drawing result) of each layer stored in the texture source (texture source in the SDRAM 250, movie buffer) in the built-in VRAM 237. (See arrow T16 in FIG. 92B). In addition, the display control circuit 230 transfers various source images stored in the texture buffer in the SDRAM 250 to the blend buffer provided in the SDRAM 250 and the copy buffer provided in the built-in VRAM 237 (the arrows T17 and FIG. 92B). T18).

  Next, the display control circuit 230 inputs / outputs various data between the blend buffer of the SDRAM 250 and the copy buffer of the built-in VRAM 237 (see arrow T19 in FIG. 92B), and performs blend calculation drawing processing. In the blending operation drawing process, an operation process is performed to combine moving image (moving) data and still image (sprite) data. Then, the display control circuit 230 transfers the result of blend calculation drawing processing (blend result) to the composition drawing buffer (see arrow T20 in FIG. 92B).

  Next, the display control circuit 230 performs drawing processing using each source image (moving image / still image decoding result, effect result, composition drawing) and blend result read out to the composition drawing buffer. Apply.

  Then, the display control circuit 230 stores the drawing result (rendering result) constructed by the drawing (rendering) processing in the texture buffer of the SDRAM 250 or a predetermined frame buffer (first frame buffer or second frame buffer) of the SDRAM 250 ( See arrows T21 or T22 in FIG. 92B). At this time, if the execution target of the drawing process is a sub-composition, the drawing result is saved in the texture buffer. If the execution target of the drawing process is the root composition, the drawing result is saved in the frame buffer. Is done. When the drawing result is saved in the frame buffer, the drawing result is saved in a frame buffer different from the frame buffer in which the drawing result is saved in the composition drawing process of the previous frame. The composition drawing process of S431 is performed as described above.

In the composition drawing process in S431, when all of the following conditions (1) to (5) are satisfied, the display control circuit 230 is stored in a texture source (a texture source in the SDRAM 250, a movie buffer). Copy and draw various source images of each layer (moving image / still image decoding result, effect result, composition drawing result) in copy buffer in built-in VRAM 237, read out various source images into composition drawing buffer and execute composition Drawing processing is performed.
(1) The upper left coordinates of the texture do not match 8 dot alignment (2) rotation, enlargement / reduction (3) use of bilinear filter (4) blend drawing operation processing is multi-rendering processing.
(5) Various source images of each layer stored in the texture source fit within the size of the copy buffer.

  In addition, when the above-described composition drawing process is continuously performed on various source images in the same texture source, various source images cached in the copy buffer are used.

  Then, after the process of S431 described above, the display control circuit 230 ends the drawing process, and moves the process to S373 in the drawing control process (see FIG. 86B).

[Voice control processing]
Next, with reference to FIGS. 93A and 93B, the voice control process performed in S209 in the sub control main process (see FIG. 72) will be described. FIG. 93A is a flowchart showing the procedure of the voice control process executed by the host control circuit 210. FIG. 93B is a flowchart showing a procedure of processing executed by the sound / LED control circuit 220 when a sound request is output from the host control circuit 210 to the sound / LED control circuit 220 in the sound control processing.

(1) Audio control process executed by the host control circuit The host control circuit 210 outputs the sound request stored in the request buffer in the animation request construction process of FIG. 85 to the audio / LED control circuit 220 (S441).

  In the present embodiment, the host control circuit 210 outputs a sound request after two frames have elapsed since generation of a request for effect control in order to synchronize the operation of sound reproduction effect by the speaker 11 with the effect operation by the display device 13 To do. This is because, as described above, in the image decoding process and the drawing process by the display control circuit 230 of the present embodiment, a period of two frames is required for the series of processes.

  Then, after the process of S441, the host control circuit 210 ends the voice control process and moves the process to S210 of the sub-control main process (see FIG. 72).

(2) Audio / LED Control Circuit Processing Performed During Audio Control Processing First, the sound request output from the host control circuit 210 is input to the audio / LED control circuit 220 (S451). Next, the voice / LED control circuit 220 determines whether or not there is a free execution system capable of executing the process (code) among the four execution systems for voice reproduction (S452).

  In S452, when the voice / LED control circuit 220 determines that there is no free execution system among the four execution systems for voice reproduction (when S452 is NO), the voice / LED control circuit 220 It waits until an execution system occurs (S453).

  After the processing of S453, or in S452, if the voice / LED control circuit 220 determines that there is an available execution system among the four execution systems of voice reproduction (in the case of YES determination in S452), the voice / LED The control circuit 220 sets an access number in a predetermined execution system that is free (S454).

  Next, the voice / LED control circuit 220 reads out access data associated with the access number from the CGROM substrate 204 based on the access number in the execution system in which the access number is set (S455).

  Next, based on the access data, the voice / LED control circuit 220 sequentially sets each of the plurality of setting data specified in the access data to the corresponding address and starts the process of executing the code (process) (S456). By this processing, the sound reproduction effect by the speaker 11 is started. In the present embodiment, the audio reproduction control is executed by simple access control.

  Next, the voice / LED control circuit 220 determines whether or not there is a plurality of accesses to the code being referred to (S457). Specifically, the voice / LED control circuit 220 determines whether or not there is access from another execution system to a code (setting data) being executed in the execution system in which the access number is set. To do. If the voice / LED control circuit 220 determines in S457 that there is not a plurality of accesses to the code being referred to (if S457 is NO), the voice / LED control circuit 220 performs the process of S459 described later. Do.

  On the other hand, if the voice / LED control circuit 220 determines that there is a plurality of accesses to the code being referred to in S457 (if YES in S457), the voice / LED control circuit 220 executes the code. On the basis of the latest sound request (S458). Specifically, for example, code 1, code 2 and code 3 are executed in a predetermined execution system based on a predetermined sound request, and code 3 in another execution system based on the next sound request. When executing the code 4 and the code 5, the sound reproduction of the code 3 having a plurality of accesses is executed based on the next sound request.

  After the processing of S458 or when S457 is NO, the voice / LED control circuit 220 sets a simple access end code (S459). Then, after the processing of S459, the voice / LED control circuit 220 ends the above-described series of processing at the time of the voice control processing, and the processing is performed in a predetermined control state (for example, standby state, voice control) of the voice / LED control circuit 220. Control state before processing, control state of processing executed after voice control processing, etc.).

[Lamp control processing]
Next, with reference to FIGS. 94A and 94B, the lamp control process performed in S210 in the sub control main process (see FIG. 72) will be described. FIG. 94A is a flowchart showing the procedure of the lamp control process executed by the host control circuit 210. FIG. 94B is a flowchart showing the procedure of the process executed by the audio / LED control circuit 220 in the lamp control process.

  In the present embodiment, an example of processing in the case where the above-described “NEXT” and “ODONLY” are not specified in the LED animation reproduction method will be described. The lamp control processing considering the case where “NEXT” and “ODONLY” are designated as the reproduction method will be described in detail in Modifications 2 and 3 (see FIGS. 105 to 107 described later).

(1) Lamp control processing executed by the host control circuit The host control circuit 210 outputs the lamp request stored in the request buffer in the animation request construction processing of FIG. 85 to the sound / LED control circuit 220 (S461). In the present embodiment, in order to synchronize the rendering operation by the group of lamps (LEDs) 18 with the rendering operation by the display device 13, the host control circuit 210 generates a lamp request after two frames have passed since the generation of the rendering control request. Output.

  Then, after the process of S461, the host control circuit 210 ends the lamp control process and moves the process to S211 of the sub-control main process (see FIG. 72).

(2) Processing of voice / LED control circuit executed during lamp control processing First, a lamp request output from the host control circuit 210 is input to the voice / LED control circuit 220 (S471).

  Next, the audio / LED control circuit 220 specifies the LED animation and data table information read out from the CGROM 206 based on the lamp request (including the ID of the LED animation) (S472). If LED animation is designated by this processing, LED data to be output to each LED 281 can be designated. Also, if data table information is designated by this processing, it is possible to designate data of reproduction method, reproduction channel, extension channel, turn-off data identification, control part and LED data name (for debugging).

  Next, the audio / LED control circuit 220 refers to the designated data table information to acquire data such as a reproduction channel (sequencer, layer) or the like on which the LED animation is to be performed (S473). Next, the audio / LED control circuit 220 determines whether or not there are a plurality of lamp requests in the same reproduction channel (S474).

  If the audio / LED control circuit 220 determines in S474 that there are a plurality of lamp requests in the same reproduction channel (if YES in S474), the audio / LED control circuit 220 determines based on the last received lamp request. Then, the LED animation is set to the playback channel or the playback channel and the extension channel (the extension channel of the same channel as the playback channel) (S475). This process overwrites the data table information currently registered in the playback channel registration buffer or each of the playback channel and extension channel registration buffers with the data table information acquired based on the last received ramp request. Is done.

  On the other hand, if the audio / LED control circuit 220 determines in S474 that there are not a plurality of lamp requests in the same playback channel (if S474 is NO), the audio / LED control circuit 220 determines that the playback channel or playback LED animation is set to the channel and the extension channel (S476). By this processing, the data table information acquired based on the lamp request received this time is registered in the registration buffer of the reproduction channel or each registration buffer of the reproduction channel and the extension channel.

  After the processing of S475 or S476, the sound / LED control circuit 220 sets LED data (output data) to be set to a predetermined port of a control target (in the control region) in a predetermined channel based on the set LED animation. (S477). The process after S477 is executed for each port.

  Next, the audio / LED control circuit 220 determines whether LED data (output data) overlap between channels at a predetermined port, that is, it is necessary to combine LED data among a plurality of channels. Is discriminated (S478).

  If the voice / LED control circuit 220 determines in S478 that there is no duplication of LED data between channels at a predetermined port (if NO in S478), the voice / LED control circuit 220 performs S480 described later. Process. On the other hand, when the audio / LED control circuit 220 determines that the LED data overlap among the channels at the predetermined port in S478 (when the determination of S478 is YES), the audio / LED control circuit 220 determines the channel in advance. LED data (luminance data) at a predetermined port is determined based on the execution priority of the LED data set to (S479).

  In the process of S479, for example, if the LED data is not set to the predetermined port to be processed before this process, the LED data acquired this time is set to the predetermined port. Further, for example, when the LED data of a predetermined port set before this processing is LED data of a channel whose execution priority is lower than that of the currently processed channel, the LED data acquired this time Overwrite the LED data of the specified port. Also, for example, when the LED data of a predetermined port set before this processing is LED data of a channel having a higher execution priority than the channel currently being processed, the LED data acquired this time And the LED data of a predetermined port is not overwritten (maintained). By repeating such processing for each channel, LED data of a plurality of channels are synthesized at a predetermined port to be processed (the LED data of the channel having the highest execution priority among the plurality of channels is set) )

  If the process of S479 or S478 is NO, the audio / LED control circuit 220 executes the process of S477 to S479 for a predetermined port for all channels (eight channels in this embodiment). It is determined whether or not (S480).

  When the voice / LED control circuit 220 determines in S480 that the process of S477 to S479 for a predetermined port is not executed for all channels (when S480 is NO), the voice / LED control circuit 220 returns the process to S477, changes the channel to be processed, and repeats the processes after S477. On the other hand, if the voice / LED control circuit 220 determines in S480 that the processing of S477 to S479 for a predetermined port has been executed for all channels (if YES in S480), the voice / LED control circuit 220 determines whether or not the port direct specification data for a predetermined port is included in the lamp request, and if the port direct specification data is included in the lamp request, the voice / LED control circuit 220 determines Port LED data is overwritten with the port direct designated data (S481).

  Next, the voice / LED control circuit 220 determines whether or not the above-described processing of S477 to S481 has been executed for all ports (S482). Here, “all ports” means all ports set in the LED registration process shown in FIG. 77, but the present invention is not limited to this. "All ports" may be all ports which can be physically set arbitrarily regardless of the ports set in the LED registration process shown in FIG. 77, or set in the LED registration process shown in FIG. It may be a partial port selected from among the selected ports.

  When the audio / LED control circuit 220 determines in S482 that the processing of S477 to S481 is not executed for all the ports (when S482 is NO), the audio / LED control circuit 220 performs the processing. The process returns to S477, the port to be processed is changed, and the processes after S477 are repeated. On the other hand, when the voice / LED control circuit 220 determines that the processes of S477 to S481 have been executed for all the ports in S482 (if YES in S482), the voice / LED control circuit 220 performs lamp control. The above-described series of processing at the time of processing is ended, and processing is performed in a predetermined control state of the voice / LED control circuit 220 (for example, standby state, control state before lamp control processing, control state of processing executed after lamp control processing, etc. ) Return to time processing.

[Accessory control processing]
Next, with reference to FIG. 95, the item control process performed in S211 in the sub control main process (see FIG. 72) will be described. FIG. 95 is a flowchart showing the procedure of the character control process according to the present embodiment.

  First, the host control circuit 210 determines whether or not the current operation status is a standby operation for receiving a command from the main control circuit 70 (S491).

  When the host control circuit 210 determines in S491 that the current operation status is not in a standby operation for receiving a command from the main control circuit 70 (when the determination in S491 is NO), the host control circuit 210 performs a bonus control process. Is ended, and the process proceeds to S212 of the sub control main process (see FIG. 72).

  On the other hand, when the host control circuit 210 determines in S491 that the current operation status is in a standby operation for receiving a command from the main control circuit 70 (when the determination in S491 is YES), the host control circuit 210 It is determined whether a command relating to an effect has been received from the control circuit 70 (S492). The commands related to the effect to be determined in this process are, for example, commands for starting fluctuation of the special symbol, stopping movement, demonstration, and jackpot, and when these commands are received by the host control circuit 210, 20 moves.

  If the host control circuit 210 determines in S492 that the command related to the effect has not been received from the main control circuit 70 (if the determination in S492 is NO), the host control circuit 210 ends the gift control process, Is transferred to S212 of the sub control main process (see FIG. 72).

  On the other hand, when the host control circuit 210 determines in S492 that the command related to the effect has been received from the main control circuit 70 (when the determination in S492 is YES), the host control circuit 210 performs the bonus processing at the time of fluctuation start command reception. This is performed (S493). In this process, the host control circuit 210 mainly sets permission / non-permission of the handpiece request between the processes related to the accessory control executed by the host control circuit 210. The details of the processing for receiving a change start command will be described later with reference to FIG. 96 described later.

  Next, the host control circuit 210 performs a role processing at the time of demo command reception (S494). Note that details of the demo command reception-purpose processing will be described later with reference to FIG. 97 described later. Next, the host control circuit 210 performs a bonus product process at the time of fluctuation stop command reception (S495). The details of the processing for receiving a change stop command will be described later with reference to FIG. Next, the host control circuit 210 performs a jackpot processing at the time of jackpot system command reception (S 496). The details of the processing for receiving a bonus game command will be described later with reference to FIG.

  Although the present embodiment has described an example in which the various-item-reception-time character object processing of S493 to S496 is performed in the character object control processing, the present invention is not limited to this. Each accessory process may be performed as an embedded process, or each accessory process may be performed immediately after the command analysis process described above (see FIG. 83).

  Next, the host control circuit 210 performs initial position recovery operation processing (S497). The details of the initial position recovery operation process will be described later with reference to FIG. 101 described later. Next, the host control circuit 210 determines whether or not the current operation status is a command reception standby operation from the main control circuit 70 (S498).

  If the host control circuit 210 determines in S498 that the current operation status is in a standby operation for receiving a command from the main control circuit 70 (if YES in S498), the host control circuit 210 proceeds to S492. , And repeat the processing after S492. On the other hand, if the host control circuit 210 determines in S498 that the current operation status is not in a standby operation for receiving a command from the main control circuit 70 (if S498 is NO), the host control circuit 210 It is determined whether the request delivery permission is set (S499).

  In S499, when the host control circuit 210 determines that the gift request delivery permission is not set (S499 is NO determination), the host control circuit 210 ends the gift control process, and the process is deputy. The process moves to S212 in the control main process (see FIG. 72).

  On the other hand, when the host control circuit 210 determines in S499 that the permission to deliver the feature request is set (when the determination in S499 is YES), the host control circuit 210 makes a request in the animation request construction process of FIG. The feature request stored in the buffer is acquired (S500). In the present embodiment, the host control circuit 210 acquires the feature request after two frames have elapsed since the request generation of the effect control, in order to synchronize the effect operation by the bonus item 20 with the effect operation by the display device 13. .

  Next, the host control circuit 210 transmits excitation data to the motor driver 271 via the I2C controller 261 based on the accessory request (S501). Next, the host control circuit 210 determines whether or not a communication error signal has been received from the I2C controller 261 (S502). In this process, the host control circuit 210 may determine whether a communication error between the I2C controller 261 and the motor controller 270 or an error of the I2C controller 261 has been detected (acquired or input).

  In S502, when the host control circuit 210 determines that a communication error signal has been received from the I2C controller 261 (S502 is YES), the host control circuit 210 sets a communication controller error (S503). Then, after the processing of S503, the host control circuit 210 ends the accessory control processing, and moves the processing to S212 of the sub-control main processing (see FIG. 72).

  On the other hand, when the host control circuit 210 determines in S502 that the communication error signal has not been received from the I2C controller 261 (when S502 is NO), the host control circuit 210 accesses the address of each motor driver 271. It is determined whether or not it is possible (S504).

  When the host control circuit 210 determines in S504 that the address of each motor driver 271 can not be accessed (S504 is NO), the host control circuit 210 sets a connection error (S505). Then, after the processing of S505, the host control circuit 210 ends the gift control processing, and shifts the processing to S212 of the sub control main processing (see FIG. 72).

  On the other hand, when the host control circuit 210 determines that the address of each motor driver 271 can be accessed in S504 (when the determination in S504 is YES), the host control circuit 210 plays a role until the rendering operation by the prize 20 ends. The object 20 (motor 272) is moved (S506). In this process, after the operation of the motor 272 is stopped, the accessory 20 (the motor 272) is moved until the sensor detects that the motor 272 (the accessory 20) has returned to the initial position.

  Next, the host control circuit 210 determines whether or not the operation of the accessory 20 (motor 272) has ended normally (S507). In S507, when the host control circuit 210 determines that the operation of the accessory 20 (motor 272) ends normally (when the determination in S507 is YES), the host control circuit 210 ends the accessory control process, The process moves to S212 of the sub control main process (see FIG. 72). On the other hand, when the host control circuit 210 determines in S507 that the operation of the accessory 20 (motor 272) has not ended normally (when S507 is NO), the host control circuit 210 sets a data error. (S508). After the process of S508, the host control circuit 210 ends the accessory control process, and moves the process to S212 of the sub-control main process (see FIG. 72).

[Function processing when variable start command is received]
Next, with reference to FIG. 96, the change start command reception-use accessory process performed in S493 during the accessory control process (see FIG. 95) will be described. FIG. 96 is a flowchart showing the procedure of the processing for receiving a change start command in this embodiment.

  First, the host control circuit 210 determines whether or not a change start command has been received (S511). Specifically, the host control circuit 210 determines, for example, whether or not the above-mentioned special symbol presentation start command has been received.

  In S511, when the host control circuit 210 determines that the change start command has not been received (when S511 is NO), the host control circuit 210 ends the change start command receiving accessory process and performs the process. Move to S494 of the gift control process (see FIG. 95). On the other hand, when it is determined in S511 that the host control circuit 210 has received the change start command (when S511 is YES), the host control circuit 210 determines whether or not all the motors 272 are in the initial positions. (S512).

  In S512, when the host control circuit 210 determines that all the motors 272 are at the initial position (when the determination in S512 is YES), the host control circuit 210 sets the delivery permission of the feature request (S513). When the transfer request for the accessory request is set, the control state of the accessory 20 shifts from the command reception standby state to the accessory request transfer permission state.

  Next, the host control circuit 210 sets “0” in the initial position recovery counter (S514). The initial position restoration counter is a counter that counts the number of executions of the initial position restoration operation of the motor 272, and is provided in the sub work RAM 210a. Then, after the processing of S514, the host control circuit 210 finishes the change start command receiving time object process, and moves the process to S494 of the object control process (see FIG. 95).

  On the other hand, when the host control circuit 210 determines that the one or more motors 272 are not at the initial position in S512 (when the determination in S512 is NO), the host control circuit 210 sets delivery non-permission of the feature request (S515). Next, the host control circuit 210 performs transition setting to the initial position recovery operation (S516). Then, after the processing of S516, the host control circuit 210 ends the change start command reception time object process, and moves the process to S494 of the object control process (see FIG. 95).

[Demonstration command receiving feature processing]
Next, with reference to FIG. 97, the demo command reception-time object processing performed in S494 in the accessory control processing (see FIG. 95) will be described. FIG. 97 is a flowchart showing the procedure of the bonus product process at the time of demonstration command reception in the present embodiment.

  First, the host control circuit 210 determines whether a demo command has been received (S521). Specifically, the host control circuit 210 determines, for example, whether or not the above-mentioned demonstration display command has been received.

  In S521, when the host control circuit 210 determines that the demo command is not received (S521 is NO determination), the host control circuit 210 ends the processing of the demonstration command at the time of demo command reception, and the processing The process moves to S495 in the control process (see FIG. 95). On the other hand, when the host control circuit 210 determines that the demo command has been received in S521 (when the determination in S521 is YES), the host control circuit 210 determines whether an error due to a malfunction of the motor 272 or the like is detected. A determination is made (S522). In this process, the host control circuit 210, for example, determines whether various errors (communication controller error, connection error, data error) or the like set in the process after S502 in the character control process (see FIG. 95) have occurred. Determine if it is not.

  In S522, when the host control circuit 210 determines that an error due to a malfunction of the motor 272 or the like is detected (when the determination in S522 is YES), the host control circuit 210 performs an error process (S523). The details of the error processing will be described later with reference to FIG. 98 described later. Next, the host control circuit 210 performs transition setting to the item operation error operation (S524). Then, after the processing of S524, the host control circuit 210 ends the accessory processing at the time of receiving the demo command, and moves the processing to S495 of the accessory control processing (see FIG. 95).

  On the other hand, when the host control circuit 210 determines in S522 that an error due to a malfunction of the motor 272 or the like is not detected (when the determination in S522 is NO), the host control circuit 210 sets all the motors 272 to their initial positions. It is determined whether there is any (S525).

  In S525, when the host control circuit 210 determines that one or more motors 272 are not in the initial position (when S525 is NO), the host control circuit 210 ends the demo command reception-time object processing, The process proceeds to S495 of the character control process (see FIG. 95). On the other hand, when the host control circuit 210 determines in S525 that all the motors 272 are at the initial position (when the determination in S525 is YES), the host control circuit 210 performs an accessory excitation release process (S526). In this process, the host control circuit 210 stops the output of the excitation data to all the motors 272 (motor drivers 271).

  Next, the host control circuit 210 sets the delivery request of the feature request (S527). Next, the host control circuit 210 sets “0” in the initial position restoration counter (S528). Then, after the processing of S528, the host control circuit 210 ends the accessory process at the time of receiving the demo command, and moves the process to S495 of the accessory control process (see FIG. 95).

[Error handling]
Next, with reference to FIG. 98, error processing performed in S523 in the demonstration command reception role product processing (see FIG. 97) will be described. FIG. 98 is a flowchart showing the procedure of error processing in this embodiment.

  First, the host control circuit 210 sets the non-permission request of the feature request (S531). Next, the host control circuit 210 stops all the motors 272 (S532).

  Next, the host control circuit 210 resets the software of the motor driver 271 (S533). Next, the host control circuit 210 resets the I2C controller 261 (S534). Then, after the processing of S534, the host control circuit 210 ends the error processing, and shifts the processing to S524 of the bonus product processing (see FIG. 97) at the time of demo command reception.

[Valuation stop command reception feature processing]
Next, with reference to FIG. 99, the variation stop command reception role item process performed in S495 in the item control process (see FIG. 95) will be described. FIG. 99 is a flowchart showing the procedure of the bonus product process when the variable stop command is received in the present embodiment.

  First, the host control circuit 210 determines whether a fluctuation stop command has been received (S541). Specifically, for example, the host control circuit 210 determines whether or not the above-described special symbol stop command has been received.

  In S541, when the host control circuit 210 determines that the change stop command has not been received (when S541 is NO), the host control circuit 210 ends the accessory process when the change stop command is received, and performs the process. Move to S496 of the gift control process (see FIG. 95). On the other hand, if it is determined in S541 that the host control circuit 210 has received the fluctuation stop command (S541 is YES), the host control circuit 210 determines whether an error due to a malfunction of the motor 272 or the like has been detected. Is discriminated (S542).

  In S542, when the host control circuit 210 determines that an error due to a malfunction of the motor 272 or the like is detected (when the determination in S542 is YES), the host control circuit 210 performs the error processing described in FIG. S543). Next, the host control circuit 210 performs transition setting to the item operation error operation (S544). Then, after the processing of S544, the host control circuit 210 ends the accessory processing at the time of receiving the change stop command, and moves the processing to S496 of the accessory control processing (see FIG. 95).

  On the other hand, when the host control circuit 210 determines that an error due to a malfunction of the motor 272 or the like is not detected in S542 (when S542 is NO), the host control circuit 210 sets all the motors 272 to their initial positions. It is determined whether there is any (S545).

  In S545, when the host control circuit 210 determines that one or more motors 272 are not in the initial position (when S545 is NO), the host control circuit 210 ends the variable stop command reception time object processing. Then, the process proceeds to S496 of the character control process (see FIG. 95). On the other hand, when the host control circuit 210 determines in S545 that all the motors 272 are at the initial position (when the determination in S545 is YES), the host control circuit 210 sets delivery permission of the feature request (S546). ).

  Next, the host control circuit 210 sets “0” in the initial position recovery counter (S547). Then, after the process of S547, the host control circuit 210 ends the accessory process at the time of the change stop command reception, and moves the process to S496 of the accessory control process (see FIG. 95).

[Big win system command reception time processing]
Next, with reference to FIG. 100, the jackpot-related command reception bonus processing performed in S496 in the bonus control processing (see FIG. 95) will be described. FIG. 100 is a flowchart showing the procedure of the jackpot processing at the time of the jackpot command reception in the present embodiment.

  First, the host control circuit 210 determines whether a big hit system command has been received (S551). Specifically, the host control circuit 210 determines, for example, whether or not the above-described special symbol hit start display command has been received.

  In S551, when the host control circuit 210 determines that the big hit system command is not received (when S551 is NO determination), the host control circuit 210 ends the big hit system command reception feature processing at the time of the big hit system command reception. Move to S497 of the gift control process (see FIG. 95). On the other hand, when the host control circuit 210 determines that the big hit system command has been received in S551 (when the determination in S551 is YES), the host control circuit 210 determines whether all the motors 272 are at the initial position. (S552).

  When the host control circuit 210 determines that the one or more motors 272 are not at the initial position in S552 (when the determination in S552 is NO), the host control circuit 210 performs the process of S554 described later. On the other hand, when the host control circuit 210 determines in S552 that all the motors 272 are in the initial position (when S552 is YES), the host control circuit 210 sets permission to pass the accessory request (S553). ).

  After the processing of S553 or when the determination of S552 is NO, the host control circuit 210 sets “0” in the initial position recovery counter (S554). Then, after the processing of S554, the host control circuit 210 finishes the big hit system command receiving accessory processing, and moves the processing to S497 of the accessory control processing (see FIG. 95).

[Initial position recovery operation processing]
Next, with reference to FIG. 101, the initial position restoration operation process performed in S497 in the character item control process (see FIG. 95) will be described. FIG. 101 is a flowchart showing the procedure of the initial position recovery operation process according to this embodiment.

  First, the host control circuit 210 determines whether or not the gift request delivery permission is set (S561).

  In S561, when the host control circuit 210 determines that the delivery permission of the feature request is set (when S561 is YES determination), the host control circuit 210 ends the initial position recovery operation processing, and the processing is performed. Transfer to S498 of the gift control process (see FIG. 95). On the other hand, when the host control circuit 210 determines in S561 that the delivery request for the accessory request is not set (NO in S561), the host control circuit 210 shifts to the error operation during the accessory operation. Is determined (S562).

  In S562, when the host control circuit 210 determines that the transition to the accessory operation error operation is not set (when S562 is NO determination), the host control circuit 210 performs the processing of S565 described later.

  On the other hand, when the host control circuit 210 determines in S562 that the transition to the accessory operation error operation is set (when the S562 is YES determination), the host control circuit 210 performs the operation of the accessory 20. The process ends (S563). Next, the host control circuit 210 performs transition setting to the initial position recovery operation (S564).

  After the process of S564 or when the determination of S562 is NO, the host control circuit 210 determines whether the transition to the initial position recovery operation is set (S565).

  If the host control circuit 210 determines in S565 that the transition to the initial position recovery operation is not set (if the determination in S565 is NO), the host control circuit 210 ends the initial position recovery operation processing, and the processing is performed. Is transferred to S498 of the gift control process (see FIG. 95). On the other hand, when the host control circuit 210 determines that the transition to the initial position recovery operation is set in S565 (when the determination in S565 is YES), the host control circuit 210 sets the value of the initial position recovery counter to “ 1 ”is added (S566).

  Next, the host control circuit 210 determines whether the value of the initial position recovery counter is "10" or more (S567).

  In S567, when the host control circuit 210 determines that the value of the initial position recovery counter is not 10 or more (when S567 is NO), the host control circuit 210 moves all the motors 272 to the initial position. (S568). Next, the host control circuit 210 determines whether all the motors 272 are at the initial position (S569).

  In S569, when the host control circuit 210 determines that one or more motors 272 are not at the initial position (when S569 is NO), the host control circuit 210 returns the process to S566, and performs the processes after S566. repeat. On the other hand, when the host control circuit 210 determines in S569 that all the motors 272 are in the initial position (when the determination in S569 is YES), the host control circuit 210 performs transition setting to the command reception standby operation ( S 570). Then, after the process of S570, the host control circuit 210 ends the initial position recovery operation process, and moves the process to S498 of the bonus feature control process (see FIG. 95).

  If the host control circuit 210 determines that the value of the initial position recovery counter is "10" or more again (S567: YES), the host control circuit 210 returns to the process of S567. The step 210 sets the delivery disapproval of the feature request (S571). Next, the host control circuit 210 stops all the motors 272 until the initialization processing is performed by turning on the power again (S572).

  In the present embodiment, as described above, the example in which the motor 272 is stopped when the value of the initial position recovery counter is “10” or more has been described, but the present invention is not limited to this. The threshold value of the initial position restoration counter for stopping the motor 272 can be arbitrarily set according to, for example, the effect operation content of the accessory 20, the performance of the motor 272, and the like.

  Then, after the process of S572, the host control circuit 210 ends the initial position recovery operation process, and moves the process to S498 of the bonus feature control process (see FIG. 95).

[Data communication processing between voice / LED control circuit and LED driver]
Next, communication processing performed between the audio / LED control circuit 220 and the LED driver 280 will be described with reference to FIGS. 102A and 102B. FIG. 102A is a flowchart showing a procedure of signal and data transmission processing executed by the audio / LED control circuit 220 in the communication processing between the audio / LED control circuit 220 and the LED driver 280. FIG. 102B is a flowchart showing the procedure of signal and data reception processing executed by the LED driver 280 in the communication processing between the audio / LED control circuit 220 and the LED driver 280.

  In this embodiment, when a lamp request is input from the host control circuit 210 to the sound / LED control circuit 220, the sound / LED control circuit 220 converts the lamp output data (LED data) into a lamp group based on the lamp request. It transmits to each LED driver 280 contained in 18. FIG. At this time, since the voice / LED control circuit 220 and the LED driver 280 are connected by the SPI bus as described above, communication of signals and serial data is performed by the SPI system between the two. In the present embodiment, the communication mode between the audio / LED control circuit 220 and the LED driver 280 is a mode in which a signal and serial data are transmitted unilaterally from the audio / LED control circuit 220 to the LED driver 280.

  The specific procedures of the signal and serial data transmission processing executed by the voice / LED control circuit 220 and the data reception processing executed by the LED driver 280 based on the lamp request are shown in FIG. And will be described with reference to the flowchart of FIG. 102B. In the present embodiment, the configuration of serial data transmitted from the audio / LED control circuit 220 is the configuration described in FIG.

(1) Audio / LED Control Circuit Serial / Data Transmission Process First, as shown in FIG. 102A, the audio / LED control circuit 220 transmits data “1” continuously to the LED driver 280 16 times or more ( S581). That is, the audio / LED control circuit 220 transmits, to the LED driver 280, data (see FIG. 39) of an area in which data “1” is continuously stored 16 bits or more, which is disposed at the head of serial data.

  Next, the audio / LED control circuit 220 transmits the device address to the LED driver 280 (S582). Next, the voice / LED control circuit 220 transmits the register address to the LED driver 280 (S583).

  Next, the voice / LED control circuit 220 transmits lamp output data (LED data) to the LED driver 280 (S584). Then, after the process of S584, the voice / LED control circuit 220 ends the serial data transmission process.

(2) LED driver reception processing (state transition processing based on received data)
First, as shown in FIG. 102B, the LED driver 280 sets the sleep state (S591). Note that "to put in the sleep state" means to put the operating state of the LED driver 280 in the sleep state (sleeping state) and put it in the operation standby state. The set sleep state is canceled when the LED driver 280 receives (detects) the first data “1” from the audio / LED control circuit 220.

  Next, the LED driver 280 determines whether the data “1” has been received (detected) 16 times consecutively from the voice / LED control circuit 220 (S592).

  In S592, when the LED driver 280 determines that the data “1” has not been received (detected) 16 times consecutively from the voice / LED control circuit 220 (when S592 is NO), the LED driver 280 processes Is returned to S591, and the process after S591 is repeated. On the other hand, if the LED driver 280 determines that the data “1” has been received (detected) 16 times consecutively from the voice / LED control circuit 220 in S592 (if YES in S592), the LED driver 280 starts The standby state is set (S593).

  Next, the LED driver 280 determines whether data "0" has been received (S594). In this process, the LED driver 280 determines whether or not the data “0” (see FIG. 39) stored in the first bit of the device address has been received.

  If the LED driver 280 determines in step S594 that the data “0” has not been received (NO in step S594), the LED driver 280 returns the processing to step S593, and repeats the processing from step S593 onward. If the LED driver 280 has not received data “0” for a predetermined time and the start standby state continues, the LED driver 280 may perform a process of returning the operation state to the sleep state as a timeout process. .

  On the other hand, if the LED driver 280 determines in S594 that data “0” has been received (YES in S594), the LED driver 280 sets the device address standby state (S595).

  Next, the LED driver 280 receives the device address transmitted from the voice / LED control circuit 220, and determines whether or not the device address matches that set in the LED driver 280 (S596). In S596, when the LED driver 280 determines that the received device address does not match that set in the LED driver 280 (when S596 is NO), the LED driver 280 returns the process to S591, and after S591 Repeat the process of On the other hand, when the LED driver 280 determines in S596 that the received device address matches that set in the LED driver 280 (when S596 is YES), the LED driver 280 sets a register address standby state. (S597).

  Next, the LED driver 280 receives the register address transmitted from the voice / LED control circuit 220, and determines whether or not the register address is an existing register address (S598). In S598, when the LED driver 280 determines that the received register address is not a register address that exists (when S598 is NO), the LED driver 280 returns the process to S591, and repeats the processes after S591.

  On the other hand, if the LED driver 280 determines in S598 that the received register address is a register address that exists (if YES in S598), the LED driver 280 sets a data reception state (S599). Thereby, reception processing of lamp output data (LED data) transmitted from the audio / LED control circuit 220 is started. Next, the LED driver 280 determines whether data “0FFH (1111111B)” (see FIG. 39) indicating the final data of the lamp output data (LED data) has been received (S600).

  In S600, when it is determined that the LED driver 280 has not received the data “0FFH” (when S600 is NO), the LED driver 280 returns the process to S599 and repeats the processes after S599. On the other hand, when it is determined in S600 that the LED driver 280 has received the data “0FFH” (S600 is YES), the LED driver 280 returns the process to S591 and repeats the processes after S591.

[Data communication processing between host control circuit and motor driver]
Next, communication processing performed between the host control circuit 210 and the motor driver 271 will be described with reference to FIGS. 103A and 103B. FIG. 103A is a flowchart showing a procedure of transmission / reception processing of signals and serial data executed by the host control circuit 210 in communication processing between the host control circuit 210 and the motor driver 271. FIG. 103B is a flowchart showing the procedure of transmission / reception processing of signals and data executed by the motor driver 271 in the communication processing between the host control circuit 210 and the motor driver 271.

  In the present embodiment, as described above, when an accessory request is generated in the host control circuit 210, the host control circuit 210 outputs excitation data to the motor driver 271 based on the accessory request. At this time, since the host control circuit 210 and the motor driver 271 are connected by an I2C bus, signals (data) are transmitted and received between them by the I2C method. In this embodiment, the communication direction between the host control circuit 210 and the motor driver 271 is bidirectional.

  The specific procedures of the signal and data transmission / reception processing executed by the host control circuit 210 and the signal and data transmission / reception processing executed by the motor driver 271 based on the accessory request are shown in FIG. And will be described with reference to the flowchart of FIG. 103B.

(1) Data transmission / reception processing (serial data input / output processing) of the host control circuit 210
First, as shown in FIG. 103A, the host control circuit 210 issues a start condition, and transmits control bytes to all motor drivers 271 connected to the host control circuit 210 via the I2C bus (S601). . In the control byte transmitted in this process, address information for specifying a predetermined motor driver 271 to which data is to be transmitted, and whether the motor driver 271 receives data from the host control circuit 210 or the motor driver A value of a transmission / reception bit described later that determines whether the data is transmitted to the host control circuit 210 is included.

  Next, the host control circuit 210 transmits / receives serial data to / from the predetermined motor driver 271 (S602). If the value of the transmission / reception bit included in the control byte transmitted to the motor driver 271 in S601 is a value corresponding to an operation in which the motor driver 271 receives data from the host control circuit 210, the host in the process of S602. The control circuit 210 transmits, for example, excitation data of the motor 272 to the motor driver 271. On the other hand, if the value of the transmission / reception bit included in the control byte transmitted to the motor driver 271 in S601 is a value corresponding to the operation of the motor driver 271 transmitting data to the host control circuit 210, the processing in S602. The host control circuit 210 receives, for example, error information and the like from the motor driver 271.

  Next, when the data transmission / reception process is completed, the host control circuit 210 issues a stop condition (S603). Then, the host control circuit 210 ends the data transmission / reception process at the time of acquisition of the feature request.

(2) Data transmission / reception processing of motor driver First, the motor driver 271 refers to the control byte information included in the start condition issued by the host control circuit 210 as shown in FIG. It is determined whether the included address matches the address of the motor driver 271 (S611). Although the configuration of serial data transmitted from host control circuit 210 to motor driver 271 is not the same as the configuration of serial data shown in FIG. 39, serial data transmitted from host control circuit 210 to motor driver 271 is An area corresponding to the device address in FIG. 39 is provided, and the information of the control byte described above is stored in the area.

  In S611, when the motor driver 271 determines that the address included in the control byte does not match the address of the motor driver 271 (when the determination in S611 is NO), the motor driver performs the processing in S614 described later. .

  On the other hand, when the motor driver 271 determines in S611 that the address included in the control byte matches the address of the motor driver 271 (when the determination in S611 is YES), the motor driver 271 is included in the control byte. Based on the transmitted / received bit value, predetermined data (such as error information) is transmitted to the host control circuit 210 or specific data (such as excitation data) is received (S612).

  Next, the motor driver 271 determines whether the stop condition issued from the host control circuit 210 has been received (S613). If it is determined in S613 that the motor driver 271 has received a stop condition issued from the host control circuit 210 (S613 is YES), the motor driver 271 performs the process of S614 described later. On the other hand, when it is determined in S613 that the motor driver 271 has not received the stop condition issued from the host control circuit 210 (when S613 is NO), the motor driver 271 returns the process to S612. The process after S612 is repeated.

  When the determination in S611 is NO or the determination in S613 is YES, the motor driver 271 shifts the state to the standby state (S614). If NO in S611, that is, if the motor driver 271 is not the motor driver 271 that transmits / receives data to / from the host control circuit 210, the process is in a standby state at the time of S614. The motor driver 271 performs processing for maintaining the standby state.

<Various modifications>
The control method of the configuration and effect operation of the pachinko gaming machine according to the present invention is not limited to the example of the above embodiment, and various modifications can be considered. Below, the various modifications are explained.

[Modification 1]
In the voice control process (see FIGS. 93A and 93B) of the above embodiment, when the voice / LED control circuit 220 sets the access number to the execution system of sound reproduction, it determines the availability of four execution systems, Although the example which sets an access number to a vacant execution system was demonstrated, this invention is not limited to this. For example, the execution system to be set for each access number may be determined in advance. In the first modification, a processing example of the voice control processing in such a case will be described.

  In the first modification, the processing other than the voice control processing can be executed in the same manner as the above embodiment, and the configuration of the pachinko gaming machine of this example can also be the same as that of the above embodiment. Therefore, only the voice control process will be described here.

  The voice control process of the modification 1 performed in S209 in the sub control main process (see FIG. 72) will be described with reference to FIGS. 104A and 104B. FIG. 104A is a flowchart showing the procedure of the voice control process of this example executed by the host control circuit 210. FIG. 104B is a flowchart showing the procedure of the process executed by the audio / LED control circuit 220 in the audio control process of this example.

(1) Audio control processing executed by host control circuit As shown in FIG. 104A, the host control circuit 210 sends the sound request stored in the request buffer in the animation request construction processing of FIG. 85 to the audio / LED control circuit 220. It outputs (S701). Also in this example, in order to synchronize the rendering operation using LED data with the rendering operation by the display device 13, the host control circuit 210 outputs a sound request after two frames have passed since the generation of the rendering control request. .

  Then, after the processing of S701, the host control circuit 210 ends the voice control processing, and shifts the processing to S210 of the sub control main processing (see FIG. 72).

(2) Processing of audio / LED control circuit executed at the time of audio control processing First, as shown in FIG. 104B, a sound request output from the host control circuit 210 is input to the audio / LED control circuit 220 (S711) . Next, the voice / LED control circuit 220 specifies an access number based on the sound request (S712). Next, the voice / LED control circuit 220 determines an execution system of sound reproduction for setting the access number based on the specified access number (S713).

  Next, the voice / LED control circuit 220 determines whether the process is being executed in the determined execution system (S714).

  In S714, when the voice / LED control circuit 220 determines that the process is not being executed in the determined execution system (when S714 is NO), the voice / LED control circuit 220 accesses the determined execution system. The number is set (S715). On the other hand, if the voice / LED control circuit 220 determines in S714 that the process is being executed in the determined execution system (if YES in S714), the voice / LED control circuit 220 performs the determined execution. After the processing of the access number currently executed in the system is completed, the access number specified in S712 is set in the execution system so that the process of the access number specified in S712 is executed (S716). In this case, in the execution system determined in S713, the operation state of the audio / LED control circuit 220 is in a standby state until the processing of the currently executed access number is completed.

  After the processing of S715 or S716, the voice / LED control circuit 220 reads the access data associated with the access number from the CGROM board 204 in the execution system in which the access number is set (S717).

  Next, based on the access data, the voice / LED control circuit 220 sequentially sets each of the plurality of setting data specified in the access data to the corresponding address and starts the process of executing the code (process) (S718). By this processing, the effect operation of sound reproduction by the speaker 11 is started. At this time, also in this example, the audio reproduction control is executed by simple access control.

  After the process of S718, the voice / LED control circuit 220 determines whether there is a plurality of accesses to the code under reference (S719). Specifically, the voice / LED control circuit 220 determines whether or not there is access from another execution system to a code (setting data) being executed in the execution system in which the access number is set. To do.

  In S719, when the voice / LED control circuit 220 determines that there is no plurality of accesses to the code being referred to (when S719 is NO), the voice / LED control circuit 220 performs the process of S721 described later. Do. On the other hand, if the voice / LED control circuit 220 determines that there is a plurality of accesses to the code being referred to in S719 (if YES in S719), the voice / LED control circuit 220 indicates that the code is referred to. The code is executed based on the latest sound request (S720).

  After the process of S720 or when S719 is NO, the voice / LED control circuit 220 sets a simple access end code (S721). Then, after the processing of S721, the voice / LED control circuit 220 ends the above-described series of processing at the time of the voice control processing, and the processing is performed in a predetermined control state (for example, standby state, voice control) of the voice / LED control circuit 220. Control state before processing, control state of processing executed after voice control processing, etc.).

[Modification 2]
In the lamp control process (see FIGS. 94A and 94B) of the above embodiment, the processing example in the case where “NEXT” and / or “ODONLY” is not designated as the reproduction method of LED data (LED animation) has been described. Is not limited to this. In the second modification, a lamp control process will be described in consideration of the case where “NEXT” and / or “ODONLY” is designated as the reproduction method of LED data (LED animation). In the second modification, a processing example using only the reproduction channel will be described.

  In the second modification, the process other than the lamp control process can be performed in the same manner as the above embodiment, and the configuration of the pachinko gaming machine of this example can be the same as that of the above embodiment. Therefore, only the lamp control process will be described here.

  With reference to FIGS. 105A and 105B, the lamp control process of the second modification performed in S210 in the sub control main process (see FIG. 72) will be described. FIG. 105A is a flowchart showing the procedure of the lamp control process of this example executed by the host control circuit 210. FIG. 105B is a flowchart showing the procedure of the process executed by the audio / LED control circuit 220 in the lamp control process of this example.

(1) Lamp control processing executed by the host control circuit As shown in FIG. 105A, the host control circuit 210 outputs the lamp request stored in the request buffer in the animation request processing of FIG. 85 to the sound / LED control circuit 220. To do (S731). Also in this example, in order to synchronize the rendering operation using LED data with the rendering operation by the display device 13, the host control circuit 210 outputs a lamp request after two frames have elapsed since the generation of the rendering control request. .

  Then, after the processing of S731, the host control circuit 210 ends the lamp control processing of this example, and shifts the processing to S211 of the sub control main processing (see FIG. 72).

(2) Processing of voice / LED control circuit executed during lamp control processing First, as shown in FIG. 105B, the lamp request transmitted from the host control circuit 210 is input to the voice / LED control circuit 220 (S741). .

  Next, the audio / LED control circuit 220 designates a reproduction channel (sequencer, layer) for executing the LED animation based on the lamp request (S742). Specifically, the voice / LED control circuit 220 designates LED animation (various LED data) and data table information to be read from the CGROM 206 based on the lamp request, and executes the LED animation by referring to the data table information. Acquire data such as playback channels (sequencer, layer).

  Next, the audio / LED control circuit 220 determines whether or not “NEXT” is designated as the LED animation reproduction method based on the data table information designated by the reproduction channel to be processed (referenced), that is, the input. It is determined whether the requested lamp request is a request to immediately execute the lamp lighting operation (S743). Although not shown here, the processing of S743 to S745, which will be described later, is repeatedly executed by the number of channels.

  When the audio / LED control circuit 220 determines in S743 that “NEXT” is not designated as the reproduction method of the LED animation of the reproduction channel being referred to (when S743 is YES determination), the audio / LED control circuit 220 Overwrites and updates the various information (data table information and LED data) currently stored in the reproduction channel registration buffer with the corresponding various information acquired when the lamp request is received this time (S744).

  On the other hand, if the sound / LED control circuit 220 determines in step S743 that “NEXT” is designated as the playback method of the LED animation of the playback channel being referred to (when S743 is NO), the sound / LED control is performed. The circuit 220 adds various information (data table information and LED data) currently stored in the registration buffer, and then stores the corresponding various information acquired at the time of receiving the lamp request this time (additional update) (S745) ).

  After the process of S744 or the process of S745, the audio / LED control circuit 220 performs a reference process of the registration buffer of each reproduction channel (S746). Next, the voice / LED control circuit 220 selects an SPI channel (physical system) to be used when transmitting LED data to the LED driver 280 based on the control part information included in the data table information stored in the registration buffer. Designate (S747).

  Next, the audio / LED control circuit 220 determines whether or not the port to be processed (under reference) is a port to be controlled (within the control region) in a predetermined channel (S 748). The determination process of S748 is executed based on the information of the control part included in the data table information stored in the registration buffer, and the processes after S748 are repeatedly executed by the number of ports.

  If the voice / LED control circuit 220 determines in S748 that the port being referred to is not a port to be controlled (if NO in S748), the voice / LED control circuit 220 performs the process of S752 described later. On the other hand, when the voice / LED control circuit 220 determines in S748 that the port being referred to is a control target port (when S748 is YES), the voice / LED control circuit 220 is based on the data table information. Then, it is determined whether or not “ODONLY” is designated as the playback method in the playback channel (control part) to be processed (S749).

  In S749, when the audio / LED control circuit 220 determines that “ODONLY” is designated as the playback method for the processing target (referenced) playback channel (when S749 is YES), the audio / LED control is performed. The circuit 220 performs port information (LED data) overwriting processing based on the execution priority set for the channel and the presence or absence of output data (S750).

  In the processing of S750, for example, the audio / LED control circuit 220 has a higher priority for execution of the channel to be processed than the channel corresponding to the LED data currently set in the port, and the port being currently referenced (control). If there is LED data (LED data other than extinguished data) output to the target port, the LED data is overwritten on the LED data currently set in the port. On the other hand, if the channel to be processed has a higher execution priority than the channel corresponding to the LED data currently set in the port and there is no LED data to be output to the port being referred to (the output data is turned off) And the LED data currently set in the port is maintained without overwriting the LED data. If the channel to be processed has a lower execution priority than the channel corresponding to the LED data currently set in the port, the LED data is displayed regardless of the presence or absence of the LED data output to the port under reference. The overwriting process is not performed, and the LED data currently set in the port is maintained.

  On the other hand, when it is determined in S749 that the audio / LED control circuit 220 determines that “ODONLY” is not designated as the reproduction method in the reproduction channel to be processed (during reference) (in the case of NO determination in S749) The LED control circuit 220 performs port information (LED data) overwriting processing based on the execution priority set for the channel (S751).

  In the process of S751, for example, if the channel to be processed has a higher execution priority than the channel corresponding to the LED data currently set in the port, the audio / LED control circuit 220 sets the LED data to The LED data currently set in the port is overwritten. At this time, overwriting processing of the LED data is also performed when the output data is LED data of the transparent definition (light-off data). On the other hand, when the channel to be processed has a lower execution priority than the channel corresponding to the LED data currently set in the port, the LED data overwrite processing is not performed, and the LED currently set in the port is Data is maintained.

  After the processing of S750 or S751, or if S748 is NO, the audio / LED control circuit 220 performs the processing of S748 to S751 described above for all reproduction channels (for eight channels) of the port being referred to. It is determined whether or not it has been executed (S752).

  In S752, when the sound / LED control circuit 220 determines that the processes of S748 to S751 are not executed for all the reproduction channels (when S752 is NO), the sound / LED control circuit 220 Is returned to S748, the playback channel to be processed is changed, and the processes after S748 are repeated.

  On the other hand, when the sound / LED control circuit 220 determines in S752 that the processes of S748 to S751 have been executed for all playback channels (when S752 is YES), the sound / LED control circuit 220 refers to The voice / LED control circuit 220 determines whether or not the port direct specification data for the internal port is included in the lamp request, and if the port direct specification data is included in the lamp request, the voice / LED control circuit 220 selects the port under reference. The LED data of is directly overwritten with the port designation data (S753).

  Next, the voice / LED control circuit 220 determines whether or not the processing of S748 to S753 described above has been executed for all ports (S754). Here, “all ports” means all ports set in the LED registration process shown in FIG. 77, but the present invention is not limited to this. "All ports" may be all ports which can be physically set arbitrarily regardless of the ports set in the LED registration process shown in FIG. 77, or set in the LED registration process shown in FIG. It may be a partial port selected from among the selected ports.

  In S754, when the voice / LED control circuit 220 determines that the processing of S748 to S753 is not executed for all ports (when S754 is NO), the voice / LED control circuit 220 performs the process. Returning to S748, the processing target port is changed, and the processing after S748 is repeated. On the other hand, when the voice / LED control circuit 220 determines in S754 that the processing of S748 to S753 has been executed for all ports (YES in S754), the voice / LED control circuit 220 performs lamp control. The above-described series of processing at the time of processing is ended, and the processing is performed in a predetermined control state of the audio / LED control circuit 220 (for example, standby state, control state before lamp control processing, control state of processing executed after lamp control processing, etc. ) Return to the process of the time.

[Modification 3]
In the third modification, in the lamp control process of the second modification, a processing example in which not only the reproduction channel but also the extension channel is used will be described. In the third modification, the processes other than the lamp control process can be executed in the same manner as the above embodiment, and the configuration of the pachinko gaming machine of this example can be the same as that of the above embodiment. Therefore, only the lamp control process will be described here.

  With reference to FIGS. 106A and 106B, the lamp control process of the modification 3 performed in S210 in the sub control main process (see FIG. 72) will be described. FIG. 106A is a flowchart showing the procedure of the lamp control process of this example executed by the host control circuit 210. FIG. 106B is a flowchart showing the procedure of the process executed by the audio / LED control circuit 220 in the lamp control process of this example.

(1) Lamp Control Process Performed by Host Control Circuit As shown in FIG. 106A, the host control circuit 210 outputs the lamp request stored in the request buffer in the animation request process of FIG. 85 to the audio / LED control circuit 220. (S761). Also in this example, in order to synchronize the rendering operation using LED data with the rendering operation by the display device 13, the host control circuit 210 transmits a lamp request after two frames have elapsed since the generation of the rendering control request. .

  Then, after the process of S761, the host control circuit 210 ends the lamp control process of this example, and shifts the process to S211 of the sub control main process (see FIG. 72).

(2) Processing of voice / LED control circuit executed at the time of lamp control processing First, as shown in FIG. 106B, the lamp request transmitted from the host control circuit 210 is inputted to the voice / LED control circuit 220 (S771) .

  Next, the audio / LED control circuit 220 designates a channel (sequencer, layer) for executing the LED animation based on the lamp request (S772). When an extension channel is used, in this process, the audio / LED control circuit 220 designates a sequencer and a layer to be used in the extension channel and the playback channel of the same channel. On the other hand, when the extension channel is not used, in this process, the audio / LED control circuit 220 designates a sequencer or a layer to be used in the reproduction channel.

  Next, the audio / LED control circuit 220 is input based on whether or not “NEXT” is designated as the LED animation playback method based on the data table information designated in the channel to be processed (referenced). It is determined whether the lamp request is a request to immediately execute the lamp lighting operation (S773). Although not illustrated here, the processes of S733 to S775 described later are repeatedly executed by the number of channels.

  In S773, when the sound / LED control circuit 220 determines that “NEXT” is not designated as the LED animation playback method of the channel being referred to (when S773 is YES), the sound / LED control circuit 220 The various information (data table information and LED data) currently stored in the channel registration buffer is overwritten and updated with the corresponding various information acquired at the time of reception of the lamp request this time (S774).

  On the other hand, if the sound / LED control circuit 220 determines in step S773 that “NEXT” is designated as the LED animation playback method of the channel being referred to (if S773 is NO), the sound / LED control circuit 220 220 stores various additional information (data table information and LED data) currently stored in the channel registration buffer, and stores (additional updates) corresponding various information acquired at the time of the current lamp request reception ( S775).

  When the extension channel is used, in the processing of S774 or S775, the audio / LED control circuit 220 performs various types of information (data table information and information for each registration buffer of the reproduction channel and the extension channel of the channel being referred to). Overwrite update processing or additional update processing of LED data) is performed. On the other hand, when the extended channel is not used, in the processing of S774 or S775, the audio / LED control circuit 220 stores various information (data table information and LED data) with respect to the reproduction buffer registration buffer of the channel being referred to. Perform overwrite update processing or additional update processing.

  After the processing of S774 or after the processing of S775, the voice / LED control circuit 220 performs data setting processing of each port (S776). With this process, the combined LED data (output data) is set to each port to be controlled. The details of the data setting process of each port will be described later with reference to FIG. 107 described later. After the process of S776, the voice / LED control circuit 220 ends the above-described series of processes at the time of the lamp control process, and the process is performed in a predetermined control state (for example, standby state, lamp control) of the voice / LED control circuit 220. Control state before processing, control state of processing executed after lamp control processing, etc.).

(3) Data setting processing of each port Next, referring to FIG. 107, the data of each port performed in S776 in the processing of the sound / LED control circuit (see FIG. 106B) executed during the lamp control processing of this example The setting process will be described. FIG. 107 is a flowchart showing a procedure of data setting processing of each port performed by the audio / LED control circuit 220 in the lamp control processing of this example.

  First, the sound / LED control circuit 220 performs a reference process of the registration buffer of each channel (S781).

  Next, the audio / LED control circuit 220 uses the two sequencers in the predetermined channel based on the data table information stored in the registration buffer of the predetermined channel to be processed (referenced) (reproduction channel and extended channel). It is determined whether or not a channel is used (S782). Although not shown here, a series of processes from S782 to S784 which will be described later are repeatedly executed by the number of channels.

  If the audio / LED control circuit 220 determines in step S782 that two sequencers are to be used for a predetermined channel (YES in step S782), the audio / LED control circuit 220 uses the registration buffers for the reproduction channel and the extended channel. The SPI channel (physical system) used in each control part controlled by each sequencer is designated based on the data table information stored in (S783). On the other hand, when the audio / LED control circuit 220 determines in S782 that two sequencers are not used in a predetermined channel (when the determination in S782 is NO), the audio / LED control circuit 220 uses the registration buffer of the reproduction channel. Based on the stored data table information, an SPI channel (physical system) to be used in a control part controlled by the playback channel sequencer is designated (S784).

  Next, the voice / LED control circuit 220 determines whether or not the port to be processed (under reference) is a port to be controlled (within the reproduction channel) in the predetermined channel (S785). The determination process of S785 is executed based on the data table information stored in the registration buffer of the reproduction channel, and the series of processes of S785 to S791, which will be described later, are repeated for the number of ports.

  If the audio / LED control circuit 220 determines in S785 that the port being referred to is not a port to be controlled (if NO in S785), the audio / LED control circuit 220 performs the process of S789 described later. On the other hand, if the voice / LED control circuit 220 determines in S785 that the port being referred to is the port to be controlled (if S785 is YES), the voice / LED control circuit 220 is based on the data table information. Then, it is determined whether or not “ODONLY” is designated as the reproduction method for the reproduction channel (control part) to be processed (referenced) (S786).

  In S786, when the sound / LED control circuit 220 determines that “ODONLY” is designated as the playback method in the playback channel being referred to (when S786 is YES), the sound / LED control circuit 220 Based on the channel execution priority and the presence / absence of output data, the port information (LED data) is overwritten (S787). In this process, the same process as S750 in the lamp control process (FIGS. 105A and 105B) of the second modification is performed.

  On the other hand, when the sound / LED control circuit 220 determines in step S786 that “ODONLY” is not designated as the playback method in the reference playback channel (when S786 is NO), the sound / LED control circuit 220 The port information (LED data) is overwritten based on the execution priority set to the channel (S788). In this process, the same process as S751 in the lamp control process (FIGS. 105A and 105B) of the second modification is performed.

  After the processing of S787 or S788, or if S788 is NO, the audio / LED control circuit 220 performs the processing of S785 to S788 described above for all reproduction channels (for eight channels) of the port being referred to. It is determined whether or not it has been executed (S789).

  When the audio / LED control circuit 220 determines in S789 that the processing of S785 to S788 is not executed for all reproduction channels (when the determination in S789 is NO), the audio / LED control circuit 220 performs the processing Is returned to S785, the playback channel to be processed is changed, and the processes after S785 are repeated.

  On the other hand, if the voice / LED control circuit 220 determines in S789 that the processing of S785 to S788 has been executed for all reproduction channels (if YES in S789), the voice / LED control circuit 220 The voice / LED control circuit 220 determines whether or not the port direct specification data for the internal port is included in the lamp request, and if the port direct specification data is included in the lamp request, the voice / LED control circuit 220 selects the port under reference. The LED data of are directly overwritten with the port designation data (S790).

  Next, the voice / LED control circuit 220 determines whether or not the above-described processing of S785 to S790 has been executed for all ports (S791).

  If the sound / LED control circuit 220 determines in S791 that the processes in S785 to S790 have not been executed for all ports (S791 is NO), the sound / LED control circuit 220 performs the process. The process returns to S785, the port to be processed is changed, and the processes after S785 are repeated. On the other hand, if the sound / LED control circuit 220 determines in S791 that the processes in S785 to S790 have been executed for all ports (S791 is YES), the sound / LED control circuit 220 is described later. The processing of S792 is performed.

  In this example, when the extension channel is also used, the same processing as the processing of S785 to S791 performed for the reproduction channel is similarly performed for the extension channel. At this time, the processing of S785 to S791 for the reproduction channel and the processing of S785 to S791 for the extension channel are simultaneously performed in parallel processing. At this time, the processing of S785 to S791 for the reproduction channel is actually executed by the sequencer set to the reproduction channel, and the processing of S785 to S791 for the extension channel is performed by the sequencer set to the extension channel. To be executed.

  If S791 is YES, has the audio / LED control circuit 220 executed the series of processes of S785 to S791 using two sequencers (a playback channel sequencer and an extension channel sequencer) in a predetermined channel? It is determined whether or not (S792). Here, although not shown, a series of processes from S792 to S794 described later are repeatedly executed by the number of channels.

  In S792, when it is determined that the voice / LED control circuit 220 has executed a series of processes of S785 to S791 using two sequencers (when S792 is YES), each of the voice / LED control circuit 220 The sequencer sets (reserves) clear data (light-out data) in the corresponding control region (S793). On the other hand, if it is determined in S782 that the voice / LED control circuit 220 has not executed the series of processing of S785 to S791 using two sequencers (S792 is NO), the voice / LED control circuit 220 220 executes a reproduction channel clear function (S794). By this processing, clear data (light-off data) is set (reserved) in the control part of the reproduction channel.

  Then, after the series of processing of S792 to S794 described above is executed in all channels, the voice / LED control circuit 220 ends the data setting processing of each port.

[Modification 4]
In the above embodiment, between the voice / LED control circuit 220 and each LED driver 280 between the voice / LED control circuit 220 (master) and each LED driver 280 (slave) connected by the SPI bus, LED data and Although the configuration for transmitting serial data including device address data and specifying the transmission LED driver 280 by the device address data included in the serial data has been described, the present invention is not limited thereto.

  For example, when serial data is transmitted / received between the audio / LED control circuit 220 and the LED driver, an LED driver to be transmitted / received by a slave select signal may be designated. In the fourth modification, a configuration example in which an LED driver that is a transmission destination of serial data (LED data or the like) is specified using a slave select signal (SS signal) will be described.

  In the following, the connection configuration between the voice / LED control circuit and the LED driver, the communication principle, and the communication processing procedure in this example will be described. In the pachinko gaming machine of this example, between the voice / LED control circuit and the LED driver The configuration other than the communication mode can be configured in the same manner as the above embodiment. Therefore, here, only the form of communication (configuration and communication control method) between the voice / LED control circuit and the LED driver will be described.

[Connection between voice / LED control circuit and LED driver]
First, the connection configuration between the audio / LED control circuit 290 and the LED driver 291 of the fourth modification will be described with reference to FIG. FIG. 108 is a diagram showing a connection configuration between the audio / LED control circuit 290 and the LED driver 291 of this example.

  Also in this example, since the audio / LED control circuit 290 and the LED driver 291 are connected by the SPI bus, in each physical system (SPI channel), the serial clock (SCL) signal wiring and the serial data ( (SDO, SDI) signal wiring is provided separately. In each physical system (SPI channel) of the sound / LED control circuit 290 (master), each output terminal (SCL1, SCL2) of the serial / clock signal of the sound / LED control circuit 290 has a plurality of corresponding LED drivers 291. It is connected in parallel to the input terminal (SCL) of the (slave) serial clock signal. Further, the serial data output terminals (SDO1, SDO2) of the audio / LED control circuit 290 are connected in parallel to the serial data input terminals (SDI) of the corresponding LED driver 291. Furthermore, the serial data input terminals (SDI1, SDI2) of the audio / LED control circuit 290 are connected in parallel to the serial data output terminals (SDO) of the corresponding plurality of LED drivers 291.

  Further, in this example, as shown in FIG. 108, the audio / LED control circuit 290 (master) is provided with a plurality of slave select terminals (SS1, SS2, SS3), and each LED driver 291 (slave) is provided. The slave select terminal (SS) is also provided. The slave select terminal (SS) provided in each LED driver 291 is additionally provided, for example, in the terminal group 280 d of the LED driver 280 in the embodiment described above with reference to FIG. Each slave / select terminal of the audio / LED control circuit 290 is connected to a slave / select terminal (SS) of the corresponding LED driver 291.

[Principle of communication]
Next, the principle of serial data communication between the audio / LED control circuit 290 (master) and the LED driver 291 (slave) will be described with reference to FIG. Note that FIG. 109 is a diagram showing an aspect of the communication operation of serial data between the audio / LED control circuit 290 (master) and the LED driver 291 (slave).

  As shown in FIG. 109, the sound / LED control circuit 290 includes a buffer (first storage means), a shift register (first input / output means), and a shift / clock generator, and each LED driver 291 includes a buffer. (Second storage means) and shift register (second input / output means). The shift register in the audio / LED control circuit 290 is composed of an 8-bit shift register. Also, the shift register in the LED driver 291 is also composed of an 8-bit shift register.

  In the serial / data communication operation between the sound / LED control circuit 290 (master) and the LED driver 291 (slave), the operation of the shift register in the sound / LED control circuit 290 is input from the shift clock generator. Controlled based on serial clock signal. In addition, the operation of the shift register in the LED driver 291 is also controlled based on the serial clock signal output from the shift clock generator in the audio / LED control circuit 290. Note that the serial clock signal output from the shift / clock generator in the sound / LED control circuit 290 is the serial clock signal wiring (the SCL terminals (SCL1, SCL2) of the sound / LED control circuit 290 and the LED driver 291). Is input to the LED driver 291 via the connection wiring between the SCL terminals of the In this example, data communication is performed in units of 8 bits.

  When the serial / data communication operation from the voice / LED control circuit 290 (master) to the LED driver 291 (slave) is started, the buffer in the voice / LED control circuit 290 (master) starts the voice / LED control circuit 290. The transmission data (8 bits) is transmitted to the shift register, and the data (M0 to M7) of each bit constituting the transmission data is stored in the corresponding register in the shift register. Also, transmission data (8 bits) is transmitted from the buffer in the LED driver 291 (slave) to the shift register in the LED driver 291, and the data (S0 to S7) of each bit constituting the transmission data is transmitted to the shift register. Stored in the corresponding register in

  Next, the 1-bit data M7 stored in the first register of the shift register in the voice / LED control circuit 290 is converted into serial data communication wiring (SDO terminal (SDO1 or SDO2) of the voice / LED control circuit 290) and the LED. It is transmitted to the LED driver 291 via the connection wiring between the SDI terminals of the driver 291). Also, at this time, the data (M0 to M6) stored in the shift register of the audio / LED control circuit 290 is shifted and stored in the first register on the head side.

  Simultaneously with the transmission processing of the data M7 of the voice / LED control circuit 290, the 1-bit data S7 stored in the head register of the shift register in the LED driver 291 is connected to the serial data communication wiring (voice / LED control). The audio / LED control circuit 290 is transmitted via the connection terminal between the SDI terminal (SDI1 or SDI2) of the circuit 290 and the SDO terminal of the LED driver 291. Also, at this time, the data (S0 to S6) stored in the shift register of the LED driver 291 is shifted and stored in the first head side register.

  Then, the data M7 transmitted from the voice / LED control circuit 290 to the LED driver 291 is stored in the last register in the shift register of the LED driver 291. At this time, the data S7 transmitted from the LED driver 291 to the voice / LED control circuit 290 is stored in the last register in the shift register of the voice / LED control circuit 290.

  FIG. 110 shows the data storage state of the shift register in the audio / LED control circuit 290 and the data storage state of the shift register in the LED driver 291 when the 1-bit data communication described above is completed. As shown in FIG. 110, in the data communication of this example, data is sequentially exchanged from the last register of each shift register.

  When the 1-bit data communication described above is repeated 8 times, the data in the shift register of the voice / LED control circuit 290 and the data in the shift register of the LED driver 291 are interchanged, and the 8-bit data Communication ends. When the 8-bit data communication is completed, the 8-bit received data (S0 to S7) stored in the shift register of the voice / LED control circuit 290 is transmitted to and stored in the buffer in the voice / LED control circuit 290. Be done. Also, 8-bit received data (M0 to M7) stored in the shift register of the LED driver 291 is transmitted to and stored in a buffer in the LED driver 291.

[Communication between voice / LED control circuit and LED driver]
Next, with reference to FIGS. 111A and 111B, communication processing of this example performed between the audio / LED control circuit 290 and the LED driver 291 will be described. FIG. 111A is a flowchart showing the procedure of signal / data transmission / reception processing of this example executed by the voice / LED control circuit 290. FIG. 111B is a flowchart illustrating a procedure of signal and data transmission / reception processing executed by the LED driver 291 in the communication processing between the voice / LED control circuit 290 and the LED driver 291 in this example.

(1) Audio / LED Control Circuit Serial / Data Input / Output Processing First, the audio / LED control circuit 290 transmits a slave selector signal (SS signal) to all LED drivers 291 as shown in FIG. 111A. (S801). At this time, the slave select signal is received only in the LED driver 291 corresponding to the device address designated by the slave select signal (address designation signal).

  Next, the voice / LED control circuit 290 performs transmission / reception processing of serial data with the LED driver 291 of the device address designated by the slave select signal (S802). At this time, the voice / LED control circuit 290 transmits / receives serial data in 8-bit units in accordance with the communication principle described using FIG. 109 and FIG. 110 above. Next, the voice / LED control circuit 290 completes the serial data transmission / reception process (S803).

  Next, the voice / LED control circuit 290 stops transmission of the slave select signal (S804). Then, after the processing of S804, the voice / LED control circuit 290 ends the serial data input / output processing.

(2) LED Driver Serial Data Input / Output Processing First, as shown in FIG. 111B, the LED driver 291 determines whether or not a slave select signal has been received (S811). In this process, if the LED driver 291 is the LED driver 291 corresponding to the device address specified by the slave select signal, the result of the determination process of S811 is YES.

  If the LED driver 291 determines in S811 that the slave select signal has not been received (NO in S811), the LED driver 291 performs the process of S814 described below. On the other hand, if the LED driver 291 determines in S811 that the slave select signal has been received (YES in S811), the LED driver 291 shifts the operating state from the standby state to the active state (S812).

  After the processing of S812, the LED driver 291 performs transmission / reception processing of serial data with the audio / LED control circuit 290 (S813). At this time, the LED driver 291 transmits and receives serial data in units of 8 bits in accordance with the communication principle described using FIG. 109 and FIG. 110 above. Then, the LED driver 291 completes the serial data transmission / reception process.

  After the process of S813 or when S811 is NO, the LED driver 291 shifts the operating state to the standby state or maintains the standby state (S814). Then, after the process of S814, the LED driver 291 ends the serial data input / output process.

  In this example, as described above, only a specific LED driver 291 can be specified by the slave select signal transmitted from the sound / LED control circuit 290, and data can be transmitted to the LED driver 291. In this case, the number of signal wirings between the sound / LED control circuit 290 and the LED driver 291 is larger than that in the above embodiment, but the processing load on the LED driver 291 can be reduced. The balance between the processing load and the processing load of the LED driver 291 can be adjusted.

[Modification 5]
In the above embodiment, a configuration in which one LED 281 is connected to each port, that is, an example (an example of static output control) in which the LED 281 is a static LED has been described, but the present invention is not limited thereto. A configuration in which a plurality of LEDs are connected to each port, that is, the LEDs may be dynamically controlled LEDs (hereinafter referred to as dynamic LEDs).

  In the fifth modification, a configuration example (a configuration example of dynamic output control) in the case where the LED is a dynamic LED will be described with reference to FIG. FIG. 112 is an example showing an example of dynamic output control of LED data. In the example shown in FIG. 112, an example in which three LEDs (red LED, blue LED and green LED) are connected to one port 1 is shown. In this example, the reproduction time (lighting time) in the LED data is “12” (approximately 48 msec), and the red component luminance data, the green component luminance data, and the blue component luminance data are “0xFE”. An example will be described. That is, in this example, the data type (format) of the LED data is the same as that of the above embodiment (see FIG. 45).

  When the LED data of the above data type is input to the LED driver, the LED driver refers to the control part information (including the LED type information) and corresponds to the type of LED connected from the LED data. The drive signal corresponding to the luminance data is output to the LED through the port 1. Therefore, only red luminance data “0xFE” in the LED data is output to the red LED, and the red LED is lit for about 48 msec at a luminance corresponding to the red luminance data “0xFE”. Further, only the blue luminance data “0xFE” in the LED data is output to the blue LED, and the blue LED is lit for about 48 msec at a luminance corresponding to the blue luminance data “0xFE”. Further, only the green luminance data “0xFE” in the LED data is output to the green LED, and the green LED is lit for about 48 msec at a luminance corresponding to the green luminance data “0xFE”. In this case, white lighting is performed by the three LEDs of red, blue and green. In this example, since the LED is dynamically controlled, when the lighting period is 48 msec, the LED driver corresponds to the luminance data “0xFE” while switching the red LED, the green LED, and the blue LED in this order at intervals of 2 msec. A drive signal is output to each LED, and the switching operation of this series of drive signals is repeated eight times.

  As described above, in this example, since the data type of the LED data is the same as that of the above embodiment, all static LEDs included in the pachinko gaming machine 1 of the above embodiment may be replaced with dynamic LEDs. Some static LEDs may be replaced with dynamic LEDs.

  In this example, as described above, the data type (format) of the LED data output to the dynamic LED can be the same as that of the static LED in the above embodiment. In this case, even when a plurality of LEDs having different LED output control methods are used at the same time, LED data of the same data type can be transmitted, so for each type of output control executed by the LED driver, There is no need to prepare LED data of different data types. Further, in this case, the LED data creation process and the LED data output process can be made common regardless of the type of output control of the LED. Therefore, even if a plurality of different LED output control methods are used in combination, the LED data used in the reproduction channel can be easily synthesized (overwritten, updated, etc.), and complicated LED output control can be easily performed. It can be done.

  Furthermore, in this example and the above embodiment, the data type of the LED data is the same regardless of the type of LED output control. Therefore, regardless of the number of LEDs in the control part controlled by the LED driver, each LED data The synthesis process is facilitated, and more complicated LED control can be implemented. That is, in this example, it is possible to increase the options for effect control using the LED, and more advanced effect control can be realized.

[Modification 6]
In the sixth modification, a configuration example of a pachinko gaming machine further having a function of detecting an excitation state (excitation continuation time or the like) of the motor 272 that drives the accessory 20 and performing error detection based on the detection result is described. Explained in. In the sixth modification, the configuration other than the excitation state detection function of the motor 272 can be configured in the same manner as the above embodiment. Therefore, only the configuration and process for realizing the detection function of the excitation state of the motor 272 will be described here.

(1) Configuration Example of Motor Excitation State Detection First, a configuration example of a detection function of the motor 272 excitation state will be described with reference to FIG. FIG. 113 is a schematic configuration diagram of a detection function unit of the excitation state of the motor 272 in the sixth modification. In this example, an example in which four motors 272 are connected to the motor driver 271 will be described.

  In this example, the excitation state detection function unit 275 of the motor 272 (hereinafter referred to as the excitation state detection unit 275) includes three OR circuits (a first OR circuit 276, a second OR circuit 277, and a third OR circuit) as shown in FIG. 278) is configured.

  One input terminal of the first OR circuit 276 in the excitation state detection unit 275 is connected to the output terminal OUT0 among the four output terminals of the motor driver 271, and the other input terminal of the first OR circuit 276 is connected to the motor driver 271. Are connected to the output terminal OUT1. Also, one input terminal of the second OR circuit 277 is connected to the output terminal OUT3 of the motor driver 271 and the other input terminal of the second OR circuit 277 is connected to the output terminal OUT4 of the motor driver 271.

  One input terminal of the third OR circuit 278 in the excitation state detection unit 275 is connected to the output terminal of the first OR circuit 276, and the other input terminal of the third OR circuit 278 is connected to the output terminal of the second OR circuit 277. Ru. The output terminal of the third OR circuit 278 is connected to a predetermined input terminal P for detecting the excitation state provided in the motor driver 271.

  In the pachinko gaming machine provided with the excitation state detection unit 275 (excitation detection means) having the configuration shown in FIG. 113, if excitation data is output from the motor driver 271 to at least one of the four motors 272, the excitation state detection unit 275. From the third OR circuit 278, data “1” is output to the motor driver 271 as an excitation detection signal (discrimination result signal). On the other hand, when excitation data is not output to any of the four motors 272 from the motor driver 271, the third OR circuit 278 in the excitation state detector 275 receives data “0” as an excitation detection signal. It is output to 271.

  In this example, the host control circuit 210 determines whether at least one of the four motors 272 is in an excited state based on the excitation detection signal (“1” or “0”) input to the motor driver 271. Do. Then, the host control circuit 210 counts the time during which the motor 272 is continuously excited (the time during which the excitation detection signal “1” is continuously detected), and the continuous excitation time becomes not less than a predetermined value. If so, the driving of all the motors 272 is stopped. Here, “all motors 272” means all motors 272 connected to the motor driver 271, but the present invention is not limited to this, and is all motors that drive the accessory 20. It may be a plurality of motors 272 connected to a plurality of motor drivers 271.

  The configuration of the excitation state detection unit 275 is not limited to the example shown in FIG. 113, and any configuration may be used as long as it can be determined whether at least one of the plurality of motors 272 is in an excitation state. can do. For example, the number of OR circuits included in the excitation state detection unit 275 and the connection form between the OR circuits can be changed as appropriate according to, for example, the number of motors 272 connected to the motor driver 271. Further, for example, the excitation state of a part of the motors 272 having a high operation rate among the plurality of motors 272 may be determined. In this case, the excitation state detection unit 275 is connected only to output terminals corresponding to some motors 272 having a high operation rate to be monitored among a plurality of output terminals of excitation data provided in the motor driver 271. Be done. Further, in the configuration in which the excitation state of a part of the motors 272 to be monitored among the plurality of motors 272 is determined, a part of the motors 272 are arbitrarily selected regardless of the operation rate, and the part of the selected part is selected. The excitation state of the motor 272 may be monitored.

(2) Accessory Control Process Next, the accessory control process of this example executed by the host control circuit 210 will be described in more detail with reference to FIG. FIG. 114 is a flowchart showing the procedure of the character control process of this example.

  First, the host control circuit 210 determines whether reset processing of the I2C controller 261 is in progress (S821).

  In S821, when the host control circuit 210 determines that the I2C controller 261 is being reset (S821 is YES), the host control circuit 210 ends the accessory control process. On the other hand, when the host control circuit 210 determines in S821 that the I2C controller 261 is not being reset (S821 is NO), the host control circuit 210 determines whether all the motors 272 are in the initial position. (S822).

  In S822, when the host control circuit 210 determines that all the motors 272 are in the initial position (when S822 is YES), the host control circuit 210 determines that each motor driver 271 (motor The excitation data is output at 272) (S823). Thereby, the rendering operation (driving operation of the motor 272) using the character 20 is started. Next, the host control circuit 210 determines whether an error has occurred during the rendering operation (driving operation of the motor 272) using the accessory 20 (S824).

  In S824, when the host control circuit 210 determines that an error has occurred (when the determination in S824 is YES), the host control circuit 210 performs the process of S830 described later. On the other hand, when the host control circuit 210 determines in S824 that no error has occurred (when S824 is NO), the host control circuit 210 determines the duration (continuous excitation time) of the excitation state of the motor 272. Measure (S825). In this process, the host control circuit 210 measures the continuous excitation time of the motor 272 based on the excitation detection signal input from the third OR circuit 278 in the excitation state detection unit 275 to the motor driver 271.

  After the processing of S825, the host control circuit 210 determines whether or not the continuation time (continuous excitation time) of the excitation state of the motor 272 is a predetermined time or more (S826).

  In S826, when the host control circuit 210 determines that the continuous excitation time of the motor 272 is equal to or longer than the predetermined time (when S826 is YES), the host control circuit 210 performs the process of S830 described later. On the other hand, when the host control circuit 210 determines in S826 that the continuous excitation time of the motor 272 is not longer than the predetermined time (when S826 is NO), the host control circuit 210 determines whether the motor 272 is being excited. It is determined (S827).

  In S827, when the host control circuit 210 determines that the motor 272 is being excited (when the determination in S827 is YES), the host control circuit 210 returns the process to S824 and performs the processes of S824 and subsequent steps. On the other hand, if the host control circuit 210 determines in S827 that the motor 272 is not exciting (NO in S827), the host control circuit 210 ends the bonus control process.

  Here, returning to the process of S822 again, in S822, when the host control circuit 210 determines that one or more motors 272 are not in the initial position (when S822 is NO), the host control circuit 210 The excitation data for moving (returning) the accessory 20 to the initial position is output to the motor 272 (S 828). Next, the host control circuit 210 determines whether or not an error has occurred in the operation of moving the accessory 20 to the initial position (drive operation of the motor 272) (S829).

  If the host control circuit 210 determines in S829 that an error has occurred (if YES in S829), the host control circuit 210 performs the process of S830 described later. On the other hand, when the host control circuit 210 determines in S829 that no error has occurred (S829 is NO), the host control circuit 210 ends the accessory control process.

  If YES in S824, S826 or S829, the host control circuit 210 stops the drive operation of all the motors 272 (S830). Specifically, the host control circuit 210 releases the excitation of all the motors 272. Then, after the processing of S830, the host control circuit 210 ends the bonus control processing.

  In the process of S830, the host control circuit 210 further controls the display device 13 to display information indicating that a driving error of the accessory 20 has occurred on the display screen. However, this error display is not canceled until the power is turned off.

  As described above, in this example, the drive operation of all the motors 272 is stopped when the continuous excitation time of the motors 272 becomes equal to or more than the predetermined time. The threshold of the continuous excitation time of the motor 272 for determining whether or not to stop the driving operation of the motor 272 (protection processing of the motor 272) is arbitrarily set according to the contents of the effect by the accessory 20, for example. It can be set. In addition, the detection process of the excitation state (continuous excitation time) of the motor 272 and the protection process of the motor 272 based on the detection result are performed as an additional process of the accessory control process (see FIG. 95) performed in the embodiment. The process after S499 in the accessory control process (see FIG. 95) of the above embodiment may be replaced with the process of the flowchart shown in FIG.

  The excitation data output from the host control circuit 210 to the motor 272 (motor driver 271) based on the accessory request may be composed of excitation data corresponding to one predetermined operation of the accessory 20. There are also cases where it is configured by a plurality of excitation data respectively corresponding to a plurality of predetermined operations.

  In the latter case, a plurality of excitation data are output in a predetermined order from the host control circuit 210 to the motor 272 (motor driver 271) based on the accessory request. Then, in this case, in the accessory control process of this example, the processing of S824 to S827 in FIG. 114 is repeated for each excitation data (every operation of the accessory). Therefore, for example, in the operation of outputting excitation data corresponding to the predetermined operation in the middle of a series of driving operations of the accessory 20, the continuous excitation time of the motor 272 becomes equal to or longer than the predetermined time (YES in S826) And the driving operation of the motor 272 is stopped at that time, and then the output processing of the excitation data for each operation to be output is also stopped.

(3) Various effects obtained by the configuration of this example As described above, in this example, the output state of the excitation data (voltage signal) output from the motor driver 271 to at least one motor 272 (the excitation state of the motor 272) Is detected by the excitation state detection unit 275, and based on the detection result, the continuous excitation time of the motor 272 (continuous drive time of the prize 20) is measured. Then, based on the measured continuous excitation time of the motor 272 (continuous drive time of the character 20), it is determined whether or not all the motors 272 are to be stopped (excitation release).

  By providing such a function for detecting the excitation state of the motor 272, for example, it is possible to detect when excitation data is excessively output to the motor 272 or when unintended motor excitation is performed. Can. As a result, the operation of the accessory 20 can be guaranteed, and the failure of the motor 272 can be suppressed.

  In addition, when the excitation state of the motor 272 is detected (managed) for each operation of the accessory 20, the driving of the motor 272 can be stopped at a timing with good separation of the production operation. A stop process of the motor 272 can be performed.

  Furthermore, in this example, when an abnormality is detected in the excitation state of the motor 272, the error display is continued on the display screen of the display device 13 until the power is turned off. Therefore, in this case, it is possible to urge the process of turning off the power to forcibly open the motor 272.

Although the pachinko game machine was mentioned as an example and demonstrated as a game machine in the said embodiment and said various modifications, this invention is not limited to this. The various techniques of the present invention described above can be applied to other gaming machines, for example, various gaming machines such as a ball game machine, a pachislot gaming machine, a gaming machine, an enclosed gaming machine, and a rotating gaming machine. It can also be applied.
As described above, a pachinko gaming machine having a plurality of types of LEDs having different output control modes has been proposed. However, for example, Patent Document 1 does not mention a specific LED output control technique. In particular, the LED output control method when executing the LED animation (turning on / off effect operation with a plurality of LEDs) is not taken into consideration.
The present invention has been made in view of the above situation, and an object of the present invention is to enable more advanced effect control in a gaming machine provided with an effect function by LED animation.
And, according to the gaming machine of the present invention of the above configuration, in the gaming machine provided with the rendering function by the LED animation (predetermined lamp lighting pattern), more advanced rendering control can be executed. The reason why this effect is obtained is as described in detail in the description of the above embodiment.

  DESCRIPTION OF SYMBOLS 1 ... pachinko game machine (game machine), 2 ... main body, 3 ... base door, 4 ... glass door, 11 ... speaker, 12 ... game board, 13 ... display device, 15 ... launch device, 16 ... payout device, 18 ... Lamp (LED) group, 20: character, 43: ball passage detector, 44: first starting opening, 45: second starting opening, 46: ordinary electric role, 51, 52: general winning opening, 53: fifth 1 large winning opening 54, second large winning opening 55 out mouth 56 56 game nail 61 special symbol display device 62 normal symbol display device 63 normal symbol holding display device 64 first special Symbol hold display device 65: second special symbol hold display device 70: main control circuit 71: main CPU 72: main ROM 73: main RAM 77: one-chip microcomputer 123: payout and firing control circuit 200 ... secondary control circuit, 201 ... relay board 202 ... sub board, 203 ... control ROM board, 204 ... CG ROM board, 205 ... sub main ROM, 206 ... CG ROM, 210 ... host control circuit, 210 a ... sub work RAM, 210 b ... SRAM, 220, 290 ... audio and LED control Circuits 230 Display control circuit 234 Video decoder 235 Still image decoder 236 SDRAM controller 237 Built-in VRAM 238 First display controller 239 Second display controller 240 3D geometry engine 241 ... Rendering engine 250 ... SDRAM ... 260 ... Built-in relay board, 261 ... I2C controller, 270 ... Motor controller, 271 ... Motor driver, 272 ... Motor, 275 ... Excitation state detection unit, 276 ... 1st OR circuit 277 ... first 2OR circuit, 278 ... first 3OR circuit, 280,291 ... LED driver, 281 ... LED

Claims (2)

Production control means capable of controlling production;
Decoding means for decoding video data;
A transfer unit that determines whether the moving image data decoded by the decoding unit is referred to in the effect drawing, and transfers the decoding result to the texture buffer when the moving image data is referred to in the effect drawing;
An alpharizing unit configured to convert one color component of a plurality of color components into an alpha component for the decode result transferred by the transfer unit; An effect for transferring effect data, which is decoded data different from the decoding result, to the texture buffer, which is used when effect rendering is performed on the decoding result transferred to the texture buffer by the transferring means. It further comprises a data transfer means
The gaming machine according to claim 1.

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