JP6552581B2 - Apparatus, method, and system - Google Patents

Description

  The present disclosure relates to computing systems, particularly (but not exclusively) point-to-point interconnects.

  Advances in semiconductor processing and logic design have enabled an increase in the amount of logic that may be present in integrated circuit devices. As a corollary, computer system configurations are integrated within a system from single or multiple integrated circuits to multiple cores, multiple hardware threads, and multiple logical processors residing on individual integrated circuits, as well as within such processors. Evolved into another interface. A processor or integrated circuit typically comprises a single physical processor die, where the processor die may include any number of cores, hardware threads, logical processors, interfaces, memory, controller hubs, and the like.

  Smaller computing devices have become more popular as a result of being able to accommodate more processing power in smaller packages. Smartphones, tablets, ultra-thin notebooks, and other user equipment are growing exponentially. However, these smaller devices rely on servers for both data storage and complex processing beyond form factors. As a result, demands in the high performance computing market (ie, server space) are also increasing. For example, in current servers, in addition to a single processor having a multi-core, a plurality of physical processors (also referred to as multi-sockets) exist to enhance computing power. However, as processing power increases with the number of devices in a computing system, communication between sockets and other devices is becoming more critical.

  In fact, interconnection has grown from a traditional multidrop bus that has primarily handled telecommunications to a full-fledged interconnection architecture that facilitates high-speed communications. Unfortunately, as a demand for future processors for even faster use, the demand is placed on the functionality of the existing interconnect architecture.

  Like reference numbers and designations in the various drawings indicate like elements.

1 illustrates an embodiment of a computing system that includes an interconnect architecture. 2 illustrates an embodiment of an interconnect architecture that includes a layered stack. Fig. 4 illustrates an embodiment of a request or packet generated or received within an interconnect architecture. Fig. 7 illustrates an embodiment of a transmitter and receiver pair for an interconnect architecture. FIG. 7 illustrates an embodiment of an interconnecting channel consisting of two exemplary connectors. FIG. 1 is a simplified block diagram of a cross section of an interconnect structure including a plurality of vias. FIG. 6 is a cross-sectional representation of an interconnect employing a via stub back drill. It is a block diagram showing the functional structure containing a lane error status register. FIG. 6 is a simplified diagram illustrating a data flow over multilane interconnection. 2 shows a representation of an exemplary framing token symbol. FIG. 4 is a simplified diagram illustrating a data flow including an exemplary skip (SKP) ordered set. It is a simple block diagram which shows the lane error which can be reported to an error register. FIG. 7 is a flow chart illustrating an example technique for reporting link lane errors. FIG. 7 is a flow chart illustrating an example technique for reporting link lane errors. FIG. 7 is a flow chart illustrating an example technique for reporting link lane errors. FIG. 7 is a flow chart illustrating an example technique for reporting link lane errors. FIG. 1 shows a block diagram of an embodiment for a computing system that includes a multi-core processor. FIG. 6 illustrates a block diagram of another embodiment for a computing system that includes a multi-core processor. FIG. 1 shows a block diagram of an embodiment of a processor. FIG. 7 shows a block diagram of another embodiment of a computing system that includes a processor. 1 illustrates a block of an embodiment of a computing system that includes multiple processors. 1 illustrates an exemplary system implemented as a system on chip (SoC).

  In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. For example, particular types of processors and system configurations, particular hardware structures, particular design and micro-design details, particular register configurations, particular instruction types, particular system components, particular dimensions / heights, etc. FIG. 6 is an illustration of certain processor pipeline stages, operations, and so on. However, it will be apparent to one skilled in the art that these specific details need not be employed to practice the invention. In other examples, specific and alternative processor architectures, specific logic circuits / codes for the described algorithms, specific firmware codes, specific interconnect operations, specific logic configurations, specific manufacturing techniques and materials For certain well known components or methods, such as particular compiler implementations, particular representations of algorithms in code, particular power down and gating techniques / logic, and other particular operational details of a computer system, the present invention may not be necessary. It is not described in detail to avoid ambiguity.

  The following embodiments may be described with respect to energy saving and energy efficiency in a particular integrated circuit, such as a computing platform or a microprocessor, but other embodiments are applicable to other types of integrated circuits and logic devices. It is. Similar techniques and teachings according to the embodiments described herein are applicable to other types of circuits or semiconductor devices, which may also benefit from greater energy efficiency and energy saving. For example, the disclosed embodiments are not limited to desktop computer systems or UltrabooksTM. It can also be used in other devices such as handheld devices, tablets, other thin notebooks, system on chip (SOC) devices, and embedded applications. Some examples of handheld devices include mobile phones, internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications are typically taught by microcontrollers, digital signal processors (DSPs), system-on-chips, network computers (net PCs), set-top boxes, network hubs, wide area network (WAN) switches, or Includes any other system capable of performing functions and operations. Furthermore, the devices, methods and systems described herein are not limited to physical computing devices, but may also relate to software optimization for energy saving and efficiency. As will be readily apparent from the following detailed description, embodiments of the methods, apparatus, systems described herein (whether related to hardware, firmware, software, or a combination thereof) perform Indispensable for the future of "green technology" that is balanced with considerations.

  As computing systems have advanced, their components have become more complex. As a result, the interconnect architecture for coupling and communicating between components is also increasing in complexity to ensure that bandwidth requirements for optimal component operation are met. In addition, various market segments require various aspects of interconnect architectures that meet market needs. For example, while the server needs more performance, the mobile ecosystem can sometimes sacrifice the overall performance for power savings. Nevertheless, providing the highest possible performance with maximum power savings is the sole purpose of most fabrics. The multiple interconnects described below will potentially benefit from the aspects of the invention described herein.

  One interconnect fabric architecture includes a peripheral component interconnect (PCI) express (PCIe) architecture. The primary purpose of PCIe is to allow components and devices from different vendors across multiple market segments such as clients (desktop and mobile), servers (standard and enterprise), and embedded and communications devices to interoperate in an open architecture. It is to do. PCI Express is a high performance general purpose I / O interconnect defined for a wide variety of future computing and communication platforms. Some PCI attributes such as their usage model, load-store architecture, and software interface are maintained through their revisions, whereas previous parallel bus implementations are highly extensible and fully serial Replaced by the interface. More recent versions of PCI Express take advantage of advances in point-to-point interconnects, switch-based technologies, and packetized protocols to provide new levels of performance and features. Some advanced features supported by PCI Express are power management, quality of service (QoS), hot plug / hot swap support, data integrity, and error handling.

  Referring to FIG. 1, there is shown one embodiment of a fabric comprised of point-to-point links that interconnect a series of components. System 100 includes a processor 105 and system memory 110 coupled to a controller hub 115. The processor 105 includes any processing element such as a microprocessor, host processor, embedded processor, coprocessor, or other processor. The processor 105 is connected to the controller hub 115 via a front side bus (FSB) 106. In one embodiment, the FSB 106 is a serial point-to-point interconnect as described below. In another embodiment, link 106 includes a serial differential interconnect architecture that conforms to different interconnect standards.

  System memory 110 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system 100. System memory 110 is coupled to controller hub 115 via memory interface 116. Examples of memory interfaces include a double data rate (DDR) memory interface, a dual channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

  In one embodiment, controller hub 115 is a root hub, root complex, or root controller in a peripheral component interconnect express (PCIe or PCIE) interconnect hierarchy. Examples of controller hub 115 include chipset, memory controller hub (MCH), north bridge, interconnect controller hub (ICH), south bridge, and route controller / hub. The term chipset often refers to a memory controller hub (MCH) coupled to two physically separate controller hubs: an interconnect controller hub (ICH). Note that while current systems typically include an MCH integrated with processor 105, controller 115 communicates with I / O devices in a manner similar to that described below. In some embodiments, peer-to-peer routing is optionally supported via the route complex 115.

  Here, the controller hub 115 is connected to the switch / bridge 120 via a serial link 119. Input / output modules 117 and 121, which may also be referred to as interfaces / ports 117 and 121, include / implement a layered protocol stack to provide communication between controller hub 115 and switch 120. In one embodiment, multiple devices can be coupled to the switch 120.

  The switch / bridge 120 is upstream from the device 125, ie towards the root complex, to the controller hub 115 above the hierarchy, and downstream, ie from the route controller to the hierarchy downward, from the processor 105 or system memory 110 to the device 125. Route packets / messages. In one embodiment, switch 120 is referred to as a logical assembly of multiple virtual PCI to PCI bridge devices. The device 125 is an I / O device, network interface controller (NIC), add-in card, audio processor, network processor, hard drive, storage device, CD / DVD ROM, monitor, printer, mouse, keyboard, router, portable storage device, Includes any built-in or external device or component coupled to the electronic system, such as a firewire device, universal serial bus (USB) device, scanner, and other input / output devices. In PCIe terminology, such devices are usually referred to as endpoints. Although not specifically shown, device 125 may include a PCIe to PCI / PCI-X bridge to support legacy or other versions of PCI devices. Endpoint devices in PCIe are typically classified as legacy endpoints, PCIe endpoints, or root complex integration endpoints.

  The graphic accelerator 130 is also connected to the controller hub 115 via the serial link 132. In one embodiment, the graphics accelerator 130 is linked to the MCH linked to the ICH. Switch 120 and, based thereon, I / O device 125 are then coupled to ICH. I / O modules 131 and 118 also implement a layered protocol stack for communicating between graphics accelerator 130 and controller hub 115. The graphic controller or graphic accelerator 130 itself may be integrated into the processor 105, as described above for the MCH.

  Turning to FIG. 2, one embodiment of a layered protocol stack is shown. The layered protocol stack 200 includes any form of layered communication stack, such as a quick path interconnect (QPI) stack, a PCIe stack, a next generation high performance computing interconnect stack, or other layered stack. Although the description immediately below with respect to FIGS. 1 to 4 relates to a PCIe stack, the same concept may be applied to other interconnect stacks. In one embodiment, protocol stack 200 is a PCIe protocol stack that includes transaction layer 205, link layer 210, and physical layer 220. Interfaces such as interfaces 117, 118, 121, 122, 126 and 131 in FIG. 1 may be represented as communication protocol stack 200. What is represented as a communication protocol stack may also be referred to as a module or interface that implements / includes the protocol stack.

  PCI Express uses packets to communicate information between components. Packets are formed in transaction layer 205 and data link layer 210 to convey information from the sending component to the receiving component. As packets to be transmitted flow through other layers, the packets are expanded with additional information necessary to process the packets at those layers. On the receiving side, the reverse process occurs, the packet is converted from what is represented as the physical layer 220 to what is represented as the data link layer 210, and finally (for transaction layer packets), the transaction of the receiving device Converted to a form that can be processed by layer 205.

  Transaction layer

  In one embodiment, transaction layer 205 provides an interface between the processing core of the device and an interconnect architecture such as data link layer 210 and physical layer 220. In this regard, the main role of transaction layer 205 is the assembly and disassembly of packets (ie, transaction layer packets or TLPs). Transaction layer 205 typically manages credit based flow control for TLP. PCIe implements split transactions, ie, transactions with time separated request and response, allowing the link to carry other traffic while the target device is collecting data for the response .

  PCIe also uses credit based flow control. In this scheme, the device notifies the initial amount of credit for each of a plurality of respective receive buffers in transaction layer 205. An external device at the other end of the link, such as the controller hub 115 of FIG. 1, counts the number of credits used by each TLP. A transaction may be sent if the transaction does not exceed the credit limit. Once the response is received, the credit amount is restored. The advantage of a credit scheme is that the credit return latency does not affect performance without facing the credit limit.

  In one embodiment, the four transaction address spaces include a configuration address space, a memory address space, an input / output address space, and a message address space. In order to transfer data to / from the memory mapped location, the memory space transaction includes one or more of a read request and a write request. In one embodiment, memory space transactions can use two different address formats, for example, a short address format, such as a 32-bit address, or a long address format, such as a 64-bit address. A configuration space transaction is used to access the configuration space of a PCIe device. Transactions to the configuration space include read requests and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.

  Thus, in one embodiment, transaction layer 205 assembles packet header / payload 206. The format for the current packet header / payload can be found in the PCIe specification at the PCIe specification website.

  With quick reference to FIG. 3, one embodiment of a PCIe transaction descriptor is shown. In one embodiment, transaction descriptor 300 is a mechanism for conveying transaction information. In this regard, transaction descriptor 300 supports the identification of transactions within the system. Other potential uses include modifying default transaction ordering and tracking the association of channels with transactions.

  Transaction descriptor 300 includes a global identifier field 302, an attribute field 304, and a channel identifier field 306. In the illustrated example, the global identifier field 302 is shown to include a local transaction identifier field 308 and a source identifier field 310. In one embodiment, the global transaction identifier 302 is unique for all outstanding requests.

  According to one implementation, the local transaction identifier field 308 is a field generated by the requesting agent, and this field is unique for all outstanding requests that require completion for that requesting agent. is there. Further, in this example, the source identifier 310 uniquely identifies the requesting agent in the PCIe hierarchy. Thus, the local transaction identifier 308 field, along with the source ID 310, provides a global identification of transactions within the hierarchical domain.

  The attribute field 304 specifies transaction characteristics and relationships. In this regard, the attribute field 304 is potentially used to provide additional information that allows for modifications to the predetermined processing of the transaction. In one embodiment, attribute field 304 includes a priority field 312, a reservation field 314, an ordering field 316, and a non-snoop field 318. Here, the priority sub-field 312 may be modified by the initiator to assign a priority to the transaction. The reservation attribute field 314 is reserved for future or vendor defined applications. A possible usage model that uses priority or security attributes may be implemented using reserved attribute fields.

  In this example, an ordering attribute field 316 is used to supply any information conveying an ordering type that may modify the predefined ordering rules. According to one exemplary implementation, the ordering attribute "0" indicates that the default ordering rule applies, in which case the ordering attribute "1" indicates relaxed ordering, in which case the writes are identical A write in the direction can be passed, and a read complete can pass a write in the same direction. The snoop attribute field 318 is used to determine if the transaction is snooped. As shown, channel ID field 306 identifies the channel with which the transaction is associated.

  Link layer

  Link layer 210, also referred to as data link layer 210, operates as an intermediate stage between transaction layer 205 and physical layer 220. In one embodiment, the role of data link layer 210 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between the two components of the link. One side of the data link layer 210 accepts the TLP assembled by the transaction layer 205, applies the packet sequence identifier 211, ie identification number or packet number, calculates and applies the error detection code, ie CRC 212, from the physical device The modified TLP is sent to the physical layer 220 for transmission across external devices.

  Physical layer

  In one embodiment, physical layer 220 includes logical sub-block 221 and electrical sub-block 222 for physically transmitting the packet to the external device. Here, the logical sub-block 221 takes charge of the "digital" function of the physical layer 221. In this regard, the logical sub-block includes a transmit section that prepares outgoing information for transmission by the physical sub-block 222, and a receive section that identifies and prepares the received information before passing it to the link layer 210. including.

  Physical block 222 includes a transmitter and a receiver. The transmitter is provided with symbols by logical sub-block 221, which serializes them and transmits them to an external device. The receiver is supplied with serialized symbols from an external device and converts the received signal into a bitstream. The bit stream is deserialized and supplied to the logical sub-block 221. In one embodiment, an 8b / 10b transmission code is employed, in which case 10-bit symbols are transmitted / received. Here, a special symbol is used to frame a packet having a plurality of frames 223. In one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

  As described above, although the transaction layer 205, link layer 210, and physical layer 220 have been described with respect to particular embodiments of the PCIe protocol stack, the layered protocol stack is not so limited. In fact, any layered protocol may be included / implemented. As an example, a typical port / interface as a layered protocol includes: (1) a first layer that assembles packets, i.e., a transaction layer, a second layer that orders packets, i.e., a link layer, and a first layer that transmits packets. Three layers are included, the physical layer. As a specific example, a common standard interface (CSI) layered protocol is utilized.

  Turning now to FIG. 4, an embodiment of a PCIe serial point to point fabric is shown. Although an embodiment of a PCIe serial point-to-point link is shown, the serial point-to-point link includes, but is not limited to, any transmission path for transmitting serial data. In the illustrated embodiment, the basic PCIe link includes two sets of low voltage, differentially driven signal pairs, a transmit pair 406/411 and a receive pair 412/407. Thus, device 405 includes transmit logic 406 for transmitting data to device 410 and receive logic 407 for receiving data from device 410. In other words, two transmit paths, ie, paths 416 and 417, and two receive paths, ie, paths 418 and 419, are included in the PCIe link.

  A transmission path refers to any path for transmitting data, such as a transmission line, copper wiring, optical line, wireless communication channel, infrared communication link, or other communication path. For example, the connection between two devices, such as device 405 and device 410, is referred to as a link, such as link 415. A link may support one lane, with each lane representing a set of differential signal pairs (one pair for transmission and one pair for reception). To extend the bandwidth, the link may aggregate multiple lanes, denoted as xN, where N is, for example, 1, 2, 4, 8, 12, 16, 32, 64, or wider, any Is the supported link width of.

  A differential pair refers to two transmission paths such as lines 416 and 417 for transmitting differential signals. As an example, if line 416 switches from a low voltage level to a high voltage level, ie, is a rising edge, line 417 drives from a high logic level to a low logic level, ie, to a falling edge. Differential signals potentially exhibit better electrical characteristics, such as better signal integrity, ie cross coupling, voltage overshoot / undershoot, ringing, etc. This allows for a better timing window, thereby allowing a faster transmission frequency.

  High speed channel

  The revision to the PCIe I / O specification is PCIe revision 4.0 (or PCIe 4.0). At 16 GT / s bit rate, PCIe 4.0 aims to double the interconnect performance bandwidth over the PCIe 3.0 specification, while maintaining compatibility with software and mechanical interfaces. Increase bandwidth from various under-developed applications with the goal of providing low cost, low power, minimal disruption at the platform level by increasing the performance bandwidth to previous generation PCIe Provide performance scaling consistent with requirements. One of the key factors in the widespread adoption of PCIe architecture is its mass production capability and its responsiveness to lower cost circuit boards, materials such as low cost connectors, etc.

  The 16 GT / s bit rate aims to provide an optimal trade-off between performance, manufacturability, cost, power and compatibility. Feasibility analysis is performed to recommend characteristics for devices and channels that support PCIe 4.0 16 GT / s bit rate. PCI-SIG analysis spanned multiple topologies. For example, it has been determined by analysis that 16 GT / s on copper is technically feasible at approximately PCIe 3.0 power levels, which doubles the bandwidth relative to the PCIe 3.0 specification . Here, 16 GT / s interconnects are potentially manufactured in mainstream silicon processing technology while maintaining compatibility with previous generation PCIe architectures, using existing low cost materials and infrastructure Be expanded.

  Faster data transfer rates for serial I / O (eg, 16 GT / s under PCIe 4.0) consume significant power and can increase circuit complexity, potentially resulting in silicon ( Si) leads to increased use of the area. These considerations also have the potential to limit the integration of PCIe 4.0 (and other such high speed interconnect architectures) into CPUs and systems that utilize more lane numbers. In some exemplary implementations, limitations are imposed on the interconnect length and number of connectors employed within high speed architectures such as, for example, PCIe 4.0. For example, such restrictions are defined at the specification level. In one example, the interconnect channel length is limited to one connector and less than 12 inches (30.48 centimeters) or 12 inches (30.48 centimeters).

  Imposing limitations on interconnect channels may limit their application to some systems. For example, in server interconnect applications, platform interconnects can sometimes be up to 20 inches (50.8 centimeters) or longer and have two connectors. Among other examples that are potentially conceivable, two 12-inches (30... 30.-in.) for architectures that limit interconnect channels to a maximum of 12-inch (30.48 centimeters) in length and a single connector. Separate repeater chips or other additional devices will be included to combine the 48 cm) channels and accommodate the distance between multiple devices in the server system.

  In some implementations, an interconnect link configured to be compliant with PCIe 4.0 and other interconnects can be provided, which allows a length of 20 while still supporting a data rate of 16 GT / s. Allows a channel consisting of two connectors equal to or longer than inches (50.8 centimeters). For example, circuits and interconnects can be optimized together such that repeaters and other devices can be omitted from longer interconnect channel runs. This may help to reduce manufacturing costs, reduce I / O latency, and extend the applicability of the faster bandwidth architecture to further applications. For example, a repeater chip may include a transmitter, a receiver, clock generation (eg, phase locked loop (PLL)), clock recovery, and related logic functions. Such components can utilize valuable substrate area. Further, among other potential drawbacks, for the x16 PCIe 4.0 interconnect, each repeater can consume extra power and introduce additional costs to the manufacture of the system. For example, repeaters can also introduce additional I / O latency.

  FIG. 5 shows an example of two connector channel configurations. For example, the channel 500 can include multiple sections such as a section on a socket (e.g., CPU), a motherboard, additional cards, riser boards, among other elements, across which channel links extend, the system Two devices (eg, 505, 510) can be connected. In this example, the plurality of channel sections may each have respective lengths, L1 = 1 inch (2.54 centimeters), L2 = 10.5 inches (26.67 centimeters), L3 = 0 Channel with .5 inches (1.27 centimeters), L4 = 4 inches (10.16 centimeters), L5 = 3 inches (7.62 centimeters), and L6 = 1 inch (2.54 centimeters) The total length of 500 is 20 inches (50.8 centimeters) in total. A channel is connectable to each device 505, 510 using a respective connector 515, 520 (in each package).

  Using conventional techniques, the configuration as shown in FIG. 5 can result in negative margins across links. In one example, among other potential features, minimize the impact of connector stub vias, minimize the impact of SPU sockets, and take advantage of improved low loss personal computer board (PCB) advances And an interconnect (eg, 500) consisting of two 20 inch (50.8 centimeter) connectors supporting a 16 GT / s bit rate can be provided, resulting in an increase in on-chip receiver front-end gain; Achieve positive gain across the link.

  The connector can include one or more vias that are used to make electrical connections between the layers. For example, vias can be used to carry signals and power between multiple layers of circuit boards or components. In high-speed systems, the parts of vias left on the connector, chip or substrate are parts that are not used, i.e. in point-to-point electrical links utilizing the vias. Turning to FIG. 6, a simplified view 600 of a cross section of a circuit board or other component is shown. The component can include one or more stub vias 605, 610. The vias can form electrical connections between multiple layers on the printed circuit board, such as through plated through hole (PTH) techniques. For example, vias can connect multiple pins of a connector to an inner signal layer (eg, a trace). For example, in the example of FIG. 6, to connect to a trace (eg, 625) that extends to another component, another via, etc. along another layer (eg, link (or channel) along component layer 630) A portion of the link can be implemented using a portion of the PTH via (eg, 615, 620). The remaining portion of the via (eg, 635) may be considered a stub. In high speed connections that utilize vias, via stubs 635 can cause resonant effects (eg, resonant frequency nulls), thereby causing signal degradation to channels (eg, lanes). Thus, in some implementations, the via stubs can be back drilled as shown at 650 to mitigate such effects. The back drill can remove the stub portion of the via that is responsible for these adverse electromagnetic effects. In some cases, the back drill can be implemented as a back-end drilling process, in which case the back drill holes are larger in diameter than the original plated through holes (PTH).

  The via stubs in the two connectors employed in the 20 inch (50.8 centimeters) 16 GT / s channel can be removed or minimized via, for example, back drills, U-turn vias, and other solutions. In the case of a back drill, the type of connector may be selected based on the connector type being a candidate suitable for back drilling. For example, depending on the connector, when it is back drilled, mechanical failure may occur and failure may occur. Other types of connectors such as surface mount connectors may be more appropriate.

  In addition to improving the electrical quality of the connector through the back drill, the electrical quality of the CPU socket is also improved, enabling a 20 inch (50.8 centimeters) 16 GT / s channel on the socket . For example, each pin on the CPU socket or other device that is connected using vias and is routed through the board and corresponds to a 20 inch (50.8 centimeters) 16 GT / s channel lane is back drilled be able to. The length of these longer, two connector, high speed channel socket stubs can also be reduced by keeping layers closer to the pins for the traces utilized by the channel. This allows the length of the socket stubs (of vias) to be bounded by routing these lanes through such multiple layers of boards.

  To minimize CPU socket effects, design the board pinout and breakout layouts so that layout priorities are given to the 20-inch (50.8 cm) 16 GT / s channel lanes. May be included. For example, the channels can be designed to be routed on layers such that a back drill is available to each pin of the CPU connected to a 20 inch (50.8 centimeters) 16 GT / s channel. Alternatively (or additionally), routing so that a 20 inch (50.8 centimeters) 16 GT / s channel utilizes multiple layers to allow socket stub lengths to be constrained Can be designed.

  FIG. 7 is a simplified representation of the cross section of the board, through which the two devices 705, 710 can be linked to an exemplary two connector link (eg, 20 inches (50.8 centimeters) of 16 GT / The one that embodies the channel of the second). In this example, the breakouts of multiple pins of device 705, 710 can be designed so that back drilling can be applied without blocking other breakout channels in the pin field. For example, the inner pin (eg, 715) can be designed to break out in the layer above the breakout of the outer pin (eg, 720) routing the lower layer of the board. In addition, the pins are positioned so that any pin whose via stub is drilled out (eg, a pin in a 20 inch (50.8 centimeter) 16 GT / s channel) is not located adjacent to the power via. Can be designed to Because back drills (e.g., 725a-725f) can run the risk of drilling holes in the power planes and shapes, they can result in potentially inefficient power delivery networks. Also, among other rules and examples, the ground pins may be positioned based on the holes that provide the ground plane after back drilling.

  An additional feature is included in the 20-inch (20.8 centimeters) two-connector channel to allow bit rates up to and exceeding 16 GT / s while still achieving positive gain across the link. obtain. For example, a low loss PC board such as a board with trace differential insertion loss less than or substantially equal to 0.48 dB / in at 4 GHz is feasible.

  In addition to mitigating the effects of stubs in the connector and socket of a 12 inch (30.48 centimeters) channel consisting of two connectors and providing a channel using a low loss board, at least 20 inches (50 The 16 GT / s rate in a channel of .8 centimeters can possibly be realized by additionally providing an additional gain at the receiver front end and / or an additional peak in the continuous time linear equalizer (CTLE) is there. In some instances, among other potential instances, the receiver front end may, for example, be a CTLE, an automatic gain control (AGC), a decision-feedback equalizer (DFE), and / or a data sampler (slicer). Can also include analog circuitry coupled in the signal data path. For example, in one implementation, adding approximately 6 dB total gain (eg, above the baseline for PCIe 4.0) at the receiver front end and / or CTLE is 20 inches (50.8 centimeters) It can help to realize a channel of 16 GT / s. Among other examples, achieving a modest amount of gain (e.g., around 6 dB) only adds slightly to the power and circuit complexity, e.g., by the addition of a single gain stage. Achievable. Furthermore, in some systems, the gain is adjustable or configurable on a separate channel. For example, the channel is programmably adjustable for applications where a speed of 16 GT / s is used, among other examples, and the gain is off for applications using slower speeds. it can.

  Reliability, availability, and serviceability (RAS)

  In some implementations, an interconnect architecture such as PCIe can include enhancements to system reliability, availability, and serviceability (RAS). While this problem may apply to all data rates, some architectures may apply a particular encoding scheme in the context of higher data rates. For example, PCIe 4.0 (as well as PCIe revision 3.0) employs a 128b / 130b encoding scheme, for example, for data transfer rates in excess of 8 GT / s. In the 128b / 130b scheme, among other examples, parity per lane is provided for each ordered set (SKP OS) of SKP (or “skip”), which lane in the link Identify that the predictive analysis could not be performed and, if appropriate, could not operate with the reduced link width. Lane parity can be an effective tool in identifying errors in a particular lane of a link. However, in some instances, if the link is primarily idle (eg, having a logical idle framing token (IDL) on the link), the risk of causing the detection functionality provided via the parity bit to be compromised Sex may exist. An error in the framing token (e.g., IDL) may result in link recovery removing parity information to that point. There may be additional blind spots in traditional architecture error detection mechanisms that can cause underestimation of errors. For example, among other drawbacks, the interconnect architecture may detect fewer or no defective lanes for detected framing token errors.

  In some architectures, a register can be provided to identify the error detected or expected on the link, and possibly the particular lane in which the error occurs. For example, as shown in FIG. 8, PCIe may provide lane error condition (LES) registers 805 associated with functional structures such as a second PCIe extended function structure. Such functional structure 800 can include, in addition to the LES register 805, a second PCIe extension function header 810, a link control 3 register 815, and an equalization control register 820. In some implementations, the LES register can include a 32-bit vector, where each bit corresponds to one lane in the link (eg, identified by a lane number), and the lane is in error. Indicates whether it has been detected. A set of errors is defined in PCIe that can result in reporting of error events in the LES register. For example, among other examples, as introduced above, in the payload of all data blocks transmitted after scrambling after the last SKP OS (or an ordered set of Start of Data Streams (SDS)) Data parity may be implemented via a data parity bit included in the SKP OS that indicates whether an even parity is detected. However, data parity can be calculated independently for each lane. The receiving device and the transmitting device calculate parity using the same technique, and the receiver compares the calculated parity of each lane with the parity calculated by the transmitter (as identified by the parity bit) And identify potential errors. For example, if the calculated and received values do not match, a bit in the LES register (eg, corresponding to the lane number where the mismatch was detected) can be set.

  As described above, and as illustrated in the simplified display 900 of FIG. 9, data can be transmitted on two or more lanes of the link. For example, as shown in the exemplary PCIe, the basic entity of data transmission may be a symbol such as a symbol implemented as an 8-bit data character. The payload of a data block is a stream of symbols defined as a data stream that can include framing tokens, transaction layer packets (TLP), data link layer packets (DLLP), and so on. Each symbol of the data stream may be placed on a single lane of the link for transmission, and the stream of symbols is placed in a strip across all lanes of the link and spans multiple block boundaries. Further, in some examples, the physical layer can use a block code for each lane. Each block can include a 2-bit synchronization header and a payload. In PCIe, two valid synchronization header encodings, 10b and 01b, are defined which define the payload type that the block contains. For example, synchronization header 10b may indicate a data block, and synchronization header 01b may indicate an ordered set of blocks. As an example, FIG. 9 shows transmission of data streams on four lanes of lanes 0, 1, 2, and 3. All lanes of the multi-lane link transmit multiple blocks simultaneously using the same synchronization header. The transmission order of the bits can start with a sync header (placed as "H0-H1" on the lane and represented by "H1 H0"), then start with "S0" and end with "S7", lane The first symbol represented by “S7-S6-S5-S4-S3-S2-S1-S0” arranged above follows.

  PCIe provides the receiver with an option to report errors to the LES register that correspond to mismatched or invalid synchronization headers in the data stream. For example, among other examples, one or more of the lanes (eg, in the first two UIs in the data stream) are synchronized with invalid values (eg, 00b, 11b). Identifying the inclusion of a header can be identified as an error on that lane, which can be reported to the LES register.

  Turning to FIG. 10, an exemplary framing token 1005, 1010, 1015, 1020, 1025 is shown. A framing token (or “token”) may be a physical layer data encapsulation that specifies or implies the number of symbols associated with the token, thereby identifying the location of the next framing token. A framing token of the data stream may be located at a first symbol (symbol 0) of a first lane (e.g. lane 0) of the first data block of the data stream. In one example, the PCIe includes a start of TLP (STP) token 1005, an end of data stream (EDS) token 1010, an end bad (EDB) token 1015, a start of DLLP (SDP) token 1020, and a logical idle (IDL) token 1025. Define five framing tokens including The STP token 1005 is four symbols long and may be followed by data link layer information. The example EDS token 1010 may be four symbols long and indicate that the next block is an ordered set of blocks. The EDB token 1015 also confirms that the TLP is "incorrect" and invalidated with a length of four symbols. EDB always follows TLP data. Further, SDP token 1020 may be two shorter symbols long, followed by DLLP information. The IDL token 1025 at the end of this example is a single symbol and is sent when no TLP, DLLP, or other framing token is sent on the link.

  FIG. 11 shows a display 1100 showing exemplary data transmitted via an exemplary x8 link, showing characteristics of data streams defined according to a particular interconnect architecture such as PCIe. In this example, the data can include transmission of an ordered set of SKPs. In this example, the stream can start with the transmission of a synchronization header H1H0 = 10b indicating a data block. Thus, an STP framing token can be sent as the first symbol 0 on lanes 0-3 to indicate the start of the TLP stream. A link cyclic redundancy check (LCRC) follows the TLP data, followed by an SDP header which indicates that DLLP data is to be transmitted (eg, in symbols 3-4). Cyclic redundancy check (CRC) data may also be provided in association with the DLLP data.

  In the example of FIG. 11, a logical idle (IDL) token is transmitted when data is not transmitted on the link during a series of UIs. An EDS token may then be sent that indicates the transition to an ordered set of data on the plurality of lanes. For example, another synchronization header (e.g., at 1105) may be encoded and transmitted as "01b" to indicate that the next plurality of data blocks are an ordered set of data blocks. In this particular example, the ordered set transmitted is the SKP ordered set (OS). As mentioned above, in some implementations, the SKP OS may include parity bits that indicate the parity status of each lane (eg, lanes 0-7) of the link. The SKP OS may further have a defined layout that is identifiable to the receiver. For example, in the case of PCIe 128b / 130b encoding, the SKP OS may include a base of 16 symbols. A grouping of four SKP symbols may be added or deleted by the port, and accordingly, the SKP OS may be 8, 12, 16, 20, or 24 symbols, etc. Furthermore, among other examples, as shown in FIG. 11, the SKP_END symbol is provided on the plurality of lanes, and the position of the end of SKP OS and the next block to be transmitted on the plurality of lanes The position of the synchronization header can be indicated.

  In some example implementations, logic may be provided to detect multiple additional lane errors in the interconnect architecture. Software in the system can monitor registers such as LES registers to track multiple errors on a lane-by-lane basis over time. A single lane error may not indicate that there is a problem with the error. However, when multiple errors occur at a statistically significant frequency in one or more specific lanes of the link, the system software may determine that there is a potential problem with the multiple specific lanes. it can. Furthermore, in some implementations, among other examples, in error prone lanes, at least some system data transmission is avoided, link reconfiguration, ticket generation for more rigorous inspection of links It is possible to take corrective measures. Depending on the error, lane-by-lane detection may be difficult. While some mechanisms are provided to detect and report portions of errors on links (e.g. based on parity or false sync headers), additional additional examples on lane specific rules are identified. Thus, other architectural features and rules may be exploited. These errors can also be reported to the register for review, along with the traditional lane error reporting, to build a more complete image of the normality of the individual lanes of the link, among other examples and considerations It is.

  In the first example, such as the PCIe example above, if a lane receives an ordered set of blocks with an immediately preceding invalid (mismatched, incorrect, or unexpected) EDS token, It can be inferred that an error has occurred on the lane where the invalid EDS token is detected. Further, errors regarding invalid EDS tokens on the lane may be reported to the error register, such as by setting the corresponding bit in the PCIe LES register.

  In another example, a predefined format for a particular ordered set can be utilized to identify multiple additional lane errors. For example, the SKP OS may include well-defined SKP symbols until a SKP END symbol is sent to identify the end of the ordered set. If an invalid or error SKP symbol is identified on a particular lane within the ordered set of expected SKP symbols (and before the SKP END symbol), the identification of the SKP symbol with that error is used, It can trigger the reporting of errors for a specific lane into an error register such as the LES register. Additionally, the defined timing of a particular OS symbol can also be used to identify that an unexpected symbol was received on a lane. For example, continuing with the example of an ordered set of SKPs, one or more particulars of the link may be specified when the number of symbols in the SKP OS is an integer multiple of four, among other potential examples. If SKP_END is not received within symbols 8, 12, 16, 20 or 24 on the lane of, then the corresponding bit in the error register can be set for that particular lane.

  In some implementations, various framing errors can occur and be detectable. For example, when processing a symbol that is expected to be a framing token, receiving a symbol or sequence of symbols that does not match the definition of the framing token may be a framing error. In addition, some framing tokens can be defined to follow other types of data, and an unexpected arrival (or delay) of a particular framing token can be a framing error. By way of example only, among many other examples, it can be specified that an EDB token is received immediately after the TLP, and if an EDB token is received at any other time (other than immediately after the TLP), the PCIe Can trigger a framing error, such as the framing error defined in the specification. While framing errors can be identified in the system, in some implementations, framing errors are not determined on a lane-by-lane basis or mapped to a specific lane on the link. In fact, in some examples, among other examples, framing errors can cause link recovery to be initiated, and link recovery can perform parity calculation and reporting (e.g., the parity bits transmitted in SKP OS Lane error detection is further complicated.

  In some implementations, logic included in the logical PHY (eg, at the receiving device) can further identify defective lanes from the framing token. In the first example, the symbol of the framing token is specifiable (as shown in the example of FIG. 10) and detecting an error in one of the symbols deviating from the expected symbol value; In addition, it is possible to identify a lane in which an erroneous token symbol is identified. For example, if the first symbol of the framing token is identifiable and the first symbol does not match the first symbol according to any one of the defined set of framing tokens for PHY, An error can be thrown. This error can be logged, for example, in the LES register. In the PCIe framing token example, if the first symbol of the received framing token does not match the first symbol defined for PCIe IDL, SDP, STP, EDB, or EDS, the first error of that error An error may be determined for the lane in which the framing token symbol appeared, and the error may be logged in the lane error registry of the identified lane.

  Second, in another example, an IDL framing token that is only one symbol long is specified to be transmitted for all lanes of the link if no TLP, DLLP, or other framing token is transmitted. obtain. Thus, if the first IDL appears on a lane with links that have 4 or more than 4 lanes, multiple instances of the IDL will have lanes n + 1, n + 2, and n + 3 (where the first lane n ( n modulo 4 = 0)) can also be expected to appear. After transmitting the IDL token, the first symbol of the next STP or SDP token can be specified to be transmitted in lane 0 at a future symbol time. Therefore, considering these constraints on the use and expected use of IDL tokens, if IDL does not repeat as expected, or if the first IDL appears in the wrong lane, the non-repeated IDL or otherwise The lane in which the error symbol appears can be identified and logged as an error for a particular lane in an error register such as the LES register.

  In yet another example, an EDB token may be defined to a particular length, such as four symbol lengths in PCIe. As a result, a framing error may occur by identifying the first EDB symbol but not identifying additional EDB symbols within the immediately following symbol contained in the next defined length. For example, in PCIe, if a framing token EDB is detected on lane n (n modulo 4 = 0) immediately after TLP, but not detected in any of lanes +1, n + 2, or n + 3, it is expected An error may be reported in the error register of any lane (eg, lanes n + 1, n + 2, or n + 3) where a valid EDB symbol is not displayed. In addition, the first symbol of the EDB token can be defined to be placed immediately after the TLP stream, which means that the preceding framing token, STP, is the last framing token displayed on the link. . Thus, among other examples, the first symbol of the EDB token is displayed on lane n, but if the immediately preceding framing token is other than an STP token, an error on lane n is identified and the error Can be reported to the register.

  Similar to the EDB token framing error example, the framing error may also be based on deviation from length, format, and placement of other framing tokens. For example, in another example, the first symbol of SDP is detected in lane n and is consistent with valid SDP token placement rules (eg, preceding DLLP traffic), but lane +1 is an SDP token If it does not match the expected second symbol, the logic PHY logic may identify an error on lane n + 1 and log the error in an error register.

  FIG. 12 shows expanded detection and multiple lane errors (eg, 1205, 1210, 1215, 1220, 1225, 1230, 1235, 1240) in an exemplary error register 1250, such as a PCIe LES register corresponding to the link. It is a simple block diagram which shows log recording. For example, in addition to reporting of sync header lane error 1205 and parity bit error 1210, additional errors that can be detected are OS blocks that do not have the preceding EDS token error 1215 and SKP OS error 1220 (described in the example above). Include lane errors of multiple ordered sets, such as For example, the first symbol framing token error 1225, IDL, among other examples that may be ordered set, data blocks, and potentially other rules that exploit rules defined for framing tokens in the architecture. Framing token error 1230 (eg, relating to properly repeating IDL after the first IDL on lane n), EDB framing token error 1235 (eg, relating to errors in the placement of EDB token symbols as outlined above in the examples) And additional errors are reported, including multiple framing token lane errors such as SDP framing token error 1240 (eg, regarding errors detected in the second symbol of SDP token) That.

  As mentioned above, in some cases, errors or other events that force link recovery can compromise lane error detection mechanisms such as parity decisions. As described above, the receiving and transmitting device can determine the parity for the data stream or other streams, and the parity information determined by the transmitter is determined by the receiver for the same data stream as the received parity information. Can be communicated to the receiver for comparison with the corresponding parity information (for that lane). Parity information may be sent periodically. For example, a transmission SKP OS including one or more parity bits in the SKP OS symbol indicating the parity determined for each lane by the transmitter can be transmitted. However, in some conventional systems, link recovery or other events may cause the parity information to be erased and / or resumed before the previously determined parity information is communicated to the receiver. It can be done. Thus, in such an example, errors determined for a particular lane based on the parity information may also be lost and remain unreported, impairing the accuracy of error reporting for that particular lane.

  In one embodiment, parity information by forcing link recovery to be automatically preceded by SKP OS, or another data set containing data reporting parity information for each lane of the link to be recovered. Can be maintained. For example, the link recovery protocol may be redefined such that the SKP OS (including parity bits) is sent in response to a framing error or other event that triggers link recovery. The SKP OS can thereby carry the parity information determined by the transmitter up to the moment link recovery is triggered and allows the receiver to identify multiple potential lane errors based on the parity information.

  In one example, parity information may be sent prior to recovery by sending the SKP OS before bringing the link into recovery from the active state (eg, L0). For example, each transmitter can transmit the SGP OS (eg, according to a predefined interval, such as a maximum interval between SKP OSs) followed by additional data blocks with EDS tokens before entering recovery. This ensures that the receiver receives parity for the previous data block received by the receiver, including one or more data blocks that may have caused a framing error. The receiver can also log the error to the appropriate LES if the parity bit comparison indicates an error.

  In another example, rather than dumping parity information before completion before recovery or other events (eg, trying to ensure that parity information is communicated before it is lost), SKP OS Parity information, such as parity, can be extended to cover parity across data streams while the link is active (eg, “LinkUp = 1b” in PCIe). In addition, parity information may also be maintained persistently for each lane of the link such that the parity information persists throughout the recovery event. In the conventional link recovery, the parity information of the preceding data block is lost (for example, interrupted by the recovery), but the parity information is continuously stored by storing the parity information continuously. , May be maintained and enabled to be communicated after recovery (eg, in the first SKP OS after recovery). In addition, among other examples, in some cases, parity information for new data blocks transmitted after link recovery (and before the next SKP OS) can also be determined, and in some cases maintained. This combined parity information may be communicated, for example, in the next SKP OS, in addition to the pre-recovery parity information being done.

  It should be understood that the above examples are non-limiting illustrations and are provided solely for the purpose of illustrating particular principles and features. In addition, some systems may include more than two or more various combinations of the features and components described above. As an example, the system can include a combination of the above exemplary error detection features, such as the lane error detection feature described above.

  Turning to FIGS. 13A-13D, exemplary flowcharts 1300a-1300d are shown that illustrate exemplary techniques for detecting errors on multiple lanes of a link. For example, in FIG. 13A, data may be received on a link that includes multiple lanes (1305). The data may include a plurality of symbols, which may be monitored to determine if one or more of the plurality of symbols is an error symbol (1310). Among other examples, the symbol of error has a framing token (eg, EDB, EDS, STP, IDL, SDP, etc.), an ordered set (eg, SKP OS, etc.), or an incorrect value. It may contain multiple symbols in other defined sequences that are in wrong or unexpected order, sent in wrong or unexpected lanes, and do not belong to a specific defined sequence. Among other examples, the lane in which the symbol of the error is transmitted may be identified (1315) and the lane error of the identified lane may be reported to the lane error register, for example, based on the symbol of the error. It can be done (1320).

  Turning to FIG. 13B, data may be sent on a link that includes multiple lanes (1325). Parity information may be maintained 1330 for each lane on the link. An indication of the parity information may be sent prior to termination from the active link state (1340) in response to identifying (1335) that the link has exited the active state (eg, associated with link recovery). ). In one example, an indication of parity information may be included in the ordered set of parity bits, such as the ordered set of PCIe SKPs, sent to the receiver. An indication of parity information may be used (eg, by the recipient of particular information) to compare with the parity information received by the recipient. A mismatch in parity information may be identified as evidence of a lane error for the lane corresponding to the mismatched parity information.

  In the example of FIG. 13C, data may be transmitted on multiple lanes of the link (1345), and based on the transmission data identified in each lane, parity information may be determined for each of the multiple lanes (1350). ). Link recovery occurs and parity information may be maintained throughout the recovery (1355). After recovery, an indication of parity information for each lane may be communicated (1370), which may be based on parity information maintained throughout link recovery. Optionally, after link recovery, additional data may be transmitted 1360 on the link, and based on this recovered data, parity information for each lane may be determined. The parity information for each lane may be updated (1365) based on both pre-recovery and post-recovery data on each lane, and an indication of the communicated parity information (1370) may include this combined parity information Can show.

  Corresponding to the example of FIG. 13C, in FIG. 13D, the first data may be received on the link (1375), and the first parity information is received in each lane based on the data received on the plurality of lanes. It can be judged against (1380). This parity information may be maintained (1385) during link recovery after receiving the first data. After link recovery, second parity data may be received 1398, as identified in the received SKP ordered set of parity bits. This second parity data is comparable to parity information maintained throughout (and beyond) link recovery. In some cases, the parity information determined for the plurality of lanes is configured based on the second data received (1390) on the plurality of lanes after link recovery, among other examples. In order to do so, the maintained parity information can be updated (1394) (for example, this corresponds to the updating of parity information by the corresponding transmitter based on the transmission of this recovered data).

  While many of the above principles and examples are described in the context of a specific revision of the PCIe and PCIe specifications, the principles, solutions, and features described herein apply equally to other protocols and systems. Note that it is possible. For example, similar lane errors may be specified on other links regarding the use, placement, and format of such structures in similar symbols, data streams and tokens, and data transmitted over these other links. It can be detected on other links using other protocols based on the rule. Additionally, alternative mechanisms and structures (e.g., other than PCIe LES registers or SKP OS) can be used to provide lane error detection and reporting functionality within the system. Furthermore, among other examples, combinations of such solutions, including combinations of logical and physical enhancements to links and their corresponding logic as described herein, may be implemented within the system. Can be applied at.

  It should be noted that the above-described apparatus, method, and system may be implemented in any electronic device or system, as described above. As a specific example, the following figure provides an exemplary system for utilizing the invention described herein. As the following system is described in more detail, a number of different interconnections are disclosed, described and reviewed from the above description. As is readily apparent, the above advances can be applied to any of their interconnects, fabrics, or architectures.

  Referring to FIG. 14, a block diagram of one embodiment of a computing system that includes a multi-core processor is shown. The processor 1400 may be any processor such as a microprocessor, embedded processor, digital signal processor (DSP), network processor, handheld processor, application processor, coprocessor, system on chip (SOC), or other device executing code. Includes processing devices. In one embodiment, processor 1400 includes at least two cores, cores 1401 and 1402, which may include an asymmetric core or a symmetric core (the illustrated embodiment). However, the processor 1400 may include any number of processing elements that may be symmetric or asymmetric.

  In one embodiment, a processing element refers to hardware or logic that supports software threads. Examples of hardware processing elements include processor states such as thread units, thread slots, threads, processing units, contexts, context units, logical processors, hardware threads, cores, and / or execution or architectural states. Includes any other element that can be held. In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with code, such as a software thread, operating system, application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit that potentially includes any number of other processing elements, such as cores or hardware threads.

  A core typically refers to logic located on an integrated circuit capable of maintaining independent architectural states, with each independently maintained architectural state associated with at least some dedicated execution resources. In contrast to the core, a hardware thread typically refers to any logic located on an integrated circuit that can maintain an independent architectural state, where the independently maintained architectural state provides access to execution resources. Share. As can be seen, when a particular resource is shared and another resource is dedicated to a particular architectural state, the lines between the hardware thread name and the core name overlap. More often, cores and hardware threads are considered by the operating system as individual logical processors, in which case the operating system can individually schedule operations for each logical processor.

  As shown in FIG. 14, the physical processor 1400 includes two cores, cores 1401 and 1402. Here, cores 1401 and 1402 are considered to be symmetric cores, i.e., cores with identical configurations, functional units, and / or logic. In another embodiment, core 1401 includes an out-of-order processor core while core 1402 includes an in-order processor core. However, cores 1401 and 1402 are native cores, software management cores, cores adapted to execute native instruction set architecture (ISA), cores adapted to execute translated instruction set architecture (ISA), joint It may be individually selected from any type of core, such as a designed core or other known cores. In a heterogeneous core environment (ie, an asymmetric core), some form of transformation, such as binary transformation, may be utilized to schedule or execute code for one or both cores. Although not yet described, the illustrated functional units within the core 1401 are described in further detail below. The units in core 1402 operate in a similar manner in the illustrated embodiment.

  As shown, core 1401 includes two hardware threads 1401a and 1401b, which may also be referred to as hardware thread slots 1401a and 1401b. Accordingly, in one embodiment, a software entity, such as an operating system, potentially views processor 1400 as four separate processors, ie, four logical processors or processing elements capable of executing four software threads simultaneously. As previously implied, the first thread may be associated with the architectural state register 1401a, the second thread may be associated with the architectural state register 1401b, the third thread may be associated with the architectural state register 1402a, May be associated with the architecture state register 1402b. Here, each of the architectural state registers (1401a, 1401b, 1402a, and 1402b) may be referred to as processing elements, thread slots, or thread units, as described above. As shown, architectural state register 1401a is duplicated in architectural state register 1401b, so that individual architectural states / contexts can be stored for logical processor 1401a and logical processor 1401b. In core 1401, other smaller resources, such as instruction pointers and renaming logic in assignment and renaming block 1430, may also be replicated for threads 1401a and 1401b. Some resources, such as the reordering buffer in reordering / retirement unit 1435, ILTB 1420, load / store buffers, and queues may be shared via partitioning. Other resources such as general internal registers, page table base registers, low-level data cache and data TLB 1420, execution unit 1440, out-of-order unit 1435 portions are potentially fully shared.

  The processor 1400 typically includes a plurality of other resources that may be fully shared, shared via partitioning, or dedicated by / to the processing element. In FIG. 14, a purely exemplary processor embodiment with exemplary logical units / resources of the processor is illustrated. Note that the processor may include or omit any of these functional units, and may include any other known functional units, logic, or firmware not shown. . As shown, core 1401 includes a simplified representative out-of-order (OOO) processor core. However, an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer 1420 that predicts the branch to be executed / fetched and an instruction translation buffer (I-TLB) 1420 that stores an address translation entry for the instruction.

  Core 1401 further includes a decode module 1425 coupled to fetch unit 1420 that decodes the fetched element. In one embodiment, the fetch logic includes individual sequences associated with thread slots 1401a, 1401b, respectively. In general, core 1401 is associated with a first ISA that defines / designates executable instructions on processor 1400. Typically, machine code instructions that are part of the first ISA include parts of instructions (referred to as opcodes) that reference / specify the instruction or action to be executed. Decode logic 1425 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions in a pipeline to process them as defined by the first ISA. For example, as described in detail later, in one embodiment, decoder 1425 includes logic designed or adapted to recognize specific instructions, such as transaction instructions. As a result of recognition by the decoder 1425, the architecture or core 1401 takes certain predefined actions to perform the tasks associated with the appropriate instructions. Any of the tasks, blocks, operations, and methods described herein may be performed in response to single or multiple instructions, some of which are new or old instructions It is important to note that it may be. Note that in one embodiment, decoder 1426 recognizes the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoder 1426 recognizes a second ISA (a subset of the first ISA or a separate ISA).

  In one example, allocation and rename block 1430 includes an allocator that reserves resources, such as a register file that stores instruction processing results. However, threads 1401a and 1401b are potentially capable of out-of-order execution, in which case the assign and rename block 1430 also reserves other resources, such as reordering buffers, to track instruction results. Unit 1430 may also include a register renamer that renames program / instruction reference registers to other registers internal to processor 1400. The reordering / retirement unit 1435 includes components such as the reordering buffer, load buffer, and store buffer described above, and supports out-of-order execution and subsequent in-order retirement of out-of-order executed instructions. .

  Scheduler and Execution Unit block 1440, in one embodiment, includes a scheduler unit that schedules instructions / operations to execution units. For example, floating point instructions are scheduled at a port of an execution unit having an available floating point execution unit. A register file associated with the execution unit is also included to store information instruction processing results. Exemplary execution units include floating point execution units, integer execution units, jump execution units, load execution units, store execution units, and other known execution units.

  A lower level data cache and data conversion buffer (D-TLB) 1450 is coupled to execution unit 1440. The data cache stores recently used / operated elements such as data operands, which are potentially held in memory coherency state. The D-TLB stores recent virtual / linear translations to physical addresses. As a specific example, the processor may include a page table structure that divides physical memory into a plurality of virtual pages.

  Here, cores 1401 and 1402 share access to higher or farther caches, such as a second level cache associated with on-chip interface 1410. It should be noted that higher levels or further away refers to cache levels that have increased or are further away from execution units. In one embodiment, the higher level cache is a last level data cache, ie, the last cache of the memory hierarchy of the processor 1400, eg, a second or third level data cache. However, higher level caches are not so limited and may be associated with or include an instruction cache. The trace cache, i.e., the type of instruction cache, may instead be concatenated after the decoder 1425 to store the recently decoded trace. Here, an instruction potentially refers to a macro instruction (ie, a general instruction recognized by a decoder), which may be decoded into a plurality of micro instructions (micro operations).

  In the illustrated configuration, processor 1400 also includes an on-chip interface module 1410. Historically, memory controllers have been included in computing systems external to processor 1400, as described in detail below. In this scenario, on-chip interface 1410 includes devices external to processor 1400, such as system memory 1475, a chipset (usually a memory controller hub connecting to memory 1475, and an I / O controller hub connecting to peripheral devices Communicate with a memory controller hub, north bridge, or other integrated circuit. Also in this scenario, bus 1405 may include any known interconnect, such as multi-drop bus, point-to-point interconnect, serial interconnect, parallel bus, coherent (eg, cache coherent) bus, layered protocol architecture. , Differential bus, and GTL bus.

  Memory 1475 may be dedicated to processor 1400 or shared with other devices in the system. Examples of common types of memory 1475 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Device 1480 may be a graphics accelerator, a processor or card coupled to a memory controller hub, data storage coupled to an I / O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device. Note that it may be included.

  Recently, however, more logic and devices have been integrated on a single die, such as an SOC, and each of these devices may be integrated on the processor 1400. For example, in one embodiment, the memory controller hub is on the same package and / or die as the processor 1400. Here, the portion of core 1410 (on-core portion) includes one or more controllers for interfacing with other devices such as memory 1475 or graphics device 1480. A configuration that includes an interconnect for interfacing with such devices and a controller is commonly referred to as an on-core (or uncore configuration). As an example, on-chip interface 1410 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 1405 for off-chip communication. Furthermore, in an SOC environment, many more devices are integrated into a single die or integrated circuit, such as a network interface, coprocessor, memory 1475, graphics processor 1480, and any other known computer device / interface. A small form factor with high functionality and low power consumption may be provided.

  In one embodiment, the processor 1400 may be a compiler for optimizing, translating, and / or optimizing application code 1476 to support or interface with the devices and methods described herein. And / or conversion code 1477 can be executed. The compiler usually includes a program or set of programs to convert source text / code into target text / code. Typically, compilation of program / application code by a compiler is performed in multiple phases and passes to convert high level programming language code into low level machine or assembly language code. However, a single pass compiler may also be used for simple compilation. The compiler may utilize any known compilation technique and may perform any known compiler operations such as lexical analysis, preprocessing, analysis, semantic analysis, code generation, code conversion, and code optimization. .

  Larger compilers typically include multiple phases, but in most cases these phases are contained within two general phases: (1) front end. That is, generally there may be syntactic processing, semantic processing, and some transformation / optimization. (2) Back end. That is, there is generally analysis, transformation, optimization, and code generation. Some compilers are called middle and show an ambiguous depiction between the front end and back end in the compiler. As a result, references to insertion, association, generation, or other behavior of the compiler may be made in any of the aforementioned phases or passes, as well as in any other known phase or pass of the compiler. As an illustrative example, the compiler potentially inserts operations, calls, functions, etc. in one or more phases of compilation. For example, call / action insertion in the front end phase of compilation, and then the call / action conversion is converted to lower level code during the conversion phase. Note that during dynamic compilation, compiler code or dynamically optimized code may not only insert such operations / calls, but also optimize the code for execution during runtime. As a specific example, binary code (already compiled code) may be dynamically optimized during runtime. Here, the program code may include dynamic optimization code, binary code, or a combination thereof.

  Similar to a compiler, a translator such as a binary translator translates code either statically or dynamically to optimize and / or translate the code. Thus, reference to execution of code, application code, program code, or other software environment may refer to (1) compiling program code, maintaining software structure, performing other operations, optimizing code, or code (2) Execution of either a dynamic or static translator, or (2) optimized / compiled application code, main program code including actions / calls Execution, (3) execution of other program code, such as a library associated with the main program code, to maintain the software structure, perform other software-related operations, or optimize the code, or (4) these Combination, the finger It may be.

  Referring now to FIG. 15, a block diagram of an embodiment of a multi-core processor is shown. As shown in the embodiment of FIG. 15, processor 1500 includes multiple domains. Specifically, the core domain 1530 includes a plurality of cores 1530A-1530N, and the graphics domain 1560 includes one or more graphics engines having a media engine 1565 and a system agent domain 1510.

  In various embodiments, system agent domain 1510 handles power control events and power management, such that individual units of domains 1530 and 1560 (eg, multiple cores and / or graphic engines) are specific units. Dynamic in the appropriate power modes / levels (eg, active, turbo, sleep, hibernate, deep sleep, or other states such as Advanced Configuration Power Interface) in terms of activity (or inactivity) occurring within It can be controlled independently to operate. Each of domains 1530 and 1560 may operate at different voltages and / or powers, and further, the individual units in the plurality of domains potentially operate at independent frequencies and voltages, respectively. Although shown with only three domains, it should be noted that the scope of the present invention is not limited in this regard and additional domains may be present in other embodiments.

  As shown, each core 1530 further includes a low level cache in addition to various execution units and additional processing elements. Here, the various cores are connected to one another and to a shared cache memory formed from a plurality of units or slices of last level cache (LLC) 1540A-1540N. These LLCs typically include storage and cache controller functions and are shared between these cores and potentially also with the graphics engine.

  As can be seen, ring interconnect 1550 couples the cores together and provides an interconnect between core domain 1530, graphics domain 1560, and system agent circuit 1510 via a plurality of ring stops 1552A-1552N. Each such ring stop is present at the connection between the core and the LLC slice. As shown in FIG. 15, interconnect 1550 is used to carry various information, including address information, data information, acknowledgment information, and snoop / invalid information. Although ring interconnections are shown, any known on-die interconnections or fabrics may be utilized. By way of illustration, some of the fabrics described above (eg, another on-die interconnect, on-chip system fabric (OSF), Advanced Microcontroller Bus Architecture (AMBA) interconnect, multidimensional mesh fabric, or other known interconnect architecture) May be utilized in a similar manner.

  As further shown, the system agent domain 1510 includes a display engine 1512 that provides control and associated interface to the associated display. The system agent domain 1510 may include other units such as an integrated memory controller 1520 that provides an interface to system memory (eg, a DRAM implemented with multiple DIMMs), and coherency logic 1522 that performs memory coherency operations. . There may be multiple interfaces that enable interconnection between the processor and other circuitry. For example, in one embodiment, at least one direct media interface (DMI) 1516 interface as well as one or more PCIe ™ interfaces 1514 are provided. The display engine and these interfaces are typically coupled to memory via a PCIe ™ bridge 1518. In addition, one or more other interfaces may be provided to provide communication between other agents such as additional processors or other circuits.

  Referring to FIG. 16, a block diagram of a representative core is shown. Specifically, it is a back-end logical block of a core such as the core 1530 of FIG. In general, the structure shown in FIG. 16 fetches incoming instructions and performs passing of multiple instructions / operations to various processing (eg, cache, decode, branch prediction, etc.) and out-of-order (OOO) engine 1680 It includes an out-of-order processor having a front end unit 1670 used. The OOO engine 1680 performs further processing on the decoded instructions.

  Specifically, in the embodiment of FIG. 16, the out-of-order engine 1680 receives decoded instructions from the front end unit 1670, which may be in the form of one or more microinstructions or microoperations, and registers them, etc. An assignment unit 1682 is assigned to the appropriate resources of The instructions are then provided to a reservation station 1684 that reserves and schedules resources for execution to one of a plurality of execution units 1686A-1686N. Various types of execution units may exist, including, for example, arithmetic logic units (ALUs), load and store units, vector processing units (VPUs), floating point execution units, among others. Results from these different execution units are provided to a reordering buffer (ROB) 1688, which takes unordered results and returns them to the correct program order.

  Still referring to FIG. 16, note that both front end unit 1670 and out of order engine 1680 are coupled to different levels of memory hierarchy. Specifically, instruction level cache 1672 is shown, followed by intermediate level cache 1676 and then last level cache 1695. In one embodiment, last level cache 1695 is implemented in on-chip (sometimes referred to as uncore) unit 1690. As an example, unit 1690 is similar to system agent 1510 of FIG. As mentioned above, uncore 1690 communicates with system memory 1699 implemented via ED RAM in the illustrated embodiment. Note that the various execution units 1686 in the out-of-order engine 1680 communicate with the first level cache 1674, which also communicates with the intermediate level cache 1676. It should also be noted that additional cores 1630 N2-1630 N can be coupled to LLC 1695. Although shown at this high level in the embodiment of FIG. 16, it should be understood that various modifications and additional components may be present.

  Referring to FIG. 17, there is shown a block diagram of an exemplary computer system formed of a processor including an execution unit for executing instructions, wherein one or more interconnects are included in one of the present inventions. In accordance with an embodiment, one or more features are implemented. System 1700 includes components such as processor 1702 that employ an execution unit that includes logic to execute an algorithm for process data in accordance with the present invention, such as the embodiments described herein. System 1700 is a typical process based on PENTIUM (R) III (TM), Pentium (R) 4 (TM), Xeon (TM), Itanium, XScale (TM) and / or StrongARM (TM) microprocessors Although a system, other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In one embodiment, sample system 1700 runs a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Wash., While other operating systems (eg, UNIX® and Linux Registered trademark)), embedded software, and / or a graphical user interface may also be used. Thus, embodiments of the present invention are not limited to any specific combination of hardware circuitry and software.

  Embodiments are not limited to computer systems. Alternative embodiments of the present invention may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cell phones, internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. The embedded application may be a microcontroller, digital signal processor (DSP), system on chip, network computer (net PC), set top box, network hub, wide area network (WAN) switch, or one or more instructions according to at least one embodiment May include any other system capable of implementing

  In this illustrated embodiment, processor 1702 includes one or more execution units 1708 that implement an algorithm to execute at least one instruction. While one embodiment may be described in the context of a single processor desktop or server system, alternative embodiments may be included in a multiprocessor system. System 1700 is an example of a "hub" system architecture. Computer system 1700 includes a processor 1702 for processing data signals. As one example, processor 1702 may be a complex instruction set computer (CISC) microprocessor, a reduced instruction set computer (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or For example, any other processor device, such as a digital signal processor. Processor 1702 is coupled to processor bus 1710 that transmits data signals between processor 1702 and other components in system 1700. Elements of system 1700 (eg, graphic accelerator 1712, memory controller hub 1716, memory 1720, I / O controller hub 1724, wireless transceiver 1726, flash BIOS 1728, network controller 1734, audio controller 1736, serial expansion port 1738, I / O Controller 1740, etc.) perform conventional functions well known to those skilled in the art.

  In one embodiment, processor 1702 includes level 1 (L1) internal cache memory 1704. Depending on the architecture, processor 1702 may have a single internal cache or multiple levels of internal cache. Other embodiments include a combination of both internal and external caches, depending on the particular implementation and needs. Register file 1706 stores different types of data in various registers, including integer registers, floating point registers, vector registers, bank registers, shadow registers, checkpoint registers, status registers, and instruction pointer registers.

  An execution unit 1708 that includes logic to perform integer and floating point operations is also present in the processor 1702. Processor 1702 includes, in one embodiment, a microcode (μcode) ROM that stores microcode that executes an algorithm for a particular microinstruction at run time or handles complex scenarios. Here, the microcode is potentially updateable to handle logic bugs / modifications for processor 1702. For one embodiment, execution unit 1708 includes logic for processing packed instruction set 1709. By including the packed instruction set 1709 in the general processor 1702 instruction set along with associated circuitry for executing instructions, operations used by many multimedia applications can be May be performed using Thus, by using the full width of the processor data bus to perform operations on packed data, many multimedia applications are accelerated and executed more efficiently. This potentially eliminates the need to transfer smaller units of data, such as one data element at a time, across the processor's data bus to perform one or more operations.

  Alternative embodiments of execution unit 1708 may also be used in microcontrollers, embedded processors, graphic devices, DSPs, and other types of logic circuits. System 1700 includes a memory 1720. Memory 1720 includes dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, or other memory devices. Memory 1720 stores instructions and / or data represented by data signals that are executed by processor 1702.

  It should be noted that any of the foregoing features or aspects of the present invention may be utilized in one or more of the interconnects illustrated in FIG. For example, an on-die interconnect (ODI), not shown, for coupling the internal units of the processor 1702 implements one or more aspects of the invention described above. Alternatively, the present invention may be processor bus 1710 (eg, otherwise known as high performance computing interconnect), high bandwidth memory path 1718 to memory 1720, point to point link to graphics accelerator 1712 (eg, peripheral component interconnect) Express (PCIe compliant fabric), controller hub interconnect 1722, I / O for coupling other illustrated components or other interconnects (eg, USB, PCI, PCIe). Some examples of such components are: Legacy I / O controller 1710 with audio controller 1736, firmware hub (flash BIOS) 1728, wireless transceiver 1726, data storage 1724, user input and keyboard interface 1742, universal A serial expansion port 1738 such as a serial bus (USB) and a network controller 1734 are included. Data storage device 1724 may comprise a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

  Turning now to FIG. 18, a block diagram of a second system 1800 in accordance with an embodiment of the present invention is shown. As shown in FIG. 18, multiprocessor system 1800 is a point-to-point interconnect system and includes a first processor 1870 and a second processor 1880 coupled via point-to-point interconnect 1850. Each of processors 1870 and 1880 may be some version of the processor. In one embodiment, 1852 and 1854 are part of a serial point-to-point coherent interconnect fabric, such as a high performance architecture. As a result, the present invention may be implemented within the QPI architecture.

  Although only two processors 1870, 1880 are shown, it should be understood that the scope of the present invention is not so limited. In other embodiments, one or more additional processors may be present at a particular processor.

  Processors 1870 and 1880 are shown to include integrated memory controller units 1872 and 1882, respectively. Processor 1870 also includes point-to-point (PP) interfaces 1876 and 1878 as part of its own bus controller unit, and similarly, second processor 1880 includes PP interfaces 1886 and 1888. Processors 1870, 1880 may exchange information via PP interface 1850 using point-to-point (PP) interface circuits 1878, 1888. As shown in FIG. 18, IMCs 1872 and 1882 couple the processors to their respective memories, namely memory 1832 and memory 1834, which are portions of main memory that are locally attached to each processor. You may

  Processors 1870, 1880 exchange information with chipset 1890 via respective PP interfaces 1852, 1854 using point-to-point interface circuits 1876, 1894, 1886, 1898, respectively. Chipset 1890 also exchanges information via high performance graphics circuitry 1838 and interface circuitry 1892 along high performance graphics interconnect 1839.

  A shared cache (not shown) may be contained internally of either processor, or external to both processors, but the local cache for either or both processors even if the processors are in low power mode It is connected to multiple processors via PP interconnection so that information can be stored in a shared cache.

  Chipset 1890 may be coupled to first bus 1816 via interface 1896. In one embodiment, the first bus 1816 may be a peripheral component interconnect (PCI) bus or a bus such as a PCI Express bus or another third generation I / O interconnect bus, although the scope of the invention Is not so limited.

  As shown in FIG. 18, various I / O devices 1814 are coupled to a first bus 1816 along with a bus bridge 1818, which couples the first bus 1816 to a second bus 1820. . In one embodiment, the second bus 1820 includes a low pin count (LPC) bus. Various devices are coupled to the second bus 1820, for example, a disk drive or other mass storage including keyboard and / or mouse 1822, communication device 1827 and, in one embodiment, instructions / code and data 1830 in one embodiment. Device-like storage unit 1828 is included. Additionally, audio I / O 1824 is shown coupled to second bus 1820. It should be noted that other architectures are possible, in which case the included components and interconnection architecture will change. For example, instead of the point-to-point architecture of FIG. 18, the system may implement a multidrop bus or other such architecture.

  Turning now to FIG. 19, one embodiment of a system on chip (SOC) design in accordance with the present invention is shown. As a specific example, SOC 1900 is included in user equipment (UE). In one embodiment, a UE is used by an end user to communicate, such as a mobile phone, a smartphone, a tablet, an ultra thin notebook, a notebook with a broadband adapter, or any other similar communication device. Point to any other device. Typically, the UE connects to a base station or node that potentially corresponds to the essential mobile station (MS) in the GSM® network.

  Here, the SOC 1900 includes two cores, 1906 and 1907. As above, cores 1906 and 1907 are Intel® Architecture CoreTM based processors, Advanced Micro Devices, Inc. (AMD) processor, MIPS based processor, ARM based processor design, or instruction set architecture of their customers and licensees or adopters etc. Cores 1906 and 1907 are coupled to cache control 1908 associated with bus interface unit 1909 and L2 cache 1911 to communicate with other portions of system 1900. Interconnect 1910 includes on-chip interconnects such as IOSF, AMBA, or other interconnects described above, potentially implementing one or more aspects described herein.

  The interface 1910 includes a subscriber identification module (SIM) 1930 for interfacing with a SIM card, a boot ROM 1935 for holding boot code executed by the cores 1906 and 1907 to initialize and boot the SOC 1900, an external memory (eg, DRAM 1960). SDRAM controller 1940 that interfaces with non-volatile memory (eg, flash 1965), peripheral controller 1950 (eg, serial peripheral interface) that interfaces with peripheral devices, input (eg, touch-enabled input) A video codec 1920 and a video interface 1925, and a GPU 1915 that performs graphic-related calculations. Providing a communication channel for the other components, such as. Any of these interfaces may incorporate aspects of the invention described herein.

  The system also shows peripheral devices for communication such as Bluetooth® module 1970, 3G modem 1975, GPS 1985, and WiFi 1985. It should be noted that, as mentioned above, the UE includes a radio for communication. As a result, not all these peripheral communication modules are required. However, the UE includes some form of wireless communication for external communication.

  While the present invention has been described with respect to a limited number of embodiments, one of ordinary skill in the art will envision many modifications and variations therefrom. The appended claims intend that all such modifications and variations fall within the true spirit and scope of the present invention.

  Design may go through various stages from creation to simulation to production. Data representing a design may represent the design in a number of ways. First, as useful in simulation, hardware may be represented using a hardware description language or another functional description language. Also, a circuit level model with logic and / or transistor gates may be generated at some stage of the design process. Furthermore, in some stages, many designs reach levels of data that represent the physical arrangement of various devices in the hardware model. When conventional semiconductor manufacturing techniques are used, the data representing the hardware model specifies the presence or absence of various features in different mask layers for the mask used in integrated circuit fabrication. It may be data. In any representation of the design, the data may be stored on any form of machine readable medium. A magnetic or optical storage, such as a memory or disk, may be the machine readable medium, transmitted via optical or electrical waves to transmit such information, modulated or otherwise generated. Store the information to be When an electrical carrier wave indicating or carrying the code or design is transmitted, a new copy is made to the extent that copying, buffering or re-transmission of the electrical signal is performed. Thus, the communication provider or the network provider may at least temporarily store, on a tangible machine readable medium, items embodying techniques of embodiments of the invention, such as carrier wave encoded information. .

  Modules, as used herein, may refer to any combination of hardware, software, and / or firmware. As an example, a module includes hardware associated with a non-transitory medium for storing code adapted to be executed by a microcontroller, such as a microcontroller. Thus, in one embodiment, reference to a module refers to hardware specifically configured to recognize and / or execute code held on a non-transitory medium. Furthermore, in another embodiment, the use of a module refers to a non-transitory medium comprising code specially adapted to be executed by a microcontroller for performing a predetermined operation. Further, as may be inferred, in yet another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-transitory medium. Usually, the boundaries of modules shown separately will generally change and potentially overlap. For example, the first and second modules share hardware, software, firmware, or a combination thereof, while potentially maintaining some independent hardware, software, or firmware. You may In one embodiment, the use of the term logic includes transistors, hardware such as registers, or other hardware such as programmable logic devices.

  In one embodiment, the use of the word “configured” refers to the placement, assembly, manufacture, and sale of devices, hardware, logic, or elements to perform a specified or determined task. Refers to making, importing, and / or designing. In this example, if the non-operating device or component thereof is designed, linked, and / or interconnected to perform the specified task, then it still performs the specified task. "It is configured. As a pure illustration, a logic gate may provide 0 or 1 during operation. However, logic gates that are "configured" to provide an enable signal to the clock do not include all potential logic gates that may provide 1s or 0s. Instead, the logic gates are connected in some manner such that an output of 1 or 0 enables the clock during operation. The use of the term “configured” does not require any action, but instead focuses on the potential state of the device, hardware, and / or element, in which case the potential It should again be noted that, in a state of affairs, the devices, hardware and / or elements are designed to perform specific tasks while the devices, hardware and / or elements are in operation.

  Further, the use of the words "want", "capable", and / or "operable" may, in one embodiment, allow devices, logic, hardware and / or elements to be used in a specified manner. Refers to a number of devices, logic, hardware, and / or elements designed to be As noted above, possible or operable use, in one embodiment, refers to a potential state of the device, logic, hardware and / or elements, where the device, logic, hardware, It should be noted that the elements and / or elements are not operating, but are designed in such a way as to allow the use of the device in a specified manner.

  The values used herein may include any known representation of numbers, states, logic states, or binary logic states. Usually, the use of logic levels, logic values or logic values is also simply referred to as 1 and 0 levels or values representing binary logic states. For example, 1 indicates a high logic level and 0 indicates a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logic value or multiple logic values. However, other representations of values in computer systems are used. For example, the decimal 10 may be represented as the binary value 1010 and in hexadecimal as the letter A. Thus, the value includes any representation of information that can be held in the computer system.

  Furthermore, states may be represented by values or parts of values. As an example, a first value such as logic 1 may represent a default or initial state, while a second value such as logic 0 may represent a non-default state. Also, in one embodiment, the terms reset and setting refer to default and updated values or states, respectively. For example, the default value potentially includes a high logic value, i.e., reset, but the updated value potentially includes a low logic value, i.e., a setting. Note that any combination of values can be utilized to represent any number of states.

  Embodiments of the above-described methods, hardware, software, firmware or code may be through machine-accessible, machine-readable, computer-accessible, or instructions or code stored on a computer-readable medium executable by a processing element. May be implemented. Non-transitory machine accessible / readable media include any mechanism that provides (ie, stores and / or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, non-transient machine accessible media include random access memory (RAM) such as static RAM (SRAM) or dynamic RAM (DRAM), ROM, magnetic or optical storage media, flash memory devices, electrical storage devices , Optical storage devices, acoustic storage devices, other forms of storage devices for holding information received from temporary (propagated) signals (eg, carrier waves, infrared signals, digital signals), etc. It is distinguished from non-transitory media that can receive information from them.

  The instructions used to program the logic to implement the embodiments of the present invention may be stored within memory in a system such as DRAM, cache, flash memory, or other storage. Further, the instructions may be distributed over a network or by other computer readable media. Thus, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (eg, a computer). Such as, but not limited to, floppy disks, optical disks, compact disks, read only memory (CD-ROM), and magneto-optical disks, read only memory (ROM), random access memory (RAM), Erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), magnetic or optical card, flash memory, or propagating signal in electrical form, optical form, acoustic form or other form (eg, carrier wave) , Tangible machine-readable storage used to transmit information via the Internet via infrared signals, digital signals, etc.). Thus, computer readable media includes any type of tangible machine readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

  The following examples relate to embodiments according to the present specification. One or more embodiments provide an apparatus, system, machine readable for providing a channel based on a peripheral component interconnect (PCI) express (PCIe) protocol supporting a bit rate of at least 16 gigatransfers per second (GT / S). Storage, machine-readable media, hardware-based and / or software-based logic, and methods may be provided, where the channel includes two connectors and has a length greater than 12 inches (30.48 centimeters).

  In at least one example, the channel includes at least one via, and stubs for the via are at least partially removed.

  In at least one example, the vias are back drilled to remove the stubs.

  In at least one example, the via is a via of the first connector of the plurality of connectors.

  In at least one example, each via utilized by the connector to connect to a first device is back drilled.

  In at least one example, the plurality of vias of the second one of the plurality of connectors utilized to connect to the second device are back drilled.

  In at least one example, the via is a processor socket via.

  In at least one example, each lane of the channel includes a corresponding portion of a respective processor socket, and each of the plurality of processor sockets corresponding to the lane of the channel having a via stub is back-drilled.

  In at least one example, a low loss circuit board is provided and the channel is at least partially mounted to the circuit board.

  In at least one example, the low loss circuit board has less trace differential insertion loss. In at least one example, gain is applied at the receiver front end of the channel.

  In at least one example, the gain comprises approximately 6 dB.

  In at least one example, gain is applied to the continuous time linear equalizer of the channel.

  In at least one example, the combined gain applied to the receiver front end and the continuous time linear equalizer is approximately 6 dB.

  In at least one example, the channel includes at least one via with a back drilled stub, the channel is at least partially implemented in a low loss circuit board, and a combined gain of approximately 6 dB is included in the channel Applied at one or more of the receiver front end and the continuous time linear equalizer of said channel.

  In at least one example, the length of the channel is at least 20 inches (50.8 centimeters).

  One or more embodiments provide an apparatus, system, machine-readable storage, machine-readable medium, hardware-based for transmitting data at a bit rate of at least 16 GT / sec over a channel comprising a multi-lane link consisting of two connectors And / or software based logic, and methods may be provided, wherein the length of the channel is greater than 12 inches (30.48 centimeters).

  In at least one example, the length of the channel is at least 20 inches (50.8 centimeters).

  In at least one example, the channel includes one or more vias, and stubs of the plurality of vias are back drilled.

  In at least one example, the one or more vias are included in one or both of the two connectors.

  In at least one example, the channel includes a plurality of processor sockets, and the plurality of processor sockets include the plurality of vias.

  In at least one example, the channel includes at least one via with a back drilled stub, the channel is at least partially implemented in a low loss circuit board, and a combined gain of approximately 6 dB is included in the channel Applied at one or more of the receiver front end and the continuous time linear equalizer of said channel.

  In at least one example, the channel comprises a PCIe based channel.

  One or more embodiments provide an apparatus, system, machine readable storage, machine readable medium for receiving data transmitted at a bit rate of at least 16 GT / sec on a channel comprising a multilane link consisting of two connectors. Hardware-based and / or software-based logic and methods may be provided, wherein the length of the channel is greater than 12 inches (30.48 centimeters).

  In at least one example, the length of the channel is at least 20 inches (50.8 centimeters).

  In at least one example, the channel includes one or more vias, and stubs of the plurality of vias are back drilled.

  In at least one example, the one or more vias are included in one or both of the two connectors.

  In at least one example, the channel includes a plurality of processor sockets, and the plurality of processor sockets include the plurality of vias.

  In at least one example, the channel includes at least one via with a back drilled stub, the channel is at least partially implemented in a low loss circuit board, and a combined gain of approximately 6 dB is included in the channel Applied at one or more of the receiver front end and the continuous time linear equalizer of said channel.

  In at least one example, the channel comprises a PCIe based channel.

  In at least one example, a system is provided that includes a first device and a second device that is communicatively coupled to the first device using an interconnect channel, wherein the interconnect channel is at least 16 GT / sec. The link includes a Peripheral Component Interconnect (PCI) Express (PCIe) protocol based link that supports bit rates, the link includes two connectors and has a length greater than 12 inches (30.48 centimeters).

  In at least one example, the system includes a server chipset.

  In at least one example, the first device comprises a processor device.

  One or more embodiments identify a first lane error on a particular one of a plurality of lanes of the link based on the detection of at least one symbol of error transmitted on the particular lane. And providing an apparatus, system, machine readable storage, machine readable medium, hardware based and / or software based logic, and method for reporting the first lane error to the lane error register.

  In at least one example, a plurality of lane errors reported in the lane error register identify corresponding lanes in the plurality of lanes.

  In at least one example, based on the detection of an error synchronization header in at least one of the plurality of lanes, a second lane error is identified on the link, and the second lane error is in the lane error register. Reported.

  In at least one example, a third lane error is identified based on the determination of parity information inconsistencies with the data stream transmitted via the link, and the third lane error is reported to the lane error register.

  In at least one example, parity information is received on an ordered set of SKPs (SKP OS).

  In at least one example, the I / O logic comprises physical layer logic.

  In at least one example, the error symbol includes an error for a symbol included in the SKP OS.

  In at least one example, the error symbols include symbols other than SKP OS detected between the first SLP OS symbol in the SKP OS and the SLP END marker in the SKP OS.

  In at least one example, the error symbol includes a SKP END placed on a symbol other than the SKP OS symbol 8, 12, 16, 20 or 24.

  In at least one example, the erroneous symbol comprises a first symbol of a framing token.

  In at least one example, the framing token comprises a PCIe framing token.

  In at least one example, the framing token includes: a logical idle token (IDL), a data link layer packet (DLLP) start of data token (SDP), a start of transaction layer packet (TLP) data token (STP), and a bad TLP token. At least one of the ends (EDB).

  In at least one example, the error symbol comprises an error IDL token symbol.

  In at least one example, a first IDL token is included in a particular lane n in a plurality of lanes, and the error symbol is detected in any one of lanes n + 1, n + 2, and n + 3 in the plurality of lanes. Contains symbols other than IDL.

  In at least one example, the erroneous symbol comprises an EDB token symbol.

  In at least one example, a first EDB token follows a TLP on a particular lane n in the plurality of lanes, and the symbol of the error is any one of lanes n + 1, n + 2, and n + 3 in the plurality of lanes. Contains symbols other than EDB detected in one.

  In at least one example, the erroneous symbol includes an EDB token symbol, and the EDB token follows a framing token other than an SDP token.

  In at least one example, the error symbol comprises an SDP token symbol.

  In at least one example, the first symbol of the SDP token is included in a specific lane n in the plurality of lanes, and the symbol of the error includes a symbol other than the SDP detected in lane n + 1 in the plurality of lanes.

  In at least one example, the lane error register includes a PCIe lane error condition (LES) register.

  In at least one example, the link comprises a PCIe compliant link.

  In at least one example, a second lane error is identified on the link based on the detection of an ordered set of blocks lacking a preceding EDS token.

  In at least one example, lane errors based on detection of errors in any one of the ordered set of symbols, IDL token symbols, SDP token symbols, STP token symbols, and EDB token symbols are identified and reported .

  In at least one example, the lane error register is monitored to identify a plurality of lane errors for a particular lane, and based on the plurality of errors identified for the particular lane in the lane error register, the particular error. It can be determined that there is a defect in the lane.

  In at least one example, determining that the particular lane is defective includes statistical analysis of the plurality of errors.

  One or more embodiments identify that a link including multiple lanes exits an active state, and based on data previously transmitted via the link, provides parity information for the multiple lanes. Apparatus, system, machine readable storage, machine readable medium, hardware based and / or software based logic, and method for maintaining and transmitting an indication of the parity information prior to the termination from the active state May be provided.

  In at least one example, the indication of the parity information is transmitted in response to the termination.

  In at least one example, the indication of the parity information is transmitted in an ordered set.

  In at least one example, the indication of the parity information for each lane is included in a respective parity bit for each lane included in the ordered set.

  In at least one example, the ordered set includes a PCIe SKP OS.

  In at least one example, the link exits the active state based on link recovery.

  In at least one example, the link recovery is based on errors detected on the link.

  In at least one example, the error includes a framing token error.

  One or more embodiments transmit data on a link including a plurality of lanes and maintain parity information for each of the plurality of lanes based on the transmitted data, wherein the link is active An apparatus, system, machine-readable storage, machine-readable medium, hardware-based and / or software-based for identifying that the state is to be terminated and transmitting the parity information prior to the termination from the active state Logic and methods may be provided.

  One or more embodiments maintain first parity information for each of the plurality of lanes of the link based on data previously transmitted over the link, and second parity information in response to an event The event causes the link to exit the active state, and the second parity information is transmitted prior to the termination from the active state. Machine readable storage, machine readable media, hardware based and / or software based logic, and methods may be provided. The first parity information is compared with the second parity information to identify a plurality of potential lane errors on one or more of the plurality of lanes.

  In at least one example, the second parity information is included in an ordered set.

  In at least one example, the second parity information is included in a plurality of parity bits included in the ordered set.

  In at least one example, the ordered set includes a SKP OS.

  In at least one example, based on the recovery of the link, the link exits the active state.

  In at least one example, the recovery is triggered by an error detected on the link.

  In at least one example, the error includes a framing token error.

  In at least one example, multiple potential lane errors are reported to the lane error register.

  In at least one example, the lane error register includes a LES register.

  In at least one example, the event includes an error detected on the link.

  In at least one example, recovery of the link is triggered based on the error, and the recovery causes the link to exit the active state.

  In at least one example, a plurality of potential lane errors are identified based on detecting that the first parity information does not match the second parity information.

  One or more embodiments receive data via a link including a plurality of lanes, maintain first parity information for each of the plurality of lanes based on the data, and For comparing the first parity information with the second parity information to identify a plurality of potential lane errors on one or more of the plurality of lanes. An apparatus, system, machine readable storage, machine readable medium, hardware and / or software based logic and method may be provided, wherein the event causes the link to exit an active state and the second. The parity information of is transmitted before the end from the active state.

  One or more embodiments maintain parity information for each of a plurality of lanes of the link based on a first portion of data transmitted over the link, and after recovery of the link, the parity An apparatus, system, machine-readable storage, machine-readable medium, hardware-based and / or software-based logic, and method for resuming the calculation of information may be provided, wherein the parity information is stored during link recovery. Maintained, and the parity information is further based on a second portion of the data transmitted over the link, and the second portion of data is considered persistent.

  In at least one example, the first portion of the data corresponds to a first data block, and the second portion of the data corresponds to a different second data block.

  In at least one example, the first data block is interrupted by the recovery, and the second block starts after the recovery.

  In at least one example, the recovery is based on errors detected on the link.

  In at least one example, an indication of the parity information calculated based on the first and second portions of the data is transmitted to a receiving device.

  In at least one example, the parity information includes first parity information, and the I / O logic further includes a first calculated from the transmitting device by the transmitting device based on the first and second portions of the data. Receiving an indication of the second parity information and comparing the indication of the second parity information with the first parity information.

  In at least one example, based on a comparison of the indication of the second parity information and the first parity information, whether there are multiple potential errors on one or more of the plurality of lanes Judgment is made.

  In at least one example, the plurality of potential errors are reported to a lane error register.

  In at least one example, the lane error register includes a PCIe LES register.

  In at least one example, the indication of the second parity information is included in the SKP OS.

  In at least one example, the indication of the second parity information comprises a plurality of parity bits of the SKP OS.

  In at least one example, the link includes a PCIe compliant link.

  One or more embodiments transmit first data on a link including a plurality of lanes and determine parity information for each of the plurality of lanes based on the transmitted first data. An apparatus and system for participating in the recovery of the link and for transmitting the second data on the link after the recovery of the link and for updating the parity information to generate updated parity information Machine-readable storage, machine-readable media, hardware-based and / or software-based logic, and methods, wherein the parity information is maintained during the recovery of the link, and the updated parity information is , Based on the first data and the second data.

  One or more embodiments receive first data from a device, determine parity information for each of the plurality of lanes based on the received first data, and participate in recovery of the link And after the recovery of the link, an apparatus, system, and machine readable storage for receiving the second data on the link from the device and updating the parity information to generate updated parity information Machine-readable media, hardware-based and / or software-based logic, and methods, wherein the first data is received on a link including a plurality of lanes, and the parity information is Maintained during recovery, the updated parity information is based on the first data and the second data.

  In at least one example, the particular parity information can be compared with other parity information to determine one or more potential lane errors.

  In at least one example, the other parity information is included in the SKP OS.

  In at least one example, the other parity information is distinguishable from a plurality of parity bits included in the SKP OS.

  One or more embodiments may receive first data from a device, determine parity information for each of the plurality of lanes based on the received first data, and recover the link. An apparatus, system, and machine readable for joining and receiving the second data on the link from the device after the recovery of the link and updating the parity information to generate updated parity information Storage, machine-readable media, hardware-based and / or software-based logic, and methods may be provided, wherein the first data is received on a link that includes a plurality of lanes, and the parity information is stored on the link. Maintained during the recovery, the updated parity information is based on the first data and the second data.

  When referring to an “one embodiment” or “an embodiment” throughout this specification, at least one embodiment of the invention includes the specific feature, structure, or characteristic described in connection with the embodiment. Means that. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Further, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

In the above specification, detailed descriptions have been set forth with regard to specific exemplary embodiments. However, it will be apparent that various changes and modifications can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and accompanying drawings are therefore to be regarded in an illustrative sense rather than a restrictive sense. Moreover, the above uses of the embodiments and other exemplary terms do not necessarily refer to the same embodiment or the same example, but to different and distinct embodiments and potentially identical embodiments. Sometimes.
(Item 1)
Identify links that contain multiple lanes to exit active state,
Maintaining parity information for the plurality of lanes based on data previously transmitted via the link,
An apparatus comprising I / O logic for transmitting an indication of the parity information prior to the termination from the active state.
(Item 2)
The apparatus of claim 1, wherein the indication of the parity information is transmitted in response to the termination.
(Item 3)
The apparatus of claim 1, wherein the indication of the parity information is transmitted in an ordered set.
(Item 4)
The apparatus according to claim 3, wherein the indication of the parity information for each lane is included in respective parity bits for each lane included in the ordered set.
(Item 5)
The apparatus of claim 3, wherein the ordered set comprises PCIe SKP OS.
(Item 6)
The apparatus of claim 1, wherein the link exits the active state based on link recovery.
(Item 7)
The apparatus of claim 6, wherein the link recovery is based on errors detected on the link.
(Item 8)
The apparatus according to Item 7, wherein the error includes a framing token error.
(Item 9)
Transmitting data on a link including a plurality of lanes;
Maintaining parity information for each of the plurality of lanes based on the transmitted data;
Identifying that the link is to exit the active state;
Sending an indication of the parity information prior to the termination from the active state.
(Item 10)
10. The method of item 9, wherein the indication of the parity information is sent in SKP OS.
(Item 11)
10. The method of item 9, wherein the indication of the parity information is sent prior to scheduled transmission of parity information based on the step of the link identifying that the active state is to end.
(Item 12)
10. The method of item 9, wherein the link exits the active state based on link recovery triggered by an error detected on the link.
(Item 13)
13. The method of item 12, further comprising receiving data indicating the error from a receiving device.
(Item 14)
At least one machine-accessible storage medium having a code stored thereon, the code executing on the machine, to the machine
Send data on a link that contains multiple lanes,
Maintaining parity information for each of the plurality of lanes based on the transmitted data;
The link identifies the termination of the active state,
At least one machine accessible storage medium causing the parity information to be transmitted prior to the termination from the active state.
(Item 15)
Maintaining first parity information for each of a plurality of lanes of the link based on data previously transmitted over the link;
Receiving second parity information in response to the event;
I / O logic that compares the first parity information to the second parity information to identify potential lane errors on one or more of the plurality of lanes,
The apparatus, wherein the event causes the link to exit an active state, and the second parity information is transmitted prior to the termination from the active state.
(Item 16)
16. The apparatus of item 15, wherein the second parity information is included in an ordered set.
(Item 17)
The apparatus according to item 16, wherein the second parity information is included in a plurality of parity bits included in the ordered set.
(Item 18)
17. The apparatus according to item 16, wherein the ordered set comprises a SKP OS.
(Item 19)
16. The apparatus of item 15, wherein the link exits the active state based on recovery of the link triggered by an error detected on the link.
(Item 20)
20. The apparatus according to item 19, wherein the error comprises a framing token error.
(Item 21)
The apparatus of item 15, wherein the I / O logic further reports a plurality of potential lane errors to a lane error register.
(Item 22)
22. The apparatus according to item 21, wherein the lane error register comprises a LES register.
(Item 23)
Receiving data via a link including multiple lanes;
Maintaining first parity information for each of the plurality of lanes based on the data;
Receiving second parity information in response to the event;
Comparing the first parity information with the second parity information to identify a plurality of potential lane errors on one or more of the plurality of lanes;
The method, wherein the event causes the link to exit an active state, and the second parity information is transmitted prior to the termination from the active state.
(Item 24)
24. The method of item 23, wherein the event comprises an error detected on the link.
(Item 25)
24. The method of item 23, wherein recovery of the link is triggered based on the error, and the recovery causes the link to exit the active state.
(Item 26)
26. The method of item 23, further comprising reporting the plurality of potential lane errors to a lane error register.
(Item 27)
Monitoring the lane error register to determine if one or more of the plurality of lanes is defective based on the plurality of lane errors reported to the lane error register 26. The method described in 26.
(Item 28)
A method according to item 23, wherein a plurality of potential lane errors are identified based on the detection that the first parity information does not match the second parity information.
(Item 29)
At least one machine-accessible storage medium having stored code, said code being
Receive data via a link that includes multiple lanes,
Maintaining first parity information for each of the plurality of lanes based on the data;
The second parity information is received in response to the event,
Comparing the first parity information with the second parity information to identify potential lane errors on one or more of the plurality of lanes;
At least one machine accessible storage medium, wherein the event causes the link to exit an active state and the second parity information is sent prior to the termination from the active state.
(Item 30)
Data links containing multiple lanes,
A first device,
A second device communicatively coupled to the first device using the data link;
The second device is
Send data to the first device on the link,
Maintaining parity information for each of the plurality of lanes based on the transmitted data;
Identify that the link is to exit the active state,
A system comprising I / O logic that transmits an indication of the parity information prior to the termination from the active state.
(Item 31)
The parity information includes first parity information, and the first device
Maintaining second parity information for each of the plurality of lanes based on the data;
Receiving the indication of the first parity information;
I / O logic that compares the first parity information to the second parity information to identify potential lane errors on one or more of the plurality of lanes. The system according to item 30.
(Item 32)
The I / O logic of the first device is further configured to generate a potential error for a particular one of the plurality of lanes based on a comparison of the first parity information and the second parity information. The system according to item 31, which determines.
(Item 33)
30. The system of clause 30, wherein the indication of the parity information is included in a SKP OS sent by the second device to the first device.

Claims (21)

A device,
A port transmitter for calculating a parity corresponding to each of a plurality of lanes of the link, the parity corresponding to the lanes, one for a plurality of payloads of the plurality of data blocks to be communicated by said lane The port transmitter having even parity; and
I / O logic for generating an ordered set (OS) of SKPs associated with a particular said lane, wherein said SKP's OS has a data parity bit, said data parity bit being The I / O logic indicating the even parity of the lane of
A transmitter for transmitting the SKP OS on the specific lane. The apparatus according to claim 1, wherein the parity is calculated separately from all other lanes. The apparatus according to claim 1 or 2, wherein the OS of each SKP includes data parity bits generated for each of the plurality of lanes of the link and indicating the calculated parity for the corresponding lanes. . A receiver for receiving a start of data sequence (SDS) OS;
The apparatus according to any one of claims 1 to 3, wherein the parity is calculated based on a set of a plurality of payloads of a plurality of data blocks communicated starting from reception of the SDS OS. The apparatus according to any one of claims 1 to 4 , wherein the SKP's OS is sent to coincide with termination from an active link state. 6. The apparatus of claim 5 , wherein the link enters recovery after the termination from the active link state. OS of the SKP An apparatus according to any one of claims 1 6 including a format in accordance with the Peripheral Component Interconnect Express (PCIe) based protocol. A device,
A receiver for receiving a plurality of data blocks on a link having a plurality of lanes and receiving an ordered set (OS) of SKPs on a particular lane of the plurality of lanes, The SKP OS is associated with the particular lane, the SKP OS includes data parity bits, and the data parity bits are transmitted by the transmitter on the particular lane of the plurality of data blocks . shows a first even parity value one calculated for a plurality of payloads, and wherein the receiver,
A parity calculator for calculating one second parity value for a plurality of payloads of the received plurality of data blocks;
Parity comparison logic for comparing the first even parity value with the second parity value to determine if an error condition exists. The apparatus according to claim 8 , wherein the first even parity value is calculated separately from parity values calculated for a plurality of data blocks transmitted on other lanes of the plurality of lanes. . The OS of each SKP is generated by the transmitter for each of the plurality of lanes of the link, and the parity calculated by the transmitter for the plurality of data blocks transmitted on the corresponding one of the lanes 10. Apparatus according to claim 8 or 9 , including data parity bits for indicating. Further comprising the transmitter for transmitting a data sequence start OS (SDS OS);
The apparatus of claim 10, wherein the parity is calculated by the transmitter based on a set of multiple payloads of multiple data blocks transmitted by the transmitter after transmission of the SDS OS. The apparatus according to any one of claims 8 to 11, wherein the SKP's OS is transmitted by the transmitter to coincide with termination from an active link state. The apparatus of claim 12 , wherein the link enters recovery after the termination from the active link state. The apparatus according to any one of claims 8 to 13 , wherein the SKP OS includes a format according to a peripheral component interconnect express (PCIe) based protocol. A method performed by the device ,
Calculating a parity corresponding to each of a plurality of lanes of the link, the parity corresponding to a lane having one even parity for a plurality of payloads of a plurality of data blocks communicated by the lane, Calculating, and
Generating an ordered set (OS) of SKPs associated with a particular said lane, wherein said SKP's OS has a data parity bit, said data parity bit being associated with said one of said lanes Said generating step indicating even parity;
Transmitting the OS of the SKP on the particular lane. A system,
Means for calculating a parity corresponding to each of a plurality of lanes of the link, wherein the parity corresponding to a lane has one even parity for a plurality of payloads of a plurality of data blocks communicated by the lane , Means for said calculating,
A means for generating an ordered set (OS) of SKPs associated with a particular said lane, wherein said SKP's OS comprises a data parity bit, said data parity bit being associated with a particular said lane Said means for generating indicating said even parity of
Means for transmitting an OS of the SKP on a particular lane. A system comprising a first device and a second device connected to the first device by a point-to-point serial data link,
The point-to-point serial data link comprises a plurality of lanes,
The second device is
A port transmitter for calculating parity corresponding to each of the plurality of lanes of the point-to-point serial data link, wherein the parity corresponding to the lane comprises a plurality of data blocks communicated on the lanes. The port transmitter having one even parity for multiple payloads;
I / O logic for generating an ordered set (OS) of SKPs associated with a particular said lane, wherein said SKP's OS has a data parity bit, said data parity bit being Said I / O logic indicating said even parity of said lane of
A transmitter for transmitting the OS of the SKP to the first device on a particular lane. The system of claim 17 , wherein the second device comprises a processor device. The system according to claim 17 or 18 , wherein the second device has a root port. The system according to any one of claims 17 to 19 , wherein the first device comprises a graphics processor. The system according to any one of claims 17 to 20 , wherein the first device has a memory controller.

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