JP6550703B2 - Merging unit, trigger signal output method, and merging unit test system - Google Patents

Description

  The present invention relates to a merging unit, a trigger signal output method, and a merging unit test system.

  Conventionally, an error evaluation device for an electronic current transformer according to International Electrotechnical Commission (IEC) 60044-8 and IEC 61850-9-2 is known (for example, Patent Document 1 etc.).

JP2013-53855A

  However, since the conventional device does not use the trigger (Trigger) signal output based on the trigger condition, there are cases where the timing at which the merging unit (merging unit) samples the electric quantity is unknown.

  Because the timing at which the merging unit samples the amount of electricity is unknown, the processing time of the merging unit may be unknown.

  One aspect of the present invention aims to clarify the timing at which a merging unit samples an amount of electricity by using a trigger signal output based on a trigger condition.

In one aspect, a merging unit that measures the amount of electricity of a power supply system, and a setting unit that sets a trigger condition that is a condition for sampling the amount of electricity of the power supply system to be measured; and when the trigger condition is satisfied A sampling unit that samples the measured electrical quantity, a data transmission unit that transmits output data generated based on the electrical quantity sampled by the sampling unit, and a trigger signal when the trigger condition is satisfied have a signal output unit for outputting to an external device, wherein the setting unit is configured as a trigger condition, the time including the time of sampling the electrical quantity of the power supply system in which the time for outputting a trigger signal, and is measured It is characterized by setting conditions .

  The timing when the merging unit samples the quantity of electricity can be specified.

It is the schematic which shows the usage example of the merging unit which concerns on one Embodiment of this invention. It is a block diagram which shows an example of the hardware constitutions of the merging unit which concerns on one Embodiment of this invention. It is a block diagram which shows an example of the system configuration | structure of the merging unit test system which concerns on one Embodiment of this invention. It is a functional block diagram which shows an example of a function structure of the merging unit which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the whole process by the merging unit test system which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the process which an oscilloscope performs in the merging unit test system which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the process which a merging unit performs in the merging unit test system which concerns on one Embodiment of this invention. It is a figure explaining an example of SV message concerning one embodiment of the present invention. It is a figure explaining an example of the setting screen of the trigger condition which concerns on one Embodiment of this invention. It is a figure explaining an example of the sampling of the electric quantity which concerns on one Embodiment of this invention. It is a figure explaining an example of the APDU structure of SV message which concerns on one Embodiment of this invention. It is a figure explaining an example of calculation of the processing time of the merging unit concerning one embodiment of the present invention. It is a figure explaining an example in the case of sampling 2 or more electric quantity which concerns on one Embodiment of this invention. It is a figure explaining an example of statistical data concerning one embodiment of the present invention.

  Embodiments of the present invention will be described below.

  FIG. 1 is a schematic diagram showing an example of use of a merging unit according to an embodiment of the present invention.

  As shown in the figure, the merging unit 1 is connected to a power supply system such as an electric wire via a current transformer 2 or a transformer 3. The merging unit 1 is connected to a protection relay 5 via a network such as a LAN (Local Area Network) 4. The protection relay 5 is connected to the circuit breaker control device 6 via the LAN 4 or the like. The circuit breaker control device 6 is connected to the circuit breaker 61. In the power system of IEC 61850 or the like, merging unit 1 is used, for example, in the configuration shown in FIG.

  The merging unit 1 measures the amount of electricity in the power supply system. The amount of electricity is the amount of current I measured by the merging unit 1 via the current transformer 2 and the amount of voltage V measured by the merging unit 1 via the transformer 3. The merging unit 1 generates output data D1 based on the measured amount of electricity, and transmits the output data D1 to the switching hub (Switching Hub) 41. The switching hub 41 transmits the output data D1 transmitted from the merging unit 1 to the protection relay 5.

  The protection relay 5 detects an accident of the power supply system based on the output data D1 transmitted from the merging unit 1. Output data D1 is periodically transmitted to the protection relay 5. The protection relay 5 periodically receives the output data D1, and monitors the change in the amount of electricity in the power supply system based on the output data D1. For example, when the amount of electricity in the power supply system changes significantly, the protection relay 5 determines that an accident has occurred in the power supply system.

  When the protective relay 5 detects an accident in the power supply system, the protective relay 5 transmits a trip (Trip) signal SIG1 to the circuit breaker control device 6 via the LAN 4. The trip signal SIG1 is a signal defined by a standard such as IEC61850. When receiving the trip signal SIG1, the circuit breaker control device 6 performs control to open the circuit breaker 61, which is a circuit breaker or the like. By opening the circuit breaker 61, the protective relay 5 cuts off the power supply system in which the accident has occurred from the other power supply systems and protects the power supply system.

  The processing time from the occurrence of an accident in the power supply system to the protection of the power supply system is determined by the standards or specifications. The processing time from the occurrence of an accident in the power supply system to the protection of the power supply system is required to be, for example, within 50 ms (milliseconds). In order to set the processing time from the occurrence of an accident of the power supply system to the protection of the power supply system within a predetermined time, each device shown in FIG. Each is required. According to IEC 61869-9, which is a related standard to IEC 61850, the processing time T in the merging unit 1 is required to be within 2 ms. The processing time from the occurrence of an accident in the power supply system to the protection of the power supply system varies depending on the power supply system etc., and processing time other than 50 ms may be required.

  The processing time T is the time from when the merging unit 1 transmits the first bit of the predetermined data included in the output data D1 after the electric quantity such as the current amount I and the voltage amount V is input to the merging unit 1 . When the merging unit 1 uses the Sampled Value protocol (Protocol) defined by IEC 61850-9-2, the processing time T is such that the amount of electric current such as the current amount I and the voltage amount V is input to the merging unit 1 It is a time until the first bit (Bit) of predetermined data included in a Sampled Value message (hereinafter referred to as an SV message) storing the value of the amount of electricity is transmitted by the merging unit 1 on the LAN 4.

  The processing time T is calculated by adding a delay time due to an analog filter or the like to the processing time of the merging unit 1. The processing time by the merging unit 1 is a predetermined time which the output data D1 has from the time when the A / D conversion is started to the electric quantity when the electric quantity such as the current amount I and the voltage amount V is input to the merging unit 1 This is the time until the first bit of data is transmitted. The delay time due to the analog filter or the like is the time taken by analog filter processing or the like performed before A / D conversion.

  The delay time due to the analog filter or the like is a fixed time determined by the specifications of the analog filter used.

  Therefore, the processing time T can be calculated from the timing when the merging unit 1 samples the amount of electricity and the timing when the merging unit 1 transmits the leading bit of the predetermined data of the output data D1.

<Hardware configuration of merging unit>
FIG. 2 is a block diagram showing an example of a hardware configuration of a merging unit according to an embodiment of the present invention.

  The merging unit 1 includes an input terminal 1H1, an A / D (Analog-Digital) converter 1H2, an FPGA (Field-Programmable Gate Array) 1H3, a CPU (Central Processing Unit) 1H4, a LAN controller 1H5, and a network output. Terminal 1H6, trigger signal generation circuit 1H7, clock (Clock) signal generator 1H8, switch 1H9, nonvolatile memory 1H10, RAM (Random Access Memory) 1H11, trigger signal output terminal 1H12, analog filter (analog filter) 1H13.

  The input terminal 1H1 is connected to the output terminal of a sensor that measures the amount of electricity. The amount of electricity measured by the merging unit 1 is input to the input terminal 1H1.

  The A / D converter 1H2 is connected to the analog filter 1H13. The A / D converter 1H2 performs A / D conversion. The A / D converter 1H2 inputs from the analog filter 1H13 the amount of electricity input to the input terminal 1H1, which is an analog value, and converts it into a digital value that can be processed by a circuit or the like. The A / D converter 1H2 is connected to the FPGA 1H3 and the like, and outputs an A / D converted digital value to the connection destination. The A / D converter 1H2 may have a low pass filter (Low-Pass Filter), and may filter the data signal of the input electric quantity before A / D conversion. The A / D converter 1H2 may include an amplifier and amplify the signal.

  The FPGA 1 H 3 and the CPU 1 H 4 perform operations for realizing various processes performed by the merging unit 1. The FPGA 1H3 and the CPU 1H4 control each hardware included in the merging unit 1. The FPGA 1H3 is connected to the CPU 1H4 and the like, and the FPGA 1H3 transmits and receives various data to and from the connection destination. The CPU 1 H 4 is connected to the FPGA 1 H 3, and the CPU 1 H 4 exchanges various data with the connection destination.

  The nonvolatile memory 1H10 and the RAM 1H11 are connected to the CPU 1H4. The nonvolatile memory 1H10 and the RAM 1H11 store various data, parameters, and the like. The nonvolatile memory 1H10 and the RAM 1H11 store data used by the CPU 1H4 for processing, programs, and the like.

  The LAN controller 1H5 is connected to the CPU 1H4 and the like, and the LAN controller 1H5 inputs data from the CPU 1H4. The LAN controller 1H5 transmits output data D1 and the like to the LAN 4 via the network output terminal 1H6. A LAN connector or the like is connected to the network output terminal 1H6, and the network output terminal 1H6 is connected to the LAN 4.

  The trigger signal generation circuit 1H7 generates a signal such as a sampling trigger signal. The trigger signal generation circuit 1H7 is connected to the clock signal generator 1H8.

  The clock signal generator 1H8 generates a clock signal and outputs a clock signal generated to the trigger signal generation circuit 1H7. The trigger signal generation circuit 1H7 operates based on the clock signal input from the clock signal generator 1H8.

  The sampling trigger signal generated by the trigger signal generation circuit 1H7 may be output from the trigger signal output terminal 1H12 to an external device such as an oscilloscope (Oscilloscope) as the trigger signal SIG2.

  The switch 1H9 is connected to the CPU 1H4, and the CPU 1H4 controls the switch 1H9. Under control of the CPU 1 H 4, the switch 1 H 9 switches whether to output the sampling trigger signal input from the trigger signal generation circuit 1 H 7 as an trigger signal SIG 2 to an external device via the trigger signal output terminal 1 H 12.

  The trigger signal output terminal 1H12 is connected to an external device such as an oscilloscope. The trigger signal output terminal 1H12 is connected to the switch 1H9, and when the sampling trigger signal is output from the switch 1H9 to the trigger signal output terminal 1H12, the trigger signal output terminal 1H12 outputs the sampling trigger signal to the external device as the trigger signal SIG2 To do.

  The analog filter 1H13 is connected to the input terminal 1H1. The analog filter 1H13 is a low-pass filter or the like. The analog filter 1H13 attenuates noise and the like included in the data signal of the electric quantity input to the input terminal 1H1.

  In the case of the configuration shown in FIG. 2, the processing time of merging unit 1 is the first bit of the predetermined data of output data D1 by network output terminal 1H6 after A / D conversion is started by A / D converter 1H2. This is the time it takes to output. In the case of the configuration shown in FIG. 2, the delay time by the analog filter or the like is the processing time by the analog filter 1H13 and the time until the signal reaches the analog filter 1H13. That is, the delay time by the analog filter or the like is the time taken for the A / D conversion to be performed by the A / D converter 1H2.

  The hardware configuration is not limited to the configuration shown in FIG. The merging unit 1 may have a configuration including an application specific integrated circuit (ASIC) that implements various processes, a digital signal processor (DSP), and the like.

<Mergeing unit test system>
FIG. 3 is a block diagram showing an example of a system configuration of a merging unit test system according to an embodiment of the present invention.

  The merging unit test system 100 includes a merging unit 1 and an oscilloscope 7. The merging unit test system 100 is connected to the signal generator 8 and the switching hub 41. The merging unit test system 100 is connected to a PC (Personal Computer) 9 via a switching hub 41.

  The system configuration shown in FIG. 3 is an example of the system configuration in the case of inspecting the merging unit 1. In an inspection or the like for obtaining the processing time T of the merging unit 1, the merging unit test system 100 shown in FIG. 3 which is a system configuration different from the system configuration when using the merging unit 1 shown in FIG. Inspection is performed. The system configuration of merging unit test system 100 is not limited to the configuration shown in FIG.

  The merging unit test system 100 is used to check whether the processing time T of the merging unit 1 is within a time defined by a standard or the like.

  In the merging unit 1, a trigger condition for outputting a trigger signal SIG2 is set by the PC 9, for example.

  As shown, a signal generator 8 is connected to the merging unit test system 100, and a test signal is input from the signal generator 8 to the merging unit 1. The test signal is a signal that replaces the electrical data signal shown in FIG. In the inspection, a test signal is used instead of the data signal of the electric quantity. When the signal generator 8 inputs a test signal to the merging unit 1 and the oscilloscope 7 analyzes and displays the output data 1 which is the output of the merging unit 1 for the input test signal, the inspection of the merging unit 1 is Done.

  The oscilloscope 7 has two or more input channels (hereinafter referred to as CH). Hereinafter, a case where the oscilloscope 7 has two channels of CH1 and CH2 will be described as an example.

  The oscilloscope 7 has a CH 1 input terminal 71 and a CH 2 input terminal 72.

  The CH1 input terminal 71 is connected to the trigger signal output terminal 1H12 of the merging unit 1, and the CH1 input terminal 71 receives the trigger signal SIG2.

  The CH2 input terminal 72 is connected to the network output terminal 1H6 of the merging unit 1, and the data signal of the output data D1 is input to the CH2 input terminal 72.

  The oscilloscope 7 analyzes the signal input to the input terminal and displays the analysis result. The oscilloscope 7 inputs a data signal from an Ethernet (registered trademark) (Ethernet) cable and analyzes the input signal.

  The oscilloscope 7 stores data for a certain time.

  The oscilloscope 7 triggers the case where the signals input to the CH1 input terminal 71 and the CH2 input terminal 72 satisfy the set conditions. The oscilloscope 7 stores the time to trigger on each CH, and calculates two time intervals.

  When the test signal is input to merging unit test system 100, in merging unit test system 100, merging unit 1 outputs trigger signal SIG2 when the trigger condition is satisfied, and merging unit 1 outputs data based on the test signal. D1 is transmitted.

  The oscilloscope 7 receives the trigger signal SIG2 and the data signal of the output data D1. For example, in the inspection, the oscilloscope 7 uses the output of the trigger signal SIG2 and transmission of a start bit signal included in predetermined data of the output data D1 as triggers, respectively, and the oscilloscope 7 calculates time intervals of two triggers.

<Functional configuration>
FIG. 4 is a functional block diagram showing an example of a functional configuration of the merging unit according to the embodiment of the present invention.

  FIG. 4 is an example of a functional configuration of the merging unit 1. Hereinafter, the functional configuration of the merging unit 1 will be described by taking as an example the case where the merging unit 1 is used in the system configuration shown in FIG.

  The merging unit 1 includes a sampling unit 1F1, a data output unit 1F2, a trigger signal output unit 1F3, and a trigger condition setting unit 1F4.

  The sampling unit 1F1 includes a filter unit 1F11, an A / D conversion unit 1F12, and a sampling control unit 1F13.

  The filter unit 1F11 performs, for example, low-pass filter processing on the signal measured by the merging unit 1 in order to attenuate noise included in the signal. The filter unit 1F11 is realized by an analog filter 1H13 or the like.

  The A / D conversion unit 1F12 performs A / D conversion on the signal measured by the merging unit 1. The quantity of electricity is sampled by A / D conversion. The A / D conversion unit 1F12 is realized by an A / D converter 1H2 or the like.

  The sampling control unit 1F13 controls the timing at which the A / D conversion unit 1F12 performs A / D conversion, and outputs a sampling trigger signal to the trigger signal output unit 1F3. The sampling control unit 1F13 is realized by the FPGA 1H3, the CPU 1H4, the trigger signal generation circuit 1H7, and the like. The sampling control unit 1F13 generates a sampling trigger signal, and the A / D conversion unit 1F12 performs A / D conversion at a timing based on the sampling trigger signal. Since the sampling control unit 1F13 periodically generates a sampling trigger signal, sampling is periodically performed, so the output data D1 is periodically output. The sampling trigger signal is a signal generated so as to be synchronized with a time source using a 1 PPS (Pulse Per Second) signal, a PTP (Precise Time Protocol), or the like.

  The sampling control unit 1F13 outputs the generated sampling trigger signal to the trigger signal output unit 1F3.

  The data output unit 1F2 includes a measured value conversion unit 1F21 and an SV message data generation unit 1F22.

  The measured value conversion unit 1F21 converts the amount of electricity to be sampled and generates electricity amount data. The measured value conversion unit 1F21 is realized by the CPU 1H4 or the like.

  The SV message data generation unit 1F22 generates output data D1. The SV message data generation unit 1F22 transmits the output data D1 to be generated to the oscilloscope 7 as an external device, the switching hub 41, and the like.

  The output data D1 is, for example, SV message data. Hereinafter, a case where the output data D1 is SV message data will be described as an example. The SV message data generated in the SV message data generation unit 1F22 includes the electric quantity data generated by the measurement value conversion unit 1F21. Details of the SV message will be described later. The SV message data generation unit 1F22 is realized by the CPU 1H4 or the like.

  The trigger signal output unit 1F3 outputs the trigger signal SIG2 to the oscilloscope 7. When the trigger condition set by the trigger condition setting unit 1F4 is satisfied, the trigger signal output unit 1F3 outputs the sampling trigger signal generated by the sampling control unit 1F13 as a trigger signal SIG2. The trigger signal output unit 1F3 receives, for example, the sampling trigger signal generated by the sampling control unit 1F13, and outputs the sampling trigger signal when the trigger condition is satisfied to the trigger signal output terminal 1H12, whereby the trigger signal SIG2 is generated. Output. The trigger signal SIG2 is a signal when the trigger condition is satisfied among the sampling trigger signals input from the sampling control unit 1F13. The trigger signal output unit 1F3 is realized by the CPU 1H4, the trigger signal generation circuit 1H7, the switch 1H9, and the like.

  The trigger condition setting unit 1F4 sets a trigger condition. The trigger condition setting unit 1F4 inputs the trigger condition setting from the PC 9 or the like. The trigger condition setting unit 1F4 is realized by the CPU 1H4 or the like.

  The sampling unit 1F1 samples the amount of electricity based on the sampling trigger signal. The data output unit 1F2 generates and transmits the output data D1 based on the amount of electricity sampled by the sampling unit 1F1.

  When the trigger condition set by the trigger condition setting unit 1F4 is satisfied, the trigger signal output unit 1F3 outputs a sampling trigger signal as a trigger signal SIG2. That is, the merging unit 1 can clearly indicate the timing at which the electrical quantity is sampled when the trigger condition is satisfied in the external device such as the oscilloscope 7 by the trigger signal SIG2.

<Overall processing>
FIG. 5 is a flow chart showing an example of the overall processing by the merging unit test system according to an embodiment of the present invention.

  FIG. 5 is a diagram for explaining an example of processing for measuring the processing time of the merging unit 1 by the merging unit test system 100 described with reference to FIGS. 3 and 4.

  In step S1, the merging unit test system 100 sets the CH of the oscilloscope 7. In the case of FIG. 3 and FIG. 4, the CH 1 input terminal 71 of the oscilloscope 7 is connected to the trigger signal output terminal 1 H 12 of the merging unit 1. Therefore, the trigger signal SIG2 is input from the merging unit 1 to the CH1 input terminal 71 of the oscilloscope 7. In step S1, the merging unit test system 100 sets the oscilloscope 7 so that, for example, the rising edge of the trigger signal SIG2 is triggered for CH1 of the oscilloscope 7.

  In the case of FIG. 3 and FIG. 4, the CH 2 input terminal 72 of the oscilloscope 7 is connected to the network output terminal 1 H 6 of the merging unit 1. Therefore, the data signal of the output data D1 is input to the CH2 input terminal 72 of the oscilloscope 7. In step S1, the merging unit test system 100 sets the oscilloscope 7 such that the leading bit of the predetermined data of the output data D1 becomes a trigger for CH2 of the oscilloscope 7.

  In step S1, the merging unit test system 100 sets the oscilloscope 7 so as to calculate the time interval of the signals input to CH1 and CH2 of the oscilloscope 7. In other words, the merging unit test system 100 is performed by the timing when the trigger signal SIG2 is output from the merging unit 1 to CH1 of the oscilloscope 7 and the timing when the first bit of the SFD data D12 is output from the merging unit 1 to CH2 of the oscilloscope 7 The oscilloscope 7 is set so as to calculate the difference between the two timings.

  In step S2, the merging unit test system 100 sets a trigger condition for the merging unit 1. The trigger condition is set by inputting each parameter of the trigger condition to the merging unit 1 from, for example, the PC 9.

  In the merging unit test system 100, when the trigger condition is set to the merging unit 1 in step S2, the merging unit 1 starts an operation corresponding to step S4. In parallel with step S4, the oscilloscope 7 performs the process of step S3 of measuring the processing time of the merging unit 1 operating in step 4 and step S5 of generating time data based on the measurement result of step S3. Do.

  In step S3, the oscilloscope 7 measures the processing time of the merging unit 1 during the operation of the merging unit 1.

  FIG. 6 is a flowchart showing an example of processing performed by the oscilloscope in the merging unit test system according to the embodiment of the present invention.

  FIG. 6 is a flowchart illustrating details of an example of step S3.

  In step S301, the oscilloscope 7 waits for the CH1 trigger signal SIG2 input. In step S301, the oscilloscope 7 performs processing of waiting for the trigger signal SIG2 to be input from the merging unit 1 to the CH1 input terminal 71 of the oscilloscope 7.

  In step S302, the oscilloscope 7 determines whether or not the trigger signal SIG2 is input to CH1. If the oscilloscope 7 determines that the trigger signal SIG2 is input to the CH1 input terminal 71 (YES in step S302), the oscilloscope 7 proceeds to step S303. If the oscilloscope 7 determines that the trigger signal SIG2 is not input to the CH1 input terminal 71 (NO in step S302), the oscilloscope 7 proceeds to step S301.

  In step S303, the oscilloscope 7 stores the time when the trigger signal SIG2 is input to CH1.

  In step S304, the oscilloscope 7 waits for the data signal input of the output data D1 of CH2. In step S304, the oscilloscope 7 performs a process of waiting for the data signal of the output data D1 to be input from the merging unit 1 as the CH2 trigger signal to the CH2 input terminal 72 of the oscilloscope 7.

  In step S305, the oscilloscope 7 determines whether or not the data signal of the output data D1 is input to CH2. If the oscilloscope 7 determines that the data signal of the output data D1 is input to the CH2 input terminal 72 (YES in step S305), the oscilloscope 7 proceeds to step S306. If the oscilloscope 7 determines that the data signal of the output data D1 is not input to the CH1 input terminal 71 (NO in step S305), the oscilloscope 7 proceeds to step S304.

  In step S306, the oscilloscope 7 stores the time when the data signal of the output data D1 is input to CH2.

  In step S307, the oscilloscope 7 calculates and stores the processing time of the merging unit 1 from the time when the trigger signal SIG2 is input to CH1 and the time when the data signal of the output data D1 is input to CH2. In step S307, the oscilloscope 7 calculates, for example, the difference between the time when the trigger signal SIG2 is input to CH1 and the time when the data signal of the output data D1 is input to CH2. Since the difference is the time taken from the time when the trigger signal SIG2 is input to CH1 to the time when the data signal of output data D1 is input to CH2, after the merging unit 1 starts A / D conversion, This is a time corresponding to the time required for the merging unit 1 to output the data signal of the output data D1. Therefore, the difference is the processing time of the merging unit 1.

  In step S4, the merging unit 1 performs a predetermined operation.

  FIG. 7 is a flowchart showing an example of processing performed by the merging unit in the merging unit test system according to the embodiment of the present invention.

  FIG. 7 is a flowchart illustrating details of an example of step S4.

  In step S401, in the merging unit 1, the sampling control unit 1F13 outputs a sampling trigger signal at sampling timing.

  When the sampling trigger signal is output in step S401, the merging unit 1 starts the processes of steps S402 to S404 and the processes of steps S405 to S407 in parallel.

  In step S402, in the merging unit 1, the A / D converter 1F12 samples the amount of electricity.

  In step S403, in the merging unit 1, the measurement value calculation unit 1F21 converts the amount of electricity into a voltage. In step S403, the merging unit 1 converts the amount of electricity sampled in step S402 by the measured value calculation unit 1F21.

  In step S404, in the merging unit 1, the SV message generator 1F22 stores and generates the electric quantity, and outputs SV message data. The processes of steps S402 to S404 are repeatedly performed in parallel regardless of the processes of steps S405 to S407.

  FIG. 8 is a diagram for explaining an example of an SV message according to an embodiment of the present invention.

  FIG. 8 is a diagram cited from IEC 61850-9-2. The data structure of the SV message data, which is the output data D1, is, for example, a structure defined by IEC 61850-9-2.

  The output data D1 includes, for example, preamble (Preamble) data D11 used for synchronization processing and the like, and Start Frame Delimiter (hereinafter, SFD) data D12 and the like. The output data D1 includes an APDU (Application Protocol Data Unit) D13 and the like.

  In the description, a case where the predetermined data included in the output data D1 is the SFD data D12 will be described as an example.

  When the predetermined data is the SFD data D12, in step S1, the merging unit test system 100 sets the oscilloscope 7 such that the leading bit of the SFD data D12 becomes a trigger for CH2 of the oscilloscope 7.

  In step S405, in the merging unit 1, the trigger signal output unit 1F3 acquires the time and updates the count value.

  In step S406, the merging unit 1 determines whether a trigger condition is satisfied. If it is determined in step S406 that the merging unit 1 satisfies the trigger condition set in step S2 (YES in step S406), the merging unit 1 proceeds to step S407. When it is determined in step S406 that the merging unit 1 does not satisfy the trigger condition set in step S2 (NO in step S406), the merging unit 1 ends the process.

  In step S407, in the merging unit 1, the trigger signal output unit 1F3 outputs the trigger signal SIG2 from the trigger signal output terminal 1H12.

  For example, when the time to start sampling is set to the time condition of “trigger output start condition”, in step S406, the merging unit 1 satisfies the trigger condition when the time set to the time condition is reached. Judge that In the case where the setting of the count value SmpCnt which is the count value condition or the "number of trigger outputs" is also set, the merging unit 1 determines the set count value condition or the condition relating to the "number of trigger outputs" in step S406. Is satisfied, it is determined that the trigger condition is satisfied.

  FIG. 9 is a diagram illustrating an example of a trigger condition setting screen according to an embodiment of the present invention.

  The trigger condition is set by the PC 9 displaying the setting screen 91 in step S 2, causing the PC 9 to input each parameter to the user, and inputting the parameter input to the merging unit 1 by the PC 9. The setting screen 91 is an operation screen displayed by, for example, an output device included in the PC 9.

  The trigger condition is not limited to the setting on the setting screen 91. The trigger condition may be set by, for example, a UI (User Interface) by an input device or the like included in the merging unit 1 and a setting file.

  The trigger condition is set, for example, by parameters such as “trigger output setting”, “trigger output terminal”, “trigger output start condition”, and “number of trigger outputs” as illustrated in the setting screen 91. Hereinafter, a case where the trigger condition is set on the setting screen 91 will be described as an example.

  “Trigger output setting” is a parameter for switching whether or not the merging unit 1 outputs the trigger signal SIG2 when the trigger condition is satisfied. When “trigger output setting” is set as “valid” on the setting screen 91, the merging unit 1 is in a state of outputting the trigger signal SIG2 when the trigger condition is satisfied.

  The “trigger output terminal” is a parameter for designating an output terminal for outputting the trigger signal SIG2 by GUI (Graphical User Interface) such as a pull-down menu. The setting screen 91 is an example of setting in which the 1PPS output terminal functions as the trigger signal output terminal 1H12.

  The “trigger output start condition” is a parameter of a time condition for setting an output start time of the trigger signal SIG2. The output start time of the trigger signal SIG2 is a method of designating the time when the merging unit 1 starts the output of the trigger signal SIG2 by year, month, day, hour, minute and second (hereinafter referred to as absolute time), and after setting the merging unit 1 as a trigger signal It is a parameter set by a method or the like designated by a waiting time (hereinafter referred to as relative time) until the output of SIG2 is started. In the case of the relative time method, the relative time starts counting the waiting time after setting "trigger output setting" to "valid". For example, in the case of setting the relative time “3 seconds”, the merging unit 1 starts outputting the trigger signal SIG2 after a waiting time of 3 seconds after the trigger condition is set.

  The “trigger output start condition” is a parameter for setting the time at which the merging unit 1 starts sampling of the electric quantity. The “trigger output start condition” is a parameter that specifies an amount of electricity to start sampling from a plurality of amounts of electricity measured at a set time. A count value SmpCnt is set in the “trigger output start condition”. The count value SmpCnt is a value obtained by counting in the order of measurement among the electrical quantities measured at the time designated by the absolute time or the relative time. Based on the count value SmpCnt, the merging unit 1 specifies the amount of electricity to be sampled from a plurality of measured amounts of electricity.

  The “trigger output number” is a parameter for setting the number of times the merging unit 1 performs sampling based on the “trigger output start condition” and the number of times the trigger signal SIG2 is output. When the “number of trigger outputs” is 2 or more, the merging unit 1 samples a plurality of electric quantities among the plural electric quantities to be measured.

  FIG. 10 is a diagram for explaining an example of sampling of electric quantity according to an embodiment of the present invention.

  Hereinafter, in setting screen 91, “after 3 seconds” in “relative time designation” of “trigger output start condition” in merging unit 1, “5” in “count value” of “trigger output start condition”, and “trigger output” A case where the trigger condition of “one time” is set in “number of times” will be described as an example.

  The time TS for setting is a timing at which a parameter for which “trigger output setting” on the setting screen 91 is set to “valid” is input to the merging unit 1. When a trigger condition is set to merging unit 1 on setting screen 91 at time TS for setting, merging unit 1 sets a standby time after “3 seconds” specified in “relative time designation” of “trigger output start condition”. Start sampling of the electric quantity on the corresponding "2014/7/31 13:15:03".

  In the case of FIG. 10, the time corresponding to the time condition is one second of the time “2014/7/31 13:15:03” including 3 seconds after the waiting time set as the relative time from the time TS for setting is there.

  In the case of an absolute time, the time corresponding to the time condition is a time set as an absolute time, for example, one second of “2014/7/31 13:15:03” or the like.

  When the power supply system has an electrical quantity of 96 samples / cycle and the power supply system is 60 Hz, the electrical quantity of the power supply system is counted at count values of 0 to 5759 per second. When the power supply system has an electrical quantity of 96 samples / cycle and the power supply system is 50 Hz, the electrical quantity of the power supply system is counted at a count value of 0 to 4799 per second.

  FIG. 10 shows an example in the case where the power supply system has an electrical quantity of 96 samples / cycle and the power supply system is 50 Hz, and the count value SmpCnt is reset to “0” at every interval of absolute time. It is.

  In the case of FIG. 10, the merging unit 1 determines that the count value SmpCnt is “on” based on the trigger condition among the electrical quantities measured at the trigger output start time TG1 “2014/7/31 13:15:03” shown. The quantity of electricity that is “5” is sampled “once”.

  In step S404, the merging unit 1 outputs the output data D1 to CH2 of the oscilloscope 7. The merging unit 1 samples the quantity of electricity in step S402, and converts the quantity of electricity, stores the quantity of electricity and generates output data D1. The generated output data D1 is SV message data shown in FIG. The merging unit 1 stores the sampled electric quantity as sampling data in the APDU D 13 to generate SV message data.

  The merging unit 1 determines whether “the number of times of trigger output” set as the trigger condition and the number of times of output of the trigger signal SIG2 are equal. If “the number of times of trigger output” and the number of times of output of the trigger signal SIG2 are equal, the merging unit 1 ends the sampling and measurement of the processing time of the merging unit 1 and generates time data. If “the number of times of trigger output” and the number of times of output of the trigger signal SIG2 are not equal, the merging unit 1 repeats sampling and measurement of the processing time of the merging unit 1.

  In the case of FIG. 10, since the trigger condition “number of trigger outputs” is set to “1”, the merging unit 1 performs step S3 once.

  FIG. 11 is a diagram for explaining an example of the APDU configuration of the SV message according to an embodiment of the present invention.

  FIG. 11 is a diagram quoted from IEC 61850-9-2.

  The APDUD 13 includes, for example, count value data D131, sampling data D132, and the like.

  In the case of the trigger condition shown in FIG. 10, the APDU D 13 stores the value “5” set in the “count value” of the “trigger output start condition” in the count value data D131.

  In the case of the trigger condition shown in FIG. 10, the APDU D13 stores the amount of electricity sampled under the trigger condition shown in FIG. 10 in the sampling data D132.

  Since “count value” is stored in the count value data D131 of the APDU 13, the quantity of electricity to be sampled is specified by the “count value”. That is, the APDUD 13 stores the amount of electricity corresponding to the “count value” stored in the count value data D131 in the sampling data D132.

  In step S5, the oscilloscope 7 generates time data.

  In step S5, the oscilloscope 7 generates time data based on the processing time of the merging unit 1 measured in step S3.

  FIG. 12 is a diagram for explaining an example of calculation of the processing time of the merging unit according to the embodiment of the present invention.

  FIG. 12 is a diagram showing an example where the oscilloscope 7 shows in a waveform chart the trigger signal SIG2 input to CH1 of the oscilloscope 7 in step S301 as CH1 data DCH1.

  Similarly, FIG. 12 is a diagram showing an example of a case where the oscilloscope 7 shows in a waveform diagram the data signal of the output data D1 input to CH2 of the oscilloscope 7 in step S304 as CH2 data DCH2.

  An example of the processing time of the merging unit 1 calculated in step S307 will be described with reference to a waveform diagram shown by the oscilloscope 7. FIG.

  Based on the trigger signal SIG2 output from the merging unit 1 in step S407 and input to CH1 of the oscilloscope 7 in step S301, the input timing (hereinafter referred to as first timing) TG1 of the trigger signal SIG2 is output to the oscilloscope 7. Be explicit. The first timing corresponds to the time stored in step S303.

  The oscilloscope 7 outputs the SFD data D12 included in the output data D1 based on the first bit of the SFD data D12 output from the merging unit 1 in step S404 and input to CH2 of the oscilloscope 7 in step S304. The input timing of the first bit (hereinafter referred to as second timing) TG2 is specified. The oscilloscope 7 analyzes the data signal of the SV message output from the merging unit 1 and detects the first bit of the SFD data D12. The oscilloscope 7 sets the timing at which the first bit of the SFD data D12 is detected as the second timing TG2. The second timing corresponds to the time stored in step S306.

  The oscilloscope 7 calculates the processing time of the merging unit 1 in step S5 based on the first timing TG1 and the second timing TG2.

  In step S5, the oscilloscope 7 generates time data. The time data is data indicating the processing time of the merging unit 1. The time data may be a processing time T which is a time obtained by adding a delay time or the like by an analog filter to the processing time of the merging unit 1 instead of the processing time of the merging unit 1. In this case, the delay time or the like due to the analog filter is input to the oscilloscope 7 in advance by a user operation, for example. The oscilloscope 7 may use a time obtained by adding a delay time or the like by an analog filter to the processing time of the merging unit 1. Hereinafter, a case where the time data is data indicating the processing time of the merging unit 1 will be described as an example.

  In FIG. 12, the oscilloscope 7 displays time data DT1 indicating the processing time of the merging unit 1 measured in step S3. That is, in the case of FIG. 12, the oscilloscope 7 can clearly indicate the processing time of the merging unit 1 which is the time interval of the first timing TG1 and the second timing by displaying the time data DT1. The time data is not limited to data displayed by the oscilloscope 7 as shown in FIG. The time data may be stored in a file or the like as the processing time value of the merging unit 1 measured by the oscilloscope 7, for example, and the time data may be output by a file or the like in which the processing time of the merging unit 1 measured is stored. . The user can calculate the processing time T by adding a delay time or the like by an analog filter to the processing time of the merging unit 1 output by a file or the like.

  In the case of IEC61968-9, in the inspection, the inspection relating to the processing time T of the merging unit 1 is performed by checking whether the time obtained by adding the delay time due to the analog filter to the time data DT1 is 2 ms or less. be able to.

  The time data may be statistical data obtained by statistically processing the processing time of two or more merging units 1.

  FIG. 13 is a diagram illustrating an example of sampling two or more electric quantities according to an embodiment of the present invention.

  FIG. 13 is a diagram illustrating, as an example, a case where the power supply system has an electrical quantity of 96 samples / cycle and the power supply system is 50 Hz, as in FIG. 10.

  When the merging unit 1 samples a plurality of electrical quantities, the oscilloscope 7 calculates the processing time of the merging unit 1 with respect to each sampling for the sampling of the electrical quantities performed by the merging unit 1 a plurality of times, and the respective mergings calculated Statistical processing for calculating an average value of the processing time of the unit 1 is performed. When the merging unit 1 samples a plurality of electrical quantities, the merging unit 1 is set with a trigger condition shown in FIG. 13, for example. The trigger condition is set, for example, on the setting screen 91 shown in FIG. 9 as in the case of FIG. Hereinafter, a case where the sampling shown in FIG. 13 is set on the setting screen 91 will be described as an example. The target of statistical processing may be processing time T which is a time obtained by adding a delay time or the like by an analog filter to the processing time of merging unit 1 instead of the processing time of merging unit 1.

  FIG. 13 shows a case where the trigger output start time TTG designated by “absolute time designation” of the “trigger output start condition” on the setting screen 91 is set to “2014/7/31 13:15:03” in absolute time. It is. That is, in the case of FIG. 13, the amount of electricity measured by the merging unit 1 at the time of “2014/7/31 13:15:03” is to be sampled.

  FIG. 13 shows the case of setting a trigger condition where “count value” of “trigger output start condition” on the setting screen 91 is “0” and “trigger output frequency” is “4800 times”. When the power supply system has a quantity of electricity of 96 samples / cycle and the power supply system is 50 Hz, the quantity of electricity measured per second is 4800. That is, when the “count value” is set to “0” and the “number of trigger outputs” is set to “4800 times”, the merging unit 1 samples 4800 quantities of electricity measured in one second.

  In the case of the setting shown in FIG. 13, the merging unit 1 starts the process of step S3 from the trigger output start time TTG. The merging unit 1 performs the process of step S3 on the electric quantity whose measured count value SmpCnt is 0 to 4799, respectively.

  In step S406, when 4800 electric quantities are not sampled, the merging unit 1 determines that the trigger condition is satisfied (YES in step S406). Therefore, when the number of times the amount of electricity has been sampled is less than 4800, the merging unit 1 outputs the trigger signal SIG2 in step S407. Therefore, the oscilloscope 7 inputs the data signal of the trigger signal SIG2 output in step S407 and the SV message data output in step S404 corresponding to step S407 4800 times.

  In step S406, if 4800 electrical quantities are sampled, the merging unit 1 determines that the trigger condition is not satisfied (NO in step S406).

  In step S5, the oscilloscope 7 generates time data obtained by statistically processing the processing times of the plurality of merging units 1 measured in step S3. The time data is statistical data T2 which is a processing result obtained by statistically processing the processing time of the merging unit 1 for each sampling. In the case of FIG. 13, the oscilloscope 7 statistically processes the processing time of 4800 merging units 1. The statistical data T2 is data indicating at least one of the average value data DT21, the variance value data DT22, the minimum value data DT23, and the maximum value data DT24. The statistical data T2 may include a standard deviation value and so-called 3σ calculated from three times the standard deviation value.

  FIG. 14 is a diagram illustrating an example of statistical data according to an embodiment of the present invention.

  As shown, the oscilloscope 7 displays statistical data DT2 calculated by statistical processing, in addition to the time data DT1 shown in FIG. 12, for example.

  The oscilloscope 7 can clearly indicate the average value of the processing time of the merging unit 1 in one second from the average value data DT21 of the statistical data DT2. The oscilloscope 7 can clearly indicate a so-called worst value, which is the longest in processing time among processing times of the plurality of merging units 1 in one second, from the maximum value data DT24 of the statistical data DT2. In the case of IEC61968-9, in order to perform an inspection to check whether the average value of the processing time T and the worst value is 2 ms or less, in the inspection, the average value of the processing time of the merging unit 1 statistically processed is The user can check whether the average value and the worst value of the processing time T are 2 ms or less by adding a delay time by an analog filter.

  Further, the oscilloscope 7 can clearly show the variation in the processing time of the merging unit 1 from the difference between the dispersion value data DT22 or the minimum value data DT23 and the maximum value data DT24. Since the delay time or the like by the analog filter is a fixed value and it can be assumed that there is no variation, the variation of the processing time T can be judged from the variation of the processing time of the merging unit 1.

  A trigger condition is set in the merging unit 1. The merging unit 1 outputs a trigger signal SIG2 based on the set trigger condition.

  The merging unit 1 samples the amount of electricity and outputs output data D1. The merging unit 1 outputs the trigger signal SIG2 based on the trigger condition, and when the trigger condition is satisfied, the merging unit 1 samples the electric quantity at the timing of the trigger signal SIG2. Therefore, the merging unit 1 can clearly indicate the timing for sampling the electric quantity in the external device such as the oscilloscope 7 by the trigger signal SIG2 when the trigger condition is satisfied.

  In the oscilloscope 7 connected to the merging unit 1, the trigger signal SIG2 output from the merging unit 1 clearly indicates the timing at which the merging unit 1 samples the electric quantity when the trigger condition is satisfied. By analyzing the output data D1 output from the merging unit 1, the oscilloscope 7 connected to the merging unit 1 clearly indicates the timing at which the merging unit 1 transmits the predetermined data of the output data D1. The oscilloscope 7 can calculate the processing time of the merging unit 1 from the time difference between the two timings. A processing time T is calculated by adding a delay time by an analog filter to the processing time of the merging unit 1. Since the processing time of the merging unit 1 to be calculated is displayed as time data DT1, it is checked whether the merging unit 1 conforms to the standard such as IEC 61869-9 if a delay time or the like by the analog filter is added. be able to.

  Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications may be made within the scope of the present invention as set forth in the claims. , Change is possible.

100 merging unit test system 1 merging unit 1 H 1 input terminal 1 H 2 A / D converter 1 H 3 FPGA
1H4 CPU
1H5 LAN controller 1H6 network output terminal 1H7 trigger signal generation circuit 1H8 clock signal generator 1H9 switch 1H10 non-volatile memory 1H11 RAM
1H12 Trigger signal output terminal 1H13 Analog filter 1F1 Sampling unit 1F11 Filter unit 1F12 A / D conversion unit 1F13 Sampling control unit 1F2 Data output unit 1F21 Measurement value conversion unit 1F22 SV message data generation unit 1F3 Trigger signal output unit 1F4 Trigger condition setting unit 2 Current transformer 3 Transformer 4 LAN
41 switching hub 5 protection relay 6 circuit breaker control device 61 circuit breaker 7 oscilloscope 71 CH1 input terminal 72 CH2 input terminal 8 signal generator 9 PC
91 Setting screen D1 Output data D11 Preamble data D12 SFD data D13 APDU
D131 Count value data D132 Sampling data DCH1 CH1 data DCH2 CH2 data DT1 Time data DT2 Statistical data DT21 Average value data DT22 Distributed value data DT23 Minimum value data DT24 Maximum value data SIG1 Trip signal SIG2 Trigger signal TG1 Input timing of trigger signal SIG2 Timing)
TG2 Input timing of the first bit of the SFD data D12 included in the output data D1 (second timing)
I Current amount V Voltage amount T Processing time TS setting time TTG Trigger output start time TG1 Trigger output start time

Claims (9)

A merging unit that measures the amount of electricity in the power supply system,
A setting unit that sets a trigger condition that is a condition for sampling the electric quantity of the power supply system to be measured;
When the trigger condition is satisfied, a sampling unit that samples the measured electric quantity;
A data transmission unit that transmits output data generated based on the electrical quantity sampled by the sampling unit;
When the trigger condition is met, it possesses a signal output section for outputting a trigger signal to an external device,
The setting unit is a merging unit that sets, as the trigger condition, a time condition including a time when the trigger signal is output and a time when the electric quantity of the power supply system to be measured is sampled .   A merging unit that measures the amount of electricity in the power supply system,
  A setting unit for setting a trigger condition which is a condition for sampling the amount of electricity of the power supply system to be measured;
  When the trigger condition is satisfied, a sampling unit that samples the measured electric quantity;
  A data transmission unit for transmitting output data generated based on the quantity of electricity sampled by the sampling unit;
  A signal output unit that outputs a trigger signal to an external device when the trigger condition is satisfied;
Have
  The setting unit includes, as the trigger condition, a time condition including a waiting time from setting the trigger condition to outputting the trigger signal, and a waiting time until sampling the electric quantity of the power system to be measured. Set
The merging unit. The setting unit samples, as the trigger condition, the time condition and the amount of electricity of the plurality of power supply systems measured at a time corresponding to the time condition by a count value for counting the amount of electricity. The merging unit according to claim 1 or 2 , wherein a count value condition for specifying an electric quantity is set. A merging unit test system comprising: a merging unit that measures an amount of electricity of a power supply system; and an oscilloscope connected to the merging unit,
A setting unit that sets a trigger condition that is a condition for sampling the electric quantity of the power supply system to be measured;
When the trigger condition is satisfied, a sampling unit that samples the measured electric quantity;
A data transmission unit for transmitting output data generated based on the electrical quantity sampled by the sampling unit to the oscilloscope;
The merging unit having a signal output unit that outputs a trigger signal to the oscilloscope when the trigger condition is satisfied;
A time calculation unit that calculates a time interval between the time when the data transmission unit transmits predetermined data included in the output data and the time when the signal output unit outputs the trigger signal;
Have a said oscilloscope and a time data generator for generating time data based on said time interval,
The merging unit test system , wherein the setting unit sets a time condition including a time when the trigger signal is output and a time when the electric quantity of the measured power supply system is sampled as the trigger condition .   A merging unit test system having a merging unit for measuring an electric quantity of a power supply system, and an oscilloscope connected to the merging unit,
  A setting unit for setting a trigger condition which is a condition for sampling the amount of electricity of the power supply system to be measured;
  When the trigger condition is satisfied, a sampling unit that samples the measured electric quantity;
  A data transmission unit for transmitting output data generated based on the quantity of electricity sampled by the sampling unit to the oscilloscope;
  A signal output unit for outputting a trigger signal to the oscilloscope when the trigger condition is satisfied;
Said merging unit having
  A time calculation unit that calculates a time interval between the time when the data transmission unit transmits predetermined data included in the output data and the time when the signal output unit outputs the trigger signal;
  A time data generation unit for generating time data based on the time interval;
With the oscilloscope with
Have
  The setting unit includes, as the trigger condition, a time condition including a waiting time from setting the trigger condition to outputting the trigger signal, and a waiting time until sampling the electric quantity of the power system to be measured. Merge unit test system to set up. The time calculation unit calculates a plurality of the time intervals,
The merging unit test system according to claim 4 or 5 , wherein the time data generation unit generates statistical data generated by performing statistical processing on the plurality of time intervals calculated by the time calculation unit as the time data. The statistical data includes at least one of an average value of the plurality of time intervals, a maximum value of the plurality of time intervals, a minimum value of the plurality of time intervals, and a variance value of the plurality of time intervals. The merging unit test system according to claim 6 , wherein the merging unit test system includes data. A trigger signal output method performed by a merging unit that measures the amount of electricity in a power supply system,
A setting procedure for setting a trigger condition which is a condition for sampling the electric quantity of the power supply system to be measured by the merging unit;
A sampling procedure in which the merging unit samples the electric quantity to be measured when the trigger condition is satisfied;
A data transmission procedure in which the merging unit transmits output data generated based on the amount of electricity sampled in the sampling procedure;
The merging unit, when the trigger condition is met, have row and a signal output procedure to output a trigger signal to an external device,
The trigger signal output method , wherein in the setting procedure, a time condition including a time at which the trigger signal is output and a time at which the measured electric quantity of the power supply system is sampled is set as the trigger condition .   A trigger signal output method performed by a merging unit that measures the amount of electricity in a power supply system,
  The merging unit sets a trigger condition that is a condition for sampling the amount of electricity of the power supply system to be measured; and
  A sampling procedure in which the merging unit samples the measured electrical quantity when the trigger condition is satisfied;
  A data transmission procedure in which the merging unit transmits output data generated based on the quantity of electricity sampled in the sampling procedure;
  The merging unit outputs a trigger signal to an external device when the trigger condition is satisfied;
Do,
  In the setting procedure, as the trigger condition, a time condition including a waiting time from setting the trigger condition to outputting the trigger signal and a waiting time until sampling the electric quantity of the power system to be measured Set
Trigger signal output method.

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