JP6537322B2 - Power supply device and image forming apparatus - Google Patents

Description

  The present invention relates to a power supply apparatus and an image forming apparatus, and more particularly to a switching power supply apparatus having a burst mode in which switching operation is stopped for a fixed period in a medium load state and a light load state.

  There is known a switching power supply device that controls an output voltage using an IC as a low voltage power supply of an electronic device. In recent years, there is a trend to further reduce the power consumption at the time of operation standby of the electronic device, and it is also required to reduce the power consumption of the switching power supply itself. As a configuration for reducing the power consumption of the switching power supply device, for example, a configuration as disclosed in Patent Document 1 has been proposed. In the conventional switching power supply device, the voltage level of the feedback terminal is made variable according to the load state on the output side, and the switching operation is controlled to extend the off period by shortening the on period of the switching power supply at light load. There is. Hereinafter, such switching operation is referred to as burst operation. The operating state of the switching power supply device includes a heavy load state, a medium load state, and a light load state. In order to reduce power consumption in the medium load state, it is effective to perform a burst operation. FIG. 6 shows the configuration of a general switching power supply device in each load state. 7 is a diagram showing an operation waveform at heavy load of the switching power supply device shown in FIG. 6, and FIG. 8 is a diagram showing an operation state at heavy load of the switching power supply device shown in FIG. Fig.9 (a) is a figure which shows the operation state at the time of medium load of the switching power supply device shown in FIG. 6, FIG.9 (b) is a figure which shows the operation state at the time of light load of the switching power supply device shown in FIG. is there. The detailed description of these will be described later.

  In the switching power supply device of FIG. 6, when the operating state of the switching power supply device is the medium load state (FIG. 9A), control to forcibly stop the switching operation of the FET 105, that is, burst operation is performed. . Thereby, the loss due to the switching of the FET 105 can be reduced, and the power consumption of the device can be reduced. However, when the burst operation is performed at medium load, the ripple voltage of the output voltage may be increased. For this reason, a pulse width limited power supply device shown in FIG. 10 has been proposed (see, for example, Patent Document 2). Operation waveforms of the pulse width limited power supply of FIG. 10 are shown in FIG. The details of FIGS. 10 and 11 will be described later. In the pulse width limited power supply device shown in FIG. 10, the ripple voltage of the output voltage at medium load is reduced without increasing the power consumption at light load by adding the pulse width limiter 305 and the reference voltage 306. be able to.

JP 2008-245419 A JP, 2014-225131, A

  However, in the pulse width limited power supply device shown in FIG. 10, when the load current fluctuates rapidly, the ripple voltage of the output voltage may increase depending on the current value after the fluctuation. FIG. 12 shows an operation waveform when the load current fluctuates rapidly. The details of FIG. 12 will be described later. In the pulse width limited power supply of FIG. 10, a load current such that the convergence voltage Vfb_f approaches the reference voltage 304 is always present regardless of the output capacity of the switching power supply. Therefore, the device to which the power supply device is applied needs to cope with the load current such that the convergence voltage Vfb_f does not become close to the reference voltage 304, which may complicate the device design.

  The present invention has been made under such circumstances, and in a switching power supply device that limits the pulse width when switching elements are on at light load and medium load, ripples that occur due to fluctuations in load current. The purpose is to suppress an increase in voltage.

  In order to solve the problems described above, the present invention comprises the following configuration.

  (1) A transformer in which the primary side and the secondary side are insulated, a switching element for performing a switching operation to turn on and off the current flowing to the primary side of the transformer, and the output voltage on the secondary side of the transformer Power supply comprising: feedback means for feeding back a feedback voltage to the primary side of the transformer; and limiting means for limiting the on width of a pulse signal for turning on the switching element based on the feedback voltage fed back by the feedback means An apparatus, wherein the second state is changed to a first time when transitioning from a first state in which the on-width is restricted by the restricting means to a second state in which the on-width is released from restriction A power supply device comprising control means for controlling to maintain.

  (2) An image forming apparatus comprising: an image forming unit for forming an image on a recording material; and the power supply device according to (1) for supplying power to the image forming unit.

  According to the present invention, it is possible to suppress an increase in ripple voltage generated due to fluctuation of load current in a switching power supply in which the pulse width of the switching element when ON at light load and medium load is limited.

The figure which shows the structure of the switching power supply device of Example 1. The figure which shows the operating waveform of the switching power supply device of Example 1. The figure which shows the structure of the switching power supply device of Example 2. The figure which shows the operating waveform of the switching power supply device of Example 2. FIG. 6 shows the configuration of an image forming apparatus according to a third embodiment. A diagram showing a configuration of a conventional switching power supply device Diagram showing operation waveforms of the conventional switching power supply device Diagram showing the state under heavy load of the conventional switching power supply device Diagram showing the state of medium load and light load of the conventional switching power supply device A diagram showing a configuration of a conventional pulse width limited power supply device Diagram showing the operation waveform of the conventional pulse width limited power supply Diagram showing an operation waveform at load fluctuation of the pulse width limited power supply of the prior art example

  Hereinafter, the best mode for carrying out the present invention will be described in detail by way of examples.

[Summary of Power Supply]
First, for comparison with the following embodiments, the circuit configuration and operation of a conventional switching power supply device will be described with reference to FIG. FIG. 6 is a circuit diagram showing a circuit configuration of a flyback type switching power supply device. In FIG. 6, the AC voltage input from the commercial AC power supply Vac10 is full-wave rectified through the diode bridge 11, smoothed by the primary electrolytic capacitor 101, and the primary electrolytic capacitor 101 is charged with a substantially constant DC voltage Vh. Be done. Then, the DC voltage Vh is supplied to a start terminal (hereinafter referred to as a VH terminal) 103h of the power supply IC 103, and the power supply IC 103 is started. The power supply IC 103 is an IC that controls the on / off state of a field effect transistor (FET) 105 (hereinafter referred to as “FET 105”), which is a switching element performing a switching operation. In addition to the primary winding 104p of the number of turns Np and the secondary winding 104s of the number of turns Ns, an auxiliary winding 104h of the number of turns Nh is wound around the isolation transformer 104 (hereinafter referred to as the transformer 104). The secondary winding 104s is configured such that the winding direction is reverse to the primary winding 104p (so-called flyback coupling), and the auxiliary winding 104h is similarly reverse to the primary winding 104p in the winding direction. It is configured to be a direction.

  The power supply IC 103 has terminals of VCC (103 c), GND (103 g), OUT (103 o), VH (103 h), IS (103 i), FB (103 f), and BTM (103 b). The reference numerals in parentheses indicate the terminals of the power supply IC 103. A DC voltage rectified and smoothed by the diode 111 and voltage 113 of the voltage V104h induced in the auxiliary winding 104h is input as a voltage for driving the power supply IC 103 via the resistor 112 to the VCC terminal 103c which is a power supply input terminal. Ru. The ground potential is input to the GND terminal 103g. The OUT terminal 103o is connected to the gate terminal of the FET 105, and controls the on / off state of the FET 105 by outputting a high level and a low level. Hereinafter, the high level is referred to as the H level, and the low level is referred to as the L level. The VH terminal 103 h is a high voltage terminal. When the input voltage to the VCC terminal 103c of the power supply IC 103 is low, such as at the start of the power supply device, the necessary voltage is supplied from the start circuit 301 inside the power supply IC 103 by the DC voltage Vh input to the VH terminal 103h. The IC 103 starts an operation at startup. The timing at which the power supply IC 103 switches the FET 105 from the on state to the off state is determined based on the input voltage of the IS terminal 103i (hereinafter referred to as IS terminal voltage) Vis and the input voltage of the FB terminal 103f (hereinafter referred to as FB terminal voltage) Vfb Be done.

  The voltage induced in the secondary winding 104s of the transformer 104 is rectified and smoothed by the rectifying diode 121 and the smoothing capacitor 122, and is output as a DC output voltage Vout. The shunt regulator 127 becomes conductive / nonconductive based on the output voltage Vout of the transformer 104. A voltage obtained by dividing the output voltage Vout on the secondary side of the transformer 104 by the resistors 123 and 124 is input to the reference (R) terminal of the shunt regulator 127. If the input voltage to the reference (R) terminal is higher than a predetermined voltage, the shunt regulator 127 becomes conductive, and the current input from the K (cathode) terminal flows to the A (anode) terminal, and vice versa If it is lower than a predetermined voltage, it becomes nonconductive. When the shunt regulator 127 becomes conductive, a current flows through the LED of the photocoupler 109, which is feedback means provided on the secondary side of the transformer 104, through the resistor 128, and the LED emits light. The on / off state of the phototransistor of the photocoupler 109 on the primary side of the transformer 104 is controlled depending on whether the LED of the photocoupler 109 emits light. The phototransistor of the photocoupler 109 is connected to the FB terminal 103 f of the power supply IC 103, and a feedback voltage that is a voltage proportional to the output voltage Vout on the secondary side of the transformer 104 is input.

  Further, to the IS terminal 103i of the power supply IC 103, a voltage generated at both ends of the current detection resistor 106 which is detection means is inputted by the current flowing through the primary winding 104p of the transformer 104. A voltage (hereinafter referred to as a BTM terminal voltage Vnh) according to the voltage V104h induced in the auxiliary winding 104h is input to the BTM terminal 103b of the power supply IC 103. The power supply IC 103 detects the end of regeneration of the transformer 104 from the voltage input to the BTM terminal 103 b, and determines the timing at which the FET 105 is switched from the off state to the on state.

[Heavy load operation]
Next, the operation under heavy load of the power supply device of FIG. 6 will be described with reference to FIG. 7 (i) shows the OUT terminal voltage of the power supply IC 103, FIG. 7 (ii) shows the drain-source voltage Vds of the FET 105, and FIG. 7 (iii) shows the drain current Id of the FET 105. 7 (iv) shows the feedback (hereinafter referred to as FB) terminal voltage Vfb of the power supply IC 103, FIG. 7 (v) shows the IS terminal voltage Vis of the power supply IC 103, and FIG. 7 (vi) shows the BTM terminal voltage Vnh of the power supply IC 103. . The horizontal axis represents time, and t10, t12, t14, t16, t18, t20, t22, t24, and t26 indicate periods, and t11, t13, t15, t17, t19, t21, t23, and t25 indicate time timings (hereinafter referred to as "time"). Show the timing).

  In FIG. 6, an AC voltage input from a commercial AC power supply Vac10 is rectified by a diode bridge 11, smoothed by a primary electrolytic capacitor 101, and a substantially constant DC voltage Vh is generated. On the other hand, the DC voltage Vh is supplied to the VH terminal 103 h for activating the power supply IC 103 via the resistor 102, and the power supply IC 103 is activated by the activation circuit 301 to turn on the FET 105. Then, the drain current Id flows in the FET 105 through the primary winding 104p on the primary side of the transformer 104 in which the primary side and the secondary side are isolated (period t10 of FIG. 7 (iii)). In the period t10, the drain current Id linearly rises with the passage of time. The drain current Id is converted into the IS terminal voltage Vis by the current detection resistor 106, and is input to the IS terminal 103 i for current detection of the power supply IC 103.

  On the other hand, the FB terminal voltage Vfb, which is a feedback voltage, is input to the FB (feedback) terminal 103f of the power supply IC 103 via the photocoupler 109 for feeding back the voltage from the secondary side to the primary side of the transformer 104. . The FB terminal voltage Vfb is an error amplification signal of the output voltage Vout, and decreases when the output voltage Vout is larger than a specified value, and increases when the output voltage Vout is smaller than the specified value. The power supply IC 103 turns off the FET 105 when the IS terminal voltage Vis rises and becomes larger than the FB terminal voltage Vfb (timing t11 in FIG. 7 (iv) and FIG. 7 (v)). When the FET 105 is turned off, the drain current Id instantaneously becomes zero. Then, the voltage Vds between the drain terminal and the source terminal of the FET 105 rises and becomes a substantially constant voltage (period t12 of FIG. 7 (ii)).

  After the FET 105 is turned off (period t12 in FIG. 7I), a positive pulse voltage is induced in the secondary winding 104s and the auxiliary winding 104h. The pulse voltage induced in the secondary winding 104 s is rectified and smoothed by the rectifying diode 121 and the smoothing capacitor 122 to become a substantially constant output voltage Vout.

  While the pulse voltage is induced in the secondary winding 104s, the current If flowing in the secondary winding 104s linearly decreases and eventually becomes zero. Then, the voltage Vds between the drain terminal and the source terminal of the FET 105 starts to fall. The voltage Vds between the drain terminal and the source terminal of the FET 105 is similar to the terminal voltage V104h of the auxiliary winding 104h. The BTM terminal 103b of the power supply IC 103 is supplied with the BTM terminal voltage Vnh corresponding to the terminal voltage V104h of the auxiliary winding 104h. The power supply IC 103 detects that the BTM terminal voltage Vnh has fallen to 0 volt at the falling edge, and turns on the FET 105 (timing t13 of FIG. 7I). When the FET 105 is turned on again at timing t13 in FIG. 7, the drain current Id flows through the FET 105 again through the primary winding 104p of the transformer 104, and the operation in the periods t10 and t12 is repeated after the period t14.

  FIG. 8 is a diagram showing a continuous operation state of the power supply device of FIG. 6 under heavy load. More specifically, FIG. 8 (i) shows the output voltage Vout, FIG. 8 (ii) shows the FB terminal voltage Vfb of the power supply IC 103, and FIG. 8 (iii) shows a switching pulse (a pulse signal outputted from the OUT terminal 103o of the power supply IC 103). And the horizontal axis shows time. The reference voltage 304 in the drawing indicates the reference voltage 304 of the load state determination unit 303 of the power supply IC 103 described later. By the above-described operation, as shown in FIG. 8 under heavy load, the FET 105 continuously oscillates, so that switching pulses are continuously output, the FB terminal voltage Vfb exceeds the reference voltage 304, and the output voltage Vout is The condition maintained at the specified value is continued.

[Overview of Power Supply IC Operation]
Next, the operation of the power supply IC 103 will be described. First, the operation of the power supply IC 103 under heavy load shown in FIG. 8 will be described with reference to the internal block diagram of the power supply IC 103 shown in FIG. 6 and FIG.

  In FIG. 6, the IS terminal voltage Vis input to the IS terminal 103i and the FB terminal voltage Vfb input to the FB terminal 103f are compared by the comparator 302c of the pulse width determination unit 302 for determining the drive time of the FET 105. Be compared. As shown in FIG. 7, in the state where the FET 105 is turned on, since the FB terminal voltage Vfb> IS terminal voltage Vis, the comparison unit 302 c outputs the L level. Therefore, the input of the reset (R) terminal (hereinafter referred to as R terminal) of the set / reset flip flop 310 (hereinafter referred to simply as FF 310), which is the switching control means, provided at the subsequent stage of the pulse width determination unit 302 is L level. It becomes. As a result, the output of the Q terminal of the FF 310 (hereinafter referred to as Q output) maintains the H level which is the output state up to that point. The Q terminal is connected to the OUT terminal 103o of the power supply IC 103, and the Q output is input to the FET 105 via the gate resistor 107 as the gate voltage Vg of the FET 105, and the FET 105 maintains the on state (FIG. 7 (i) Period t10).

  At the point when the IS terminal voltage Vis rises and becomes slightly higher than the FB terminal voltage Vfb with the rise of the drain current Id of the FET 105 (the timing t11 in FIG. 7 (iv) and (v)), The output of the comparator 302c of 302 goes from L level to H level. As a result, since a signal at H level is input to the R terminal of the FF 310, the FF 310 is reset, the Q output changes from H level to L level, the output from the OUT terminal 103o becomes L level, and the FET 105 is turned off (see FIG. 7 (i) timing t11).

  Thereafter, when the current If flowing through the secondary winding 104s decreases to 0, the terminal voltage V104h of the auxiliary winding 104h decreases and becomes a negative voltage. A voltage corresponding to the terminal voltage V104h of the auxiliary winding 104h is input to the BTM terminal 103b as the BTM terminal voltage Vnh. When the BTM terminal voltage Vnh is a falling edge and becomes 0 volt (at timing t13 in FIG. 7 (vi)), the output of the bottom detection circuit 307 of the power supply IC 103 is inverted from the previous L level to H level And then H level is maintained.

  The H level output from the bottom detection circuit 307 is input to one input terminal of an AND circuit (hereinafter referred to as an AND circuit) 309. The output of the load state determination unit 303 is input to the other input terminal of the AND circuit 309. As described later, load state determination unit 303 compares FB terminal voltage Vfb with reference voltage 304, and outputs H level if FB terminal voltage Vfb is higher and L level if FB terminal voltage Vfb is lower. Output As shown in FIG. 8, since the FB terminal voltage Vfb is higher than the reference voltage 304 under heavy load, the output of the load state determination unit 303 always becomes H level, and as a result, the output of the AND circuit 309 becomes H level. The FF 310 is set by inputting an H level signal to the set (S) terminal (hereinafter referred to as the S terminal) of the FF 310, and the output of the Q terminal becomes H level. As a result, the H level is output from the OUT terminal 103o, and the FET 105 is turned on (period t14 of FIG. 7I). The output of the bottom detection circuit 307 is reset when the output of the comparison unit 302c of the pulse width determination unit 302 becomes H level, that is, when the IS terminal voltage Vis becomes slightly higher than the FB terminal voltage Vfb, It becomes L level (timing t15 of FIG. 7).

[Overview of operation at medium load]
Next, an operation at a medium load of the switching power supply apparatus, that is, when the load is smaller than that at the heavy load described above will be described. Fig.9 (a) is a figure which shows the continuous operation state at the time of the medium load of a power supply device, and Fig.9 (a) (i)-FIG.9 (a) (iii) are FIG. Since this corresponds to 8 (iii), duplicate explanations will be omitted. Further, in the horizontal axis, t101, t103, t105, t107, t109, and t111 indicate periods, and t100, t102, t104, t106, t108, t110, and t112 indicate time timing (hereinafter referred to as timing). In FIG. 9A showing the operating state at medium load, there are periods (for example, periods t101, t105, t109) in which the switching pulse of the FET 105 is stopped, as compared with the state of FIG. 8 at heavy load.

  In the case of a medium load as shown in FIG. 9A, when the operations of periods t10 and t12 of FIG. 7 are repeated, the power supplied to the secondary side through the transformer 104 is the power consumed on the secondary side. It becomes bigger than. Therefore, the FB terminal voltage Vfb falls below the reference voltage 304 (period t105 of FIG. 9A, etc.), and the output of the load state determination unit 303 of the power supply IC 103 becomes L level. The output of load state determination unit 303 is input to AND circuit 309, and while the output of load state determination unit 303 is at L level, the output of AND circuit 309 is L regardless of the output level of bottom detection circuit 307. The Q output of the FF 310 maintains the L level. Therefore, a signal at L level is output from the OUT terminal 103o, and the FET 105 continues to be in the off state (period t105 in FIG. 9A, and the like). At this time, in period t105, the power supply to the secondary side via the transformer 104 is temporarily stopped.

  When the current If flowing through the secondary winding 104s becomes 0 while the FET 105 continues the off state, the output to the AND circuit 309 of the bottom detection circuit 307 becomes H level (timing in FIG. 7). t13). Since the power supply to the secondary side of the transformer 104 is temporarily stopped, the FB terminal voltage Vfb rises gently. Then, when the FB terminal voltage Vfb exceeds the reference voltage 304 which is the stop voltage of the switching pulse, the output of the load state determination unit 303 changes from L level to H level (timing t106 of FIG. 9A). As a result, the output of the AND circuit 309 becomes H level, and when the input to the S terminal becomes H level, the Q output of the FF 310 becomes H level. Further, at this time, since the FET 105 continues to be in the off state, the relationship between the FB terminal voltage Vfb and the IS terminal voltage Vis is Vfb> Vis. However, when the Q output of the FF 310 becomes H level, the output from the OUT terminal 103 o becomes H level, and as a result, the FET 105 is turned on. Then, the switching operation in the periods t10 and t12 (FIG. 7) is repeated until the FB terminal voltage Vfb becomes lower than the reference voltage 304 which is the stop voltage of the switching pulse again (period t107 in FIG. 9A). As described above, at medium load, control to forcibly stop the switching operation of the FET 105 (so-called burst operation) is performed. Thereby, the loss due to the switching of the FET 105 can be reduced, and the power consumption of the device can be reduced.

[Operation at light load]
Next, the operation at light load will be described. Recently, there is a strong demand for reduction of standby power of electronic devices, and in a power supply device, power consumption at light load corresponds to standby power. FIGS. 9 (b) (i) to 9 (b) (iii) are diagrams showing the continuous operation state of the power supply device under light load, corresponding to FIGS. 8 (i) to 8 (iii) Therefore, duplicate explanations are omitted. In the horizontal axis, t201, t203, t205, t207 and t209 indicate periods, and t200, t202, t204, t206, t208 and t210 indicate time timing (hereinafter referred to as timing).

  In the light load state shown in FIG. 9B, the period (time width) in which the FET 105 is forcibly turned off as in the period t203 is the period t105 in the medium load state shown in FIG. It will be longer than the time width). This is because at light load, the load current on the secondary side of the transformer 104 is smaller than at medium load, and the drop in output voltage is gradual. Further, since the power consumption on the secondary side of the transformer 104 is smaller than that at the medium load, the period t201 in which the FET 105 is on during the light load is the medium load shown in FIG. 9A. It is shorter than the period t103. Further, the number of ONs per unit time of the FET 105 at light load is also smaller than the number of ONs at medium load. Furthermore, the time of one pulse output to the FET 105 at light load is also shorter than the time of one pulse at medium load. Although the time difference between the period t105 and the period t203 varies depending on the load current, in the case of a load state equivalent to the above-described standby power, the relationship of the period t105 <the period t203 is obtained.

As described above, the frequency Fbst_low of the burst operation at the light load is lower than the frequency Fbst_mid of the burst operation at the medium load, and the loss due to the switching of the FET 105 can be reduced to further reduce the power consumption of the device. it can. Therefore, the relationship of the following equation (1) generally holds for the frequency Fbst_mid of the burst operation at medium load and the frequency Fbst_low of the burst operation at light load.
Fbst_mid> Fbst_low (1)

[Relationship between output load condition, pulse width of FET and number of switching]
Next, the relationship between the output load condition, the pulse width of the FET 105, and the number of times of switching will be described. As described above, in order to reduce power consumption at light load, it is also important to reduce the number of switchings in addition to reducing the switching frequency of the FET 105. This is because when the number of times of switching of the FET 105 is increased, switching loss generated when the FET 105 is turned on is increased, and power consumption is increased.

  Further, the power supply IC 103 determines the number of continuous switchings by comparing the FB terminal voltage Vfb with the reference voltage 304 which is the stop voltage of the switching pulse. Furthermore, the power supply IC 103 determines the pulse width of the switching pulse of the FET 105 by comparing the IS terminal voltage Vis input to the IS terminal 103i with the FB terminal voltage Vfb input to the FB terminal 103f. That is, since the number of continuous switchings is continued until the FB terminal voltage Vfb becomes lower than the reference voltage 304, the number of switchings increases as the load current increases.

Therefore, the relationship of the following formula (2) generally holds for the continuous switching number Sbst_nm in the burst operation at medium load and the continuous switching number Sbst_nl in the burst operation at light load.
Sbst_nm> Sbst_nl (2)

Further, from the above, it is also understood that the number of switching times of the FET 105 per unit time is as follows. That is, the following equation (3) holds for continuous switching number Snh in continuous switching operation under heavy load, continuous switching number Snm in burst operation under medium load, and continuous switching number Snl in burst operation under light load .
Snh>Snm> Snl (3)

Furthermore, the larger the difference between the IS terminal voltage Vis and the FB terminal voltage Vfb, the longer the on pulse width of the switching pulse for turning on the FET 105, and the larger the load current, the longer it becomes. However, depending on conditions such as the response of the feedback loop, the maximum pulse width at heavy load and at medium load may be equal. That is, for the maximum pulse width PWh_Max at heavy load, the maximum pulse width PWm_Max at medium load, and the maximum pulse width PWl_Max at light load of the switching pulse of the FET 105, the relationship of the following equation (4) generally holds.
PWh_Max PW PWm_Max> PWl_Max (4)

[Problem about output ripple]
As described above, in the power supply apparatus, in order to reduce power consumption not only at light load but also at medium load, it is required to increase the pulse width when the FET 105 is on and to reduce the number of switchings. Further, the power supply IC 103 compares the IS terminal voltage Vis input to the IS terminal 103i with the FB terminal voltage Vfb input to the FB terminal 103f by the comparison unit 302c of the pulse width determination unit 302, and based on the result The on time of the FET 105 is determined. In the switching power supply, in the load area immediately before the transition from switching operation at medium load to switching operation at heavy load, although the load current is relatively large, the burst operation is performed and the output ripple becomes large. . That is, the output ripple becomes large in the transition period of the operating state from the medium load to the heavy load.

  Since the load current is relatively large during the medium load shown in FIG. 9A described above, the change in the output voltage and the FB terminal voltage in the off period of the FET 105 (the period of forced off in the burst operation) is also large. Therefore, the pulse width of the ON of the FET 105 determined by the comparison unit 302c also becomes long. When the pulse width when the FET 105 is on is long, the instantaneous power transmitted to the secondary side via the transformer 104 is also large, and the output voltage during the on period of the FET 105 and the change in the FB terminal voltage Vfb are also large. Ripple voltage increases.

  Further, as described above, from the recent trend of reducing power consumption, the frequency Fbst_low of the burst operation at light load and the frequency Fbst_mid of the burst operation at medium load tend to be lower than before. Therefore, when the frequency Fbst_mid of the burst operation becomes lower, the off period of the FET 105 and the pulse width at the time of ON of the FET 105 become longer, and the phenomenon that the ripple voltage of the output voltage becomes larger tends to be more prominent. There is a trade-off between reducing power consumption in the switching power supply and increasing the ripple voltage of the output voltage, and the ripple voltage of the output voltage in switching power supplies today that places importance on reducing power consumption. Tends to increase.

[Summary of Pulse Width Limited Power Supply]
In the above-described burst operation, it is known that ripples of the output voltage occur at light and medium loads. In order to reduce this ripple, it is effective to perform control to limit the pulse width of the switching pulse when turning on a switching element (for example, a field effect transistor or the like). The circuit configuration and operation of a switching power supply (hereinafter also referred to as a pulse width limited power supply) in which the on pulse width of the switching element is limited will be described below.

[Circuit configuration]
FIG. 10 is a circuit diagram showing a circuit configuration of the pulse width limited power supply device. The circuit configuration similar to that of the switching power supply device shown in FIG. The pulse width limited power supply device shown in FIG. 10 has a configuration in which a pulse width limiting unit 305 which is limiting means and a reference voltage 306 are added to the switching power supply device described in FIG. The pulse width limiting unit 305 determines the drive pulse time of the FET 105 which is a switching element, that is, the on width of the pulse signal which is the time during which the FET 105 is on. Further, the reference voltage 306 is used for determination to limit the upper limit of the drive pulse time of the switching element FET 105.

First, the magnitude relation between the reference voltage 304 which is the first voltage and the reference voltage 306 which is the second voltage has the relationship shown by the following equation (5) in order to make the pulse width limiting section 305 have hysteresis characteristics. Become.
Reference voltage 306> Reference voltage 304 (5)

  The pulse width limiting unit 305 includes a pulse width limitation determination unit 305a, a mask signal generation unit 305b, a timer 305c, and an OR circuit (hereinafter referred to as an OR circuit) 305d. The output of the pulse width limiting unit 305 is input to the R terminal of the FF 310 and the bottom detection circuit 307. The pulse width limiting unit 305 is determined by (a) pulse width limitation, determination of limitation release, (b) measurement of duration of H level output of Q output of the FF 310 by the timer, (c) (a), (b) (D) the mask signal, and the final output from the comparing unit 302c.

  First, for (a), the pulse width limit determination unit 305a compares the FB terminal voltage Vfb input to the FB terminal 103f, the reference voltage 304, and the reference voltage 306, and limits and limits the pulse width based on the comparison result. Determine the release. Specifically, when the FB terminal voltage Vfb becomes lower than the reference voltage 304, the pulse width limit determination unit 305a outputs an H level to the mask signal generation unit 305b to limit the pulse width. On the other hand, when the FB terminal voltage Vfb becomes higher than the reference voltage 306, the pulse width limit determination unit 305a outputs L level to the mask signal generation unit 305b to release the pulse width limit. When the FB terminal voltage Vfb is higher than the reference voltage 304 and lower than the reference voltage 306, the pulse width limit determination unit 305a holds the previous state.

  (B) is performed only when the output of the pulse width limit determination unit 305a is at the H level. That is, when the output of the pulse width limit determination unit 305a is H level, when the Q output of the FF 310 becomes H level, the mask signal generation unit 305b starts the timer 305c, and the Q output of the FF 310 continues H level. Start measuring time When the output of the pulse width limitation determination unit 305a is L level (when the limitation of the pulse width is released) or the Q output of the FF 310 is L level (the FET 105 is in the off state), time measurement is not performed.

  The generation of the mask signal in (c) is performed by the mask signal generation unit 305b, and the comparison result between the FB terminal voltage Vfb and the IS terminal voltage Vis by the comparison unit 302c is valid (mask release state) or invalid (mask state To decide. Here, when the value of the timer 305c according to (b) is less than the predetermined value, the mask is released, and the mask signal generation unit 305b outputs L level, and when the value of the timer 305c according to (b) is more than the predetermined value. In the mask state, the mask signal generation unit 305 b outputs the H level.

  For (d), the pulse width determination unit 302 outputs a signal to the R terminal of the FF 310. Here, using the OR circuit 305d, the OR circuit 305d outputs the H level when the output of the mask signal generation unit 305b according to (c) or the output of the comparison unit 302c is in the H level state. If the output of the mask signal generation unit 305b is H level, the output to the R terminal of the FF 310 of the OR circuit 305d becomes H level even if the output of the comparison unit 302c is L level. As described above, the pulse width determination unit 302 performs the above-described operation, whereby the ON pulse width limiting operation of the FET 105 having hysteresis characteristics is performed.

[Operation at medium load]
The feature of the pulse width limited power supply is the operation at medium load, and the operation at medium load will be described in association with the operation waveform of FIG. FIG. 11 is a diagram showing a continuous operation state at medium load of the pulse width limited power supply. 11 (i) shows the current waveform of the load current flowing from the pulse width limited power supply to the load, FIG. 11 (ii) shows the voltage waveform of the output voltage Vout, and FIG. 11 (iii) shows the voltage waveform of the FB terminal voltage Vfb. . FIG. 11 (iv) shows a waveform of a switching pulse indicating the ON state of the FET 105, and the horizontal axis shows time in each case. Reference voltage 304 and reference voltage 306 in the figure indicate reference voltage 304 and reference voltage 306 input to pulse width limiting unit 305 of power supply IC 103. In the horizontal axis, t300, t302, t304, t306 and t308 indicate periods, and t301, t303, t305, t307, t309, t310, t311 and t312 indicate time timing (hereinafter referred to as timing).

  In the pulse width limited power supply, when the Q output of the FF 310 becomes H level, in the pulse width limiting unit 305, the timer 305c starts measuring the H level duration of the Q output of the FF 310. When the FET 105 is turned on, in the case of the switching power supply shown in FIG. 6, the power supply IC 103 turns off the FET 105 when the IS terminal voltage Vis rises and becomes slightly higher than the FB terminal voltage Vfb. On the other hand, in the pulse width limited power supply device of FIG. 10, the pulse width of the switching pulse of the FET 105 is limited by the operation (a) to (d) described above in the pulse width limiting unit 305. Therefore, for example, even when the IS terminal voltage Vis does not reach the FB terminal voltage Vfb, when the timer value of the timer 305c measuring the H level continuation time of the Q output of the FF 310 described above reaches a predetermined value, The output of the pulse width limiting unit 305 becomes H level. As a result, when the signal of H level is input to the R terminal of the FF 310, the Q output of the FF 310 becomes L level, and the FET 105 is turned off.

  Under certain medium load conditions, if the FET 105 is turned off before the IS terminal voltage Vis reaches the FB terminal voltage Vfb as described above, the power transmitted to the secondary side of the transformer 104 instantaneously compared to the switching power supply shown in FIG. Becomes smaller. Therefore, the number of times the FET 105 is turned on per burst cycle is larger than that of the switching power supply device shown in FIG. This means that in the middle load burst operation, necessary power is supplied by reducing instantaneous power supplied at one time and increasing switching frequency. As described above, in the burst operation, the pulse width limiting unit 305 limits the pulse width of the switching pulse that turns on the FET 105, thereby reducing the instantaneous power supplied to the secondary side of the transformer 104 at one time. As a result, changes in the output voltage Vout and the FB terminal voltage Vfb also become gentle, and it becomes possible to reduce the ripple voltage of the output voltage Vout.

  In the pulse width limited power supply, since the upper limit of the pulse width of the switching pulse for turning on the FET 105 is set in the burst operation, the necessary power can not be sufficiently supplied on the secondary side of the transformer 104 Load conditions exist. In such a case, the state transitions from medium load to heavy load.

  In FIG. 11, the timing after t309 shows the load condition under which the state shifts from the medium load to the heavy load. In FIG. 11, even if the FB terminal voltage Vfb becomes higher than the reference voltage 304 at timing t309, as described above, the pulse width limiting unit 305 performs the switching operation of the FET 105 while limiting the pulse width of the switching pulse that turns on the FET 105. Control. Thereafter, when the load current increases at timing t310 and the output voltage Vout decreases again, sufficient power can not be supplied to the necessary power consumption on the secondary side of the transformer 104, and the FB terminal voltage Vfb rises to the reference voltage 306. Then (timing t311). When the FB terminal voltage Vfb becomes higher than the reference voltage 306, the pulse width limiting unit 305 cancels the limitation of the pulse width. As a result, in the power supply IC 103, the FET 105 continues to operate until the point when the IS terminal voltage Vis rises and becomes slightly higher than the FB terminal voltage Vfb, similar to the operation waveform of the switching power supply under heavy load shown in FIG. It is turned on (after timing t311).

[Overview of operation at light load]
Next, the light load operation of the pulse width limited power supply will be described. In the pulse width limited power supply, in the burst operation, the pulse width limiting unit 305 performs the pulse width limitation of the switching pulse for turning on the FET 105. When such pulse width limitation is performed, the number of times of switching increases, and there is a concern that the power consumption may increase at the time of light load where it is required to reduce the power consumption. In view of such circumstances, in the pulse width limited power supply apparatus, the pulse width determined by the pulse width limitation is set to be larger than the pulse width at light load where pulse limitation is not performed. That is, assuming that the maximum pulse width determined by the pulse width limitation is PLSlim and the pulse width determined by comparing the FB terminal voltage Vfb with the IS terminal voltage Vis at light load is PLSlow, the relationship shown in the following equation (6) Is true. Thereby, the power consumption at the time of light load can be made comparable to a general switching power supply device.
PLSlim> PLSlow (6)
As described above, in the pulse width limited power supply device, by adding the pulse width limiting unit 305 and the reference voltage 306, it is possible to reduce the output ripple at medium load without increasing the power consumption at light load. it can.

[Problems of Pulse Width Limited Power Supply]
However, in the pulse width limited power supply device of FIG. 10, when the load current fluctuates rapidly, the ripple voltage of the output voltage may increase depending on the current value after the fluctuation. Hereinafter, this will be described in detail with reference to FIG. FIG. 12 shows an operation waveform when a sudden load fluctuation occurs in the pulse width limited power supply device, and FIGS. 12 (i) to 12 (iv) correspond to FIGS. 11 (i) to 11 (iv). Since it corresponds, the same description is omitted. In the horizontal axis, t401, t403 and t407 indicate periods, and t400, t402, t404, t405 and t408 indicate time timing (hereinafter referred to as timing). First, when the load current increases at timing t400, the FB terminal voltage Vfb rises to the reference voltage 306 because sufficient power can not be supplied with respect to the necessary power consumption on the secondary side (period t401). When the FB terminal voltage Vfb exceeds the reference voltage 306 at timing t402, the pulse width limiting unit 305 cancels the pulse width limitation by stopping the counting of the pulse width by the timer 305c. Thus, the power supply IC 103 turns on the FET 105 until the IS terminal voltage Vis rises and becomes slightly higher than the FB terminal voltage Vfb.

  At this time, the FB terminal voltage Vfb finally converges to the following voltage value (after t312 in FIG. 11). That is, the pulse width when the FET 105 is turned on so that the power consumption on the secondary side after the load current increases (after timing t310 in FIG. 11) and the power supplied via the transformer 104 become equal. Converge to a voltage value that The convergence value of the FB terminal voltage after the load current increases is hereinafter referred to as a convergence voltage Vfb_f. However, when the load current after the increase at timing t400 becomes a current value such that the convergence voltage Vfb_f of the FB terminal voltage Vfb becomes close to the reference voltage 304 as shown in FIG. 12, the following problem occurs. . That is, immediately after the timing t402 when the pulse width limitation is released, the pulse width at the ON time of the FET 105 becomes too wide relative to the power consumption on the secondary side, and the power supplied becomes excessive. Overshoot occurs (period t403).

  When the output voltage value becomes larger than the target value as shown in FIG. 12 (ii), the FB terminal voltage Vfb starts to decrease as shown in FIG. 12 (iii). However, when overshoot occurs in the output voltage Vout, the output voltage Vout is larger than the target voltage at timing t404 when the FB terminal voltage Vfb reaches the convergence voltage Vfb_f. Therefore, an undershoot occurs in the FB terminal voltage Vfb.

  At this time, if the convergence voltage Vfb_f is a voltage value close to the reference voltage 304 as shown in FIG. 12, the undershoot causes the voltage to fall below the reference voltage 304 at timing t405. Therefore, the pulse width is limited again at timing t405 (period t407), and the operation from t400 to t408 is repeated thereafter. At this time, as shown in FIG. 12 (ii), the overshoot and the undershoot repeatedly occur in the output voltage Vout, so that the ripple voltage of the output voltage Vout becomes large, and the necessary voltage accuracy may not be satisfied. There is. A load current with which the convergence voltage Vfb_f is close to the reference voltage 304 is always present regardless of the output capacity of the switching power supply. For this reason, it is necessary for the electronic device to which the power supply is applied to cope with the load current so that the convergence voltage Vfb_f does not become close to the reference voltage 304, which may complicate the design of the device.

[Circuit configuration of power supply unit]
FIG. 1 shows the switching power supply device of the first embodiment. The same components as those of the pulse width limited power supply described with reference to FIG. This embodiment has a configuration in which a pulse width restriction prohibition time generation unit 305e (hereinafter, simply referred to as a generation unit 305e), which is control means, is added to the switching power supply device described in FIG. The generation unit 305 e is connected between the reference voltage 304 and the pulse width limit determination unit 305 a. Specifically, the reference voltage 304 is input to the generation unit 305e, and the generation unit 305e outputs a predetermined voltage to the pulse width limit determination unit 305a. Further, the signal output from the pulse width limit determination unit 305a is input to the generation unit 305e. Furthermore, the generation unit 305e can measure time using the timer 305c.

  First, the operation of the generation unit 305e will be described. When the output of the pulse width limit determination unit 305a changes from H level to L level, that is, when the pulse width limit is released, the generation unit 305e outputs 0 V to the pulse width limit determination unit 305a. The generation unit 305e has a counter 305g that operates according to the timer 305c, and when the output of the pulse width limit determination unit 305a changes from H level to L level (when the pulse width limit is released), the counter Start counting by 305g. At this time, 0 V, not the reference voltage 304, is input to the pulse width limit determination unit 305a as a reference voltage for limiting the pulse width. Therefore, while the generating unit 305e is outputting 0 V to the pulse width limit determining unit 305a, the pulse width is not limited even if the FB terminal voltage Vfb falls below the reference voltage 304. As described above, in the present embodiment, the generation unit 305 e transitions from the first state in which the pulse width is limited by the pulse width restriction determination unit 305 a to the second state in which the pulse width restriction is released. Control is performed to maintain the second state in which the limitation of the pulse width is released for the first time. Here, the first time corresponds to the time from timing t502 to timing t507 in FIG. 2 described later, and the elapse of the first time is determined by the count of the counter 305g.

  When the value of the counter 305g becomes a predetermined value, the generation unit 305e outputs the voltage of the reference voltage 304 as it is to the pulse width restriction determination unit 305a, and clears the value of the counter 305g. The predetermined value is, for example, a value determined in advance, such as a value according to the time from when the load current changes to when the FB terminal voltage Vfb converges to the convergence voltage Vfb_f. Shall be stored in While the generation unit 305e outputs the reference voltage 304 to the pulse width limit determination unit 305a, the pulse width limited power supply circuit of this embodiment operates in the same manner as a normal pulse width limited power supply device (for example, FIG. 10). Do.

[Operation of switching power supply unit]
The operation of the switching power supply of this embodiment will be described in association with the operation waveform of FIG. 2 (i) shows the current waveform of the load current, FIG. 2 (ii) shows the voltage waveform of the output voltage Vout, and FIG. 2 (iii) shows the voltage waveform of the FB terminal voltage Vfb of the power supply IC 103. FIG. 2 (iv) is a voltage waveform of the voltage output from the generation unit 305e to the pulse width limit judging unit 305a, and FIG. 2 (v) is a diagram showing the waveforms of switching pulses when driving the switching element 105. is there. In each case, the horizontal axis indicates time. Further, on the horizontal axis, t501 and t503 indicate periods, and t500, t502, t504, t505, t506 and t507 indicate time timing (hereinafter referred to as timing).

  First, when the load current increases at timing t500 (FIG. 2 (i)), sufficient power supply can not be performed, and the FB terminal voltage Vfb rises to the reference voltage 306 (period t501). When the FB terminal voltage Vfb exceeds the reference voltage 306 at timing t502, the pulse width limiting unit 305 cancels the limitation of the pulse width by stopping the counting of the pulse width by the internal timer 305c. As a result, the power supply IC 103 turns on the FET 105 until the IS terminal voltage Vis rises and becomes slightly higher than the FB terminal voltage Vfb, as in the conventional example shown in FIG.

  At this time, when the load current after the increase becomes a current value such that the convergence voltage Vfb_f becomes close to the reference voltage 304, an overshoot of the output voltage Vout occurs immediately after releasing the pulse width limitation. That is, since the pulse width of the FET 105 ON becomes too wide and the power to be supplied becomes excessive with respect to the power consumption on the secondary side, an overshoot occurs in the output voltage Vout (FIG. 2 (FIG. ii)). When the output voltage value becomes larger than the target value, the FB terminal voltage Vfb starts to decrease. In the situation where the overshoot occurs in the output voltage, the output voltage Vout is still larger than the target voltage even when the FB terminal voltage Vfb reaches the convergence voltage Vfb_f (timing t504). Therefore, an undershoot occurs in the FB terminal voltage Vfb. At this time, when the convergence voltage Vfb_f is a voltage value close to the reference voltage 304 as shown in FIG. 2 (iii), the FB terminal voltage Vfb falls below the reference voltage 304 due to the undershoot (timing t505).

  When the pulse width limit determination unit 305a transitions from the H level to the L level (timing t502), the generation unit 305e of the present embodiment sends the pulse width limit determination unit 305a until the value of the counter 305g reaches a predetermined value. It outputs 0 V instead of the reference voltage 304. At timing t505, as shown in FIG. 2 (iv), since the output of the generation unit 305e is 0 V, the switching operation is stopped, but the pulse width is not limited. Thereafter, at timing t506, the FB terminal voltage Vfb again exceeds the reference voltage 304, and the switching operation is started. At timing t507, the output of the generation unit 305e changes from 0 V to the voltage of the reference voltage 304. However, at timing t507, the FB terminal voltage Vfb exceeds the reference voltage 304, so the pulse width is not limited.

  As described above, according to the present embodiment, in the switching power supply that limits the pulse width when the switching element is on at light load and medium load, increase in ripple voltage generated due to fluctuation of load current is obtained. It can be suppressed. That is, since the pulse width limited power supply apparatus includes the generation unit 305e of the present embodiment, the pulse width limitation and the limitation release are not repeated even after the load current increases. This makes it possible to suppress the increase in ripple voltage caused by the fluctuation of the load current.

[Circuit configuration]
FIG. 3 shows the switching power supply device of the second embodiment. The same components as those of the switching power supply devices of the conventional example and the first embodiment are denoted by the same reference numerals and the description thereof is omitted. The difference between the present embodiment and the first embodiment is that the pulse width limit release prohibition time generation unit 305f (hereinafter referred to simply as the generation unit 305f), which is a control means, is different from the switching power supply of the first embodiment described in FIG. ) Is added. The generation unit 305 f is connected between the reference voltage 306 and the pulse width limit determination unit 305 a. Specifically, the reference voltage 306 is input to the generation unit 305f, and the generation unit 305f outputs a predetermined voltage to the pulse width restriction determination unit 305a. Further, the signal output from the pulse width limit determination unit 305a is input to the generation unit 305f. Furthermore, the generation unit 305 f can measure time using the timer 305 c.

First, the operation of the generation unit 305 f will be described. When the output of the pulse width limit determination unit 305 a changes from L level to H level, that is, when the pulse width is limited, the generation unit 305 f does not generate the reference voltage 306 for the pulse width limit determination unit 305 a but a predetermined voltage Va Output The generation unit 305e has a counter 305h that operates according to the timer 305c, and starts counting by the counter 305h when the output of the pulse width limitation determination unit 305a changes from L level to H level. Here, the relationship between the predetermined voltage Va and the reference voltage 306 is the relationship of the following equation (7), as shown in FIG. 4 (iv) described later.
Predetermined voltage Va> reference voltage 306 (7)

  In the case where the generation unit 305 f is not provided, when the FB terminal voltage Vfb exceeds the reference voltage 306, the limitation of the pulse width is released. However, in the present embodiment, while the generation unit 305f is outputting the predetermined voltage Va larger than the reference voltage 306, the restriction on the pulse width is not released even if the FB terminal voltage Vfb exceeds the reference voltage 306. Ie the pulse width is limited. As described above, in the present embodiment, when the generation unit 305 f transitions from the second state in which the pulse width restriction determination unit 305 a has released the restriction on the pulse width to the first state in which the pulse width is restricted, Control is performed to maintain the first state in which the pulse width is limited for a second time. Here, the second time corresponds to the time from timing t602 to timing t608 in FIG. 4 described later, and the elapse of the second time is determined by the count of the counter 305h.

  When the value of the counter 305h in the generation unit 305f becomes a predetermined value, the generation unit 305f outputs the reference voltage 306 as it is to the pulse width restriction determination unit 305a, and clears the value of the counter 305h. The predetermined value is, for example, a value determined in advance, such as a value according to the time from when the load current changes to when the FB terminal voltage Vfb converges to the convergence voltage Vfb_f. Shall be stored in While the generation unit 305 f outputs the reference voltage 306, the generation unit 305 f operates in the same manner as the power supply of FIG. 1 of the first embodiment.

[Operation of switching power supply unit]
The operation of the switching power supply device according to this embodiment will be described in association with the operation waveform of FIG. 4 (i) to FIG. 4 (v) correspond to FIG. 2 (i) to FIG. 2 (v), and the description overlapping with the explanation of FIG. 2 is omitted. Further, in the horizontal axis, t601, t604, and t605 indicate periods, and t600, t602, t603, t606, t607, and t608 indicate time timing (hereinafter referred to as timing). First, when the load current decreases at timing t600, the power to be supplied becomes excessive with respect to the power consumption on the secondary side. Therefore, the FB terminal voltage Vfb decreases to the reference voltage 304 (period t601).

  When the FB terminal voltage Vfb falls below the reference voltage 304 at timing t602, the power supply IC 103 stops the switching operation (section t604). When the switching operation is stopped, the power supply is interrupted and the output voltage is lowered (FIG. 4 (ii)), and the FB terminal voltage Vfb is turned to rise at the timing when the output voltage falls below the target voltage. Further, at timing t602, the signal input from the pulse width limitation determination unit 305a to the generation unit 305f changes from L level to H level. As a result, the generation unit 305 f outputs the predetermined voltage Va to the pulse width limit determination unit 305 a. Thereafter, at timing t603, since the FB terminal voltage Vfb again exceeds the reference voltage 304, the switching operation is started. At this time, since the pulse width is limited by the pulse width limiting unit 305, the output voltage Vout continues to decrease while the FB terminal voltage Vfb is low (section t605).

  In response to the rise of the FB terminal voltage Vfb, the limited width of the pulse also widens, so the output voltage Vout turns to rise. Here, when the FB terminal voltage Vfb becomes the value of the convergence voltage Vfb_f in FIG. 4 (iii) with the pulse width limited, the load current after reduction in FIG. Power consumption on the next side is equal. However, in FIG. 4, the output voltage Vout does not reach the target voltage at timing t606 when the FB terminal voltage Vfb becomes the value of the convergence voltage Vfb_f due to the influence of the undershoot. Therefore, the FB terminal voltage Vfb continues to rise and exceeds the reference voltage 306 at timing t607.

  In the configuration of the first embodiment, when the FB terminal voltage Vfb exceeds the reference voltage 306, the limitation of the pulse width is released (timing t502 in FIG. 2). As a result, the pulse width at which the FET 105 turns on becomes too wide, and an overshoot occurs in the output voltage Vout. Thereafter, the power supply is also reduced because the FB terminal voltage Vfb is reduced, but the value of the load current shown in FIG. 2 (i) becomes excessive when the pulse width limitation is released. For this reason, the FB terminal voltage Vfb falls again to fall below the reference voltage 304, causing an undershoot, and a ripple voltage is generated in the output voltage Vout.

  On the other hand, in the configuration of the present embodiment, at timing t607, the generation unit 305f outputs the predetermined voltage Va to the pulse width restriction determination unit 305a. Therefore, even if the FB terminal voltage Vfb exceeds the reference voltage 306, the pulse width limitation is not released, and the state in which the pulse width is limited is maintained. At timing t608, the output of the generation unit 305f becomes the voltage of the reference voltage 306. At timing t608, the FB terminal voltage Vfb is lower than the reference voltage 306, and the pulse width is subsequently limited. Therefore, the pulse width of the FET 105 on is not so wide that overshoot does not occur.

  As described above, according to the present embodiment, in the switching power supply device that limits the pulse width of the switching element at the time of light load and medium load, it is possible to suppress an increase in ripple voltage generated due to fluctuation of load current. it can. In particular, in the present embodiment, it is possible to suppress an increase in output ripple voltage caused by a decrease in load current.

  The power supply apparatus described in the first and second embodiments can be applied, for example, as a low-voltage power supply of an image forming apparatus, that is, a power supply for supplying power to a controller (control unit) or a drive unit such as a motor. Hereinafter, the configuration of the image forming apparatus to which the power supply apparatus of the first and second embodiments is applied will be described.

[Configuration of image forming apparatus]
A laser beam printer will be described as an example of the image forming apparatus. FIG. 5 shows a schematic configuration of a laser beam printer which is an example of an electrophotographic printer. The laser beam printer 300 includes a photosensitive drum 311 as an image carrier on which an electrostatic latent image is formed, a charging unit 317 (charging unit) for uniformly charging the photosensitive drum 311, and an electrostatic latent formed on the photosensitive drum 311. The developing unit 312 (developing unit) develops the image with toner. Then, the toner image developed on the photosensitive drum 311 is transferred to a sheet (not shown) as a recording material supplied from the cassette 316 by the transfer unit 318 (transfer means), and the toner image transferred to the sheet is fixed to the fixing device 314 And the sheet is discharged to the tray 315. The photosensitive drum 311, the charging unit 317, the developing unit 312, and the transfer unit 318 are image forming units. In addition, the laser beam printer 300 includes the power supply device 400 described in the first and second embodiments. The image forming apparatus to which the power supply apparatus 400 according to the first and second embodiments can be applied is not limited to that illustrated in FIG. 5, and may be an image forming apparatus including a plurality of image forming units, for example. Furthermore, the image forming apparatus may be provided with a primary transfer portion for transferring the toner image on the photosensitive drum 311 to the intermediate transfer belt, and a secondary transfer portion for transferring the toner image on the intermediate transfer belt to the sheet.

  The laser beam printer 300 includes a controller 320 that controls an image forming operation by an image forming unit and a sheet conveying operation, and the power supply device 400 described in the first and second embodiments supplies power to the controller 320, for example. . Further, the power supply device 400 described in the first and second embodiments supplies power to a drive unit such as a motor for rotating the photosensitive drum 311 or for driving various rollers for transporting a sheet. In the image forming apparatus to which the power supply device of the first embodiment is applied, it is possible to suppress the ripple voltage of the output voltage Vout generated due to the increase of the load current. Further, in the image forming apparatus to which the power supply device of the second embodiment is applied, it is possible to suppress the ripple voltage of the output voltage Vout generated due to the decrease of the load current.

  As described above, according to the present embodiment, in the switching power supply device that limits the pulse width of the switching element at the time of light load and medium load, it is possible to suppress an increase in ripple voltage generated due to fluctuation of load current. it can.

104 transformer 105 FET
109 Photocoupler 305 Pulse Width Limiting Unit 305 e Pulse Width Limiting Prohibition Time Generation Unit

Claims (10)

A transformer whose primary and secondary sides are isolated,
A switching element for performing a switching operation of turning on and off the current flowing to the primary side of the transformer;
Feedback means for feeding back a feedback voltage according to the output voltage on the secondary side of the transformer to the primary side of the transformer;
Limiting means for limiting an on width of a pulse signal for turning on the switching element based on the feedback voltage fed back by the feedback means;
A power supply comprising
Control is performed to maintain the second state for a first period of time when transitioning from the first state in which the on-width is restricted by the restriction means to a second state in which the restriction on the on-width is released. A power supply apparatus comprising:   The first time means that the feedback voltage becomes lower than the first voltage when the feedback voltage exceeds a second voltage higher than the first voltage, and then the first voltage is higher than the first voltage. The power supply device according to claim 1, which is a time to reach a predetermined voltage exceeding. The power supply according to claim 2 , wherein the control means controls the first state to be maintained for a second time when transitioning from the second state to the first state. apparatus.   The second time is a time from when the feedback voltage becomes lower than the first voltage and thereafter reaches a predetermined voltage smaller than the second voltage after exceeding the second voltage. The power supply device according to claim 3, wherein the power supply device is provided.   The invention is characterized in that the limiting means limits the ON width until the feedback voltage becomes lower than a first voltage and then becomes higher than a second voltage higher than the first voltage. The power supply device according to any one of Items 1 to 4.   6. The apparatus according to claim 5, wherein the limiting means releases the limitation on the on-width until the feedback voltage becomes higher than the second voltage and becomes lower than the first voltage. Power supply. A detection unit that detects a voltage corresponding to the current flowing to the primary side of the transformer;
The power supply device according to claim 6, wherein the control means controls the on width in the second state based on the feedback voltage and the voltage detected by the detection means.   The power supply apparatus according to any one of claims 5 to 7, wherein the control means stops the switching operation of the switching element when the feedback voltage is lower than the first voltage. . The transformer has an auxiliary winding,
9. The control means turns on the switching element according to the timing when the voltage corresponding to the voltage induced in the auxiliary winding falls and becomes 0. The power supply device according to any one of the preceding claims. An image forming unit for forming an image on a recording material;
The power supply device according to any one of claims 1 to 9, which supplies power to the image forming means.
An image forming apparatus comprising:

Images