JP6534345B2 - Overvoltage protection device - Google Patents

Description

  The present invention relates to a technique for protecting a device that transmits a signal using a signal line from an overvoltage of the signal line.

  As a technique for protecting a device that transmits a signal using a signal line from an overvoltage of the signal line, as shown in FIG. 7a, a signal line CL is connected to a terminal 710 for signal transmission of the device 700 via a resistor 701. In addition, a diode 702 in which the cathode is connected to the ground at the terminal 710 of the device 700 and a diode 703 in which the cathode is connected to the anode at the terminal 710 of the device 700 are provided. While the diode 702 suppresses the voltage applied to the terminal 710 from falling to a potential lower than the ground potential, the diode 703 suppresses the voltage applied to the terminal 710 from rising to a potential higher than the power supply potential. Is known (for example, patent document 1).

  In addition, as a technique for protecting the device 700 for transmitting a signal using a signal line from an overvoltage of the signal line, as shown in FIG. 7b, a cathode is connected to a terminal 710 for signal transmission of the device 700 and an anode is connected to ground. A technique is known that provides a zener diode 712 and suppresses the current flowing to the terminal 710 with the resistor 711 while preventing the voltage applied to the terminal 710 with the zener diode 713 from rising to a potential higher than the zener voltage of the zener diode 712. (E.g., Patent Document 2).

Japanese Patent Laid-Open No. 3-85016 JP, 2009-71373, A

  According to the technique shown in FIG. 7a, when the overvoltage occurs in the signal line CL and the current flowing into the power supply through the diode 703 becomes larger than the consumption current of the device 700, the potential of the power supply of the device 700 is higher than the rated voltage of the device 700. As a result, the device 700 may be destroyed.

  Further, according to the technique of FIG. 7b, when an overvoltage occurs on the signal line CL while the power of the device 700 is off, the voltage applied to the terminal 710 exceeds the absolute rated voltage, and the device 700 is broken. It may be done.

  That is, for example, when the absolute rated voltage of terminal 710 is in the range between ground potential -0.5V and power supply potential + 0.5V, the power supply voltage is 5V and the Zener voltage of Zener diode 712 is 5V when the power is on. If the power is on, the range of the absolute rated voltage is in the range of -0.5 V and 5.5 V (5 V + 0.5 V). When the power is on, the voltage applied to the terminal 710 is limited to 5 V or less of the Zener voltage, so the voltage applied to the terminal 710 falls within the range of the absolute rated voltage. On the other hand, when the power supply potential of the device 700 is off and the power supply potential is 0 V, the absolute rated voltage is in the range between -0.5 V and +0.5 V. Therefore, the voltage applied to the terminal 710 is 5 V or less of the Zener voltage. Even if limited, the voltage applied to the terminal 710 can not be limited within the range of the absolute rated voltage.

In addition, there is also a problem that individual differences are large in the Zener voltage of a general Zener diode.
Then, this invention makes it a subject to protect the apparatus which transmits a signal using a signal wire from the overvoltage of a signal wire irrespective of the ON / OFF state of the power supply of a device.

  In order to achieve the above object, the present invention is a signal which is a terminal of the device for inputting or outputting a signal transmitted by the signal line to an overvoltage protection device for protecting a device for transmitting a signal using the signal line from overvoltage. When the voltage of the terminal becomes higher than the voltage of the power supply terminal, which is the terminal of the device to which the power of the device is supplied, by a predetermined level or more, the signal terminal of the device and the ground of the device are turned on. It has a switch to be connected.

  According to such an overvoltage protection device, the switch connects the power supply terminal to the ground when the voltage of the signal terminal of the device is greater than the voltage of the power supply terminal of the device by a predetermined level or more. Therefore, when the power supply voltage is supplied to the power supply terminal of the device, the voltage of the signal terminal is limited not to exceed the voltage obtained by adding the predetermined level to the power supply voltage, and the power supply voltage is supplied to the power supply terminal of the device. When not, it is limited so as not to exceed the voltage of the predetermined level. That is, the voltage of the signal terminal is always limited to the voltage of the power supply terminal plus the predetermined level or less. Therefore, by setting the predetermined level appropriately, the voltage at the signal terminal can be prevented from deviating from the range of the rated voltage of the device. Further, since the signal terminal and the power supply terminal are not directly connected, the voltage rise of the power supply terminal is also suppressed.

  Further, the present invention is a terminal of the device for inputting or outputting a signal transmitted through the signal line to an overvoltage protection device for protecting a device transmitting a signal using the signal line from overvoltage in order to achieve the above object. An emitter is connected to the signal terminal, a base is connected to a power supply terminal which is a terminal of the device to which the power supply of the device is supplied, and a PNP transistor having a collector connected to the ground of the device is provided.

  Here, the overvoltage protection device preferably includes a diode whose cathode is connected to the emitter of the transistor and whose anode is connected to the ground of the device. In this case, it is also preferable that the cathode of the diode has a resistor whose first end is connected to the signal line and whose second end is connected to the signal line.

According to these overvoltage protection devices, when the voltage at the signal terminal of the device exceeds the voltage at the power supply terminal of the device by at least the junction saturation voltage (V _BE ) of the transistor, the transistor connects the power terminal to the ground. Be done. Therefore, the voltage of the signal terminal is limited not to be equal to or higher than the sum of the transistor junction saturation voltage (V _BE ) and the power supply voltage when the power supply voltage is supplied to the power supply terminal of the device. When the power supply voltage is not supplied to the terminal, the voltage is limited so as not to exceed the junction saturation voltage (V _BE ) of the transistor. That is, the voltage at the signal terminal is always limited to the voltage at the power supply terminal plus the junction saturation voltage (V _BE ) of the transistor. Therefore, by using a transistor with an appropriate junction saturation voltage (V _BE ), the voltage at the signal terminal can be prevented from deviating from the rated voltage range of the device. Further, since the signal terminal and the power supply terminal are not directly connected, the voltage rise of the power supply terminal is also suppressed.

  Further, to achieve the above object, according to the present invention, an overvoltage protection device for protecting a device for transmitting a signal using a signal line from an overvoltage is controlled by the device to switch on and off states. A switch, a resistor, and a second switch are provided. Here, the first switch connects a power terminal, which is a terminal of the device to which power is supplied to the device when in the on state, and the first end of the resistor, and the second end of the resistor Is connected to the ground of the device, and the voltage of the signal terminal, which is a terminal of the device to which the second switch inputs or outputs the signal transmitted through the signal line, is the voltage of the first end of the resistor. It turns on when the voltage exceeds a predetermined level, and the signal terminal of the device is connected to the ground of the device.

Here, in this overvoltage protection device, it is preferable to use a Darlington connection circuit as the second switch.
According to such an overvoltage protection device, when the first switch is turned on, the voltage of the signal terminal is limited to a voltage equal to or lower than the sum of the power supply voltage and the predetermined level, and the first switch is turned off. When this is the case, the voltage at the signal terminal is limited below the voltage of the predetermined level. Also, when the first switch is turned off, the supply of power from the power supply to the voltage protection circuit is cut off.

  Therefore, the voltage of the signal terminal can be limited to less than or equal to the sum of the power supply voltage and the predetermined level if the first switch is turned on during a period in which the device performs a normal operation including a signal transmission operation. Also, by configuring the overvoltage protection device so that the first switch is turned off during the period when the power supply voltage of the device is not supplied, the period when the power supply voltage of the device is not supplied. The voltage of the signal terminal can be limited so as not to exceed the voltage of the predetermined level. Therefore, during these periods, the voltage of the signal terminal can always be limited to the voltage of the power supply terminal plus the predetermined level or less, so by appropriately setting the predetermined level, the signal terminal Can be prevented from deviating out of the range of the rated voltage of the device.

  In addition, when the device is in a standby state in which the signal transmission operation is not performed, the first switch is set to the off state, and the voltage of the signal terminal is limited so as not to exceed the voltage of the predetermined level. It is possible to suppress the consumption of the power of the power supply by the overvoltage protection device while preventing the voltage from deviating out of the range of the rated voltage of the device.

  Further, in order to achieve the above object, the present invention provides an overvoltage protection device for protecting a device transmitting a signal using a signal line from overvoltage, a first transistor, a second transistor, and a third transistor. , A first diode, a first resistor, and a second resistor. Here, in the first transistor, an emitter is connected to a power supply terminal which is a terminal of the device to which power of the device is supplied, and a base is connected to a terminal for outputting a control signal of the overvoltage protection device of the device. And a collector is connected to an anode of the first diode, and a cathode of the first diode is connected to a first end of the first resistor, and a second of the first resistor is connected. An end is connected to the ground of the device, an emitter is connected to a signal terminal which is a terminal of the device which inputs or outputs a signal transmitted through the signal line, and the second transistor is connected to the ground of the first resistor. A PNP type transistor having a base connected to a first end and a collector connected to a first end of the second resistor, and a second end of the second resistor connected to the ground of the device; Three tigers The transistor is an NPN transistor having a collector connected to the signal terminal of the device, a base connected to the first end of the second resistor, and an emitter connected to the ground of the device.

Here, in the overvoltage protection device, it is preferable that a forward voltage of the first diode be equal to a junction saturation voltage (V _BE ) of the second transistor.
Preferably, the overvoltage protection device further comprises a second diode having a cathode connected to the collector of the third transistor and an anode connected to the ground of the device. In this case, it is also preferable to provide a resistor whose first end is connected to the cathode of the second diode and whose second end is connected to the signal line.

According to the above overvoltage protection device, when the first transistor is turned on by the control signal output of the device, the voltage at the signal terminal is the sum of the junction saturation voltage (V _BE ) of the second transistor and the power supply voltage. When the first transistor is turned off by the control signal output of the device, the voltage of the signal terminal is limited to less than the junction saturation voltage (V _BE ) of the second transistor. Further, when the first transistor is turned off, the supply of power from the power supply to the voltage protection circuit is shut off.

Therefore, if the first transistor is turned on while the device is in normal operation with signal transmission, the voltage at the signal terminal is added to the power supply voltage and the junction saturation voltage (V _BE ) of the second transistor is added. It can be limited to less than the specified voltage. Also, while the power supply voltage is not supplied to the power supply terminal of the device, the first transistor is turned off, so the voltage of the signal terminal is higher than the junction saturation voltage (V _BE ) of the second transistor. It is limited not to.

Therefore, during these periods, it is possible to limit the voltage of the signal terminal to a voltage equal to or less than the voltage of the power supply terminal plus the junction saturation voltage (V _BE ) of the second transistor. By using the second transistor V _BE ), the voltage at the signal terminal can be prevented from deviating from the range of the rated voltage of the device.

In addition, when the device is in a standby state in which no signal transmission operation is performed, the voltage at the signal terminal does not exceed the junction saturation voltage (V _BE ) of the second transistor by setting the first transistor to the off state. Thus, the consumption of the power of the power supply by the over voltage protection device can be suppressed while restricting the voltage of the signal terminal from deviating out of the range of the rated voltage of the device.

  As described above, according to the present invention, an apparatus that transmits a signal using a signal line can be protected from an overvoltage of the signal line regardless of the power on / off state of the apparatus.

It is a block diagram showing composition of a processing device concerning a 1st embodiment of the present invention. It is a circuit diagram showing composition of a protection circuit concerning a 1st embodiment of the present invention. It is a figure which shows operation | movement of the protection circuit which concerns on 1st Embodiment of this invention. It is a block diagram which shows the structure of the processing apparatus which concerns on 2nd Embodiment of this invention. It is a circuit diagram showing composition of a protection circuit concerning a 2nd embodiment of the present invention. It is a figure which shows operation | movement of the protection circuit which concerns on 2nd Embodiment of this invention. It is a figure which shows the technique of the conventional overvoltage protection.

Hereinafter, embodiments of the present invention will be described.
First, the first embodiment will be described. FIG. 1 shows the configuration of a processing apparatus according to the first embodiment.
The processing device is, for example, an electronic device mounted on a car, and is a device that transmits signals and data with the other processing devices using the signal line SL.
Then, as illustrated, the processing apparatus 1 includes a power supply circuit 11, a processor 12, and a protection circuit 13.
The application circuit 11 generates an internal power supply VDD from the external power supply VCC and supplies the internal power supply VDD to each part of the processing apparatus 1. The external power source is, for example, a battery of a car.
The processor 12 is a device that performs data processing, such as a microcomputer, operates with the power supply VDD supplied to the power supply terminal 121, transmits a signal from the communication terminal 122, or receives a signal at the communication terminal 122.

  The protection circuit 13 is disposed between a communication line CL used for communication with another processing apparatus 1 and an internal signal line SL connected to the communication terminal 122 of the processor 12 and includes the communication line CL and the internal signal line SL. , And protect the processor 12 from the overvoltage of the communication line CL.

Next, FIG. 2 shows the configuration of the protection circuit 13.
As illustrated, the protection circuit 13 includes a current limiting resistor R connected in series between the internal signal line SL connected to the communication terminal 122 of the processor 12 and the communication line CL, and the internal signal line SL. A PNP type transistor Q having a cathode connected, a diode D connected to the ground GND and a base connected to the power terminal 121 of the processor 12, an emitter connected to the internal signal line SL, and a collector connected to the ground GND Is equipped.

According to such a protective circuit 13, as shown in FIG. 3a, when the power supply of voltage V1 is supplied to the power supply terminal 121 of the processor 12 with the power supply VDD on, an overvoltage is applied to the communication line CL. The voltage of the internal signal line SL rises, and the potential of the emitter of the transistor Q becomes higher than the potential V1 of the base by more than the junction saturation voltage V _{BE of the} transistor Q. The junction saturation voltage V _BE is a voltage between the emitter and the collector when a base current flows in the transistor, and is substantially constant regardless of the magnitude of the base current.

Then, the potential of the emitter, the transistor Q junction saturation voltage V _BE above, becomes larger than the base potential V1, the base current I _B flows, through the internal signal line SL, and current, the emitter of the transistor Q, the collector Therefore, it flows to ground GND. At this time, the potential of the internal signal line SL is clamped to V1 + _VBE .

Therefore, the voltage applied to the communication line CL when the power supply VDD is in the on state is limited so as not to exceed V1 + _VBE .
Therefore, by using a transistor having an appropriate V _BE value as the transistor Q, it is possible to prevent an overvoltage exceeding the range of the rated voltage from being applied to the processor 12.

Further, according to such a protection circuit 13, as shown in FIG. 3b, in the state where the power supply VDD is off, that is, in the state where the power supply VDD supplied to the power supply terminal 121 of the processor 12 is 0V, the communication line CL. joined by overvoltage rises the voltage of the internal signal line SL, and the emitter potential of the transistor Q is than 0V, becomes greater than the junction saturation voltage V _bE of the transistor Q, flows the base current I _B, the internal signal lines From SL, current flows through the emitter and the collector of the transistor Q to the ground GND. At this time, the potential of the internal signal line SL is clamped at 0 V + V _BE .

Therefore, the voltage applied to the communication line CL when the power supply VDD is in the off state is limited so as not to exceed V _BE .
Therefore, by using a transistor having an appropriate V _BE value as the transistor Q, even when the power supply VDD is off, an overvoltage exceeding the range of the rated voltage can be prevented from being applied to the processor 12.

  Further, according to such a protection circuit 13, as shown in FIG. 3c, when a voltage lower than the ground GND is applied to the communication line CL, the internal signal line SL is connected to the ground GND via the diode D. The potential of the internal signal line SL is maintained by subtracting the forward voltage VF of the diode D from the potential of the ground GND.

The first embodiment of the present invention has been described above.
Hereinafter, a second embodiment of the present invention will be described.
FIG. 4 shows the configuration of the processing apparatus 1 according to the second embodiment.
As illustrated, the configuration of the processing apparatus 1 according to the second embodiment is the same as that of the first embodiment shown in FIG. 1 and the control line CNT is connected from the processor 12 to the protection circuit 13 and the configuration of the processing apparatus 1. The only difference is that Further, in the second embodiment, the processor 12 has, as an operation mode, a normal operation mode performing a normal operation including transmission of a signal through the signal line CL, and a standby mode operating with low power consumption. It shall be.

FIG. 5 shows the configuration of the protection circuit 13 according to the second embodiment.
As illustrated, the protection circuit 13 includes a first resistor R1 for current limitation, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, and a first transistor Q1. A second transistor Q2 and a third transistor Q3 are provided.

  Here, the first resistor R1 is connected in series between the internal signal line SL connected to the communication terminal 122 of the processor 12 and the communication line CL. The cathode of the first diode D1 is connected to the internal signal line SL, and the anode is connected to the ground GND.

  The first transistor Q1 is a PNP type transistor, the emitter is connected to the power supply terminal 121 of the processor 12, the control line CNT from the processor 12 is connected to the base, and the anode of the second diode D2 is connected to the collector doing.

The first end of the second resistor R2 is connected to the cathode of the second diode D2, and the second end is connected to the ground GND.
The second transistor Q2 is a PNP transistor, the base is connected to the cathode of the second diode D2 and the first end of the second resistor R2, and the emitter is connected to the internal signal line SL.

The first end of the third resistor R3 is connected to the collector of the second transistor Q2, and the second end is connected to the ground GND.
The base of the third transistor Q3 is an NPN transistor, the base is connected to the collector of the second transistor Q2 and the first end of the third resistor R3, the collector is connected to the internal signal line SL, and the emitter is Connected to ground GND.

Here, the second transistor Q2, the third resistor R3 and the third transistor Q3 form a Darlington connection circuit 500.
Now, as shown in FIG. 6a, when the power supply voltage of V1 is supplied to the power supply terminal 121 of the processor 12 with the power supply VDD on and the processor 12 is in the normal operation mode, the processor 12 controls the control line CNT. A signal is applied to maintain the first transistor Q1 in the ON state.

  As a result, in the protection circuit 13, the voltage of the potential V1-VF is applied to the base of the second transistor Q2 through the first transistor Q1 and the second diode D2 controlled to be in the on state. Here, VF is a forward voltage of the second diode VF.

In this state, when an overvoltage is applied to the communication line CL, the voltage of the internal signal line SL rises, and the potential of the emitter of the second transistor Q2 is saturated with the junction of the second transistor Q2 from the potential V1-VF of the base. It becomes larger than the voltage V _BE .

When the junction saturation voltage V _{BE of} the second transistor Q 2 is greater than the potential V 1 -V F of the base, the base current I _B flows through the second transistor Q 2, and the current flows from the internal signal line SL. Of the third resistor R3 to the ground GND, and the potential at the first end of the third resistor R3 is applied to the third transistor Q3.

Then, the potential of the base of the third transistor Q3 becomes higher than the potential of the emitter by the junction saturation voltage V _{BE of} the third transistor Q3 and the current flows from the internal signal line SL to the collector of the third transistor Q3, It flows to ground GND through the emitter.

At this time, the junction portion saturation voltage V _BE of the second transistor Q 2 is set to V _{BE —} Q 2, and the potential of the internal signal line SL is clamped to V 1 −VF + V _BE _Q 2.

Therefore, the power supply VDD is turned on and, when the operation mode of the processor 12 is in its normal operating mode, the voltage applied to the communication line CL is limited so as not to exceed the V1-VF + V _BE _Q2.

Therefore, by using a transistor having an appropriate value of V _BE as the second transistor Q2 and a diode having an appropriate value of VF as the second diode D2, an overvoltage exceeding the range of the rated voltage is applied to the processor 12 You can prevent it from

In particular, by selecting the transistor used as the second transistor Q2 and the diode used as the second diode D2 so that the VF of the second diode D2 matches the V _BE of the second transistor Q2, application to the communication line CL voltage can be as _{V1-VF + V bE _Q2 =} V1 , and the voltage of the internal signal line SL does not exceed the voltage V1 of the power supply VDD.

  Further, according to such a protection circuit 13, the Darlington connection circuit 500 having a large hfe (amplification factor) is used as a circuit for drawing a current from the internal signal line SL to the ground GND. In addition, when the operation mode of the processor 12 is the normal operation mode, the power consumption of the power supply VDD by the protection circuit 13 can be suppressed small, and the resistance value of the first resistor R1 can be set small. High-speed communication using line CL can be enabled.

  Next, as shown in FIG. 6b, when the power supply voltage 121 is supplied to the power supply terminal 121 of the processor 12 with the power supply VDD turned on, and the processor 12 is in the standby mode, the processor 12 controls the control line CNT. The first signal Q1 is maintained at the off state.

  As a result, in the protection circuit 13, the first transistor Q1 is turned off, and the potential of the base of the second transistor Q2 is pulled down to the ground GND by the second resistor R2 and becomes 0V.

Then, in this state, when an overvoltage is applied to the communication line CL, the voltage of the internal signal line SL rises, and the potential of the emitter of the second transistor Q2 becomes higher than 0 V, the junction saturation voltage V _{BE of} the second transistor Q2 It becomes bigger than that.

The potential of the emitter of the second transistor Q2 is than 0V, the larger junction saturation voltage V _BE above the second transistor Q2, the base current I _B flows through the second transistor Q2, the internal signal line SL, and current Flows through the emitter and collector of the second transistor Q2 and the third resistor R3 to the ground GND, and the potential at the first end of the third resistor R3 is applied to the third transistor Q3.

Then, the potential of the base of the third transistor Q3 becomes larger than the potential of the emitter by the junction saturation voltage V _{BE of} the third transistor Q3 and the current flows from the internal signal line SL to the collector of the third transistor Q3. , Flows to ground GND through the emitter.

Then, at this time, with the junction saturation voltage V _BE of the second transistor Q 2 as V _{BE —} Q 2, the potential of the internal signal line SL is clamped at 0 V + V _{BE —} Q 2.
Therefore, when the power supply VDD is on and the operation mode of the processor 12 is in the standby mode, the voltage of the internal signal line SL is limited so as not to exceed V _BE _Q 2.
When the operation mode of the processor 12 is the standby mode, communication using the communication line SL is not performed. In addition, since Darlington connection circuit 500 having a large hfe (amplification factor) is used as a circuit for drawing current to ground GND, the base current of the second transistor Q2 flowing through the second resistor R2 is small, and the second resistor R2 One end is maintained at approximately 0V.

Therefore, by using a transistor having an appropriate V _BE value as the second transistor Q 2, when the power supply VDD is on and the operation mode of the processor 12 is in the standby mode, an overvoltage exceeding the rated voltage range is generated. The application to the processor 12 can be suppressed.

  Further, according to such a protection circuit 13, the power supply of the voltage V1 is supplied while the power supply VDD is on, and the first transistor Q1 is controlled to be in the off state when the processor 12 is in the standby mode. The consumption of the power of the power supply Vdd by the protection circuit 13 can be made zero.

Next, in the protection circuit 13 in the state where the power supply VDD is off, that is, the power supply VDD supplied to the power supply terminal 121 of the processor 12 is 0 V or the power supply VDD is not connected to the power supply terminal 121 of the processor 12. The operation is the same as the operation when the power supply VDD is on and the operation mode of the processor 12 is the standby mode shown in FIG. 5b, and the voltage of the internal signal line SL is limited so as not to exceed V _BE _Q 2 Be done.

  Next, in such a protective circuit 13, as shown in FIG. 6c, when a voltage lower than the ground GND is applied to the communication line CL, the internal signal line SL is connected to the ground GND via the first diode D1. The potential of the internal signal line SL is maintained at the potential obtained by subtracting the forward voltage VF_D1 of the first diode D1 from the potential of the ground GND.

  The embodiments of the present invention have been described above.

  DESCRIPTION OF SYMBOLS 1 ... Processing apparatus, 11 ... Power supply circuit, 12 ... Processor, 13 ... Protection circuit, 121 ... Power supply terminal, 122 ... Terminal for communication, 500 ... Darlington connection circuit, D, D1, D2 ... Diode, R, R1, R2, R3 ... resistance, Q, Q1, Q2, Q3 ... transistor.

Claims (6)

An overvoltage protection device for protecting a device transmitting a signal using a signal line from overvoltage,
A first switch controlled by the device to switch between on and off states, a resistor, and a second switch;
The first switch connects a power terminal, which is a terminal of the device to which power is supplied to the device when in the on state, and the first end of the resistor.
The second end of the resistor is connected to the ground of the device;
When the voltage of the signal terminal, which is a terminal of the device that inputs or outputs the signal transmitted through the signal line, is higher than the voltage of the first end of the resistor by a predetermined level or more, the second switch An overvoltage protection device which is turned on and connects the signal terminal of the device and the ground of the device. The overvoltage protection device according to claim 1, wherein
The overvoltage protection device, wherein the second switch is a Darlington connection circuit. An overvoltage protection device for protecting a device transmitting a signal using a signal line from overvoltage,
A first transistor, a second transistor, a third transistor, a first diode, a first resistor, and a second resistor,
In the first transistor, an emitter is connected to a power supply terminal which is a terminal of the device to which power of the device is supplied, and a base is connected to a terminal for outputting a control signal of the overvoltage protection device of the device. A PNP transistor whose collector is connected to the anode of the first diode,
The cathode of the first diode is connected to the first end of the first resistor,
The second end of the first resistor is connected to the ground of the device;
The second transistor has an emitter connected to a signal terminal which is a terminal of the device for inputting or outputting a signal transmitted through the signal line, and a base connected to the first end of the first resistor, A PNP transistor whose collector is connected to the first end of the second resistor,
The second end of the second resistor is connected to the ground of the device;
  The third transistor is an NPN transistor having a collector connected to the signal terminal of the device, a base connected to the first end of the second resistor, and an emitter connected to the ground of the device. An overvoltage protection device characterized by The overvoltage protection device according to claim 3, wherein
The forward voltage of the first diode is the junction saturation voltage (V of the second transistor). _BE An overvoltage protection device characterized in that it is equal to The overvoltage protection device according to claim 3 or 4, wherein
An overvoltage protection device, comprising: a second diode having a cathode connected to the collector of the third transistor and an anode connected to the ground of the device. The overvoltage protection device according to claim 5, wherein
An overvoltage protection device comprising: a resistor having a first end connected to the cathode of the second diode and a second end connected to the signal line.