JP6520656B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

  There is known a technique in which a heat generating portion is joined to a heat dissipation member by solder (solder) and cooled (see, for example, Patent Documents 1 and 2). In this technology, the adhesion between the heat dissipation member and the solder is important.

  Regarding this technology, it has been proposed to provide a Ni-P alloy layer on the surface of the heat dissipation member. By interposing the Ni-P alloy layer, the adhesion between the heat dissipation member and the solder is improved, and the heat dissipation efficiency is improved (see, for example, Patent Documents 1 and 2). Furthermore, it is known that solder wettability is improved by providing a Ni-B alloy layer on the Ni-P alloy layer (see, for example, Patent Document 2).

Japanese Patent Publication No. 61-20988 Unexamined-Japanese-Patent No. 2003-152141

  In the technique described above, the portion of the heat generating portion in contact with the solder is Cu (copper) having good adhesion to the solder. For example, the heat generating portion is a circuit board on which a semiconductor chip is mounted on the front surface side and a Cu plate is provided on the back surface (see, for example, Patent Document 2).

  A semiconductor chip having a large amount of heat generation, such as a high-performance CPU (Central Processing Unit), is directly bonded to the heat dissipation member by a thermal interface material (TIM, Thermal Interface Material) containing In (indium) solder. According to this structure, a large amount of heat generated by the semiconductor chip can be efficiently released.

  However, In is easily fused to the heat dissipating member containing Cu, but not fused to the semiconductor chip. Therefore, a Ti layer adhering to the semiconductor is provided on the back surface of the semiconductor chip, and a Ni layer adhering to both In and Ti is further provided on the Ti layer, whereby a semiconductor chip (heat generation portion) such as CPU and a heat dissipation member Is bonded with In solder. That is, a semiconductor chip having a large amount of heat generation such as a CPU and a heat radiating member are joined by a thermal interface material having a Ti layer, a Ni layer and an In layer (that is, In solder).

  However, the thermal conductivity of Ti is much smaller than that of Ni and In. Therefore, in the semiconductor device having the thermal interface material containing In, heat conduction is suppressed by the Ti layer, and there is a problem that there is a limit to the efficiency of heat dissipation. Then, this invention makes it a subject to solve such a problem.

  In order to solve the above problems, according to one aspect of the present invention, a semiconductor chip having an integrated circuit disposed on the front side and a semiconductor disposed on the back side and containing boron, and heat generated by the integrated circuit A thermal interface member including: a heat radiating member for emitting the heat; a barrier layer in contact with the semiconductor and at least a region in contact with the semiconductor includes nickel and boron; and a junction joining the barrier layer and the heat radiating member. A semiconductor device having the same is provided.

  According to the disclosed semiconductor device, the heat dissipation efficiency of the semiconductor device in which the semiconductor chip and the heat dissipation member are joined can be improved by the thermal interface material containing the low melting point metal (for example, In).

FIG. 1 is an example of a plan view for explaining the semiconductor device 18 according to the first embodiment. FIG. 2 is a view of a cross section taken along the line II-II in FIG. 1 as viewed from the direction of the arrow. FIG. 3 is a diagram for explaining the structure of the area A in FIG. FIG. 4 is a flowchart for explaining a method of manufacturing the semiconductor device 18 of the first embodiment. FIG. 5 is a cross-sectional view for explaining the method of manufacturing the semiconductor device 18. FIG. 6 is a cross-sectional view for explaining the method of manufacturing the semiconductor device 18. FIG. 7 is a cross-sectional view for explaining a semiconductor device 118 conventionally manufactured by the inventors. FIG. 8 is a table showing the adhesion and solderability of the Ni-B layer. FIG. 9 is a view for explaining the atomic level structure near the interface 46 between the Si substrate 50 and the Ni-B layer 52. As shown in FIG. FIG. 10 is a diagram for explaining the growth of the Ni-B layer. FIG. 11 is a view for explaining the peeling of the Ni-B layer. FIG. 12 is a diagram for explaining the solder barrier property of a pure Ni layer. FIG. 13 is a diagram for explaining the solder barrier property of a pure Ni layer. FIG. 14 is a diagram for explaining the atomic level structure of the region B in FIG. 12 (a). FIG. 15 is a view for explaining the atomic level structure of the region C in FIG. 13 (a). FIG. 16 is a diagram for explaining the solder barrier property of the Ni-B layer. FIG. 17 is a diagram for explaining the solder barrier property of the Ni-B layer. FIG. 18 is a diagram for explaining a modification 318 of the first embodiment. FIG. 19 is a cross-sectional view for explaining the semiconductor device 218 of the second embodiment. FIG. 20 is a flowchart for explaining a method of manufacturing the semiconductor device 218 of the second embodiment. FIG. 21 is a cross-sectional view for explaining the method of manufacturing the semiconductor device 218.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and the equivalents thereof. The parts having the same structure are denoted by the same reference numerals even if the drawings are different, and the description thereof is omitted.

Embodiment 1
(1) Structure FIG. 1 is an example of a plan view for explaining the semiconductor device 18 according to the first embodiment. FIG. 2 is a view of a cross section taken along line II-II in FIG. 1 as viewed in the direction of the arrow. FIG. 3 is a diagram for explaining the structure of the area A in FIG. The heat sink 22 is shown with the semiconductor device 18 by FIGS. Also shown in FIG. 2 is a circuit board 20 (eg, a system board). The heat sink 22 is, for example, a heat dissipating member having fins (not shown).

  In the example shown in FIGS. 1 and 2, the semiconductor device 18 is electrically connected to the circuit board 20 via the solder bumps 24 (see FIG. 2). Further, in the example shown in FIGS. 1 and 2, the semiconductor device 18 is connected to the heat sink 22 via a thermal grease 28 containing, for example, Ag particles. The heat sink 22 is fixed to the circuit board 20 by, for example, a support 26.

  The heat sink 22 is a heat dissipating member that releases the heat generated by the semiconductor device 18. The thermal grease 28 is a thermal interface material (TIM) that reduces the interface thermal resistance (contact thermal resistance) between the semiconductor device 18 and the heat sink 22.

  As shown in FIG. 3, the semiconductor device 18 according to the first embodiment has a semiconductor chip 6, a heat dissipation member 8 and a thermal interface member 14. The semiconductor device 18 may have a package substrate 30 (see FIG. 2). The semiconductor chip 6 is electrically connected to the package substrate 30 by, for example, solder bumps 124.

-Semiconductor chip-
The semiconductor chip 6 of the first embodiment is a semiconductor element having an integrated circuit 2 (see FIG. 3) disposed on the front side and a semiconductor 4 (eg, silicon) disposed on the back side and containing boron (B). is there. Specifically, the semiconductor 4 is, for example, a p-type Si substrate doped with B. The concentration of B is, for example, 10 ¹³ to 10 ¹⁷ atoms / cm ³ . The integrated circuit 2 is, for example, a CPU formed on the surface side of a p-type Si substrate.

-Heat dissipation member-
The heat dissipation member 8 of the first embodiment is a member that releases the heat generated by the integrated circuit 2. The heat dissipation member 8 is, for example, a lid formed of Cu or Al.

-Thermal interface member-
The thermal interface member 14 of the first embodiment is a member that reduces the interface thermal resistance between the semiconductor chip 6 and the heat dissipation member 8. The thermal interface member 14 has a barrier layer 10 and a junction 12. The thermal interface member 14 joins the semiconductor chip 6 and the heat dissipation member 8.

  The barrier layer 10 is a layer of Ni (nickel) in contact with the semiconductor 4 and containing B. That is, the barrier layer 10 is a layer containing B and Ni. Hereinafter, the layer of Ni containing B is called a Ni-B layer. The thickness of the barrier layer 10 is, for example, 100 nm or more and 400 nm or less (for example, 200 nm).

  The Ni-B layer is a metal layer having a solder barrier property higher than Ni (see “(4-4) solder barrier property”). Therefore, the barrier layer 10 of Embodiment 1 is suitable as a barrier layer.

  The bonding portion 12 is, for example, a metal layer for bonding the barrier layer 10 and the heat dissipation member 8. Specifically, for example, the bonding portion 12 is a metal layer including In (indium) disposed between the heat dissipation member 8 and the barrier layer 10 and fused to both the heat dissipation member 8 and the barrier layer 10.

  The heat generated by the integrated circuit 2 mainly propagates to the heat dissipation member 8 mainly through the thermal interface member 14. Part of the heat that has reached the heat dissipation member 8 is transmitted to the heat sink 22 via the thermal grease 28, and the remaining heat is mainly released from the heat dissipation member 8 to the atmosphere. The heat that has reached the heat sink 22 is mainly released to the atmosphere.

  As described later, the Ni-B layer adheres to the B-doped semiconductor (see “(4-1) Adhesion”). Therefore, the thermal interface member 14 and the semiconductor chip 6 are in close contact (stiff adhesion) even if a high thermal resistance Ti layer (that is, a layer of low thermal conductivity Ti) is not disposed between the semiconductor 4 and the barrier layer 10 ).

  Therefore, according to the first embodiment, the heat dissipation efficiency of the semiconductor device 18 in which the semiconductor chip 6 and the heat dissipation member 8 are joined can be improved by the thermal interface material containing a low melting point metal such as In (( 2) Thermal resistance "). The thermal interface member 14 is a thermal interface material in which the semiconductor chip 6 and the heat dissipation member 8 are joined (see “(2) Manufacturing method”).

(2) Manufacturing Method FIG. 4 is a flowchart for explaining a method of manufacturing the semiconductor device 18 according to the first embodiment. 5 to 6 are cross-sectional views for explaining the method of manufacturing the semiconductor device 18.

(2-1) Formation of barrier layer (see FIG. 5A)
A substrate 32 is prepared in which the integrated circuit 2 is formed on the front side and the semiconductor 4 containing boron is disposed on the back side. The substrate 32 is, for example, a p-type silicon wafer doped with B and having the integrated circuit 2 formed on the surface side. That is, the semiconductor 4 is, for example, a p-type silicon wafer doped with B.

  The back side of the substrate 32 is back ground and thinned to about 500 μm. As shown in FIG. 5A, the barrier layer 110 in contact with the semiconductor 4 is formed on the back surface of the substrate 32 by electroless plating (S2).

  The plating time of the barrier layer 110 is, for example, about 1800 seconds. The barrier layer 110 is, for example, a layer of Ni containing 0.5% by weight (0.5% by weight) of B.

(2-2) Mounting on Package Substrate Next, the substrate 32 is singulated by dicing, for example, to form the semiconductor chip 6. The semiconductor chip 6 is mounted on the package substrate 30 (see FIG. 2) via the solder bumps 124 (S4).

(2-3) Mounting on Circuit Board The package board 30 on which the semiconductor chip 6 is mounted is mounted on the circuit board 20 (see FIG. 2) (S6).

(2-4) Arrangement of bonding material (refer to FIG. 5 (b))
As shown in FIG. 5B, the bonding material 34 is disposed on the barrier layer 110 (S8). The bonding material 34 is, for example, a 100 μm thick In foil (ie, In solder). In FIG. 5B, the circuit board 20 is omitted (the same applies to FIGS. 6A to 6B).

  As described later, the solder wettability of the Ni-B layer is good (see “(4-3) solder wettability”). Therefore, the barrier layer 110 (see FIG. 6), which is a Ni-B layer, may not be covered with an oxidation suppression layer such as an Au layer.

(2-5) Bonding (see FIGS. 6 (a) and 6 (b))
Finally, the heat dissipation member 8 is bonded to the barrier layer 110 by the bonding material 34 (S10). The heat dissipation member 8 is, for example, a lid formed of Cu. Thus, the semiconductor device 18 is completed.

  Specifically, first, the heat dissipation member 8 is placed on the bonding material 34 so as to cover the semiconductor chip 6 (see FIG. 6A). Thereafter, the bonding material 34 is melted by reflow, and the heat dissipation member 8 and the bonding material 34 are bonded. The reflow temperature is, for example, 180.degree. The reflow time is, for example, 60 seconds. The reflow atmosphere is nitrogen. The reflow temperature may be 160 ° C to 220 ° C. The reflow time may be 30 seconds to 120 seconds.

  The bonding material 34 is melted by reflow and fills the gap between the heat dissipation member 8 and the barrier layer 110. In remaining without filling the gap is pushed out from between the heat dissipation member 8 and the barrier layer 110 by the weight of the heat dissipation member 8.

  A large number of asperities exist on the back surface of the semiconductor chip 6. This unevenness is reflected on the barrier layer 110, and a large number of unevenness is also generated on the surface of the barrier layer 110. Similarly, the surface of the heat dissipation member 8 also has a large number of irregularities. Therefore, even if the barrier layer 110 is in contact with the heat dissipation member 8, the portion of the barrier layer 110 actually contacting is small. Therefore, most of the area of the barrier layer 110 faces the heat dissipation member 8 with a gap. The bonding portion 12 fills such a gap to reduce the interface thermal resistance between the semiconductor chip 6 and the heat dissipation member 8.

-Bonding process-
When the bonding material 34 melts, it reacts with the barrier layer 110 to form an Intermetallic Compound 36 between the bonding material 34 (see FIG. 6B) and the barrier layer 110. The intermetallic compound 36 is, for example, an alloy of In and Ni. An intermetallic compound 136 is also formed between the bonding material 34 and the heat dissipation member 8. The intermetallic compound 136 is, for example, an alloy of Cu (a constituent element of the heat dissipation member 8) and Ni. The heat dissipating member 8 is bonded to the barrier layer 110 by the formation of the intermetallic compounds 36 and 136.

  The bonding portion 12 (see FIG. 3) of the semiconductor device 18 is a member having the intermetallic compounds 36 and 136 and the unreacted bonding material 34. The barrier layer 10 of the semiconductor device 18 described with reference to FIG. 3 is an unreacted portion of the barrier layer 110 formed by electroless plating.

(3) Ti / Ni / Au / In Thermal Interface Material FIG. 7 is a cross-sectional view for explaining a semiconductor device 118 conventionally manufactured by the inventors. FIG. 7 shows a state before the heat dissipation member 8 and the semiconductor chip 6 are joined by the thermal interface material 156.

  The thermal interface material 156 is a laminated film (hereinafter referred to as a Ti / Ni / Au / In laminated film) in which a Ti layer 38, an Ni layer 40, an Au layer 42, and an In layer 44 are laminated in this order. The Ti layer 38, the Ni layer 40 and the Au layer 42 are formed on the back surface of the semiconductor chip 6 by sputtering. The In layer 44 is an In foil placed on the Au layer 42. The thickness of the Ti layer 38 is, for example, 100 nm. The thickness of the Ni layer 40 is, for example, 300 nm.

  After formation of the thermal interface material 156 (Ti / Ni / Au / In laminated film), the heat dissipation member 8 is placed on the thermal interface material 156. The heat dissipation member 8 is a lid formed of, for example, Cu. After the heat dissipation member 8 is placed, the Ni layer 40 and the In layer 44 are joined and the heat dissipation member 8 and the In layer 44 are joined by reflow.

  When In is melted by reflow, it reacts with a constituent element (for example, Cu) of the heat dissipation member 8 to form an intermetallic compound. By this intermetallic compound, In and the heat dissipation member 8 are bonded (ie, fused). However, In does not fuse with semiconductors such as silicon. Therefore, a laminated film of Ti layer 38, Ni layer 40 and Au layer 42 (hereinafter referred to as Ti / Ni / Au laminated film) is provided between semiconductor chip 6 and In layer 44, and Ti layer 38 and Ni layer 40 are formed. And the semiconductor chip 6 and the In layer 44 are bonded to each other.

  In and Ni fuse well. However, when the surface of the Ni layer 40 is oxidized, the Ni layer 40 and the In layer 44 do not fuse. Therefore, the Au layer 42 is disposed on the Ni layer 40 to suppress the oxidation of the Ni layer 40. When the In layer 44 is melted by reflow or the like, the Au layer 42 is absorbed by the In layer 44 and disappears. Therefore, even if the Au layer 42 is disposed, the reaction between the In layer 44 and the Ni layer 40 is not hindered.

  By the way, Ti and In do not fuse. Therefore, even if only the Ti layer 38 is provided on the back surface of the semiconductor chip 6, the semiconductor chip 6 and the heat dissipation member 8 can not be joined. On the other hand, Ni adheres to both Ti and In. Therefore, the Ni layer 40 is provided on the Ti layer 38, and the Ni layer 40 and the In layer 44 are fused.

  However, the thermal conductivity of Ti is much smaller than the thermal conductivity of Ni and In. For example, the thermal conductivity of Ti is 17 W / m · K. The thermal conductivity of Ni is 90 W / m · K. Therefore, in the semiconductor device 118 of FIG. 7 having a Ti layer, the heat conduction is suppressed by the Ti layer 38, and therefore, there is a problem that the efficiency of the heat generated by the integrated circuit 2 is limited.

  As described above, the Ti / Ni / Au laminated film is formed by sputtering. Sputtering is performed using a sputtering apparatus evacuated for several minutes. Therefore, the formation time of the Ti / Ni / Au laminated film is about 1 hour at the shortest. On the other hand, the barrier layer 110 of the first embodiment does not include a Ti layer which is difficult to form a plating. Therefore, the barrier layer 110 of the first embodiment can be formed by plating for a relatively short time (for example, 1800 seconds). Therefore, according to the first embodiment, the manufacturing time of the semiconductor device 18 in which the semiconductor chip 6 and the heat dissipation member 8 are joined can be shortened by the thermal interface material 56 containing In solder or the like.

(4) Characteristics of Barrier Layer FIG. 8 is a table (hereinafter referred to as Table 1) showing the adhesion of the Ni-B layer and the solder wettability. The second column of Table 1 shows the characteristics of a pure Ni layer not containing B (hereinafter referred to as a pure Ni layer).

  The third column of Table 1 shows the characteristics of the Ni-B layer containing 0.3 wt% B. The fourth column of Table 1 shows the characteristics of the Ni-B layer containing 1.0 wt% B. The fifth column of Table 1 shows the characteristics of the Ni-B layer containing 3.0 wt% B. The sixth column of Table 1 shows the characteristics of a layer of Ni containing 7.0% by weight of P (phosphorus) (hereinafter referred to as the Ni-P layer).

The concentrations of B and P were measured by ICP-AES (Inductively Coupled Plasma Auger Electron Spectroscopy). The Ni-based metal layer (pure Ni layer, Ni-B layer, Ni-P layer) of each row was grown by electroless plating on a silicon substrate doped with B (hereinafter referred to as B-doped Si substrate) It is a 3 μm thick metal layer. The B concentration of the Si substrate is 10 ¹³ to 10 ¹⁷ cm ⁻³ . If it is in this range, the evaluation result (characteristics of Table 1) of each Ni-based metal layer did not depend on the B concentration of the Si substrate.

  The second row of Table 1 shows the adhesion between the B-doped Si substrate and the Ni-based metal layer. “X” indicates that the grown Ni-based metal layer was peeled off from the B-doped Si substrate. “○” indicates that the grown Ni-based metal layer did not peel from the B-doped Si substrate. "(Triangle | delta)" has shown that the case where the grown Ni type metal layer exfoliated, and the case where it did not exfoliate were both.

  The third row of Table 1 shows the solder wettability of the Ni-based metal layer. “×” indicates that molten In is repelled by the Ni-based metal layer and does not cover a part or the entire surface of the Ni-based metal layer. "(Circle)" has shown that fuse | melted In covers substantially the whole surface of Ni-type metal layer. The conditions for melting In are the same as the conditions for reflow (180 ° C., 60 seconds) described in “(2) Manufacturing method”.

  To evaluate the solderability of Ni-B layers containing 1.0 wt% or 3.0 wt% B, plating grown on B-doped Si substrate via 0.3 wt% Ni-B layers A layer (e.g., a 1.0 wt% Ni-B layer) was used. The plated layer (for example, pure Ni layer) grown through the Ti layer on the Si substrate was used to evaluate the solder wettability of the pure Ni layer and the Ni-P layer.

(4-1) Adhesion As shown in the second column and the second row of Table 1, a pure Ni layer does not adhere to a B-doped Si substrate. Although not shown in Table 1, the pure Ni layer does not adhere to Si substrates other than B-doped (for example, P-doped Si substrates and non-doped Si substrates).

  As shown in the second row of the third to fourth columns of Table 1, when the B concentration is 0.3% by weight or more, the Ni-B layer adheres to the B-doped Si substrate. That is, the adhesion between the Ni-B layer and the B-doped Si substrate is good.

  However, when the B concentration exceeds 1.0% by weight, the Ni--B layer hardly adheres to the B-doped Si substrate (see the second row of the fifth column in Table 1). Therefore, the preferable B concentration range of the barrier layer 10 is 0.3% by weight or more and 1.0% by weight or less. A further preferable B concentration range is 0.4% by weight or more and 0.9% by weight or less. The most preferable range of B concentration is 0.5% by weight or more and 0.8% by weight or less.

  FIG. 9 is a view for explaining the atomic level structure near the interface 46 between the Si substrate 50 and the Ni-B layer 52. As shown in FIG. The elemental symbol (for example, "Si") in FIG. 9 represents an atom (for example, a Si atom) of the element corresponding to the elemental symbol. The same applies to FIG. A line segment 48 between elemental symbols indicates that atoms in contact with both ends of the line segment 48 are bonded to each other.

  As shown in FIG. 9, Ni atoms and Si atoms do not bond. Therefore, the pure Ni layer and the Si substrate do not adhere to each other. On the other hand, Ni atoms bond to B atoms. Therefore, when the Si substrate 50 contains B atoms, B atoms 54 (see FIG. 9) in the Si substrate 50 and B atoms 154 in the Ni—B layer 52 are bonded. By this bonding, the Si substrate 50 and the Ni-B layer 52 adhere tightly (that is, adhere).

  Table 1 (see FIG. 8) also shows the adhesion of the Ni-P layer. As shown in Table 1, the Ni-P layer does not adhere to the B-doped Si substrate. Although not shown in Table 1, the Ni-P layer does not adhere to Si substrates other than B-doped.

  In addition, P density | concentration of Ni-P layer of Table 1 is 7.0 weight%. This is because it is difficult to form an Ni-P layer of 3.0% by weight or less by electroless plating.

-Growth of Ni-B layer-
FIG. 10 is a diagram for explaining the growth of the Ni-B layer.

  When the back surface of the Si substrate 50 comes in contact with the electroless plating solution 58 (hereinafter referred to as a plating solution), B atoms 54 exposed on the back surface of the Si substrate 50 are B atoms (or B ions in the plating solution 58) 254 Joins. A Ni atom (or Ni ion, hereinafter the same) 60 in the plating solution is sequentially bonded to the B atom 254 to grow a Ni-B layer. Therefore, the Ni—B layer grows with the B atom 254 bonded to the back surface of the Si substrate 50 as a nucleus.

  The B atoms 245 are uniformly bonded to the entire back surface of the Si substrate 50 one by one. Then, nuclei of uniform size are uniformly formed on the entire back surface of the Si substrate 50. From these nuclei, a uniform, non-uniform Ni-B layer that hardly peels off from the base grows and adheres to the Si substrate 50.

  It is thought that a Ni-B film (see Table 1) having a B concentration of 1.0 wt% or less adheres to the Si substrate 50 without peeling from the Si substrate 50 by such a mechanism.

-Peeling of Ni-B layer-
FIG. 11 is a view for explaining the peeling of the Ni-B layer. When the concentration of hydrogen ions in the plating solution 58 decreases, B atoms are likely to precipitate out of the plating solution 58. Then, another B atom 354 is further bonded to the B atom 254 bonded to the Si substrate 50 to generate a mass 64 of B atoms 254 and 354 (see FIG. 11). A Ni-B layer having a high B concentration grows with the B atom clusters 64 as nuclei.

  The number of B atoms contained in the mass 64 is not constant but fluctuates. As a result, a large number of irregular nuclei of size are generated on the back surface of the Si substrate 50. From these nuclei, a non-uniform and uneven Ni-B layer which easily peels off from the substrate grows.

  Increasing the B concentration further increases the internal stress of the Ni-B layer. Therefore, the Ni-B layer having a high B concentration is further easily peeled off from the Si substrate 50.

  Therefore, as the B concentration in the Ni-B layer 52 (see FIG. 9) increases, the force to peel the Ni-B layer 52 from the Si substrate 50 increases. Finally, when the force to peel off the Ni-B layer exceeds the bonding force between B atoms 54 and 154 which make the Si substrate 50 and the Ni-B layer 52 adhere, the Si substrate 50 to the Ni-B layer 52 peels off.

  A Ni-B layer (see Table 1) having a B concentration of greater than 1.0 wt% is considered to be peeled off from the Si substrate 50 by such a mechanism.

  By the way, when a P-doped Si substrate is used as a substrate, P atoms of the P-doped Si substrate and P atoms of the Ni-P layer are bonded to each other, and it seems that the P-doped Si substrate and the Ni-P layer are in close contact.

  However, the Ni-P layer does not adhere to the P-doped Si substrate. This is considered to be because formation of a Ni-P layer whose P concentration is 3.0% by weight or less is difficult.

  A Ni-P layer having a P concentration of more than 3.0% by weight is considered to be nonuniform and to have a large internal stress. Such a Ni-P layer is easily peeled off from the P-doped Si substrate and does not adhere to the P-doped Si substrate.

(4-2) Thermal Resistance As described in “(4-1) Adhesion”, the Ni—B layer adheres to the B-doped Si substrate. Therefore, the barrier layer 10 (see FIG. 3), which is a Ni—B layer, adheres closely to the semiconductor 4 doped with B on the back surface side of the semiconductor chip 6. Therefore, in the first embodiment, the Ti layer is not provided between the barrier layer 10 and the semiconductor chip 6.

  The thermal conductivity (17 W / m · K) of Ti is about 1⁄4 of the thermal conductivity (90 W / m · K) of Ni and Ni-B. Therefore, the thermal resistance of the thermal interface member 14 of the first embodiment is smaller than the thermal resistance of the thermal interface material 156 having the Ti layer 38 (see FIG. 7). Therefore, according to the first embodiment, the heat dissipation efficiency of the semiconductor device in which the semiconductor chip 6 and the heat dissipation member 8 are joined can be improved by the thermal interface material containing the low melting point metal (for example, In).

Now, the thicknesses of the Ti layer 38 and the Ni layer 40 of the thermal interface material 156 (see FIG. 7) are set to 100 nm and 200 nm, respectively. In this case, the thermal resistance of the base portion of the thermal interface material 156 (the laminated film of the Ti layer 38 and the Ni layer 40) is 8.1 × 10 ⁻⁹ m ² · K / W (= 100 × 10 ⁻⁹ / 17 + 200 × 10 ⁻⁹ / 90).

On the other hand, when the thickness of the barrier layer 10 is 200 nm, the thermal resistance of the base portion (barrier layer 10) of the thermal interface member 14 of the first embodiment is 2.2 × 10 ⁻⁹ m ² · K / W (= 200 × 10 ⁻⁹ / 90). In this example, the thermal resistance of the base portion of the thermal interface member 14 of Embodiment 1 is about 1⁄4 of the thermal resistance of the base portion of the thermal interface material 156 having the Ti layer 38. As described above, according to the first embodiment, it is possible to improve the heat dissipation efficiency of a semiconductor device in which the semiconductor chip 6 and the heat dissipation member 8 are joined by a thermal interface material containing a low melting point metal (for example, In).

  By the way, if the Ti layer 38 (see FIG. 7) is thinned, the thermal resistance of the thermal interface material 156 is reduced. However, if the Ti layer 38 is made too thin, it will be difficult for the Ni layer 40 and the semiconductor chip 6 to be in close contact. Specifically, when the Ti layer 38 is less than 100 nm, the Ni layer 40 and the semiconductor chip 6 do not easily adhere to each other.

(4-3) Solder wettability As shown in the third row of the second column of Table 1, the solder wettability of a pure Ni layer is low. Pure Ni is easily oxidized, and the surface is covered with an oxide film. Since the oxide film repels molten In, the Ni layer does not get wet with the molten In.

  On the other hand, the solder wettability of the Ni-B layer is good as shown in the third row of the third to fifth columns of Table 1. Therefore, the barrier layer 110 (see FIG. 6), which is a Ni-B layer, fuses with In even if it is not covered with the Au layer. However, in order to ensure that the bonding material 34 is fused to the barrier layer 110, the barrier layer 110 may be covered with an Au layer.

  However, when the B concentration of the Ni-B layer is too high (for example, when the B concentration is 10%), the Ni-B layer does not get wet with In. In the first embodiment, the B concentration of the barrier layer 110 which is a Ni-B layer is, for example, 0.5% by weight. If the B concentration is this level, the solder wettability of the Ni-B layer is sufficiently ensured.

  The third row of the sixth column in Table 1 also shows the solder wettability of Ni-P. As shown in Table 1, the solder wettability of Ni-P is as low as pure Ni.

(4-4) Solder barrier property The low melting point metal (for example, In) reacts with the barrier layer to form an intermetallic compound and adheres to the barrier layer. However, when the intermetallic compound is excessively formed, all the barrier layers react with the low melting point metal, and the intermetallic compound and the semiconductor chip (or Ti layer) are in direct contact. Then, the intermetallic compound peels off from the semiconductor chip. Therefore, the ability to suppress the contact between the intermetallic compound and the semiconductor chip (hereinafter referred to as solder barrier property) is important for the barrier layer.

  When an Ni—B layer is used as a barrier layer, B is swept out (deposited) on the Ni—B layer when an intermetallic compound is formed. When the formation of the intermetallic compound does not stop midway and all the Ni-B layer changes to an intermetallic compound, a large amount of B is swept out between the intermetallic compound and the semiconductor chip to form a B segregation layer. .

  Then, the intermetallic compound is blocked by the segregation layer of B and can not contact the semiconductor chip. Therefore, even if the Ni-B layer reacts almost all with the low melting point metal, the intermetallic compounds of the low melting point metal and the Ni-B layer do not peel off from the semiconductor chip. The formation of such a segregation layer is confirmed by EPMA (Electron Probe MicroAnalyzer).

  On the other hand, when a pure Ni layer is used as the barrier layer, the intermetallic compound comes in contact with the semiconductor chip (precisely, the Ti layer provided on the back surface of the semiconductor chip) and peels off from the semiconductor chip.

  For this reason, according to Embodiment 1 in which the Ni-B layer is provided as the barrier layer, peeling of the thermal interface material due to reflow or subsequent time-dependent change is more than in the case of using the Ti / Ni / Au / In thermal interface material (TIM). It is hard to happen. The solder barrier property of the pure Ni layer and the solder barrier property of the Ni-B layer will be described in detail below with reference to the drawings.

-Solder barrier property of pure Ni layer-
12-14 is a figure explaining the solder barrier property of a pure Ni layer.

  Now, consider the case where a thermal interface material 156 having a Ti layer 38 is formed on the back surface of the semiconductor chip 6 as shown in FIG. 12 (a). The thermal interface material 156 is a Ti / Ni / Au / In laminated film (see “(3) Ti / Ni / Au / In thermal interface material”).

  When a heat dissipation member (not shown) is placed on the thermal interface material 156 and the In layer 44 is melted by reflow or the like, In and Ni react to form a metal of In and Ni between the In layer 44 and the Ni layer 40. An intermediate compound 236 (see FIG. 12 (b)) is produced. By this intermetallic compound 236, the In layer 44 and the Ni layer 40 adhere to each other. Similarly, a constituent element (for example, Cu) of the heat dissipation member reacts with In to generate an intermetallic compound (not shown), and the heat dissipation member and the In layer 44 adhere to each other.

  When the integrated circuit 2 of the semiconductor chip 6 is operated after completion of the semiconductor device, the thermal interface material 156 is exposed to the heat generated by the integrated circuit 2. Then, the intermetallic compound 236 of In and Ni gradually grows to erode the Ni layer 40. When the semiconductor chip 6 is used for a long time, the intermetallic compound 236 finally reaches the Ti layer 38 (see FIG. 13A). Then, portions of the thermal interface material 156 other than the Ti layer 38 are peeled off from the semiconductor chip 6 (see FIG. 13B).

  FIG. 14 is a diagram for explaining the atomic level structure of the region B in FIG. 12 (a). In the thermal interface material 156 before reflow, a bond is formed across the interface 146 between the Ni atoms in the Ni layer 40 (see FIG. 14) and the Ti atoms in the Ti layer 38. This bonding causes the Ni layer 40 and the Ti layer 38 to adhere.

  FIG. 15 is a view for explaining the atomic level structure of the region C in FIG. 13 (a). As shown in FIG. 15, in the thermal interface material 156 (see FIG. 13A) immediately before peeling, In atoms as constituent elements of the intermetallic compound 236 reach the Ti layer 38 and are bonded to the Ti atoms. Replace the Ni atom. Since the In atoms do not bond to the Ti atoms, the bonds across the interface 246 are reduced, and the thermal interface material 156 is easily peeled off from the Ti layer 38. As a result, as shown in FIG. 13B, the portion of the thermal interface material 156 other than the Ti layer 38 is peeled off from the semiconductor chip 6. That is, the barrier properties of the Ni layer are not perfect.

-Solder barrier property of Ni-B layer-
16 to 17 illustrate the solder barrier properties of the Ni-B layer. Now, consider the case where the thermal interface material 56 is formed on the back surface of the semiconductor chip 6 as shown in FIG. The thermal interface material 56 is a laminated film of the Ni-B layer 52 and the In layer 44.

  When a heat dissipation member (not shown) is placed on the thermal interface material 56 and the In layer 44 is melted by reflow or the like, the In and Ni react to form In and Ni between the In layer 44 and the Ni-B layer 52. The intermetallic compound 236 (see FIG. 16 (b)) is formed. By this intermetallic compound 236, the In layer 44 and the Ni-B layer 52 adhere to each other. The B atoms contained in the Ni-B layer 52 are not taken into the intermetallic compound 236 and are swept out to the Ni-B layer 52. Similarly, a constituent element (for example, Cu) of the heat dissipation member reacts with In to generate an intermetallic compound (not shown), and the heat dissipation member and the In layer 44 adhere to each other.

When the integrated circuit 2 of the semiconductor chip 6 is operated after completion of the semiconductor device 18, the thermal interface material 56 is exposed to the heat generated by the integrated circuit 2. Then, the intermetallic compound 236 of In and Ni gradually grows to erode the Ni-B layer 52. When the semiconductor chip 6 is used for a long time, finally, the Ni-B layer 52 almost completely changes to the intermetallic compound 236 (see FIG. 17). Furthermore, the B atoms swept out of the intermetallic compound 236 accumulate between the intermetallic compound 236 and the semiconductor 4 to form a layer in which B is segregated (hereinafter referred to as a segregated layer 66). Since In does not react with B, In atoms can not be advanced by the segregation layer 66 and can not contact the semiconductor chip 6. Therefore, even if the semiconductor chip 6 is used for a long time, the intermetallic compound 236 hardly peels off the semiconductor chip 6. Thus, the barrier properties of Ni-B layers are higher than pure Ni layers. The segregation layer 66 is a layer having a high B concentration containing, for example, Ni ₂ B and the like.

  The barrier layer 10 of the first embodiment is a Ni-B layer higher in solder barrier property than a pure Ni layer. Therefore, the barrier layer 10 of the first embodiment may be thinner than the Ni layer 40 (barrier layer) of the Ti / Ni / Au / In thermal interface material 156 (see FIG. 7). Therefore, according to the first embodiment, thinning of the barrier layer is possible. By thinning the barrier layer, the thermal resistance of the thermal interface member 14 of the first embodiment is further reduced.

(5) Modification FIG. 18 is a view for explaining a modification 318 of the first embodiment.

  In the example described with reference to FIG. 3, the entire barrier layer 10 is a Ni—B layer having a constant B concentration. However, in the barrier layer 10, the first region 68a (see FIG. 18) in contact with the semiconductor 4 includes B and Ni, and the second region 68b on the first region 68a includes, for example, only Ni (ie, pure Ni Layer).

  Even in such a case, the barrier layer 10 adheres to the semiconductor 4 because the first region 68 a in contact with the semiconductor 4 contains B. Therefore, also in this case, the thermal resistance of the thermal interface member 14 can be reduced without providing the Ti layer 38.

  In the barrier layer 310 of the modification 318, the first region 68a in contact with the semiconductor 4 is a layer including B and Ni. The second region 68 b on the first region 68 a may be a region different in composition from the first region 68 a as long as it is a region to be joined to the bonding material 34.

  The second region 68 b may be, for example, a pure Ni region. The second region 68b may be a region of Ni-B containing B at a lower concentration than the first region 68a. The second region 68 b may be a Cu region. The modification 318 can be manufactured by forming the barrier layer 310 in which the region 68a in contact with the semiconductor 4 includes Ni and B, instead of the barrier layer 110 described with reference to FIG.

  The preferred B concentration of the first region 68a is the same as the preferred B concentration of the barrier layer 110 described with reference to FIG. That is, the preferable B concentration range of the first region 68a is 0.3% by weight or more and 1.0% by weight or less. A further preferable B concentration range is 0.4% by weight or more and 0.9% by weight or less. The most preferable range of B concentration is 0.5% by weight or more and 0.8% by weight or less.

(6) Application Example The semiconductor device 18 of the first embodiment preferably includes the semiconductor chip 6 having a large amount of heat generation. Specifically, the semiconductor chip 6 is a semiconductor element having an integrated circuit 2 such as a CPU, a graphic card, and a memory. The semiconductor device 18 is mounted on, for example, a circuit board (for example, a system board) of a server or a super computer.

  In the above example, the bonding material 34 (solder) is In. However, the bonding material 34 may be a low melting point metal other than In. The bonding material 34 may be, for example, an alloy containing In and Ag (i.e., an In-Ag alloy). The concentration of Ag is, for example, 1% by weight or more and 10% by weight or less.

  The bonding material 34 may be Sn or an alloy of Sn and Ag. The Ni-B layer also has high solder barrier properties and high solder wettability with respect to these bonding materials (solder).

  As described above, the barrier layers 10 and 310 of the first embodiment are in contact with the semiconductor 4 and at least a region in contact with the semiconductor 4 is a barrier layer containing Ni and B. The barrier layer 10 adheres to the semiconductor 4 by the region containing Ni and B. Therefore, no Ti layer is provided between the barrier layer 10 and the semiconductor chip 6. Therefore, according to the first embodiment, the heat dissipation efficiency of the semiconductor device in which the semiconductor chip and the heat dissipation member are joined can be improved by the thermal interface material containing the low melting point metal (for example, In).

  In addition, since the Ni-B layer has a higher solder barrier property than the Ni layer, according to the first embodiment, it is possible to suppress peeling of the thermal interface member 14 (see FIG. 3) due to reflow or aging.

Second Embodiment
The second embodiment is different from the first embodiment in that the barrier layer has a high B concentration in the region on the surface side. In the other points, the second embodiment is substantially the same as the first embodiment. Therefore, the description of the same parts as the first embodiment will be omitted or simplified.

(1) Structure FIG. 19 is a cross-sectional view for explaining the semiconductor device 218 of the second embodiment. The structure between the semiconductor chip 6 and the heat dissipation member 8 is shown in FIG. The barrier layer 210 of the second embodiment has a lower barrier region 16 and an upper barrier region 116 as shown in FIG. “○” in FIG. 19 represents the concentration of B atoms. The density of "o" was increased in the region of high B concentration, and the density of "o" was decreased in the region of low B concentration. The same applies to FIG.

  The lower barrier region 16 is a Ni-B layer in contact with the semiconductor 4. The upper barrier region 116 is a Ni—B layer disposed between the lower barrier region 16 and the junction 12 and having a higher B concentration than the lower barrier region 16. The B concentration (first concentration) of the lower barrier region 16 is, for example, 0.3% by weight. The B concentration (second concentration) of the upper barrier region 116 is, for example, 2.0% by weight. Except for the above points, the structure of the semiconductor device 218 is substantially the same as the structure of the semiconductor device 18 (see FIG. 3) of the first embodiment.

  As described in the first embodiment, even if the barrier layer 10 (see FIG. 3), which is a Ni-B layer, is eroded by the bonding portion 12 (for example, In solder) and disappears, the intermetallic compound 236 (see FIG. 17) is blocked by the segregation layer 66 of B and does not contact the semiconductor chip 6. Therefore, even if the semiconductor device 18 (see FIG. 3) is used for a long time, the thermal interface member 14 hardly peels off. The barrier properties of such a Ni-B layer become higher as the segregation layer 66 of B becomes thicker.

  The segregation layer 66 becomes thicker as the amount of B swept out from the Ni-B layer increases. Therefore, the higher the B concentration in the Ni-B layer, the higher the solder barrier property of the Ni-B layer. On the other hand, when the B concentration becomes too high, the adhesion of the Ni-B layer to the semiconductor chip 6 becomes low (see “(4-1) Adhesion” in the first embodiment).

  According to the second embodiment, a large amount of B is supplied to the segregation layer 66 by the upper barrier region 116 having a high B concentration while securing the adhesiveness of the barrier layer 210 by the lower barrier region 16 having a low B concentration. The solder barrier properties of layer 210 can be enhanced.

  Alternatively, even if the upper barrier region 116 having a high B concentration is thinned to some extent, a sufficient amount of B can be supplied to the segregation layer 66 to secure the solder barrier property. When the upper barrier region 116 is thinned, the entire barrier layer 210 is also thinned. Then, the thermal resistance of the barrier layer 210 is reduced, and the heat dissipation characteristics of the semiconductor device 218 are improved. Therefore, according to the second embodiment, the heat dissipation characteristic of the semiconductor device 218 can be improved more than the semiconductor device 18 of the first embodiment while securing the solder barrier property of the barrier layer 210.

  For example, when the B concentration of the upper barrier region 116 is 2.0% by weight, even if the thickness of the upper barrier region 116 is 100 nm, it is possible to secure the solder barrier property similar to that of the barrier layer 10 of the first embodiment. Furthermore, when B in the lower barrier region 16 is 0.3% by weight, the adhesion of the barrier layer 210 can be secured if the thickness of the lower barrier region 16 is about 50 nm.

  Therefore, the thickness of the barrier layer 210 can be, for example, 150 nm. This thickness is thinner than the thickness 200 nm of the barrier layer 10 exemplified in the first embodiment. As described above, according to the second embodiment, since the barrier layer 210 can be thinned, the heat dissipation characteristics of the semiconductor device 218 can be improved as compared to the semiconductor device 18 of the first embodiment.

  The preferred B concentration range of lower barrier region 16 and upper barrier region 116 can be derived from Table 1. The B concentration (first concentration) of the lower barrier region 16 is preferably 0.3% by weight or more and 1.0% by weight or less at which the Ni—B layer adheres to the semiconductor 4. The B concentration (second concentration) of the upper barrier region 116 is preferably a concentration greater than 1.0 wt% at which adhesion of the Ni-B layer to the semiconductor 4 becomes difficult.

  More preferably, the B concentration in the lower barrier region 16 is 0.4 wt% or more and 0.9 wt% or less, and the B concentration in the upper barrier region 116 is a concentration greater than 1.5 wt%. Most preferably, the B concentration in the lower barrier region 16 is 0.5 wt% or more and 0.8 wt% or less, and the B concentration in the upper barrier region 116 is a concentration greater than 2.5 wt% or more. However, the B concentration of the upper barrier region 116 is preferably 3.0% by weight or less at which barrier properties are confirmed.

  The thickness of the lower barrier region 16 is preferably 25 nm or more and 75 nm or less. The thickness of the upper barrier region 116 is preferably 50 nm or more and 150 nm or less.

(2) Manufacturing Method FIG. 20 is a flowchart for explaining a method of manufacturing the semiconductor device 218 of the second embodiment. FIG. 21 is a cross-sectional view for explaining the method of manufacturing the semiconductor device 218.

  In the manufacturing method of the second embodiment, “formation of lower barrier region” (S2 in FIG. 20) and “upper barrier region” are used instead of “formation of barrier layer” (see S2 in FIG. 4) in the first embodiment. It is different from the manufacturing method of the first embodiment in that “formation” (S4 in FIG. 20) is performed. Except for this point, the manufacturing method of the first embodiment and the manufacturing method of the second embodiment are substantially the same. Therefore, the description of the same portions (S6 to S12) as in the first embodiment is omitted.

(2-1) Formation of lower barrier region (see FIG. 21 (a))
A semiconductor substrate 70 (for example, a Si substrate) on which B is doped and the integrated circuit 2 (see FIG. 21A) is formed on the front surface side is back ground from the back surface to reduce the thickness to, for example, about 300 μm. By this process, the integrated circuit 2 is formed on the front surface side, and the substrate 132 on which the semiconductor 4 containing boron is disposed on the back surface side is formed.

  The lower barrier region 16 (see FIG. 21A) having a thickness of, for example, 50 nm is formed on the back surface of the substrate 132 by electroless plating (S2).

  The plating time of the lower barrier region 16 is, for example, 450 seconds. The B concentration in the lower barrier region 16 is, for example, 0.3% by weight.

(2-2) Formation of upper barrier region (see FIG. 21 (b))
An upper barrier region 116 (see FIG. 21B) having a thickness of, for example, 100 nm is formed on the lower barrier region 16 by electroless plating (S4).

  The plating time of the upper barrier region 116 is, for example, 900 seconds. The B concentration of the upper barrier region 116 is, for example, 2.0% by weight. The upper barrier region 116 can be formed, for example, by adding an ammonia water to the electroless plating solution used to form the lower barrier region 16 to increase the pH value.

  Through the above steps, the barrier layer 210 having the lower barrier region 16 and the upper barrier region 116 is formed. The adhesion, the solder wettability and the solder barrier property of the barrier layer 210 are good.

  In the example shown in FIG. 19, the B concentration increases stepwise from the semiconductor chip 6 toward the junction 12. However, the B concentration may be increased in forms other than stepwise. For example, the B concentration may increase like a slope.

  According to the second embodiment, the lower barrier region 16 having a low B concentration can ensure the adhesion of the barrier layer 210, while the upper barrier region 116 having a high B concentration can enhance the solder barrier property of the barrier layer 210.

  As mentioned above, although embodiment of this invention was described, Embodiment 1-2 is an illustration and it is not restrictive. For example, in the first and second embodiments, the semiconductor 4 in contact with the barrier layer is Si doped with B. However, the semiconductor 4 may be a semiconductor other than Si. The semiconductor 4 may be, for example, Ge or SiC doped with B.

  In the first and second embodiments, the semiconductor 4 is a semiconductor substrate. However, the semiconductor 4 may not be a semiconductor substrate. For example, the semiconductor 4 may be a Si layer on the back surface side of an SOI (Silicon on Insulator) substrate.

  In the first and second embodiments, the heat dissipation member 8 is a lid. However, the heat dissipation member 8 may be a member other than the lid. For example, the heat dissipation member 8 may be a heat sink having fins.

  The following appendices will be further disclosed regarding the above-described first and second embodiments.

(Supplementary Note 1)
A semiconductor chip having an integrated circuit disposed on the front side and a semiconductor disposed on the back side and containing boron;
A heat dissipation member for releasing the heat generated by the integrated circuit;
A semiconductor device comprising: a thermal interface member including a barrier layer in contact with the semiconductor and at least a region in contact with the semiconductor, the barrier layer including nickel and boron, and a bonding portion bonding the barrier layer and the heat dissipation member.

(Supplementary Note 2)
The semiconductor device according to claim 1, wherein the semiconductor is silicon.

(Supplementary Note 3)
The semiconductor device according to claim 1 or 2, wherein at least the region of the barrier layer in contact with the semiconductor includes 0.3 weight percent or more and 1.0 weight percent or less of boron.

(Supplementary Note 4)
The barrier layer is disposed between the lower barrier region in contact with the semiconductor and having a first concentration of boron, the lower barrier region and the junction, and a second concentration having a concentration of boron higher than the first concentration. The semiconductor device according to claim 1 or 2, further comprising a certain upper barrier region.

(Supplementary Note 5)
The first concentration is 0.3 weight percent or more and 1.0 weight percent or less,
The semiconductor device according to claim 4, wherein the second concentration is greater than 1.0 weight percent.

(Supplementary Note 6)
Forming a barrier layer in contact with the semiconductor and at least a region in contact with the semiconductor includes nickel and boron on the back side of the substrate on which the integrated circuit is formed on the front side and the semiconductor containing boron is disposed on the back side;
Placing a bonding material on the barrier layer;
Bonding a heat dissipation member that releases heat generated by the integrated circuit to the barrier layer with the bonding material.

DESCRIPTION OF SYMBOLS 2 ... Integrated circuit 4 ... Semiconductor 6 ... Semiconductor chip 8 ... Heat dissipation member 10, 110 ... Barrier layer 12 ... Bonding part 14 ... Thermal interface member 16 ... Lower barrier region 116 ... Upper barrier region 32 ... Substrate

Claims (5)

A semiconductor chip having an integrated circuit disposed on the front side and a semiconductor disposed on the back side and containing boron;
A heat dissipation member for releasing the heat generated by the integrated circuit;
A semiconductor device comprising: a thermal interface member including a barrier layer in contact with the semiconductor and at least a region in contact with the semiconductor, the barrier layer including nickel and boron, and a bonding portion bonding the barrier layer and the heat dissipation member. 2. The semiconductor device according to claim 1, wherein at least the region of the barrier layer in contact with the semiconductor contains 0.3 weight percent or more and 1.0 weight percent or less of boron. The barrier layer is disposed between the lower barrier region in contact with the semiconductor and having a first concentration of boron, the lower barrier region and the junction, and a second concentration having a concentration of boron higher than the first concentration. The semiconductor device according to claim 1, comprising a certain upper barrier region. The first concentration is 0.3 weight percent or more and 1.0 weight percent or less,
The semiconductor device according to claim 3, wherein the second concentration is greater than 1.0 weight percent. Forming a barrier layer in contact with the semiconductor and at least a region in contact with the semiconductor includes nickel and boron on the back side of the substrate on which the integrated circuit is formed on the front side and the semiconductor containing boron is disposed on the back side;
Placing a bonding material on the barrier layer;
Bonding a heat dissipation member that releases heat generated by the integrated circuit to the barrier layer with the bonding material.

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