JP6520454B2 - Method of manufacturing vertical cavity surface emitting laser - Google Patents

Description

  The present invention relates to a method of manufacturing a vertical cavity surface emitting laser.

  A vertical cavity surface emitting laser (VCSEL: Vertical Cavity Surface Emitting Laser) is a laser device that outputs laser light in the direction perpendicular to the substrate surface by forming an optical resonator in the direction perpendicular to the substrate surface. Usually, in a VCSEL, a current confinement structure is formed to concentrate current in a light emitting region.

  In many cases, an open structure formed by oxidizing the outer peripheral side of an AlAs (aluminum-arsenic) layer is used as a current confinement structure. Specifically, oxidation of the AlAs layer is achieved by holding the substrate on which the laminate (object to be oxidized) formed into a mesa shape so that the AlAs layer is exposed on the side surface (object to be oxidized) in heated steam at 400 to 500 ° C. To be executed. In order to produce the current confinement layer as designed, it is necessary to precisely control the amount of oxidation of the AlAs layer.

  For example, Japanese Patent Application Laid-Open No. 2006-228811 (Patent Document 1) discloses a method for precisely controlling the oxidation amount of an AlAs layer. Specifically, the method of this document includes the steps of interrupting the treatment during oxidation treatment of the sample in the treatment vessel, detecting the oxidation amount of the sample through the observation window provided in the treatment vessel during interruption of the oxidation treatment, and detecting And determining the amount of additional oxidation on the basis of the amount of oxidation, and additionally oxidizing the sample by the determined amount of additional oxidation. In the step of detecting the amount of oxidation of the sample, the microscope acquires a magnified image of the sample. In the acquired magnified image, the boundary between the oxidized region and the unoxidized region of the AlAs layer can be clearly recognized.

  Japanese Patent Laid-Open No. 2006-303415 (Patent Document 2) discloses the same method as the above-mentioned document. In the method of this document, the boundary between the oxidized area and the unoxidized area of the AlAs layer is determined based on the difference in the amount of reflected light when the laser light is scanned on the sample surface.

Unexamined-Japanese-Patent No. 2006-228811 JP, 2006-303415, A

  In the manufacturing method described in the above-mentioned Japanese Patent Application Laid-Open No. 2006-228811 (Patent Document 1), after the mixed gas of steam and nitrogen is introduced into the processing container, the heater is turned on and the temperature of the sample reaches a predetermined oxidation temperature. To be raised. For this reason, it is considered that the oxidation of the sample proceeds to some extent also during the rise of the temperature of the sample, but the influence of the oxidation during the temperature rise is not considered at all.

  In the manufacturing method described in the above-mentioned Japanese Patent Application Laid-Open No. 2006-303415 (Patent Document 2), the oxidation process is started by putting the sample in an oxidation furnace which is set to a predetermined temperature while the oxidation gas is jetted. In this case, there is a problem that the progress of oxidation is not constant because the temperature of the sample is not stable immediately after the sample is put into the oxidation furnace.

  The present invention has been made in consideration of the above problems, and its object is to provide a vertical cavity surface emitting laser capable of further improving the controllability of the amount of oxidation when producing a current confinement layer. It is to provide a manufacturing method of

  The present invention is a method of manufacturing a vertical cavity surface emitting laser, comprising forming on a substrate a laminate including first and second reflector layers, an active layer, and an oxidized layer to be a current narrowing structure. And processing the laminate so that at least the side surface of the layer to be oxidized is exposed; and oxidizing the layer to be oxidized from the side surface to form a current confinement structure after processing the laminate. . This oxidation step is performed at least N times (N ≧ 3). The oxidation step of each time includes a first step of raising the temperature of the processed laminate, and a second step of performing steam oxidation of the processed laminate for a preset oxidation time at a preset oxidation temperature. And a third step of stopping the supply of water vapor to lower the temperature of the processed laminate. The manufacturing method further includes the steps of measuring the amount of oxidation of the layer to be oxidized each time after the completion of each of the first to N-1th oxidation steps, and the first to N-1th times. The oxidation amount of the layer to be oxidized in the second oxidation step and the oxidation amount of the layer to be oxidized in the second step based on the measured value of the oxidation amount and the set value of the oxidation time for each time Estimating the oxidation rate, and determining the oxidation time in the Nth oxidation step based on the estimated oxidation amount and the oxidation rate.

  According to the above manufacturing method, other than the second step, that is, the first step (during temperature rising), the third step (during temperature lowering), switching from the first step to the second step, and the second to third steps. Since the oxidation amount at the time of switching to the step is also taken into consideration, the oxidation time in the Nth oxidation step can be determined more accurately.

  Preferably, the step of determining the oxidation time is a step of fitting the relationship between the first to (N-1) th times of the measured value of the oxidation amount and the set value of the oxidation time to an approximate straight line; Estimating the oxidation amount of the layer to be oxidized in steps other than the second step on the basis of the intercept of the approximate straight line at the time of, and estimating the oxidation rate of the oxidized layer in the second step based on the slope of the approximate straight line And the step of

  By performing the linear approximation as described above, it is possible to perform the oxidation of the current confinement layer accurately in the oxidation step at least three times (N = 3).

  Preferably, in the method of manufacturing a vertical cavity surface emitting laser, the steps of: preoxidizing the layer to be oxidized from the side before the first oxidizing step; and after the end of the preoxidizing step. Determining the reference position in the measurement of the oxidation amount by the first oxidation step by measuring the oxidation amount of the oxide layer.

  According to the above manufacturing method, the problem that the progress amount of oxidation in the first oxidation step is not stable due to the influence of the natural oxide film existing on the side surface of the current confinement layer after mesa post processing (before oxidation) it can.

  Preferably, in the first step described above, the temperature of the processed laminate is raised while supplying water vapor. In the first step, the water vapor may not necessarily be supplied, but the water vapor may be supplied in this stage in advance in order to stabilize the atmosphere in the internal space of the oxidation furnace.

  Preferably, the supply amount of steam and the conditions of temperature rise in the first step of each of the first to N-th times are the same. As a result, it is possible to improve the estimation accuracy of the oxidation amount of the layer to be oxidized other than the second step.

  Preferably, each oxidation step is carried out in a closed oxidation furnace. Then, in the third step, the inside of the oxidation furnace is exhausted and then the laminate after processing is cooled. By this, it is not necessary to consider the influence of oxidation due to residual water vapor at the time of temperature decrease.

  Therefore, according to the present invention, the controllability of the amount of oxidation when producing the current confinement layer of the vertical cavity surface emitting laser can be further enhanced.

It is a top view which shows the structure of VCSEL typically. It is a figure which shows typically the cross-section which followed the II-II line of FIG. FIG. 3 is a cross-sectional view showing a portion related to generation of laser light in FIG. 2; It is a distribution map of Al composition of each layer of FIG. It is sectional drawing which shows typically formation of a mesa post structure in the preparation process of VCSEL. It is sectional drawing which shows typically oxidation of the outer peripheral part of a current confinement layer in the preparation process of VCSEL. It is a flowchart which shows the preparation process of VCSEL. It is a figure which shows the structure of the semiconductor oxidation device used for formation of a current confinement layer. In the manufacturing method of the vertical cavity surface emitting laser according to the first embodiment, it is a flowchart showing the oxidation procedure of the current confinement layer. It is a flowchart which shows the detail of the oxidation process of FIG. It is a timing diagram which shows the change of the temperature in each oxidation process. It is a figure which shows an example of the enlarged image of the semiconductor sample 111 image | photographed with the microscope 130 of FIG. It is a figure which shows typically the relationship between oxidation time and oxidation width. It is a figure which shows the result of having measured the change of the oxidation width | variety with respect to each oxidation time experimentally. It is a figure which shows the relationship between the temperature rising / oxidation time of the integration | stacking from the 1st oxidation process, and the oxidation amount of integration. In the manufacturing method of the vertical cavity surface emitting laser according to the second embodiment, it is a flow chart showing the oxidation procedure of the current confinement layer. In the case of 2nd Embodiment, it is a timing diagram which shows the change of the temperature in each oxidation process. FIG. 9 is a view showing an example of a magnified image of the semiconductor sample 111 taken by the microscope 130 of FIG. 8 in the case of the second embodiment. It is a figure which shows the relationship between the temperature rising / oxidation time of the integration from a preliminary oxidation process, and the oxidation width of integration.

  Hereinafter, each embodiment will be described in detail with reference to the drawings. In the following, first, the entire structure of the VCSEL and a method of manufacturing the same will be briefly described, and then a method of manufacturing the current confinement layer will be described in detail. In the following description, the same or corresponding parts may be denoted by the same reference numerals, and the description thereof may not be repeated.

First Embodiment
[Configuration of VCSEL]
FIG. 1 is a plan view schematically showing the structure of a VCSEL. FIG. 2 is a view schematically showing a cross-sectional structure taken along line II-II of FIG. FIG. 3 is a cross-sectional view showing a portion related to generation of laser light in FIG. The sectional views shown in FIGS. 2 and 3 are schematic views. The thickness of each layer in the figure is not proportional to the thickness of the actual device, and the thickness of FIG. 2 and the thickness of FIG. 3 are also not proportional to each other.

  Referring to FIGS. 1 to 3, the VCSEL 1 includes a substrate 10, semiconductor multilayer film reflector layers (DBR: Distributed Bragg Reflectors) 11 and 15, cladding layers 12 and 14, an active layer 13, and a semiconductor multilayer film. It includes a current narrowing layer 16 provided inside the reflecting mirror layer 15, an anode electrode layer 19, and a cathode electrode layer 20.

  In this embodiment, a GaAs (gallium arsenide) semiconductor substrate exhibiting N-type conductivity is used as the substrate 10. A cathode electrode layer (back surface electrode layer) 20 is formed on the back surface of the substrate 10.

On the main surface of the substrate 10, a DBR layer 11 made of a compound semiconductor exhibiting an N-type conductivity type is formed. DBR layer 11 (the lambda represents the emission wavelength) for example Al _0.15 Ga _0.85 As and Al _0.9 Ga _0.1 As optical thickness lambda / 4 comprises a structure of alternately laminated one by. Si (silicon) is doped to give an N type conductivity, and its concentration is, for example, 2 to 3 × 10 ¹⁸ [cm ⁻³ ]. Si is likely to be a donor by coordinating to the Ga (Al) site. P-type impurities are intentionally not doped.

Al _x Ga _(1-x) As (aluminum gallium arsenide) is a mixed crystal semiconductor of GaAs and AlAs. The higher the Al composition (X), the wider the energy gap and the lower the refractive index. Since the lattice constant hardly changes according to the Al composition (X), an Al _x Ga _(1-x) As film of any Al composition (X) can be epitaxially grown on a GaAs substrate. In this specification, when the Al composition (X) is not specified, it may be described as AlGaAs.

  An active region for generating laser light is formed on the DBR layer 11. The active region is constituted of cladding layers 12 and 14 and an active layer 13 having optical gain sandwiched between cladding layers 12 and 14. The film thickness and material of the active layer 13 and the cladding layers 12 and 14 can be appropriately adjusted according to the oscillation wavelength. For example, in the active layer 13, a multiple quantum well (MQW: Multiple Quantum Well) in which a quantum well layer and a barrier layer are stacked in multiple layers is formed. The active layer 13 is a non-doped region in which an impurity is not intentionally introduced.

  The cladding layers 12 and 14 can be non-doped or partially doped depending on the design of the device resistance. In this embodiment, a part of the cladding layers 12 and 14 in contact with the N-type and P-type DBR layers 11 and 15 is doped with an impurity of the same conductivity type as that of the adjacent DBR layers 11 and 15. Therefore, the region 31 doped with the P-type impurity (hereinafter referred to as the P-type doped region 31) extends from the DBR layer 15 on the upper layer side to a part of the cladding layer 14 on the upper layer side. The region 30 doped with N-type impurities (hereinafter referred to as the N-type doped region 30) extends from the lower DBR layer 11 to a part of the lower cladding layer 12.

An upper DBR layer 15 formed of a P-type compound semiconductor is formed on the active region. The upper DBR layer 15 constitutes an optical resonator together with the lower DBR layer 11. The DBR layer 15 has, for example, Al _0.15 Ga _0.85 As and Al _0.9 Ga _0.1 As alternately with an optical film thickness λ / 4, similarly to the DBR layer 11 on the lower layer side (substrate side) except for the current confinement layer 16. Includes stacked structures. C (carbon) is doped to give a P type conductivity, and its concentration is, for example, 2 to 3 × 10 ¹⁸ [cm ⁻³ ]. C is likely to be an acceptor by coordinating to the As site.

  Here, the conductivity type may be opposite to the above, the substrate 10 may be a P-type semiconductor substrate, the conductivity type of the lower DBR layer 11 may be P-type, and the conductivity type of the upper DBR layer 15 may be N-type. . When the first and second conductivity types are described in this specification, one of the first and second conductivity types is P-type, and the other is N-type.

Furthermore, current is efficiently injected into the active region in a part of the upper DBR layer 15 to form a current confinement layer 16 that provides a lens effect. As shown in FIG. 3, the current confinement layer 16 has an unoxidized portion 18 at the central portion and an oxidized portion 17 of a substantially insulator around it. In this structure, the layer to be oxidized to be the current confinement layer 16 is formed of Al _x Ga _(1-x) As in 0.95 ≦ x ≦ 1 (in the case of X = 1, that is, including AlAs) After processing the epitaxial multilayer film including the layer into a mesa post shape, it is obtained by selectively oxidizing the layer to be oxidized from the periphery under a heated water vapor atmosphere. Since only the unoxidized portion 18 in the central portion is a current path, current can be efficiently injected into the active region.

  As shown in FIG. 1 and FIG. 2, a moisture-proof insulating film 21 (also referred to as a moisture-resistant film) is formed on the epitaxial multilayer film having a mesa post structure. An opening is formed in the insulating film 21 at the top of the mesa post so that the upper surface of the DBR layer 15 (surface on the side far from the substrate) is exposed. The anode electrode layer 19 (ring electrode layer) is connected to the top surface of the exposed DBR layer 15. A pad electrode 23 for bonding is connected to the anode electrode layer 19. An insulating layer (polyimide pattern) 22 is provided between the pad electrode 23 and the DBR layer 11 in order to reduce parasitic capacitance.

  Although different from the case of FIGS. 1 to 3, it is also possible to use a non-doped GaAs substrate showing semi-insulation as the substrate 10. In this case, in FIG. 2, for example, an N-type semiconductor contact layer is formed between the substrate 10 and the N-type DBR layer 11 at the stage of the film forming process. After the formation of the mesa post structure and the moisture resistant film 21, the upper surface of the N-type semiconductor contact layer is exposed by forming a digging pattern that penetrates the moisture resistant film 21 and the N-type DBR layer 11 (a portion on the left side of the mesa post structure in FIG. 2). Let A cathode electrode can be formed on the exposed N-type semiconductor contact layer.

[Al composition distribution]
FIG. 4 is a distribution diagram of the Al composition of each layer of FIG. The vertical axis in FIG. 4 indicates the Al composition (X) of Al _x Ga _(1-x) As, and the horizontal axis indicates the depth direction of the VCSEL in arbitrary units (AU). In the case of X = 0, it means GaAs, and in the case of X = 1, it means AlAs.

  Referring to FIG. 4, in the DBR layers 11 and 15, a low refractive index layer having a high Al content and a high refractive index layer having a low Al content are alternately stacked. The region adjacent to the cladding layers 12 and 14 in the DBR layers 11 and 15 corresponds to the first low refractive index layer. In the case of FIG. 4, the current confinement layer 16 is formed in the first low refractive index layer of the DBR layer 15 at a position most distant from the active layer 13. The current confinement layer 16 may be disposed on the lower side (for example, a position adjacent to the cladding layer 14) in the first low refractive index layer.

  Although the current confinement layer 16 is formed inside the first low refractive index layer constituting the DBR layer 15, it may be disposed closer to the active layer 13, such as inside the cladding layer 14. It is possible. Therefore, more generally speaking, the current confinement layer 16 is disposed inside the DBR layer 15 or between the DBR layer 15 and the active layer 13. Alternatively, the current confinement layer 16 can be disposed closer to the substrate 10 than the active layer 13, and may be disposed inside the DBR layer 11 or between the DBR layer 11 and the active layer 13.

[Process of fabricating VCSEL]
Next, a process of manufacturing a VCSEL will be described.

  FIG. 5 is a cross-sectional view schematically showing the formation of a mesa post structure in the process of fabricating a VCSEL. FIG. 6 is a cross-sectional view schematically showing oxidation of the outer peripheral portion of the current confinement layer in the manufacturing process of the VCSEL. FIG. 7 is a flowchart showing a process of manufacturing a VCSEL. Hereinafter, a method of manufacturing the VCSEL 1 will be described with reference to FIGS. 2 and 5 to 7.

  First, multilayer epitaxial films 11 to 16 are formed on a semiconductor substrate 10 (here, an N-type GaAs substrate) (step S100). The formation of the epitaxial film is preferably a method such as MOCVD (Metal Organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy).

  Specifically, first, on the GaAs substrate 10, a DBR layer 11 showing an N-type conductivity type is formed. Next, an active layer 13 including a quantum well (QW: Quantum Well) is formed on the N-type DBR layer 11 so as to be sandwiched between the cladding layers 12 and 14. Next, P-type DBR layers 15 and 15A are formed on the cladding layer 14. During the formation of the P-type DBR layers 15 and 15A, an oxidized layer to be the current confinement layer 16 is formed.

In the case of the structure described with reference to FIGS. 1 to 4, an oxidized layer to be the current confinement layer 16 is formed in the first low refractive index layer in contact with the cladding layer 14. For example, while introducing an Al _X Ga _(1-X) As layer 15A (where X = 0.65) and C (carbon) of about 2 to 3 x 10 ¹⁸ [cm ^-3 ] on the cladding layer 14 formed, then, by increasing the Al composition X 0.95 or more, Al _X Ga _(1-X) as layer as the layer to be oxidized (where, 0.95 ≦ X ≦ 1) a 2 to 3 × It is formed while introducing C (carbon) of about 10 ¹⁸ [cm ^-3 ]. Since the distortion of the layer to be oxidized, which is to become the current confinement layer 16, is caused by volume contraction during the oxidation process, it is desirable to set the thickness to 40 nm or less in order to suppress the influence of the distortion.

  Next, as shown in FIG. 5, the epitaxial multilayer film (laminated body) formed on the substrate 10 is processed into, for example, a mesa post structure with a diameter of 30 μm (step S105). The mesa post structure is formed by photolithography and dry etching. The dry etching needs to be performed at least until the side surface of the oxidized layer to be the current confinement layer 16 is exposed. In the case of FIG. 5, the upper surface (the surface far from the substrate) of the lower DBR layer 11 is exposed. I'm going to the depth I want.

  Next, the substrate with the epitaxial multilayer film processed into the mesa post pattern is heated to about 400 to 500 ° C. in a water vapor atmosphere. As a result, oxidation proceeds from the outer peripheral portion of the oxide film to be the current confinement layer 16 to form an oxidized portion 17 as shown in FIG. 6 (step S110). The oxidation process will be described in detail later.

  Thereafter, a silicon nitride film or a silicon oxide film is formed as the moisture resistant film 21 (step S115). The moisture-resistant film 21 can be formed by a method such as CVD or sputtering. An opening for a contact electrode layer is formed in the moisture-resistant film 21 on the top of the mesa post by photolithography and dry etching.

  Next, an anode electrode layer (contact electrode layer) 19 is formed in the above-mentioned opening by, for example, photolithography and vapor deposition (step S120). As the anode electrode layer 19, for example, a laminated film made of Ti (titanium), Pt (platinum), and Au (gold) can be used.

  Next, the insulating layer (polyimide pattern) 22 is formed for the purpose of capacity reduction under the pad electrode 23 (step S125). Thereafter, a pad electrode 23 connected to the P-type contact electrode layer 19 is formed, for example, by photolithography and sputtering film formation (step S130).

  Next, after adjusting the thickness of the substrate 10, the cathode electrode layer (rear surface electrode layer) 20 is formed (step S135). As the back electrode layer 20, for example, a laminated film of Au, Ge, and Ni can be used. Furthermore, the VCSEL is completed by performing annealing treatment for ohmic contact between the electrode layers 19 and 20 and the semiconductor layer.

[Details of formation method of current confinement layer]
Hereinafter, the method of forming the current confinement layer by heating steam oxidation (step S110 in FIG. 7) will be described in detail.

(Configuration of semiconductor oxidation device)
FIG. 8 is a diagram showing the configuration of a semiconductor oxidation device used to form a current confinement layer. Referring to FIG. 8, the semiconductor oxidation apparatus 100 includes an oxidation furnace 101, a base 110 for supporting a semiconductor sample 111, a rotary lift mechanism 120, a microscope 130, an image processing unit 131, and a pipe 140. , 150, 160, solenoid valves 143, 144, 151, 161, a nitrogen supply source 145, a water vapor supply source 146, a vacuum device 152, and a control device 170.

  The oxidation furnace 101 is a pressure-tight sealed container separated from the outside by a metal wall such as stainless steel. A base 110 for supporting the semiconductor sample 111 is provided at the bottom of the internal space 105 of the oxidation furnace 101. An observation window 104 formed of a transparent heat-resistant material is provided on the ceiling wall 103 of the oxidation furnace 101 at a position facing the base 110.

  The base 110 includes a heating table 113 and a sample table 112. The heating table 113 includes a heater 114 such as a heating wire or a lamp heater, and heats the semiconductor sample 111 via the sample table 112. The heating table 113 can be rotated and raised and lowered by the rotating and raising and lowering mechanism 120. The sample table 112 is a member for supporting and fixing the semiconductor sample 111 and transferring the heat generated by the heating table 113 to the semiconductor sample 111. The sample table 112 and the heating table 113 may be integrated.

  The rotation lift mechanism 120 includes a drive shaft 121, a motor 122, and a lift mechanism 123. The drive shaft 121 is connected to the heating table 113 inside the oxidation furnace 101 by penetrating the bottom wall 102 of the container 101 in the vertical direction. The motor 122 is connected to the drive shaft 121 outside the oxidation furnace 101 and rotates the drive shaft 121 about its axis. Based on the drive of the motor 122, the base 110 rotates around the drive shaft 121. The lifting mechanism 123 moves the motor 122 together with the drive shaft 121 in the vertical direction. In the case of FIG. 8, the elevating mechanism 123 is configured by the motor 124 and a rack and pinion (not shown), but may be another configuration, for example, a hydraulic cylinder or a pneumatic cylinder. Based on the driving of the lifting mechanism 123, the base 110 moves between an oxidation position (falling position) shown by a solid line and an observation position (raising position) shown by a dotted line.

  The microscope 130 is a camera with a microscope, and is configured to be movable in two horizontal directions and one vertical direction by a moving mechanism (not shown). The microscope 130 images the semiconductor sample 111 when the base 110 is at the observation position. The photographed image is processed by the image processing unit 131.

  In order to control the atmosphere of the internal space 105 of the oxidation furnace 101, pipes 140, 150, and 160 which penetrate the wall of the oxidation furnace 101 are provided.

  The pipe 140 branches into two pipes 141 and 142 outside the oxidation furnace 101. One branched pipe 141 is connected to a nitrogen supply source 145 via a solenoid valve 143. The other branched pipe 142 is connected to the water vapor supply source 146 via the solenoid valve 144. Thus, steam and / or nitrogen can be supplied to the internal space 105 of the oxidation furnace 101.

  The pipe 150 is connected to the vacuum device 152 via the solenoid valve 151 outside the oxidation furnace 101. The internal space 105 of the oxidation furnace 101 can be evacuated by a vacuum device 152. The vacuum device 152 is used when the residual gas in the internal space of the oxidation furnace 101 is rapidly exhausted.

  The pipe 160 is connected to the solenoid valve 161. By opening the solenoid valve 161 at the time of supply of water vapor and / or nitrogen, circulation (flow) of water vapor and / or nitrogen can be maintained.

  The control device 170 is configured based on a computer including a central processing unit (CPU) and a memory. The controller 170 controls the entire semiconductor oxidation apparatus 100 such as temperature control of the heater 114, opening and closing of the solenoid valves 143, 144, 151 and 161, drive control of the motor 122, drive control of the elevation mechanism 123, control of the microscope 130, and so on. Control.

(Details of oxidation method)
Next, the details of the oxidation method using the above-described semiconductor oxidation apparatus 100 will be described. As described in step S110 of FIG. 7, the oxidation progresses from the outer peripheral portion of the film to be oxidized by heating the substrate with the epitaxial multilayer film processed into the mesa post pattern to about 400 to 500 ° C. in a water vapor atmosphere. Do.

  FIG. 9 is a flowchart showing an oxidation procedure of the current confinement layer in the method of manufacturing the vertical cavity surface emitting laser according to the first embodiment. A feature is that a total of three oxidation steps are performed to form a current confinement layer (steps S210, S220, and S235).

FIG. 10 is a flowchart showing details of the oxidation process of FIG.
Referring to FIGS. 8 to 10, first, semiconductor sample 111 is fixed on sample table 112 in oxidation furnace 101 (step S200). The control device 170 moves the base 110 to the oxidation position (lower position) by driving the lifting mechanism 123. In this state, the control device 170 raises the temperature of the semiconductor sample 111 to the standby temperature TEMP1 by heating the semiconductor sample 111 by the heater 114 (step S205). The standby temperature TEMP1 is, for example, about 200 ° C., and is a temperature at which oxidation of a layer to be oxidized (for example, an AlAs layer) hardly progresses even in a water vapor atmosphere.

  Next, a first oxidation step is performed (step S210). Specifically, the control device 170 circulates the mixed gas of nitrogen and water vapor in the internal space 105 of the oxidation furnace 101 by first opening the solenoid valves 143, 144, 161 of FIG. 8 (step S300).

  When the atmosphere in the internal space 105 of the oxidation furnace 101 is stabilized, the controller 170 raises the temperature of the semiconductor sample 111 from the standby temperature TEMP1 to the oxidation temperature TEMP2 by gradually increasing the output of the heater 114 (step S305). . The above-mentioned temperature rising process conditions are the same in any of the three oxidation steps.

  When the temperature of the semiconductor sample 111 reaches the oxidation temperature TEMP2, the controller 170 maintains the output of the heater 114 at a constant oxidation temperature TEMP2 and the temperature of the semiconductor sample 111 reaches the oxidation temperature TEMP2 Measure the passage of time. Thereby, the oxidation of the semiconductor sample 111 at the set oxidation temperature TEMP2 is started (step S310). During oxidation, the semiconductor sample 111 is desirably rotated by the motor 122. Thus, the supply of water vapor into the surface of the semiconductor substrate can be made uniform.

  In the above-described temperature raising process (steps S300 and S305), the water vapor may not necessarily be supplied. In this case, while circulating only nitrogen gas in the internal space 105 of the oxidation furnace 101 (step S300), the temperature of the semiconductor sample 111 is raised from the standby temperature TEMP1 to the oxidation temperature TEMP2 (step S305). When the temperature of the semiconductor sample 111 reaches the oxidation temperature TEMP2 or before the oxidation temperature TEMP2 is reached, steam is further introduced into the internal space 105 of the oxidation furnace 101 in addition to nitrogen gas. After the temperature of the semiconductor sample 111 reaches the oxidation temperature TEMP2 and water vapor is introduced into the internal space 105 of the oxidation furnace 101, measurement of the oxidation time is started. The oxidation of the semiconductor sample 111 proceeds during the time from the introduction of water vapor into the inner space 105 to the start of the measurement of the oxidation time, but the amount of oxidation during this time is included in the segment b of the approximate straight line described later.

  When the measurement time reaches the preset oxidation time Tox1, the controller 170 stops the supply of water vapor by closing the solenoid valve 144 (step S315). By continuing the supply of nitrogen, the water vapor remaining in the internal space of the oxidation furnace 101 is discharged from the pipe 160 to the outside. The controller 170 further reduces the temperature of the semiconductor sample 111 from the oxidation temperature TEMP2 to the standby temperature TEMP1 by decreasing the output of the heater 114 (step S320). The process conditions for temperature lowering are the same in all three oxidation steps. Thus, the first oxidation process is completed.

  When the first oxidation process is completed, the control device 170 moves the base 110 to the observation position (the raised position) by driving the elevation mechanism 123. In this state, the control device 170 acquires a magnified image of the semiconductor sample 111 from the direction perpendicular to the semiconductor substrate by the microscope 130. In the acquired magnified image, the boundary between the oxidized region and the unoxidized region of the current confinement layer can be clearly recognized. The image processing unit 131 measures the amount of progress of oxidation (oxidation width W1) in the first oxidation process based on the acquired enlarged image (step S215).

  The method of measuring the oxidation width may be another method. For example, the oxidized portion 17 and the unoxidized portion 18 in FIG. 3 can be detected from the difference in the intensity of the reflected light when the surface of the semiconductor sample 111 is scanned with a laser beam.

  Next, the control device 170 moves the base 110 to the oxidation position (lower position) by driving the elevation mechanism 123, and then executes the second oxidation process (step S220). In the second oxidation step, the oxidation time at the oxidation temperature TEMP2 is changed to Tox2, but the other conditions are the same as in the first oxidation step.

  When the second oxidation process is completed, the control device 170 moves the base 110 to the observation position (raising position) by driving the elevation mechanism 123, and then the direction perpendicular to the semiconductor substrate by the microscope 130. To obtain an enlarged image of the semiconductor sample 111. The image processing unit 131 measures the amount of progress of oxidation (oxidation width W2) in the second oxidation step based on the acquired enlarged image (step S225).

  The controller 170 is finally desired based on the oxidation width W1 detected as the oxidation time Tox1 of the first oxidation step, and the oxidation width W2 detected as the oxidation time Tox2 of the second oxidation step. The additional oxidation width W3 required to obtain the dimensions of the unoxidized portion 18 is determined. Further, the oxidation time Tox3 required to obtain the additional oxidation width W3 is determined (step S230). A specific method of determining the oxidation time will be described later with reference to FIGS. 13 to 15.

  Thereafter, the control device 170 moves the base 110 to the oxidation position (falling position) by driving the elevation mechanism 123, and then executes the third oxidation step (step S235). In the third oxidation step, the oxidation time at the oxidation temperature TEMP2 is changed to the oxidation time Tox3 determined in step 230, but the other conditions are the same as in the first and second oxidation steps.

  After completion of the third oxidation step, the semiconductor sample 111 is taken out of the oxidation furnace 101. Note that the progress of oxidation in each oxidation step is stabilized by preventing the semiconductor sample 111 from being taken out of the oxidation furnace 101 from the start of the first oxidation step to the end of the third oxidation step. Can.

  FIG. 11 is a timing chart showing changes in temperature in each oxidation step. The horizontal axis represents time, and the vertical axis represents the temperature of the semiconductor sample 111. Further, FIG. 11 also shows the type of gas supplied into the oxidation furnace 101.

  Referring to FIG. 11, the first oxidation step corresponds to time t11 to time t14. The second oxidation step corresponds to time t21 to time t24. The third oxidation step corresponds to time t31 to time t34. The temperature rising times Tup1, Tup2 and Tup3 in the respective oxidation steps are the same, and the temperature rising speed is also the same. The temperature lowering time Tdown1, Tdown2 and Tdown3 in each oxidation step are the same, and the temperature lowering speed is also the same.

  Temperature reduction period (from time t13 to time t14, from time t23 to time t24, from time t33 to time t34) and a period maintained at the standby temperature TEMP1 to measure the oxidation width (from time t14 to time t21, From time t24 to time t31), nitrogen is supplied into the internal space 105 of the oxidation furnace 101. Instead of the supply of nitrogen, the internal space 105 of the oxidation furnace 101 may be evacuated by using the vacuum device 152 of FIG. In this case, it is not necessary to equalize the temperature lowering time Tdown1, Tdown2 and Tdown3 in each oxidation step, and it is not necessary to make the temperature decreasing rate the same.

  FIG. 12 is a view showing an example of a magnified image of the semiconductor sample 111 taken by the microscope 130 of FIG. Although FIG. 12 shows an example in which the mesa post shape is cylindrical, the cross-sectional shape of the mesa post is not limited to a circle, and may be any shape such as a square or a rectangle.

  FIG. 12A shows an example of a magnified image of the semiconductor sample 111 after completion of the first oxidation step. In the first oxidation step, oxidation proceeds from the end 50 of the mesa post structure to the boundary 51 between the oxidized portion and the unoxidized portion. The oxidation width at this time is W1.

  FIG. 12B shows an example of a magnified image of the semiconductor sample 111 after completion of the second oxidation step. In the second oxidation step, oxidation proceeds by an oxidation width W2 from the boundary 51 between the oxidized portion and the unoxidized portion in the first oxidation step.

  FIG. 12C shows an example of a magnified image of the semiconductor sample 111 after completion of the third oxidation step. In the third oxidation step, oxidation proceeds by an oxidation width W3 further from the boundary 52 between the oxidized portion and the unoxidized portion in the second oxidation step. Finally, the oxidation width from the end 50 of the mesa post structure to the boundary 53 between the oxidized portion and the unoxidized portion is W1 + W2 + W3.

[Method of determining oxidation time]
Next, the method of determining the oxidation time in step S230 of FIG. 9 will be described.

  FIG. 13 is a view schematically showing the relationship between the oxidation time and the oxidation width. In FIG. 13, the oxidation width W1 detected as the oxidation time Tox1 in the first oxidation step, the oxidation width W2 detected as the oxidation time Tox2 in the second oxidation process, and the oxidation time in the third oxidation step The Tox3 and the detected oxidation width W3 are plotted. As shown in FIG. 13, the relationship between the oxidation times Tox1, Tox2, Tox3 and the oxidation widths W1, W2, W3 can be approximated by a straight line having a slope a and an intercept b.

The slope a and the intercept b of the approximate straight line are calculated from the amounts of progress of oxidation in the first and second oxidation steps (ie, the oxidation widths W1 and W2 with respect to the oxidation times Tox1 and Tox2),
a = (W1-W2) / (Tox1-Tox2) (1)
b = W1-a × Tox1 = W2-a × Tox2 (2)
It can be asked according to

  The above slope a means the oxidation rate of the current confinement layer in the first and second oxidation steps. Therefore, if the supply amount of water vapor and the oxidation temperature TEMP2 are the same in the third oxidation step, it is presumed that the oxidation rate of the current confinement layer in the third oxidation step also has the same oxidation rate a.

  The above section b means the amount of oxidation at temperatures other than the oxidation temperature TEMP2 in the first and second oxidation steps, that is, the sum of the amount of oxidation at temperature rising and the amount of oxidation by residual water vapor at temperature lowering. ing. Therefore, if the supply amount of steam, temperature increase time, temperature decrease time, temperature increase rate, and temperature decrease rate are the same in the third oxidation step, the oxidation temperature TEMP2 other than the third oxidation step The amount of oxidation at the temperature of is also estimated to have the same amount of oxidation b.

Therefore, assuming that the additional oxidation width necessary to obtain the desired size of the unoxidized portion 18 is W3 (determined by subtracting W1 + W2 from the design dimension of the oxidized portion 17), the oxidation of the third oxidation step Time Tox3
W3 = a × Tox3 + b (3)
It can be seen that the relational expression of That is, the oxidation time Tox3
Tox3 = (W3-b) / a (4)
It can be determined by

  When the oxidation at the oxidation temperature TEMP2 is completed, if the inside of the oxidation furnace 101 is rapidly exhausted using the vacuum device 152, it is not necessary to consider the influence of the oxidation due to the residual water vapor in the temperature lowering period. That is, the above segment b means only the amount of oxidation at the time of temperature rise.

  FIG. 14 is a diagram showing the results of experimentally measuring the change in oxidation width with respect to each oxidation time. In FIG. 14, experimental results in the case of three oxidation temperatures A, B and C are shown. It has been demonstrated that the oxidation time and the oxidation width can be approximated by a straight line at any oxidation temperature.

  FIG. 15 is a diagram showing the relationship between the temperature increase / oxidation time integrated from the first oxidation step and the oxidation amount integrated. In FIG. 15, the influence of oxidation due to residual water vapor during the temperature lowering period is assumed to be negligible.

  Referring to FIG. 15, temperature rising times Tup1, Tup2 and Tup3 of the respective oxidation steps are all the same. In this case, the oxidation proceeds by the oxidation width b every heating period of each oxidation process. However, when the temperature of the semiconductor sample 111 is close to the standby temperature TEMP1, oxidation hardly progresses, and as the temperature of the semiconductor sample 111 approaches the oxidation temperature TEMP2, oxidation progresses, so the oxidation amount b at the time of temperature rise and temperature rise time There is no proportional relationship with Tup1, Tup2 and Tup3.

  On the other hand, the oxidation amounts w1, w2, w3 at the oxidation temperature TEMP2 of each oxidation step are in proportion to the oxidation times Tox1, Tox2, Tox3 (proportional constant a). The oxidation widths W1, W2 and W3 detected by the microscope 130 can be obtained by adding the oxidation amount b at the time of temperature rise to the oxidation amounts w1, w2 and w3 at the oxidation temperature TEMP2.

[Effect of First Embodiment]
As described above, according to the first embodiment, the approximate straight line representing the relationship between the oxidation time and the oxidation amount based on the oxidation time and the measured value of the oxidation amount in each of the first and second oxidation steps. The slope and intercept of are determined. Since the oxidation time in the third oxidation step is determined using the determined slope and section, the current confinement layer can be fabricated with good controllability.

Second Embodiment
In the second embodiment, a preliminary oxidation step is added before the first oxidation step in the first embodiment. That is, the present invention is characterized in that a total of four oxidation steps are performed to form a current confinement layer. In this case, the preliminary oxidation step is performed only to determine the reference position of measurement of the amount of oxidation in the first oxidation step, and the measurement value of the oxidation width in the preliminary oxidation step is the oxidation time and oxidation It is not used to obtain the coefficient (slope) a and the intercept b of the approximate straight line representing the relationship with the width. The reason is that the amount of progress of oxidation in the first oxidation step may not be stable due to the influence of the natural oxide film present on the side surface of the current confinement layer after mesa post processing (before oxidation). Hereinafter, the method of forming the current confinement layer (the method of oxidizing the layer to be oxidized) in the second embodiment will be described in detail. The same semiconductor oxidation apparatus as in the first embodiment is used.

[About the oxidation method]
FIG. 16 is a flow chart showing the oxidation procedure of the current confinement layer in the method of manufacturing the vertical cavity surface emitting laser according to the second embodiment. The flowchart of FIG. 16 has a step S206 for performing the preliminary oxidation step (oxidation time Tox0) and a step S207 for measuring the oxidation width W0 using the microscope 130 after the completion of the preliminary oxidation step. This point is different from the flow chart of FIG. 9 in the case of the first embodiment. In the following, differences from the flowchart of FIG. 9 will be mainly described, and the description of the common points will not be repeated.

  Referring to FIGS. 8 and 16, first, semiconductor sample 111 is fixed on sample table 112 in oxidation furnace 101 (step S200), and the temperature of semiconductor sample 111 rises to standby temperature TEMP1 (step S205). And a preliminary oxidation step (oxidation time Tox0) is performed (step S206). The details of the oxidation step are the same as those described with reference to FIG. The preliminary oxidation step is performed to determine the reference position in the measurement of the oxidation width W1 in the first oxidation step.

  When the preliminary oxidation process is completed, the control device 170 moves the base 110 to the observation position (the raised position) by driving the elevating mechanism 123. In that state, the control device 170 acquires a magnified image of the semiconductor sample 111 from the direction perpendicular to the semiconductor substrate by the microscope 130. The image processing unit 131 measures the amount of progress of oxidation (oxidation width W0) in the preliminary oxidation step based on the acquired enlarged image (step S207).

  Next, the control device 170 moves the base 110 to the oxidation position (lower position) by driving the lifting mechanism 123, and then executes the first oxidation step (step S210). The procedures after the first oxidation step are the same as in the case of FIG. Note that the progress of oxidation in the first to third oxidation steps is prevented by preventing the semiconductor sample 111 from being taken out of the oxidation furnace 101 from the start of the preliminary oxidation step to the end of the third oxidation step. Can be stabilized.

  FIG. 17 is a timing chart showing changes in temperature in each oxidation step in the case of the second embodiment. The horizontal axis represents time, and the vertical axis represents the temperature of the semiconductor sample 111. Further, FIG. 17 also shows the type of gas supplied into the oxidation furnace 101.

  Referring to FIG. 17, the preliminary oxidation step corresponds to time t1 to time t4. The temperature rising time Tup0 of the preliminary oxidation step and the temperature rising speed do not have to be the same as the temperature rising times Tup1, Tup2, Tup3 and the temperature rising speed in the first to third oxidation steps. Similarly, the temperature decrease time Tdown0 of the preliminary oxidation step and the temperature decrease rate do not have to be the same as the temperature decrease rates Tdown1, Tdown2 and Tdown3 and the temperature decrease rate in the first to third oxidation steps. Furthermore, although the oxidation temperature in the preliminary oxidation step is the same as the oxidation temperature TEMP2 in the first to third oxidation steps in the case of FIG. 17, it does not necessarily have to be the same. The timing chart of the first to third oxidation steps is the same as that of FIG. 11, and therefore the description will not be repeated.

  FIG. 18 is a view showing an example of a magnified image of the semiconductor sample 111 taken by the microscope 130 of FIG. 8 in the case of the second embodiment.

  FIG. 18A shows an example of a magnified image of the semiconductor sample 111 after completion of the preliminary oxidation step. In the preliminary oxidation step, oxidation proceeds from the end 50 of the mesa post structure to the boundary 50A between the oxidized portion and the unoxidized portion. The oxidation width at this time is W0.

  FIG. 18B shows an example of a magnified image of the semiconductor sample 111 after completion of the first oxidation step. In the first oxidation step, oxidation proceeds by an oxidation width W1 from the boundary 50A between the oxidized portion and the unoxidized portion in the preliminary oxidation step.

  FIG. 18C shows an example of a magnified image of the semiconductor sample 111 after completion of the second oxidation step. In the second oxidation step, oxidation proceeds by an oxidation width W2 from the boundary 51 between the oxidized portion and the unoxidized portion in the first oxidation step.

  FIG. 18D shows an example of a magnified image of the semiconductor sample 111 after completion of the third oxidation step. In the third oxidation step, oxidation proceeds by an oxidation width W3 further from the boundary 52 between the oxidized portion and the unoxidized portion in the second oxidation step. Finally, the oxidation width from the end 50 of the mesa post structure to the boundary 53 between the oxidized portion and the unoxidized portion is W0 + W1 + W2 + W3.

[Method of determining oxidation time]
Next, a method of determining the oxidation time in the third oxidation step in step S230 of FIG. 16 will be described. The method of determining the oxidation time is basically the same as the method described in connection with FIG. However, the additional oxidation width W3 in the third oxidation time is obtained by subtracting W0 + W1 + W2 from the design size of the oxidation portion 17. The point that the oxidation time Tox3 corresponding to the oxidation width W3 is obtained according to the above-mentioned equation (4) is the same as the case of the first embodiment.

  FIG. 19 is a diagram showing the relationship between the integrated temperature rise / oxidation time from the preliminary oxidation step and the integrated oxidation width. In FIG. 19, the influence of oxidation due to residual water vapor during the temperature lowering period is assumed to be negligible.

  Referring to FIG. 19, temperature rising time Tup1, Tup2 and Tup3 in the first to third oxidation steps are all the same. In this case, in the first to third oxidation steps, the oxidation proceeds by a common oxidation width b every heating period. However, when the temperature of the semiconductor sample 111 is close to the standby temperature TEMP1, oxidation hardly progresses, and as the temperature of the semiconductor sample 111 approaches the oxidation temperature TEMP2, oxidation progresses, so the oxidation amount b at the time of temperature rise and temperature rise time There is no proportional relationship with Tup1, Tup2 and Tup3.

  On the other hand, in the first to third oxidation steps, the oxidation amounts w1, w2, w3 at the oxidation temperature TEMP2 are in proportion to the oxidation times Tox1, Tox2, Tox3 (proportional constant a). The detected oxidation widths W1, W2 and W3 can be obtained by adding the oxidation amount b at the time of temperature rise to the oxidation amounts w1, w2 and w3 at the oxidation temperature TEMP2.

  Even if the amount of oxidation c at the time of temperature rise in the preliminary oxidation step is the same as the temperature rise times Tup1, Tup2 and Tup3 in the first and subsequent oxidation steps, the oxidation amount c at the first and subsequent times is It may not be equal to the oxidation amount b in the process. The reason is that the amount of progress of oxidation in the preliminary oxidation step is not stable due to the influence of the natural oxide film present on the side surface of the current confinement layer after mesa post processing (before oxidation). In addition, since the oxidation immediately after the start of the oxidation at the oxidation temperature TEMP2 in the preliminary oxidation step is considered to be affected by the natural oxide film, the oxidation amount w0 may not be proportional to the oxidation time Tox0.

  Thus, in the second embodiment, a preliminary oxidation step is performed only to determine the reference position of measurement of the amount of oxidation in the first oxidation step. The coefficients (slope) a and intercept b of the approximate straight line representing the relationship between the oxidation time and the oxidation width indicate the oxidation time and the oxidation width in the first and second oxidation steps after execution of the preliminary oxidation step. Calculated using. Thus, the oxidation time Tox3 in the third oxidation step can be determined more accurately than in the first embodiment.

[Modification]
In the above embodiment, the laminate including the DBR layers 11 and 15, the cladding layers 12 and 14, the active layer 13, and the oxidized layer to be the current confinement layer 16 is processed into a mesa post. Instead of this, the laminate may be processed into a recess structure. Also in the case of the recess structure, the oxidation proceeds from the side surface of the oxidized layer to be the current confinement layer 16 to form an oxidized portion so as to surround the unoxidized portion.

  In the above embodiment, a total of three oxidation steps are performed except for the preliminary oxidation step, but more than three oxidation steps may be performed. For example, when N (N ≧ 3) oxidation steps are performed, let the oxidation times in the first to (N−1) th oxidation steps be Tox1, Tox2,. The progress of oxidation (oxidation width) in the first to the (N-1) th oxidation steps is W1, W2, ..., WN-1, respectively. The relationship between these N-1 oxidation times and the corresponding N-1 oxidation widths is approximated by a straight line having a slope a and an intercept b. As the number of data points increases, the accuracy of the linear approximation can be enhanced, so that the determination accuracy of the oxidation time ToxN in the Nth oxidation process necessary to obtain the desired amount of oxidation can be enhanced.

  The embodiments disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the scope of claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of claims.

  Reference Signs List 1 VCSEL, 10 substrate, 11, 15 semiconductor multilayer reflector layer (DBR layer), 12, 14 cladding layer, 13 active layer, 16 current confinement layer, 17 oxidized portion, 18 unoxidized portion, 19 contact electrode layer (anode Electrode layer), 20 back electrode layer (cathode electrode layer), 21 moisture resistant film (insulation film), 22 polyimide pattern, 23 pad electrode, 25 high resistance region, 30 N type doped region, 31 P type doped region, 100 semiconductor oxide Apparatus, 101 oxidation furnace, 104 observation window, 105 internal space, 110 base, 111 semiconductor sample, 112 sample table, 113 heating table, 114 heater, 120 rotation lift mechanism, 121 drive shaft, 122, 124 motor, 123 lift mechanism , 130 microscope, 131 image processing unit, 145 nitrogen source, 146 Water vapor source, 152 vacuum unit, 170 control unit.

Claims (5)

A method of manufacturing a vertical cavity surface emitting laser, comprising:
Forming on the substrate a laminate including a first and second reflecting mirror layer, an active layer, and an oxidized layer to be a current narrowing structure;
Processing the laminate such that at least the side surface of the layer to be oxidized is exposed;
Oxidizing the oxidized layer from the side surface to form a current confinement structure after processing the laminate.
The oxidizing step is performed at least N times (N ≧ 3),
The oxidizing step of each time is
A first step of raising the temperature of the laminated body after the processing;
A second step of steam oxidation of said processed laminate for a preset oxidation time at a preset oxidation temperature;
And d) stopping the supply of water vapor to lower the temperature of the processed laminate.
The method further includes
Measuring the amount of oxidation of the layer to be oxidized each time after the completion of each of the first to (N-1) -th oxidation steps;
The oxidized layer other than the second step in the Nth oxidation step based on the first to (N-1) th measured values of the oxidation amount and the set value of the oxidation time each time And estimating the oxidation rate of the layer to be oxidized in the second step, and determining the oxidation time in the Nth oxidation step based on the estimated oxidation amount and the oxidation rate. and,
Pre-oxidizing the layer to be oxidized from the side prior to the first oxidizing step;
Determining the reference position in the measurement of the oxidation amount by the first oxidation step by measuring the oxidation amount of the layer to be oxidized after the completion of the preliminary oxidation step. Method of manufacturing a resonator type surface emitting laser. The step of determining the oxidation time is
Fitting the relationship between the first to (N-1) -th measured values of the amount of oxidation and the set value of the oxidation time to an approximate straight line;
Estimating the amount of oxidation of the layer to be oxidized in steps other than the second step based on the intercept of the approximate straight line when the oxidation time is zero;
And V. estimating the oxidation rate of the layer to be oxidized in the second step based on the slope of the approximate straight line. The method of manufacturing a vertical cavity surface emitting laser according to claim 1 or 2 , wherein in the first step, the processed laminate is heated while supplying water vapor. The method for manufacturing a vertical cavity surface emitting laser according to claim 3 , wherein the conditions for the supply of water vapor and the temperature rise in the first step of each of the first to N-th times are the same. Each said oxidizing step is carried out in a closed oxidation furnace,
The method for manufacturing a vertical cavity surface emitting laser according to any one of claims 1 to 4 , wherein in the third step, the inside of the oxidation furnace is evacuated and then the temperature of the processed laminate is lowered.

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