JP6519185B2 - Video encoder - Google Patents

Description

  The present invention relates to video coding technology.

  H.264 | MPEG-4 Advanced Video Coding Standard (hereinafter referred to as "AVC") and H. 265 | MPEG-H High Efficiency as standardized techniques for video coding and video decoding. The Video Coding standard (hereinafter referred to as "HEVC") is known. In these techniques, a technique of providing a filter in a coding loop is employed in order to reduce the deterioration of image quality due to block distortion and the like due to coding. Several techniques are known for this in-loop filter.

  For example, there is known a technique for reducing the memory capacity of a memory used for in-loop filtering. This technique is premised on the case where the filter operation of an image within a predetermined range from the right block boundary is performed with a filter size in which the number of taps in the horizontal direction orthogonal to the right block boundary is minimum. In this technique, a memory stores image data of an area not included in the predetermined range used for the filter operation. Here, when the filter size in which the number of taps in the horizontal direction is not the smallest is selected, the filter control unit does not store image data in the tap and memory located within the predetermined range based on the position of the filter processing target pixel. Determine the tap. Then, the filter control unit changes the set of coefficients used for copying or filtering the image data for the determined tap so that the filter operation is performed without using the image data which is not stored in the memory and within the predetermined range. I do.

  There is also known a technique for enabling in-loop filtering by low-speed filtering means. This technique is premised on a moving picture coding and decoding method of coding with reference to a filtered image. In this technique, when performing filter processing, an image is divided into two or more partial areas and processed independently for each partial area, and the range affected by the filter processing result of adjacent partial areas among the partial areas is After the end of the filtering process of the adjacent partial area, the filtering process is performed.

  Furthermore, the deblocking filter process executed as the in-loop filter process is also performed when the encoding process is performed in parallel, and the processing delay when performing the encoding process in parallel is reduced. Are known. This technology is premised on a moving picture coding apparatus of AVC. In this technique, deblocking filter processing is divided into first filter processing including deblocking filter processing of boundary edges of slices adjacent to each other and second filter processing as deblocking filter processing other than the first filter processing. A plurality of image encoding units capable of performing at least the second filter processing in parallel are provided. This technique further includes at least one variable length coding unit that performs variable length coding on the data generated by the image coding unit. The image encoding unit has a filter unit that performs the second filter process. Here, the filter unit of the at least one image encoding unit performs the second filtering process and then performs the first filtering process.

JP, 2013-98873, A Unexamined-Japanese-Patent No. 2007-235886 JP, 2012-114637, A

  In HEVC, in addition to the processing of the deblocking filter (hereinafter referred to as “DF”) that is also adopted in AVC as in-loop filter processing, the processing of sample adaptive offset (hereinafter referred to as “SAO”). Is newly added. This SAO process is processed subsequent to the DF process. In such a two-stage filtering process, many pixels are involved in the filtering process. Therefore, when processing the in-loop filter in such a manner that the screen is divided into a plurality of areas and each divided area is allocated to each of the plurality of processing devices, the amount of data transfer between the processing devices is very large. turn into.

  An object according to one aspect of the present invention is to reduce the amount of data received from a processing apparatus that processes adjacent divided areas for SAO processing when dividing a screen and performing encoding processing.

One of the moving picture coding devices described later in this specification includes a coding unit, a local decoding unit, an image processing unit, and a prediction unit. Here, the encoding unit encodes the difference between the input image and the predicted image of the input image. The local decoding unit decodes the encoded data output from the encoding unit, and obtains a local decoded image based on the result of the decoding and the above-described predicted image. The image processing unit performs image processing on the local decoded image. The prediction unit obtains the above-described predicted image based on the locally decoded image after the image processing. In this configuration, the image processing unit includes a first module and a second module. The first module includes a first filter processing unit, a second filter processing unit, and a transfer unit. The first filter processing unit includes a first filtering process on each block in the screen of the local decoded image divided into a plurality of rectangular blocks, the pixels included in the blocks and the blocks adjacent to the blocks. It does based on the pixel value of a pixel. The second filter processing unit performs a second filter process on each block after the first filter process is performed, based on the pixels included in the block and the pixel values of the pixels adjacent to the block. The transfer unit is configured to select a pixel adjacent to the specific block among pixels included in a specific adjacent block adjacent to the specific block on the opposite side to the specific block in contact with the specific boundary of the plurality of rectangular blocks. 1) Store the pixel value of the pixel after the filter processing is performed. The second module performs the first filtering process on the specific block, and then specifies the second filtering process on the pixels adjacent to the specific block among the pixels in the specific adjacent block, which are received from the first module and are specified It carries out using the pixel value of the pixel after performing the 1st filter processing with respect to an adjacent block. The video encoding apparatus determines whether or not the first filtering process has a possibility of changing the pixel value of a specific adjacent pixel adjacent to a specific adjacent block among the pixels included in the specific block. If it is determined that there is a possibility of changing, the second filter processing unit is controlled to limit the second filter processing for the specific adjacent block to one based on pixels other than the specific adjacent pixel. The control unit further includes a control unit that controls the second filter processing unit not to perform the restriction to the second filtering process on the specific adjacent block when it is determined that the second filtering process is not to be performed.

  According to the above-described aspect, the amount of data received from the processing device that processes adjacent divided areas for SAO processing when the screen is divided to perform encoding processing is reduced.

It is a block diagram of an example of a moving picture encoding device. It is explanatory drawing (the 1) of a deblocking filter. It is explanatory drawing (the 2) of a deblocking filter. It is a flowchart showing the processing content of the deblocking filter processing. It is explanatory drawing (the 1) of the pixel in connection with in-loop filter processing. It is explanatory drawing (the 2) of the pixel in connection with the in-loop filter processing. FIG. 17 is a diagram (part 1) for explaining a method of reducing the amount of data transfer in the processing of the in-loop filter at the Chip division boundary in the horizontal direction. FIG. 17 is a second diagram illustrating a method of reducing the amount of data transfer in in-loop filter processing at the Chip division boundary in the horizontal direction. FIG. 16 is a diagram (part 1) for explaining a method of reducing the amount of data transfer in the processing of the in-loop filter at the chip division boundary in the vertical direction. FIG. 17 is a second diagram illustrating a method of reducing the amount of data transfer in the processing of the in-loop filter at the chip division boundary in the vertical direction; It is an example of the structure of the in-loop filter. It is the flowchart which illustrated the processing contents of the 1st example of SAO processing control processing. It is explanatory drawing of the edge offset class in an edge offset process. It is explanatory drawing of the 2nd example of SAO process control processing. It is the flowchart which illustrated the processing contents of the 2nd example of SAO processing control processing. It is a functional block diagram of an example of a large scale integrated circuit device which performs a moving picture coding process. It is explanatory drawing of the procedure of the data transfer for division | segmentation boundary area | region filter processing. It is an example of hardware constitutions of a computer. It is the flowchart which illustrates the processing content of the moving picture coding processing.

  FIG. 1 is a block diagram of an example of a moving picture coding apparatus. The video encoding device 100 is a device compliant with HEVC. The operation of each part of the moving picture coding apparatus 100 will be briefly described.

  The block division unit 101 divides each picture in the input moving image into square pixel blocks called a coding tree unit (CTU).

  The subtractor 102 obtains a prediction error which is a difference between the picture output from the block division unit 101 and the prediction value for the picture.

  The transform and quantization unit 103 orthogonally transforms the prediction error output from the subtractor 102, quantizes the value obtained by the transform, and outputs the quantized data obtained by the quantization.

  The above subtractor 102 and the transform and quantization unit 103 are an example of an encoding unit that encodes the difference between an input image and a predicted image of the input image.

  The inverse quantization and inverse transformation unit 104 performs inverse quantization and inverse orthogonal transformation on the quantized data output from the transformation and quantization unit 103 to obtain a prediction error.

  The adder 105 adds the prediction value input to the subtractor 102 to the prediction error output from the inverse quantization and inverse transformation unit 104 to obtain the pixel value of the picture, thereby reconstructing the picture of the picture. The image of the reconstructed picture output from the adder 105 is referred to as a local decoded image or the like.

  The above inverse quantization and inverse transformation unit 104 and the adder 105 decode the encoded data output from the encoding unit and obtain a locally decoded image based on the result of the decoding and the predicted image. It is an example.

  The in-loop filter 106 reduces block distortion and ringing that occur in the local decoded image. The filter control unit 107 controls the filtering process performed by the in-loop filter 106. The in-loop filter 106 and the filter control unit 107 are an example of an image processing unit that performs image processing on a local decoded image. The in-loop filter 106 will be further described later.

  The frame memory 108 stores the picture of the picture subjected to the filtering process by the in-loop filter 106.

  The intra prediction unit 109 predicts a picture by intra prediction that predicts the pixel value of a pixel based on the correlation of pixels in a picture. The in-screen evaluation unit 110 evaluates a picture to be predicted, and controls the processing of prediction by the in-screen prediction unit 109.

  The motion evaluation unit 111 obtains the motion vector of the subject shown in the picture group stored in the frame memory 108. The motion compensation unit 112 performs motion compensation based on the group of pictures stored in the frame memory 108 and the motion vector obtained by the motion evaluation unit 111, and performs picture prediction.

  The switch 113 selects one of the prediction result by the intra prediction unit 109 and the prediction result by the motion compensation unit 112 as the prediction result of the picture and outputs the result to the subtractor 102 and the adder 105.

  The in-screen prediction unit 109, the in-screen evaluation unit 110, the motion evaluation unit 111, the motion compensation unit 112, and the switch 113 described above are an example of a prediction unit that obtains a predicted image based on the locally decoded image after the image processing described above. is there.

The control unit 114 controls the operation of each unit of the video encoding device 100.
The entropy coding unit 115 uses data obtained by performing entropy coding on the quantized values output from the transform and quantization unit 103 to generate various types of information obtained from each unit of the moving picture coding apparatus 100. It adds in a predetermined format to generate and output encoded data.

  Next, the in-loop filter 106 will be further described. In HEVC, the in-loop filter 106 is configured of the above-described DF and SAO.

First, DF will be described with reference to FIGS. 2A and 2B and FIG.
DF is a filter that reduces block distortion that occurs in the local decoded image. DF targets eight pixels in the vicinity of the block boundary, which is represented as “filter target boundary” in FIG. 2A. More specifically, as shown in FIG. 2B, DF refers to the pixel value of the pixel located within the range of up to 4 pixels from the border of the filter, and up to 3 pixels from the border of the filter Is a process of changing the pixel value of the pixel located within the range of.

  In the DF processing, processing is performed in units of rectangular blocks of 4 pixels × 4 pixels obtained by dividing the local decoded image. Therefore, DF processing is performed on each block in the screen of the local decoded image divided into a plurality of rectangular blocks, and is included in a block adjacent to each block across the pixel of the block and the filter target boundary It can be said that the filtering process is based on the pixel value of the pixel. That is, the DF process is an example of the first filter process.

  Note that the block of 16 pixels × 16 pixels indicated as “CTB” in FIG. 2A is a block called a coding tree block (Coding Tree Block), and is a block constituting the above-mentioned CTU. The filter target boundary is a block of 8 pixels × 8 pixels, and the CTB boundary line is the filter target boundary.

  FIG. 3 is a flowchart showing the processing content of the DF processing. This process is performed by, for example, an arithmetic processing unit.

  In FIG. 3, first, in S101, filter parameter calculation processing is performed. This process is a process of calculating various parameters for controlling the DF. As this filter parameter, there are, for example, a value of Block Boundary Strength (Bs) value calculated from information on blocks on both sides of the filter target boundary, a variation of pixel value of the block boundary area, and the like.

  In S102, based on the parameter calculated in the process of S101, a process of determining a DF processing method at the filter target boundary of the vertical edge on the screen is performed. In this process, application / non-application of DF processing to luminance signals, application / non-application of DF processing to color difference signals, and selection of types of DF processing when applied to luminance signals (strong filtering or weak filtering) A decision about is made.

  In S103, the content of the determination by the process of S102 is determined, and when it is determined that the determination content is the application of the DF process, in S104, the process of DF in the filter target boundary of the vertical edge is performed. On the other hand, when it is determined that the determined content is not applied to the DF process, the process proceeds to S105 without performing the process of S104. The determination process of S103 is performed separately for the luminance signal and the color difference signal. Further, in the process of S104 for the luminance signal, the type of the DF process for the luminance signal selected in the process of S102 is performed, and in the process of S104 for the color difference signal, the DF process for the color difference signal is performed. It will be.

  In S105, based on the parameter calculated in the process of S101, a process of determining the processing method of the DF at the filter target boundary of the horizontal edge on the screen is performed. In this process, application / non-application of DF processing to luminance signals, application / non-application of DF processing to color difference signals, and selection of types of DF processing when applied to luminance signals (strong filtering or weak filtering) A decision about is made.

  In S106, the content of the determination by the processing of S105 is determined, and when it is determined that the determination content is the application of the DF processing, processing of DF in the filter target boundary of the horizontal edge is performed in S107, and then the processing is performed. finish. On the other hand, when it is determined that the determination content is not the application of the DF process, the process ends without performing the process of S107. The determination process of S106 is performed separately for the luminance signal and the color difference signal. Further, in the process of S107 for the luminance signal, the type of the DF process for the luminance signal selected in the process of S105 is performed, and in the process of S107 for the color difference signal, the DF process for the color difference signal is performed. It will be.

  The above processing is the DF processing. Thus, in the DF processing, processing on the filter target boundary of the vertical edge on the screen is performed first, and then processing on the filter target boundary of the horizontal edge on the screen is performed.

  Next, SAO will be described. The SAO processing includes edge offset processing that reduces ringing that occurs around edges in a locally decoded image, and band offset processing that reduces degradation of specific tones in the locally decoded image.

  The edge offset processing is performed on the basis of the relative positional relationship between the pixel to be processed and two of eight adjacent pixels surrounding the pixel to be processed and the pixel to be processed based on the relative magnitude of the pixel value. Give an offset to Therefore, in the edge offset processing, the pixel value of the processing target pixel is changed based on the pixel located in the range of one processing pixel from the processing target pixel.

  On the other hand, in the band offset process, an offset according to the band is given to the pixel value of the processing target pixel only when the pixel value of the processing target pixel is included in the band of the pixel value of the specific range. It is. Therefore, the band offset process changes the pixel value of the processing target pixel itself based on the processing target pixel.

  Summarizing the above-mentioned edge offset processing and band offset processing, the SAO processing refers to the pixels located within the range of one pixel from the processing target pixel, and based on these pixels, the pixel value of the processing target pixel Is a process to change Here, a rectangular block which is a processing unit of the DF processing is considered. In this case, the SAO process is performed on each block after the DF process, which is an example of the first filter process, performed on the pixels included in the block and the pixel values of the pixels adjacent to the block. It can be said that it is a filtering process performed based on it. That is, the SAO process is an example of the second filter process.

  By the way, it is assumed that the moving picture coding apparatus 100 of FIG. 1 is configured such that the screen is divided into a plurality of areas and each divided area is allocated to each of a plurality of processing devices. In this case, in order to process the in-loop filter 106 on the boundary of the divided area, the processing device in charge of processing the divided area adjacent to the boundary processes the in-loop filter 106 in the vicinity of the boundary. Information of the pixel values of the pixels involved in the However, as described above, the moving picture coding apparatus 100 of FIG. 1 performs two-stage filter processing of DF and SAO as the in-loop filter 106, so that even pixels far from the filter target boundary are in the loop. It is involved in the processing of the filter 106. For this reason, the transfer amount of the information of the pixel value of the pixel involved in the processing of the in-loop filter 106 between the processing devices becomes very large.

  Here, the pixels involved in the processing of the in-loop filter 106 will be described using FIGS. 4A and 4B.

  In FIGS. 4A and 4B, it is assumed that the DF processing and the SAO processing are performed on the filter target boundary represented as “Chip division boundary” among the filter target boundaries.

  In the case of FIG. 4A, the case where the chip division boundary is in the horizontal direction on the screen is assumed, and in FIG. 4B, the case where the chip division boundary is in the vertical direction on the screen is assumed. In the case where the moving image coding apparatus 100 of FIG. 1 is configured by dividing the screen into a plurality of areas and dividing each of the divided areas into a plurality of areas, the chip division boundary of Be a boundary.

  Of the pixels represented by circles in FIGS. 4A and 4B, the pixels represented by black circles are changed in pixel value when the DF processing and the SAO processing are performed on the Chip division boundary. Represents possible pixels.

  First, the case where the processing of the in-loop filter 106 is performed on the chip division boundary in the horizontal direction will be described.

  As described with reference to FIG. 2, the DF processing changes the pixel values of the pixels located within the range of maximum 3 pixels from the filter target boundary. The arrow [A] shown in FIG. 4A represents a range within 3 pixels from the chip division boundary, and the pixel value may be changed when DF processing is performed on the chip division boundary in the horizontal direction. It represents the range of existence of pixels having a property.

  On the other hand, as described above, it is assumed that the SAO process is a process of referring to the pixels located in the range from the processing target pixel to the range of one pixel and changing the pixel value of the processing target pixel based on these pixels. It can be said. Therefore, when the SAO processing is performed following the DF processing on the chip division boundary in the horizontal direction, the range of pixels in which the pixel value may be changed is the range of up to 4 pixels from the chip division boundary. To expand.

  The arrow [B] shown in FIG. 4A represents a range of four pixels or less from the chip division boundary in the horizontal direction. That is, in the range represented by the arrow [B], the pixel value may be changed from that before the DF processing when the SAO processing is performed following the DF processing on the chip division boundary in the horizontal direction. It represents the existing range of the pixels it has.

  Also, the arrow [C] shown in FIG. 4A represents a range of 5 pixels or less from the chip division boundary in the horizontal direction. This range is the pixel referred to in the case where the SAO process is performed with each of the pixels located within the range of four pixels (that is, the range of the arrow [B]) from the Chip division boundary in the horizontal direction. It represents the range of existence.

  In the following description, a pixel to be referred to when a certain process is performed is referred to as a “reference target pixel”.

  Here, the pixel at the position of the fifth pixel from the chip division boundary in the horizontal direction included in the range of the arrow [C] is noted. The pixel at this position is not the processing target pixel in the DF processing for the chip division boundary in the horizontal direction, but the processing target pixel in the DF processing for the other filtering target boundaries in the horizontal direction and the vertical direction Contains pixels that are That is, the pixel values of these pixels are the pixel values of the result of performing the DF processing on the other filter target boundaries, which set these pixels as processing target pixels.

  As shown in FIG. 4A, the DF processing is performed in units of image blocks of 4 pixels × 4 pixels having the filter target boundary as a reference boundary. Therefore, in the DF process on another filter target boundary where the pixel at the fifth pixel position from the chip division boundary in the horizontal direction is the processing target pixel, the pixels in the range from the chip division boundary to 8 pixels are referenced It becomes a target pixel. From the above, when performing the SAO process following the DF process on the chip division boundary in the horizontal direction, the pixels within a range of eight pixels from the chip division boundary become the reference target pixels in the processing of this combination. .

  Arrow [D] in FIG. 4A represents a range within 8 pixels from the chip division boundary in the horizontal direction, and the presence range of the reference target pixel in the case of performing the SAO processing following the DF processing on the chip division boundary It represents. These reference target pixels are involved in the processing of the in-loop filter 106 at the chip division boundary in the horizontal direction.

  Next, the case where the processing of the in-loop filter 106 is performed on the chip division boundary in the vertical direction will be described.

  As described with reference to FIG. 2, the DF processing changes the pixel values of the pixels located within the range of maximum 3 pixels from the filter target boundary. Further, as described with reference to FIG. 3, in the DF processing, processing in the filter target boundary in the vertical direction is performed first, and then processing in the filter target boundary in the horizontal direction is performed. Therefore, there is a possibility that the pixel value of the pixel located within the range of up to 4 pixels from the filter target boundary may be changed when performing the DF processing on the chip division boundary which is the vertical direction. .

  The arrow [A] shown in FIG. 4B represents a range within 4 pixels from the chip division boundary, and the pixel value may be changed when DF processing is performed on the chip division boundary in the vertical direction. It represents the range of existence of pixels having a property.

  In addition, as described above, it is assumed that the SAO process refers to a pixel located within a range from the processing target pixel to one pixel, and changes the pixel value of the processing target pixel based on these pixels. It can be said. Therefore, when the SAO processing is performed following the DF processing on the chip division boundary in the vertical direction, the range of pixels in which the pixel value may be changed is a range of up to 5 pixels from the chip division boundary. To expand.

  The arrow [B] represented in FIG. 4B represents a range of 5 pixels or less from the chip division boundary in the vertical direction. That is, in the range represented by the arrow [B], the pixel value may be changed from that before the DF processing when the SAO processing is performed following the DF processing on the chip division boundary in the vertical direction. It represents the existing range of the pixels it has.

  Also, the arrow [C] represents a range within 6 pixels from the chip division boundary in the vertical direction. This range is the presence of the reference target pixel in the case where the SAO processing is performed with each of the pixels located within the range of 5 pixels or less (that is, the range of the arrow [B]) from the chip division boundary in the vertical direction. It represents the range.

  Here, the pixel at the position of the sixth pixel from the chip division boundary in the horizontal direction included in the range of the arrow [C] is noted. The pixel values of these pixels are the pixel values as a result of performing DF processing on the other filter target boundaries with these pixels as processing target pixels. To the fifth pixel position.

  As shown in FIG. 4B, the DF processing is performed in units of blocks of 4 pixels × 4 pixels having the filter target boundary as a reference boundary. Also, the DF processing may change the pixel values of the pixels located within the range of maximum 3 pixels from the filter target boundary. Therefore, in the DF processing on another filter target boundary in which the pixel at the position of the sixth pixel from the chip division boundary in the vertical direction is a processing target pixel, the DF processing of the filter target boundary eight pixels inside of the Chip division boundary Since the result is also required, the pixel in the range from the chip division boundary to 12 pixels is the reference target pixel. That is, in the case where the SAO processing is performed following the DF processing on the chip division boundary in the vertical direction, pixels within a range of 12 pixels from the chip division boundary become a reference target pixel in the processing of this combination.

  The arrow [D] in FIG. 4B represents the range within 12 pixels from the chip division boundary in the vertical direction, and the presence range of the reference target pixel in the case of performing the SAO processing following the DF processing on the chip division boundary It represents. These reference target pixels are involved in the processing of the in-loop filter 106 at the chip division boundary in the vertical direction.

  As described above, when the Chip division boundary is in the horizontal direction and in the vertical direction, the pixels located within a wide range of 8 pixels or 12 pixels within the Chip division boundary are referred to in the processing of the in-loop filter 106 in the Chip division boundary. It is involved as a pixel.

  By the way, when the screen is divided and each divided area is shared by a plurality of processing devices to realize the moving image encoding process of the whole screen, each processing device operates on pixels outside the divided area for which it is in charge of processing. Management of the pixel value data of is usually not performed. Therefore, in order to process the in-loop filter 106 at the Chip division boundary, each processing unit takes within 8 pixels or 12 pixels from the Chip division boundary from the processing unit in charge of the division area adjacent to the processing divided area. It is necessary to have the pixel value data of the pixels located in the range transferred.

  Therefore, the in-loop filter 106 is configured as described above to reduce the amount of data transfer received from the processing unit in charge of the adjacent divided area for the processing of the in-loop filter 106 of the Chip division boundary.

  First, a method for reducing the amount of data transfer in the processing of the in-loop filter 106 at the Chip division boundary in the horizontal direction will be described using FIGS. 5A and 5B.

FIG. 5A shows the relationship between the position of a pixel and the change in pixel value due to the DF processing.
In FIG. 5A, the pixel at the position of the black circle and the pixel at the shaded circle are both changed in pixel value when DF processing is performed in the chip division boundary in the horizontal direction. It represents possible pixels. Among these, the pixel at the black circle mark represents a pixel whose pixel value may be changed when the DF process is performed on the Chip division boundary which is a horizontal edge.

  On the other hand, in FIG. 5A, both the pixel at the shaded circle and the pixel at the white circle are pixels whose pixel values are not changed even if DF processing is performed on the filter target boundary of the horizontal direction edge Represents Among these, the shaded pixels at the circled positions indicate pixels in which the pixel values may be changed when the DF processing at the filter target boundary of the vertical edge is performed. The pixel at the white circle mark indicates a pixel whose pixel value is not changed even if the DF processing at the filter target boundary of the vertical edge is performed.

Here, terms used in the following description are defined.
As described above, the DF process is a filter process performed on a block on the screen based on the pixel values of the pixels included in the block adjacent to the block across the filter target boundary. Therefore, a block to be processed in DF processing on a chip division boundary is referred to as a "specific block", and a block adjacent to the specific block on the opposite side to the chip division boundary is referred to as a "specific adjacent block". In FIG. 5A, a block included in the range of [A] is a specific block, and a block included in the range of [B] is a specific adjacent block.

  Referring to FIG. 5A, it can be seen that pixels separated by four or more pixels from the chip division boundary in the horizontal direction are not affected by the DF processing at the horizontal edge which is the chip division boundary. In addition, as described above, the SAO processing performed after the DF processing in the processing of the in-loop filter 106 refers to the pixels located within the range of one pixel from the processing target pixel, and the processing is performed based on these pixels. This is processing of changing the pixel value of the target pixel.

  Therefore, the normal SAO processing is performed after the DF processing illustrated in FIG. 5A for the pixels in the range of 5 pixels or more from the horizontal chip division boundary including the pixels in the specific adjacent block, and the in-loop filter 106 is performed. Complete the process of

  On the other hand, the processing of the in-loop filter 106 for pixels in the range from the chip division boundary in the horizontal direction to the four pixels included in the specific block is performed as follows.

  First, DF processing is performed on pixels in the range from the chip division boundary in the horizontal direction to four pixels included in the specific block. In this DF processing, pixel values before DF processing for pixels in the range from the chip division boundary to the four pixels from another processing device in charge of processing the division region in contact with the chip division boundary as a reference target pixel Receive data transfer.

  Note that this DF processing is based on the pixel values of the pixels included in the specific block and the pixels included in the block facing the specific block across the chip division boundary with respect to the specific block in contact with the chip division boundary in the horizontal direction. It can be said that the filtering process is performed. That is, in this DF process, the pixel value data before the DF process for the pixels included in the opposing block is processed by another processing device in charge of processing the image area including the opposing block as a reference target pixel. Receive a transfer. Hereinafter, DF processing in the chip division boundary in the horizontal direction is referred to as “horizontal boundary DF processing”.

  Next, SAO processing is performed on the pixels after horizontal boundary DF processing using the received pixel value data. In this SAO process, a pixel value after DF processing for a pixel in a range of the fifth pixel from the chip division boundary from another processing device in charge of processing the division region in contact with the chip division boundary as a reference target pixel. Receive data transfer. That is, in this SAO process, the pixel adjacent to the opposing block on the opposite side to the chip division boundary is further connected to the opposing block than the other processing apparatus in charge of processing the area including the opposing block described above as a reference target pixel. It receives transfer of pixel value data after DF processing.

  FIG. 5B is a process in charge of processing the divided area in contact with the chip division boundary in the case where the processing of the in-loop filter 106 for pixels in the range from the chip division boundary in the horizontal direction to 4 pixels is performed as described above. It represents the position of a pixel to be transferred from the device.

  In FIG. 5B, the pixels located in the range of [A], that is, the pixels located in the range from the chip division boundary in the horizontal direction to the four pixels (pixels included in the above-mentioned opposing block) Pixels to be transferred as reference target pixels. For these pixels, pixel value data before DF processing is used as data to be transferred. Further, in FIG. 5B, the pixel located in the range of [B], that is, the fifth pixel from the chip division boundary in the horizontal direction (the pixel adjacent to the above-mentioned opposing block on the opposite side to the chip division boundary) Is a pixel to be transferred as a reference target pixel for SAO. For these pixels, pixel value data after DF processing is used as data to be transferred.

  By performing the processing of the in-loop filter 106 on the chip division boundary in the horizontal direction in this way, the pixel range to which pixel value data is to be transferred is from the range from the chip division boundary to 8 pixels to 5 pixels Narrow to the range of, resulting in a reduction in the amount of data transfer.

  Next, a method of reducing the amount of data transfer in the processing of the in-loop filter 106 at the Chip division boundary in the vertical direction will be described with reference to FIGS. 6A and 6B.

FIG. 6A shows the relationship between the position of a pixel and the change in pixel value due to the DF processing.
In FIG. 6A, the pixel at the black circle mark indicates a pixel whose pixel value may be changed when the DF processing is performed in the chip division boundary which is the vertical direction.

  On the other hand, the shaded pixel, the shaded circle, and the white circle are all in the vertical direction of the chip division boundary. Represents a pixel whose pixel value is not changed even when DF processing is performed. Among these, the shaded pixels at the circled positions indicate pixels that may change in pixel value when the DF process is performed on the filter target boundary of the horizontal edge. In addition, the pixel at the shaded circle and the pixel at the white circle both represent pixels whose pixel values are not changed even if the DF processing is performed on the filtering target boundary of the horizontal edge. Among these, the shaded pixel at the position of the circle represents a pixel whose pixel value may be changed when the DF processing at the filter target boundary which is the vertical edge is performed. The pixel at the white circle mark indicates a pixel whose pixel value is not changed even if the DF process is performed on the filter target boundary which is a vertical edge.

  Referring to FIG. 6A, it can be seen that pixels which are separated by 5 or more pixels from the vertical chip division boundary are not affected by the DF processing at the chip division boundary. However, as described above, the SAO processing performed after the DF processing in the processing of the in-loop filter 106 refers to the pixels located in the range from the processing target pixel to the range of one pixel, and the processing is performed based on these pixels. This is processing of changing the pixel value of the target pixel. For this reason, in the SAO process in which the pixel at the position of the fifth pixel from the chip division boundary in the vertical direction is the processing target pixel, the pixel at the fourth pixel position from the chip division boundary is referred to. The pixel represented by the black circle in FIG. 6A, that is, the pixel value may be changed in the pixel at the position of the fourth pixel, that is, when the DF processing is performed at the chip division boundary in the vertical direction. Pixel is included.

  Therefore, first, for pixels in a range of 5 pixels or more from the chip division boundary in the vertical direction including the pixels in the specific adjacent block, the SAO processing is performed after the DF processing. However, the processing mode is limited for the SAO processing to the pixels included in the specific adjacent block, and the SAO processing in the processing mode that refers to the position of the fourth pixel from the chip division boundary is not performed.

  Note that the pixel at the position of the fourth pixel from the Chip division boundary in the vertical direction can be said to be the pixel adjacent to the specific adjacent block among the pixels included in the specific block. This pixel is referred to as a "specified adjacent pixel". That is, with regard to the SAO processing for the pixels included in the specific adjacent block, the processing mode is limited, and the SAO processing is performed in which pixels other than the specific adjacent pixels are the reference target pixels.

  However, when DF processing is performed on the filter target boundary in the vertical direction, the specific adjacent pixel may be changed in pixel value, but may not actually be changed by the DF processing. Therefore, when the pixel value of the specific adjacent pixel is not changed by the DF process, the process mode in the above-described SAO process may not be limited.

  On the other hand, the processing of the in-loop filter 106 for pixels in the range from the vertical chip division boundary to four pixels included in the specific block is performed as follows.

  First, DF processing is performed on pixels in a range from the vertical chip division boundary to four pixels included in the specific block. In this DF processing, pixel values before DF processing for pixels in the range from the chip division boundary to the four pixels from another processing device in charge of processing the division region in contact with the chip division boundary as a reference target pixel Receive data transfer.

  In the DF processing, for a specific block in contact with the chip division boundary in the vertical direction, the pixel values of the pixels included in the specific block and the pixels included in the block facing the specific block across the chip division boundary are used. It can be said that this is filter processing performed on the basis of this. That is, in this DF process, the pixel value data before the DF process for the pixels included in the opposing block is processed by another processing device in charge of processing the image area including the opposing block as a reference target pixel. Receive a transfer. Hereinafter, DF processing in the chip division boundary in the vertical direction is referred to as “vertical boundary DF processing”.

  Next, an SAO process is performed on the pixel after the vertical boundary DF process using the received pixel value data. In this SAO process, pixel value data after DF processing for a pixel in the range of the fifth pixel from the Chip division boundary, from another processing device in charge of processing the division region in contact with the Chip division boundary as a reference target pixel. Receive transfers. That is, also in this SAO process, the DF process is performed on the pixel adjacent to the specific adjacent block on the opposite side to the chip division boundary than the other processing apparatus in charge of processing the area including the specific adjacent block as the reference target pixel. Receives the transfer of pixel value data later.

  FIG. 6B is a process in charge of processing the divided area in contact with the chip division boundary in the case where the processing of the in-loop filter 106 is performed as described above for pixels ranging from the chip division boundary in the vertical direction to four pixels. It represents the position of a pixel to be transferred from the device.

  In FIG. 6B, the pixels located in the range of [A], that is, the pixels located in the range from the chip division boundary in the vertical direction to the four pixels (pixels included in the above opposing block) Pixels to be transferred as reference target pixels. For these pixels, pixel value data before DF processing is used as data to be transferred. Further, in FIG. 6B, the pixel located in the range of [B], that is, the fifth pixel from the vertical chip division boundary (the pixel adjacent to the above-mentioned opposing block on the opposite side to the chip division boundary) Is a pixel to be transferred as a reference target pixel for SAO processing. For these pixels, pixel value data after DF processing is used as data to be transferred.

  By performing the processing of the in-loop filter 106 on the chip division boundary in the vertical direction in this way, the pixel range to which pixel value data is to be transferred is from the range from the chip division boundary to 8 pixels to 5 pixels Narrow to the range of, resulting in a reduction in the amount of data transfer.

  In the following description, when the distinction between the horizontal boundary DF processing and the vertical boundary DF processing is not necessary, it will be referred to simply as the “boundary DF processing”. That is, the boundary DF processing is performed on a specific block in contact with a specific boundary (Chip division boundary), and is based on the pixel values of the pixels included in the opposing block adjacent to the specific block across the boundary. It can be said that this is DF processing.

  Next, FIG. 7 will be described. FIG. 7 shows an example of the configuration of the in-loop filter 106 in FIG.

  The in-loop filter 106 of FIG. 7 includes filtering units 200-1 and 200-2. Each of the filter processing units 200-1 and 200-2 takes charge of one of divided areas obtained by dividing an image into two at a chip division boundary.

  Each of the filter processing units 200-1 and 200-2 is an image of a divided area in which the video decoding apparatus 100 of FIG. Is input. The image of this divided area is divided into a plurality of rectangular blocks.

  The filter processing unit 200-1 and the filter processing unit 200-2 have the same configuration. The configuration of the filter processing unit 200-1 will be described below.

  The filter processing unit 200-1 includes a DF processing unit 201, an SAO processing unit 202, an SAO processing control unit 203, and a memory 204.

  The image of the divided area is input to the DF processing unit 201. This image is referred to as "pre-DF image". The DF processing unit 201 performs DF processing on the pre-DF image based on the DF processing parameters sent from the filter control unit 107. The DF processing parameter is, for example, coded information on blocks on both sides of a block boundary. The image subjected to the DF processing on the pre-DF image and output from the DF processing unit 201 is referred to as a “post-DF image”.

  As described above, the DF process is an example of the first filter process. Therefore, in the DF processing unit 201, for each block in the screen of the local decoded image divided into a plurality of rectangular blocks, the pixels included in the blocks and the pixels included in the blocks adjacent to the blocks are A first filter process based on pixels is performed. The DF processing unit 201 is an example of a first filter processing unit.

  The SAO processing unit 202 performs SAO processing on the image after DF based on the SAO processing parameter sent from the filter control unit 107. The SAO processing parameter is, for example, an offset amount. An image subjected to SAO processing on the image after DF and output from the SAO processing unit 202 is referred to as “image after SAO”.

  The image after SAO output from the SAO processing unit 202 of the filter processing unit 200-1 is stored in the frame memory 210-1. Further, the SAO image output from the SAO processing unit 202 of the filter processing unit 200-2 is stored in the frame memory 210-2.

  As described above, the SAO process is an example of the second filter process. Therefore, in the SAO processing unit 202, for each block after the first filter processing is performed, the second filter processing based on the pixel included in the block and the pixel value of the pixel adjacent to the block is performed. To be done. The SAO processing unit 202 is an example of a second filter processing unit.

  The SAO processing control unit 203 has a possibility that the DF processing by the DF processing unit changes the pixel value of the specific adjacent pixel adjacent to the specific adjacent block among the pixels included in the specific block in contact with the chip division boundary. If it does, the SAO processing unit 202 is controlled. In this control, the SAO process for the specific adjacent block is limited to one based on pixels other than the specific adjacent pixel. By this control, SAO processing is performed on a specific adjacent block without always using pixels included in the specific block. Therefore, it becomes unnecessary to receive transfer of pixel value data of pixels necessary for calculation of pixel values of pixels included in a specific block after DF processing from another processing device, and the amount of data transferred between processing devices Is reduced.

  The SAO process control unit 203 may determine whether the DF process on the specific block changes the pixel value of the specific adjacent pixel. In this case, when the SAO process control unit 203 determines that the DF process does not change the pixel value of the specific adjacent pixel, the SAO process unit 202 does not perform the above-described restriction on the SAO process for the specific adjacent block. Control.

  The memory 204 is a storage device that temporarily stores data transferred from the filter processing unit 200-1. The memory 204 stores pixel value data of pixels adjacent to the specific adjacent pixel that are included in the specific adjacent block among the pixels of the image after DF. The memory 204 also includes pixel value data of pixels included in a specific block among the pixels of the image before DF, DF processing parameters used for DF processing and SAO processing on Chip division boundaries, and SAO processing. Parameter data is also stored.

  The above data temporarily stored in the memory of the filter processing unit 200-1 is then transferred to the boundary processing data memory 220-1. Further, the above-described data temporarily stored in the memory of the filter processing unit 200-2 is thereafter transferred to the boundary processing data memory 220-2.

  The division boundary filter processing unit 230 performs DF processing and SAO processing on the chip division boundary. The division boundary filter processing unit 230 includes a boundary DF processing unit 231 and a boundary SAO processing unit 232.

  The boundary DF processing unit 231 performs DF processing based on pixel values included in each of a pair of specific blocks sandwiching the chip division boundary, stored in each of the boundary processing data memories 220-1 and 220-2. The process is performed on each of the pair of specific blocks. In the DF processing, DF processing parameters for DF processing on the chip division boundary are read from the boundary processing data memories 220-1 and 220-2 and used. The boundary DF processing unit 231 is also an example of the first filter processing unit.

  The boundary SAO processing unit 232 performs SAO processing on each of the pair of specific blocks after the DF processing by the boundary DF processing unit 231. This SAO process is included in the specific adjacent block among the pixels of the image after DF, which are included in the pair of specific blocks after the DF process and in the boundary processing data memories 220-1 and 220-2. Based on the pixel value of a pixel adjacent to a specific adjacent pixel. Further, in this SAO process, SAO process parameters for SAO process on the chip division boundary are read out from the division boundary processing data memories 220-1 and 220-2 and used. The boundary SAO processing unit 232 is also an example of a second filter processing unit.

  Pixel value data of pixels included in the pair of specific blocks after the SAO process has been performed by the boundary SAO processing unit 232 is stored in the frame memories 210-1 and 210-2.

  Since the SA memory after the processing by the filter processing unit 200-1 is stored in the frame memory 210-1, a part of the specific block of the images is processed by the division boundary filter processing unit 230. Replace with the corresponding one of the blocks and store it. The frame memory 210-2 stores the SAO-processed image processed by the filter processing unit 200-2, and a portion of the specific block of the images is processed by the division boundary filter processing unit 230. Replace with the corresponding one of the specific blocks and store. The frame memories 210-1 and 210-2 correspond to the frame memory 108 in FIG. That is, by combining the images respectively stored in the frame memories 210-1 and 210-2, an image after the filtering process by the in-loop filter 106 is obtained.

  Next, control processing by the SAO processing control unit 203 will be described. FIG. 8 is a flowchart illustrating the process contents of a first example of the SAO process control process performed by the SAO process control unit 203.

  The process of FIG. 8 is performed for each pixel constituting an image after DF, which is an object of the SAO process by the SAO processing unit 202.

  In FIG. 8, first, in S201, the SAO processing control unit 203 is a block in which the block to be processed includes the pixels of the above-described specific adjacent block (a specific block adjacent to the chip division boundary on the other side). It is determined whether or not it is. Here, when the SAO process control unit 203 determines that the block includes the pixels of the specific adjacent block (when the determination result is Yes), the process proceeds to S202. On the other hand, when the SAO process control unit 203 determines that the block is not a block including the pixels of the specific adjacent block (when the determination result is No), the process proceeds to S204.

  Next, in S202, the SAO processing control unit 203 determines whether or not the Chip division boundary in which the specific block adjacent to the specific adjacent block including the pixel to be processed is in contact with the screen in the vertical direction. Do the processing. Here, when the SAO process control unit 203 determines that the Chip division boundary is in the vertical direction on the screen (when the determination result is Yes), the process proceeds to S203. On the other hand, when the SAO processing control unit 203 determines that the Chip division boundary is not the vertical direction on the screen (that is, the horizontal direction on the screen) (when the determination result is No), the process proceeds to S204. .

  When the determination result of the determination process of S202 is Yes, it is a case where the DF process on the specific block has a possibility of changing the pixel value of the specific adjacent pixel. Therefore, in S203, the SAO process control unit 203 controls the SAO processing unit 202 so that the SAO process on the specific adjacent block is performed in a processing mode in which the SAO process is limited to those based on pixels other than the specific adjacent pixel. Do the process. Then, after that, the SAO process control unit 203 ends the process of FIG.

  On the other hand, when the determination result of the S202 determination process is No, it is certain that in the DF process on the specific block, the pixel value of the specific adjacent pixel does not change. In S204, the SAO processing control unit 203 controls the SAO processing unit 202 to release the above-described restriction on the processing mode in the SAO processing, and performs processing for preventing the restriction in the SAO processing from being performed, and thereafter. Ends the process of FIG.

The above-described process is a first example of the SAO process control process.
Here, the limitation of the processing mode to the SAO processing in the processing of S203 of FIG. 8 will be described.

  As described above, the SAO processing is processing including edge offset processing and band offset processing. Among these, since the band offset process changes the pixel value of the process target pixel itself based on the process target pixel, the band offset process for the specific adjacent block is not performed based on the specific adjacent pixel. . On the other hand, in the edge offset processing, the processing object is processed based on the relative positional relationship between the pixel to be processed and two of the eight adjacent pixels surrounding the pixel to be processed and the magnitude relationship of the pixel values. The offset is given to the pixel of. Therefore, edge offset processing for a specific adjacent block may be performed based on a specific adjacent pixel.

  Here, classes in edge offset processing will be described with reference to FIG. In HEVC, four types of edge offset classes are defined for the relative positional relationship between the pixel to be processed and two adjacent pixels, which is referenced to determine the offset amount given to the target pixel in edge offset processing. . FIG. 9 illustrates the arrangement of pixels defined in this class.

  In FIG. 9, class 0 is a class in which a processing target pixel and a pair of adjacent pixels facing and adjacent to each other on both sides of the processing target pixel are arranged in the horizontal direction (direction of 0 degrees) on the screen. Class 1 is a class in which a processing target pixel and a pair of adjacent pixels facing and adjacent to each other on both sides of the processing target pixel are arranged in the vertical direction (90-degree direction) on the screen. Furthermore, class 2 is a class in which the processing target pixel and a pair of adjacent pixels facing and adjacent to each other on both sides of the processing target pixel are arranged in the direction from the upper left to the lower right on the screen (diagonal 45 degrees). is there. The class 3 is a class in which the processing target pixel and a pair of adjacent pixels facing and adjacent to each other on both sides of the processing target pixel are arranged in the direction from the lower left to the upper right on the screen (a direction of 135 degrees diagonally). .

  Of the edge offset classes shown in FIG. 9, in the classes 0, 2 and 3, adjacent pixels in the horizontal or diagonal direction with respect to the pixel to be processed are referred to in the edge offset processing. For this reason, if these classes are selected in the edge offset processing for the specific adjacent block in the case where the Chip division boundary is in the vertical direction in the screen, the specific adjacent pixel is referred to for processing.

  Therefore, the SAO process control unit 203 controls the SAO processing unit 202 in the process of S203 of FIG. 8 to execute the process of class 1 when performing the edge offset process. In class 1, since the pixel to be processed and the adjacent pixels are arranged in the vertical direction on the screen, this makes edge offset processing for a specific adjacent block in the case where the Chip division boundary is in the vertical direction on the screen, Specific adjacent pixels are not referenced.

  Next, a second example of the SAO process control process performed by the SAO process control unit 203 will be described with reference to FIG.

  In the first example described above, when the Chip division boundary in which the specific block adjacent to the specific adjacent block is in contact is in the vertical direction on the screen, the DF processing for the specific block changes the pixel value of the specific adjacent pixel It is determined that it has the possibility. However, even if this is the case, DF processing may not actually be applied to a specific block. In the second example to be described below, the case where the DF process is not applied to this specific block is specified, and in this case, the above-mentioned limitation to the process mode in the SAO process is not performed.

  As described with reference to FIG. 2B, the DF processing refers to the pixel value of the pixel located within the range of maximum 4 pixels from the boundary for filtering, and locates the range of maximum 3 pixels from the boundary for filtering It is processing to change the pixel value of the pixel being processed. Further, as described with reference to FIG. 3, in the DF processing, the DF processing in the filter target boundary of the vertical edge in the screen is performed first, and thereafter, the DF processing in the filter target boundary of the horizontal edge in the screen is performed . Therefore, in the DF processing at the filter target boundary of the vertical edge of the DF processing for the specific block in the case where the Chip division boundary is in the vertical direction in the screen, the pixel value of the specific adjacent pixel does not change. That is, in this case, it is the DF process on a specific block at the filter target boundary of the horizontal edge that changes the pixel value of the specific adjacent pixel.

  In HEVC, the filter target boundary is defined as a boundary of a block of 8 pixels × 8 pixels and a boundary of a prediction unit (PU) or a transform unit (TU). Here, PU is a unit block in the process of screen prediction in the moving picture coding apparatus 100. Moreover, TU is a unit block in the process of orthogonal transformation in the moving picture coding apparatus 100. Here, this filter target boundary is referred to as a “determination target filter boundary”.

  Here, for the purpose of the following description, FIG. 10 shows each of the pixels adjacent to the specific adjacent pixel and the Chip division boundary among the pixels in the pair of specific blocks adjacent to each other across the judgment target filter boundary. As illustrated, give an identifier according to the placement.

  That is, among the pixels included in the specific block P which is one of the pair of specific blocks, for the pixels adjacent to the Chip division boundary, p_0, 0, p_1, 0 in the order from the determination target filter boundary. , P_2,0, and p_3,0. Further, among the pixels included in the specific block P, specific adjacent pixels are given names as p_0, 3, p_1, 3, p_2, 3 and p_3, 3 in order of proximity to the determination target filter boundary. Furthermore, among the pixels included in the specific block Q that is the other of the pair of specific blocks, for the pixels adjacent to the Chip division boundary, q_0, q0, q_1, 0 in order of proximity to the determination target filter boundary. , Q_2,0, and q_3,0. Then, among the pixels included in the specific block Q, specific adjacent pixels are given names as q_0, 3, q_1, 3, q_2, 3, and q_3, 3 in order of proximity to the determination target filter boundary.

In HEVC, when either of the following two conditions is satisfied, DF processing is not performed on a pair of specific blocks P and Q adjacent to each other across the determination target filter boundary.
[1] The boundary strength value Bs for the judgment target filter boundary is not 1 or more (is 0).
[2] The following [Expression 1] does not hold for the pixel values of the pixels included in the specific blocks P and Q.

| p_2.0-2 * p_1.0 + p_0.0 | + | p_2.3-2 * p_1.3 + p_0.3 | +
| q_2.0-2 * q_1.0 + q_0.0 | + | q_2.3-2 * q_1.3 + q_0.3 | <β ......... [Expression 1]

The boundary strength value Bs is an index that represents the strength of block distortion at the judgment target filter boundary, and the case where this value is 0 is a case where it is judged that there is no block distortion at the judgment target filter boundary. . More specifically, Bs is set to 2 when at least one of the specific blocks P and Q is an intra prediction block. Also, in the case where both blocks of the specific blocks P and Q are inter prediction prediction blocks, at least one of the following three conditions [a], [b], and [c] is satisfied: Bs is set to 1. And Bs is set to 0 in other cases.
[A] At least one specific block includes orthogonal transform coefficients that are not zero.
[B] The difference between the motion vectors of the specific block P and the specific block Q is one or more pixels.
[C] The reference image in motion compensation is different between the specific block P and the specific block Q, or the number of motion vectors is different.

  Further, the left side of the above [Equation 1] is for calculating an index representing the flatness of the original image (original image), and the “*” mark represents multiplication. Β on the right side is a threshold. That is, the case where [Expression 1] is established is the case where it is determined that the original image is flat. The value of the threshold β is determined based on the value obtained by giving a predetermined offset to the average value of the quantization parameter of each of the specific blocks P and Q.

  In the second example of the SAO processing control process, even if it is determined that the first example has the possibility of changing the pixel value of the specific adjacent pixel, the above-mentioned [1] If either of the conditions [2] is not satisfied, it is determined that the pixel value of the specific adjacent pixel does not change. Then, when this determination is made, the above-described restriction on the processing mode in the SAO processing is not performed. However, in order to eliminate the influence of the DF processing on the vertical edge of the chip division boundary, the condition of [2] above is changed to [Equation 1] anew with [Equation 2] as the condition with only the pixel values for specific adjacent pixels Make it possible to make judgments.

      | p_2.3-2 * p_1.3 + p_0.3 | + | q_2.3-2 * q_1.3 + q_0.3 | <β ..... [Equation 2]

  Here, FIG. 11 will be described. FIG. 10 is a flowchart illustrating the process content of the second example of the SAO process control process performed by the SAO process control unit 203.

  In FIG. 11, the same processing steps as those in the flowchart of the first example illustrated in FIG. 8 are assigned the same processing step numbers, and description of these processing steps is omitted.

  In FIG. 11, when the determination result in S202 is Yes, the SAO process control unit 203 proceeds with the process to S211. In S211, the SAO processing control unit 203 obtains boundary strength values Bs of all judgment target filter boundaries for a specific block in contact with the chip division boundary in the vertical direction on the screen, and determines whether any of them is 1 or more. Perform processing to judge. The various parameters used to obtain the boundary strength value Bs are received from the filter control unit 107 (FIG. 1).

  When the SAO process control unit 203 determines that the determination target filter boundary whose boundary strength value Bs is 1 or more exists in the determination process of S211 (when the determination result is Yes), the process proceeds to S212. On the other hand, when it is determined that the SAO process control unit 203 determines that the determination target filter boundary whose boundary strength value Bs is 1 or more does not exist (the boundary strength values Bs are all 0) (when the determination result is No) Then, the process proceeds to S204 described above.

  Next, in S212, the SAO process control unit 203 performs a process of determining whether or not any of the judgment target filter boundaries described above holds the above-mentioned [Expression 2]. The various parameters used in Equation 1 are received from the filter control unit 107 (FIG. 1).

  When the SAO processing control unit 203 determines that the judgment object filter boundary in which the above-mentioned [Equation 2] is satisfied exists in the judgment processing of S212 (when the judgment result is Yes), the processing is performed in S203 described above. Advance. On the other hand, when the SAO process control unit 203 determines that there is no determination object filter boundary where the above-mentioned [Equation 2] holds (when the determination result is No), the process proceeds to S204 described above.

The SAO process control unit 203 may perform the second example of the process control process described above.
Next, FIG. 12 will be described. FIG. 12 is a functional block diagram of an example of a large scale integrated circuit device that performs moving image encoding processing.

  Large Scale Integration (LSI) 1000 is a large scale integrated circuit device that performs moving image coding processing compliant with HEVC. The LSI 1000 has a function in charge of moving image encoding processing for one of the divided areas when the screen is divided into a plurality of areas. The LSI 1000 is referred to as being connected to a synchronous dynamic random access memory (SDRAM) 2000.

  The LSI 1000 includes an image input unit 1100, an encoding processing unit 1300, a divided boundary area filter processing unit 1400, an inter-chip data transfer IF 1500, a memory control unit 1600, and an overall control unit 1700.

  The image input unit 1100 receives a moving image which is an input image. The received input image is stored in the SDRAM 2000 via the memory control unit 1600.

  The stream output unit 1200 reads out and outputs, via the memory control unit 1600, the encoded data stream obtained by the moving image encoding process and stored in the SDRAM 2000.

  The encoding processing unit 1300 performs encoding processing on a moving image, which is an input image, to generate an encoded data stream. The input image is read from the SDRAM 2000 via the memory control unit 1600, and the generated encoded data stream is stored in the SDRAM 2000 via the memory control unit 1600.

  The division boundary area filter processing unit 1400 performs DF processing and SAO processing on a specific block in contact with the division boundary in the division area that the LSI 1000 is in charge of. The divided boundary area filter processing unit 1400 acquires various data required for processing from the divided boundary filter data storage memory area 2100 in the SDRAM 2000 via the memory control unit 1600. Also, divided boundary area filter processing section 1400 stores the processed data in frame memory area 2200 for storing local decoded image in SDRAM 2000 via memory control section 1600. That is, the divided boundary area filter processing unit 1400 provides the function of the divided boundary filter processing unit 230 in FIG. 7. The divided boundary filter data storage memory area 2100 and the local decoded image storage frame memory area 2200 in the SDRAM 2000 function as the boundary processing data memory 220 and the frame memory 210 in FIG. 7, respectively.

  The inter-chip data transfer IF 1500 exchanges various types of data with other processing devices in charge of the moving image encoding processing of the divided region adjacent to the divided region in which the LSI 1000 is in charge of processing.

  The memory control unit 1600 controls exchange of various data between the image input unit 1100, the encoding processing unit 1300, the divided boundary area filter processing unit 1400, the inter-chip data transfer IF 1500, and the SDRAM 2000.

  The overall control unit 1700 controls operations of the image input unit 1100, the encoding processing unit 1300, the division boundary area filter processing unit 1400, the inter-chip data transfer IF 1500, and the memory control unit 1600, which are included in the LSI 1000. Do.

  Next, the detailed configuration of the encoding processing unit 1300 will be described. The encoding processing unit 1300 includes a data transfer interface unit 1310, an image preprocessing unit 1320, an image encoding processing unit 1330, a variable length encoding processing unit 1340, an adjacent pixel / adjacency information buffer 1350, and a codec control unit 1360. There is.

  The data transfer interface unit 1310 exchanges various data with the SDRAM 2000 via the memory control unit 1600.

  The image pre-processing unit 1320 includes an intra prediction unit 1321 and a motion vector pre-search unit 1322. The intra prediction unit 1321 selects a prediction mode in intra prediction based on the input image. The motion vector pre-stage search unit 1322 narrows down the motion vector candidates before the motion vector search performed by the image coding processing unit 1330.

  The image coding processing unit 1330 obtains an input image stored in the SDRAM 2000 via the memory control unit 1600, performs coding processing on the input image, and outputs coded data. The detailed configuration of the image coding processing unit 1330 will be described.

  A subtractor (DIFF) 1331 obtains a prediction error which is a difference between the input image and a predicted image of the input image.

  The transform unit (T) 1332 orthogonally transforms the prediction error output from the subtractor 1331 and outputs the obtained transform coefficient.

  A quantization unit (Q) 1333 quantizes the transform coefficient output from the transform unit 1332 to obtain quantized data.

  The inverse quantization unit (IQ) 1334 inversely quantizes the quantized data output from the quantization unit 1333 to obtain a transform coefficient.

  The inverse transform unit (IT) 1335 performs inverse orthogonal transform on the transform coefficient output from the inverse quantization unit 1334 to obtain a prediction error.

  The motion vector search unit 1336 searches for a motion vector using the processing result of the image preprocessing unit 1320 to determine a motion vector.

  The prediction image generation unit 1337 performs in-screen prediction using the processing result of the image preprocessing unit 1320 to generate a prediction image.

  The motion compensation unit 1339 generates a local decoded image using the transform coefficient output from the inverse transform unit 1335, the motion vector determined by the motion vector search unit 1336, and the predicted image generated by the predicted image generation unit 1337.

  The in-loop filter (LF) 1339 reduces block distortion and ringing occurring in the local decoded image, and the processed image is stored in the frame memory area 2200 for storing local decoded image in the SDRAM 2000 via the memory control unit 1600. Store. The in-loop filter 1339 provides the function of the filter processing unit 200 in FIG.

  The variable-length coding processing unit 1340 includes a Context Adaptive Binary Arithmetic Coding (CABAC) processing unit 1341. The CABAC processing unit 1341 performs entropy coding processing on the quantized data output from the quantization unit 1333, and stores the obtained data as coded data in the SDRAM 2000 via the memory control unit 1600.

  The adjacent pixel / adjacent information buffer 1350 is a buffer for storing information of adjacent pixels used in the processing in the encoding processing unit 1300.

  The CODEC control unit 1360 controls the operation of each unit included in the image coding processing unit 1330.

The LSI 1000 of FIG. 12 has the above configuration.
Next, in the case where each divided area when the screen is divided is divided by the LSI 1000 of FIG. 12 to perform moving image encoding processing, divided boundary area filter processing in the LSI 1000 that is in charge of adjacent divided areas. The data transfer procedure will be described with reference to FIG.

  13, LSIs 1000-1 and 1000-2 are a pair of divided areas adjacent to each other across a Chip divided area in the case where moving image encoding processing is performed by dividing each divided area when the screen is divided. Are large-scale integrated circuit devices in charge of each. The LSIs 1000-1 and 1000-2 both have the same configuration as the LSI 1000 illustrated in FIG. 12. The inter-chip data transfer bridge 3000 manages the exchange of various data between the LSI 1000-1 and the LSI 1000-2.

  First, the LSIs 1000-1 and 1000-2 execute the DF processing and the SAO processing on the divided areas they are in charge in parallel, using the LFs 1339-1 and 1339-2 which they respectively have. . The LSIs 1000-1 and 1000-2 carry out the images (SAO-processed images) of the respective divided areas after these processes to the frame memory areas 2200-1 and 2200-2 for storing local decoded images in the SDRAM 2000-1 and 2000-2. Store each in. (Arrow [1] in FIG. 13)

  Next, the LSI 1000-2 calculates pixel value data before DF processing for pixels in the range from the chip division boundary to 4 pixels and pixel value data after DF processing for pixels in the fifth pixel range from the chip division boundary. And to the LSI 1000-1. These pixel value data are received by the LSI 1000-1 via the inter-chip data transfer bridge 3000, and stored in the divided boundary filter data storage memory area 2100-1 in the SDRAM 2000-1. (The arrow [2] in FIG. 13) The LSI 1000-2 also stores these transfer data in the divided boundary filter data storage memory area 2100-2 in the SDRAM 2000-2.

  Next, the LSI 1000-1 executes pixel value data before DF processing for pixels in the range from the Chip division boundary to 4 pixels and pixel value data after DF processing for pixels in the fifth pixel range from the Chip division boundary. And are transferred to the LSI 1000-2. These pixel value data are received by the LSI 1000-2 through the inter-chip data transfer bridge 3000. (The arrow [3] in FIG. 13) The LSI 1000-1 stores these transfer data in the division boundary filter data storage memory area 2100-1 in the SDRAM 2000-1.

  Next, the LSIs 1000-1 and 1000-2 respectively execute DF processing on a specific block on a chip division boundary. In this DF processing, pixel value data of pixels in the range from the chip division boundary to four pixels before the DF processing of its own and DFs in the range from the chip division boundary to the four pixels transferred The pixel value data before processing is used. Thereafter, the LSIs 1000-1 and 1000-2 respectively execute the SAO process on the specific block after the DF process. In this process, the pixel value data of the pixels included in the specific block after the DF processing, the pixel of the fifth pixel from the chip division boundary which the processor itself has, and the pixel of the fifth pixel from the chip division boundary transferred And pixel value data after DF processing are used. The LSIs 1000-1 and 1000-2 read the pixel value data used for the DF process and the SAO process from the divided boundary filter data storage memory areas 2100-1 and 2100-2 in the SDRAM 2000-1 and 2000-2, respectively. Use. (Arrow [4] in FIG. 13)

After that, the LSI 1000-1 stores the pixel value data after the above-mentioned SAO processing is performed in the storage position for the pixel of the specific block in the frame memory area for local decoded image storage 2200-1 in the SDRAM 2000-1. The LSI 1000-2 also stores the pixel value data after the above-described SAO processing is performed in the storage position for the pixel of the specific block in the frame memory area 2200-2 for storing the local decoded image in the SDRAM 2000-2. (Arrow [5] in FIG. 13)
By performing the processing as described above, the amount of data transferred for in-loop filter processing between the LSI 1000-1 and the LSI 1000-2 decreases.

  As an example, the reduction effect of the data transfer amount per eight boundary pixels when performing the in-loop filter processing at the Chip division boundary will be described.

  When pixel value data before DF processing of a pixel located within a range of 8 pixels from the chip division boundary is transferred and performed, pixel value data of 8 pixels × 8 pixels = 64 pixels is transferred. On the other hand, when transferring pixel value data of a pixel located within a range of eight pixels from the Chip division boundary before DF processing and pixel value data after DF processing located at the fifth pixel from the boundary, 4 + 1) pixels × 8 pixels = 40 pixels. Therefore, the transfer amount of pixel value data is reduced by 37.5%. In addition to this, in the case of the former, parameters for DF processing are transferred by 4 blocks, while in the case of the latter, transfer of parameters for DF processing of 2 blocks is sufficient. Transfer volume is reduced by 50%. (DF process parameters (prediction mode (within screen / between screens) flag, motion vector, reference image identification information, coefficient presence / absence flag, TU edge flag, quantization parameter, etc.) are about 14 bytes per block. The transfer amount of the SAO processing parameter does not change between the former case and the latter case. (Note that the SAO processing parameter (SAO offset value, etc.) is about 14 Bytes per CTB.) If the above are combined, the data transfer amount is reduced by about 40% as a whole between the former case and the latter case.

  Next, the case where a moving image encoding process is executed by a computer will be described. FIG. 14 illustrates an example of the hardware configuration of the computer 3000.

  A micro processing unit (MPU) 3001 is an arithmetic processing unit that controls the overall operation of the computer 3000.

  The Read Only Memory (ROM) 3002 is a read only semiconductor memory in which a predetermined basic control program is prerecorded. The MPU 3001 performs operation control of each component of the computer 3000 by reading out and executing this basic control program when the computer 3000 is started.

  The Random Access Memory (RAM) 3003 is a semiconductor memory that can be written and read as needed, which is used as a working storage area as needed when the MPU 3001 executes various control programs.

  The hard disk drive 3004 is a storage device for storing various control programs executed by the MPU 3001 and various data. The MPU 3001 performs various control processes by reading out and executing a predetermined control program stored in the hard disk device 34. The hard disk drive 3004 may be, for example, a solid state drive (SSD) using a semiconductor memory.

  The input device 3005 is, for example, a keyboard device or a mouse device. When operated by the user, for example, the input device 3005 acquires an input of various information from the user associated with the operation content, and acquires the acquired input information as the MPU 3001 Send to

  The display device 3006 is, for example, a liquid crystal display, and displays various texts and images according to display data sent from the MPU 3001.

  The interface device 3007 manages exchange of various information with various devices connected to the computer 3000.

  The recording medium drive device 3008 is a device that reads various control programs and data recorded on a portable recording medium 3010. The MPU 3001 may perform various control processes to be described later by reading out and executing a predetermined control program recorded in the portable recording medium 3010 via the recording medium drive device 3008. The portable recording medium 3010 may be, for example, a compact disc read only memory (CD-ROM) or a digital versatile disc read only memory (DVD-ROM). Furthermore, as the portable recording medium 3010, for example, a flash memory provided with a connector of Universal Serial Bus (USB) standard may be used.

  The components included in the computer 3000 are connected via a bus line 3009, and exchange of various data is performed mutually under the control of the MPU 3001.

  In order to cause the computer 3000 to perform the moving image encoding process, for example, a control program for causing the MPU 3001 to perform the moving image encoding process described below is created. The created control program is stored in advance in the hard disk drive 3004 or the portable recording medium 3010, and the MPU 3001 is given a predetermined instruction to read out the control program for execution. In this way, the moving picture encoding process by the computer 3000 is realized.

  Next, FIG. 15 will be described. FIG. 15 is a flowchart illustrating the processing content of the moving picture coding process.

  When the process of FIG. 15 is started, the MPU 3001 first performs an input image acquisition process in S301. This process is a process of acquiring an input image which is a moving image and temporarily storing it in the RAM 3003.

  Next, the MPU 3001 performs encoding processing in S302. In this processing, the input image stored in the RAM 3003 is read, the difference between the input image and the predicted image of the input image is encoded to generate encoded data, and the encoded data is temporarily stored in the RAM 3003. is there. In the process of S302, in the moving picture coding apparatus 100 of FIG. 1, the in-screen prediction unit 109, the in-screen evaluation unit 110, the motion evaluation unit 111, the motion compensation unit 112, the switch 113, and the subtractor 102. And the transformation and quantization unit 103.

  Next, the MPU 3001 performs local decoding processing in S303. This process is a process of reading out and decoding the encoded data stored in the RAM 3003, and forming a locally decoded image based on the result of the decoding and the above-described predicted image. The process of S303 is a process performed by the inverse quantization and inverse transformation unit 104 and the adder 105 in the moving picture coding apparatus 100 of FIG.

  Next, the MPU 3001 performs a DF process in S304. The DF process is a process performed on each block in the screen of the local decoded image based on the pixels included in the block and the pixels of the pixels included in the blocks adjacent to the block. The MPU 3001 also performs processing of storing the pixel value data after processing in the RAM 3003. The process of S304 is a process performed by the DF processing unit 201 in the configuration of FIG.

  Next, the MPU 3001 performs SAO processing control processing in S305. This control process has a possibility of changing the pixel value of the specific adjacent pixel adjacent to the specific adjacent block among the pixels included in the specific block in contact with the chip division boundary in the processing in S304. It is a process which controls the processing content of the SAO process of S306. In this control, the SAO process for the specific adjacent block is limited to one based on pixels other than the specific adjacent pixel. More specifically, the MPU 3001 performs one of the first example and the second example of the SAO process control process illustrated in FIGS. 8 and 11 as the process of S305. The process of S305 is a process performed by the SAO process control unit 203 in the configuration of FIG.

  Next, the MPU 3001 performs SAO processing in S306. This SAO process is a process performed on each block after the DF process of S304 based on the pixels included in the block and the pixel values of the pixels adjacent to the block, and the SAO of S305. It is processing performed under control by processing control processing. The MPU 3001 also performs processing of storing the pixel value data after processing in the RAM 3003. The process of S306 is a process performed by the SAO processing unit 202 in the configuration of FIG.

  Next, the MPU 3001 performs encoded data output processing in S307. In this process, encoded data stored in the RAM 3003 is read and subjected to entropy coding, and various information is added to the obtained data in a predetermined format to generate and output a coded data stream. It is. The process of S307 is a process performed by the entropy coding unit 115 in the moving picture coding apparatus 100 of FIG.

  Next, the MPU 3001 performs divided boundary processing data transmission processing in S308. This processing includes pixel value data before DF processing in S304 for pixels in the range from the chip division boundary to 4 pixels and pixel value data after DF processing in S304 for the pixels in the fifth pixel range from the chip division boundary. Are read from the RAM 3003 and transmitted. The destination of these data is the moving image encoding process of the divided area in which the computer 3000 is in charge of processing the input image, and the divided area adjacent to each other across the Chip division boundary. It is a processing device.

  Next, the MPU 3001 performs divided boundary processing data transmission processing in S309. This processing includes pixel value data before DF processing in S304 for pixels in the range from the chip division boundary to 4 pixels and pixel value data after DF processing in S304 for the pixels in the fifth pixel range from the chip division boundary. And is stored in the RAM 3003. Note that the transmission source of these data is the processing device of the transmission destination of the data in the process of S308.

  Next, the MPU 3001 performs division boundary DF processing in S310. This process is a process of performing a DF process based on pixel values included in each of a pair of specific blocks sandwiching a chip division boundary, stored in the RAM 3003, on each of the pair of specific blocks. The process of S310 is a process performed by the boundary DF processing unit 231 in the configuration of FIG.

  Next, the MPU 3001 performs division boundary SAO processing in S311. This process is an SAO process performed on each of the pair of specific blocks after the boundary DF process of S310. In this division boundary SAO processing, the pixels included in the pair of specific blocks after the boundary DF processing in S310 and the pixels in the specific adjacent block among the pixels of the image after DF stored in the RAM 3003 are specific adjacent This processing is based on the pixel value of the pixel adjacent to the pixel. The process of S311 is a process performed by the boundary SAO processing unit 232 in the configuration of FIG.

  After finishing the process of S311, the MPU 3001 returns the process to S301 and repeats the above-described process.

  The above process is the moving picture coding process illustrated by the flowchart in FIG. This process is executed by the computer 3000 to realize moving picture coding using the computer 3000.

The following appendices will be further disclosed regarding the embodiment including each example described above.
(Supplementary Note 1)
An encoding unit that encodes a difference between an input image and a predicted image of the input image;
A local decoding unit that decodes the encoded data output from the encoding unit and obtains a local decoded image based on the result of the decoding and the predicted image;
An image processing unit that performs image processing on the local decoded image;
A prediction unit for obtaining the predicted image based on the local decoded image after the image processing;
Equipped with
The image processing unit
The first filtering process for each block in the screen of the local decoded image divided into a plurality of rectangular blocks is based on the pixels included in the block and the pixel values of the pixels included in the block adjacent to the block. A first filter processing unit, and
A second filter processing unit that performs second filter processing on each block after the first filter processing is performed based on pixels included in each block and pixel values of pixels adjacent to each block;
The first filter for the pixels adjacent to the specific block among the pixels included in the specific adjacent block adjacent to the specific block on the opposite side to the specific block among the plurality of rectangular blocks on the opposite side to the specific line A memory for storing pixel values of pixels after the processing has been performed;
Equipped with
The second filter processing unit stores, in the memory, the second filtering process for the specific block after the first filtering process is performed, the specification of the pixels in the specific adjacent block. It is performed using the pixel value of the pixel adjacent to the block and after the first filtering process is performed on the specific adjacent block.
A moving picture coding apparatus characterized in that.
(Supplementary Note 2)
When the first filter processing has a possibility of changing the pixel value of a specific adjacent pixel adjacent to the specific adjacent block among the pixels included in the specific block, the second filter processing unit The moving image according to Additional Note 1, further comprising: a control unit configured to control the second filter process on the specific adjacent block to be performed based on pixels other than the specific adjacent pixel. Encoding device.
(Supplementary Note 3)
The control unit determines whether the first filter process for the specific block changes the pixel value of the specific adjacent pixel, and determines that the first filter process does not change the pixel value of the specific adjacent pixel The moving picture coding apparatus according to claim 2, wherein the second filter processing unit is controlled such that the restriction to the second filtering process on the specific adjacent block is not performed in the case where the second filtering process is performed.
(Supplementary Note 4)
The first filtering process is a deblocking filtering process in the H. 265 | MPEG-H High Efficiency Video Coding (HEVC) standard,
The second filtering process is a sample adaptive offset (SAO) process in the HEVC standard.
The video encoding apparatus according to any one of appendices 1 to 3, characterized in that:
(Supplementary Note 5)
The first filtering process is a deblocking filtering process in the H. 265 | MPEG-H High Efficiency Video Coding (HEVC) standard,
The second filter processing is sample adaptive offset (SAO) processing in the HEVC standard,
The control unit performs the restriction to the second filter process on the specific adjacent block by selecting a class of a pixel array adjacent in the vertical direction as an edge offset class in the SAO process. The moving picture coding device according to supplementary note 2 or 3.
(Supplementary Note 6)
The first filtering process is a deblocking filtering process in the H. 265 | MPEG-H High Efficiency Video Coding (HEVC) standard,
The control unit determines that the first filtering process for the specific block does not change the pixel value of the specific adjacent pixel when the direction of the boundary is not the vertical direction on the screen.
The moving picture coding apparatus according to claim 3, characterized in that
(Appendix 7)
Even when the direction of the boundary is the vertical direction of the screen, the control unit has a boundary strength value of 1 or more in the boundary where the specific blocks in contact with the boundary are adjacent to each other. The moving image encoding apparatus according to claim 6, wherein, in the case of not being performed, it is determined that the first filter process on the specific block does not change the pixel value of the specific adjacent pixel.
(Supplementary Note 8)
The control unit is configured such that the direction of the boundary is the vertical direction on the screen, and there are one or more boundary strength values for boundaries between specific blocks adjacent to the boundary. In such a case, pixel values of three pixels in order of proximity from the boundary among specific adjacent pixels included in one of a pair of specific blocks adjacent to each other across the boundary are p_0, 3, p_1, 3, p_2, respectively. Let the pixel values of three pixels in order of proximity from the boundary among the specific adjacent pixels included in the other of the pair of specific blocks be q_0, 3, q_1, 3, q_2, 3, and β is a predetermined threshold. If the following equation,
| p_2.3-2 * p_1.3 + p_0.3 | + | q_2.3-2 * q_1.3 + q_0.3 | <β
It is determined whether the first filter process on the specific block does not change the pixel value of the specific adjacent pixel when it is determined that the first block process does not change. The moving picture coding apparatus according to claim 1.
(Appendix 9)
A moving picture coding method performed by a moving picture coding apparatus, comprising:
Encoding the difference between the input image and the predicted image for the input image to generate encoded data;
The encoded data is decoded, and a locally decoded image is formed based on the result of the decoding and the predicted image,
Perform image processing on the local decoded image;
Generating the predicted image based on the local decoded image after the image processing;
In the image processing,
The first filtering process for each block in the screen of the local decoded image divided into a plurality of rectangular blocks is based on the pixels included in the block and the pixel values of the pixels included in the block adjacent to the block. Done,
The first filter for the pixels adjacent to the specific block among the pixels included in the specific adjacent block adjacent to the specific block on the opposite side to the specific block among the plurality of rectangular blocks on the opposite side to the specific line The pixel value of the pixel after the processing is stored in a memory included in the video encoding device,
Performing a second filtering process on each block after the first filtering process based on pixels included in the block and pixel values of pixels adjacent to the block;
The second filtering process for the specific block after the first filtering process is a pixel adjacent to the specific block among the pixels in the specific adjacent block stored in the memory. And using the pixel value of the pixel after the first filtering process is performed on the specific adjacent block,
A moving picture coding method characterized in that.
(Supplementary Note 10)
A program that causes a computer to execute a moving image encoding process, and
Encoding the difference between the input image and the predicted image for the input image to generate encoded data;
The encoded data is decoded, and a locally decoded image is formed based on the result of the decoding and the predicted image,
Perform image processing on the local decoded image;
Making a computer execute a process of generating the predicted image based on the locally decoded image after the image processing;
In the image processing,
The first filtering process for each block in the screen of the local decoded image divided into a plurality of rectangular blocks is based on the pixels included in the block and the pixel values of the pixels included in the block adjacent to the block. Done,
The first filter for the pixels adjacent to the specific block among the pixels included in the specific adjacent block adjacent to the specific block on the opposite side to the specific block among the plurality of rectangular blocks on the opposite side to the specific line Storing the pixel value of the pixel after the processing is performed in a memory provided in the computer,
Performing a second filtering process on each block after the first filtering process based on pixels included in the block and pixel values of pixels adjacent to the block;
The second filtering process for the specific block after the first filtering process is a pixel adjacent to the specific block among the pixels in the specific adjacent block stored in the memory. And using the pixel value of the pixel after the first filtering process is performed on the specific adjacent block,
A program characterized by

DESCRIPTION OF SYMBOLS 100 Video encoding device 101 Block division part 102 Subtractor 103 Transformation and quantization part 104 Inverse quantization and inverse transformation part 105 Adder 106 In-loop filter 107 Filter control part 108, 210-1, 210-2 Frame memory 109 Intra prediction unit 110 In-screen evaluation unit 111 Motion evaluation unit 112 Motion compensation unit 113 Switch 114 Control unit 115 Entropy coding unit 200-1 and 200-2 Filter processing unit 201 DF processing unit 202 SAO processing unit 203 SAO processing control unit 204 memories 220-1 and 220-2 boundary processing data memory 230 division boundary filter processing unit 231 boundary DF processing unit 232 boundary ASO processing unit 1000 LSI
1100 image input unit 1200 stream output unit 1300 encoding processing unit 1400 division boundary area filter processing unit 1500 data transfer between chips
1600 memory control unit 1700 overall control unit 2000 SDRAM
2100 Data storage memory area for division boundary filter 2200 Frame memory area for storing locally decoded image 3000 computer 3001 MPU
3002 ROM
3003 RAM
3004 hard disk drive 3005 input device 3006 display device 3007 interface device 3008 recording medium drive device 3009 bus line 3010 portable recording medium

Claims (1)

An encoding unit that encodes a difference between an input image and a predicted image of the input image;
A local decoding unit that decodes the encoded data output from the encoding unit and obtains a local decoded image based on the result of the decoding and the predicted image;
An image processing unit that performs image processing on the local decoded image;
A prediction unit for obtaining the predicted image based on the local decoded image after the image processing;
A video encoding apparatus Ru provided with,
The image processing unit includes a first module and a second module,
The first module is
The first filtering process for each block in the screen of the local decoded image divided into a plurality of rectangular blocks is based on the pixels included in the block and the pixel values of the pixels included in the block adjacent to the block. A first filter processing unit, and
A second filter processing unit that performs second filter processing on each block after the first filter processing is performed based on pixels included in each block and pixel values of pixels adjacent to each block;
The first filter for the pixels adjacent to the specific block among the pixels included in the specific adjacent block adjacent to the specific block on the opposite side to the specific block among the plurality of rectangular blocks on the opposite side to the specific line A transfer unit for transferring the pixel value of the pixel after processing to the second module;
Equipped with
The second module is adjacent to the specific block among the pixels in the specific adjacent block, which has received the second filtering process from the first module after performing the first filtering process on the specific block. there row using the pixel values of the pixels after the first filtering and for the specific adjacent block a pixel is made to be,
The video encoding apparatus has a possibility that the first filtering process has a possibility of changing the pixel value of a specific adjacent pixel adjacent to the specific adjacent block among the pixels included in the specific block. If it is determined that the second filter processing unit is determined to have the possibility of changing the second filter processing unit, the second filter processing for the specific adjacent block is performed by using the second filter processing unit other than the specific adjacent pixel. A control unit that controls the second filter processing unit so as not to perform the restriction to the second filter processing on the specific adjacent block when it is determined that the restriction is performed based on pixels and is not changed Further comprising
A moving picture coding apparatus characterized in that.