JP6514533B2 - Calculation method of switching waveform of circuit model for simulation of electronic circuit - Google Patents

Description

  The present invention relates to a circuit model for simulation of an electronic circuit composed of a diode connected in parallel with a switching element, and to a method of calculating a switching waveform of the circuit model for simulation.

  In order to reduce the power loss of power electronics devices, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or Insulated Gate Bipolar Transistors (IGBTs) are used as switching elements that turn on and off the drive current flowing to electrical devices. Power devices such as are used.

  Then, when these switching elements switch, a temporal change (dV / dt) in voltage occurs. Conducted noise is generated on the wiring due to a time-dependent change of this voltage and a parasitic inductance of the wiring or a parasitic element such as a parasitic capacitance between the wiring and the ground. The conducted noise affects other devices through the wiring and is emitted from the wiring into the air to become a radiation noise.

  By the way, in order to reduce the switching loss of the switching element, the switching speed of the switching element tends to increase year by year. Furthermore, recently, power MOSFETs using silicon carbide (SiC: Silicon Carbide) or gallium nitride (GaN: Gallium Nitride) instead of IGBTs have been mass-produced as high-voltage power devices, and their switching speed has been increased. As a result, the conducted noise tends to increase.

  For conducted noise, many countries have established the EMC (Electro Magnetic Compatibility) standard in compliance with the International Special Committee on Radio Interference (CISPR) of the international standard, and it is necessary to satisfy this standard for mass production. There is. It is necessary to evaluate whether it passes EMC standard with the same product as mass production, but since it is necessary to redesign when it is rejected, it takes much time for conducted noise measures. For this reason, there is an increasing demand to obtain conduction noise in advance by numerical analysis.

  In order to obtain the conducted noise by numerical analysis, it is necessary to have a device model that faithfully reproduces an actual waveform reflecting temporal changes in voltage and current of the switching element. As a device model, a device simulation model that analyzes the structure of a device such as a diffusion layer and the thickness of an oxide film by a two-dimensional or three-dimensional finite element method can faithfully reproduce the switching waveform of the switching element.

  By the way, in order to analyze an electronic circuit, it is necessary to consider a control pattern related to the time of pulse width modulation (PWM) as well as modeling of a peripheral circuit such as a wiring cable and a motor. Although the model for device simulation depends on the number of meshes of the model, it takes one hour or more to calculate the switching waveform for 1 μs. Also, the PWM cycle is on the order of ms, and using the device simulation model takes more than 1000 hours, which is not practical for actual design. On the other hand, in the circuit simulator, although it depends on the circuit size, it can be calculated in about one hour to calculate the switching waveform for 1 ms.

  As a circuit simulation model for IGBT, a model which exists in Unexamined-Japanese-Patent No. 2010-257174 (patent document 1) is proposed. The model in this patent document 1 is composed of an Nch MOSFET model, a PNP BJT model, and a current controlled current source. The current controlled current source takes any current flowing in the collector electrode of the PNP BJT model as an input. The tail current can be simulated by outputting the current between the drain electrode and the source electrode of the Nch-type MOSFET model, and the simulation result based on the measurement result can be obtained.

  Further, as a circuit simulation model, Japanese Patent Laid-Open No. 2009-26298 (Patent Document 2) proposes a method of reproducing a switching waveform with high accuracy by expressing voltage and voltage change by a mathematical expression. In Patent Document 2, an input data generation unit that generates input data from an electric circuit model and a device model, a solver unit that executes a simulation using input data, and an output editing unit that edits and outputs a simulation result are described. The circuit calculation is performed by approximating the static characteristics of the IGBT, the MOSFET, and the diode with broken lines, and the static characteristic approximate circuit calculation unit of the solver unit performs the circuit calculation. According to this, it is possible to simulate the transient characteristics of the IGBT with high accuracy.

JP, 2010-257174, A JP, 2009-26298, A

  Then, in a control device using a switching element such as an IGBT or a MOSFET, a configuration is adopted in which an electronic circuit in which a switching element and a diode are connected in parallel is one arm, and two upper and lower arms are connected in series. And the electric load of a motor etc. is controlled by controlling the gate of two switching elements of an up-and-down arm. Such a control device is often used in inverter control of a motor or the like.

  When analyzing an electronic circuit in which such a switching element and a diode are connected in parallel, simulate (simulate) the voltage waveform of the collector-emitter voltage of the switching element of each arm and the current waveform of the collector current. is necessary.

  However, when controlling the gates of the two switching elements of the upper and lower arms in this way, for example, the waveforms of the collector-emitter voltage and the collector current of the upper arm together with the state of the gate terminal voltage of the upper arm It is known to be determined by the state of the terminal voltage. In particular, since the collector current of the upper arm changes the transient waveform due to the operation of the switching element of the lower arm, the information of only the gate voltage of the upper arm can not accurately reproduce the waveform of the collector current of the upper arm transient state There was a problem. Similarly, the collector current of the lower arm changes the transient waveform due to the operation of the switching element of the upper arm. In this way, the upper and lower arms interact with each other with respect to the collector current.

  In Patent Document 1 and Patent Document 2, no description suggesting the above-mentioned problems is found. In particular, in Patent Document 2, only the gate terminal of the own arm is incorporated in the model, and the waveform of the collector current in the transient state of the control device using the upper and lower arms can not be accurately reproduced.

  An object of the present invention is to provide a simulation circuit model capable of accurately reproducing the waveform of collector-emitter voltage and collector current in a transient state, and a method of calculating a switching waveform thereof.

  A feature of the present invention models an electronic circuit in which two switching elements and two diodes connected in parallel are connected in series as one arm, and functions of respective waveforms of collector-emitter voltage and collector current of each switching element are functioned. It is expressed by the equation, and the gate voltage of one arm and the other arm is input, and the functional equation of the collector-emitter voltage and the collector current is selected according to the gate voltage.

  According to the present invention, the waveform of the collector-emitter voltage and the collector current is selected by selecting the functional equation of the collector-emitter voltage and the collector current of the switching element according to the gate voltage of one arm and the other arm. It becomes possible to reproduce accurately.

It is a circuit block diagram of the electronic circuit which connected in series what connected IGBT and the diode in parallel. FIG. 2 is a circuit diagram when a load is provided between the emitter terminal and the collector terminal of the upper arm of the circuit shown in FIG. 1 and this load is connected to a high voltage power supply. FIG. 3 is a characteristic diagram showing a collector voltage and collector current of an upper arm corresponding to a gate voltage of an upper arm, a current flowing to a diode of the lower arm, and an anode-cathode voltage of this diode in the circuit configuration shown in FIG. It is a block diagram which shows the structure of the circuit model for simulation of the electronic circuit shown in FIG. FIG. 5 is a flow chart diagram for calculating a voltage waveform by selecting a functional expression of the own arm when the gate voltage of the own arm is switched from on to off in the circuit model for simulation shown in FIG. 4. FIG. 5 is a flowchart for calculating a current waveform by selecting a functional expression of the own arm when the gate voltage of the other arm is switched from on to off in the circuit model for simulation shown in FIG. 4. FIG. 5 is a flow chart diagram for calculating a voltage waveform by selecting a functional expression of the own arm when the gate voltage of the own arm is switched from off to on in the circuit model for simulation shown in FIG. 4. FIG. 5 is a flow chart diagram for calculating a current waveform by selecting a functional expression of the own arm when the gate voltage of the other arm is switched from off to on in the circuit model for simulation shown in FIG. 4.

  Hereinafter, although the embodiment of the present invention will be described in detail with reference to the drawings, the present invention is not limited to the following embodiment, and various modifications and applications can be made within the technical concept of the present invention. Is also included in that range.

  FIG. 1 shows a general electronic circuit in which an IGBT as a switching element and a diode connected in parallel are used as one arm, and two of them are connected in series.

  In FIG. 1, the upper arm is composed of an upper IGBT 1a and an upper diode 2a connected in parallel thereto, and the upper IGBT 1a includes an upper gate terminal 10a, an upper emitter terminal 11a and an upper collector terminal 12a. The upper emitter terminal 11a and the upper collector terminal 12a are connected to the upper diode 2a, and are connected in parallel to the upper IGBT 1a.

  On the other hand, the lower arm is composed of a lower IGBT 1 b and a lower diode 2 b connected in parallel thereto, and the lower IGBT 1 b includes a lower gate terminal 10 b, a lower emitter terminal 11 b and a lower collector terminal 12 b. The lower emitter terminal 11b and the lower collector terminal 12b are connected to the lower diode 2b, and are connected in parallel to the lower IGBT 1b.

  The upper collector terminal 12a of the upper arm is connected to the high voltage side of a high voltage power supply not shown in the drawing. The upper emitter terminal 11a of the upper arm and the lower collector terminal 12b of the lower arm are connected to each other. The connection portion is connected to the output terminal 13, and the output terminal 13 is connected to an electric load such as a motor (not shown). Furthermore, the emitter terminal 11b of the lower arm is connected to the low voltage side of a high voltage power supply not shown in the drawing. The electronic circuit composed of the upper and lower arms described above is well known and is used in a control device such as a motor.

  Next, the state of change of the collector-emitter voltage and collector current of each arm (upper arm in the following description) in the transition state when the gate voltage is switched will be described. FIG. 2 shows a circuit when switching is performed by connecting an inductance load 200 between the upper collector terminal 12a and the upper emitter terminal 11a of the upper arm.

  One terminal of the inductance load 200 is connected to the upper collector terminal 12a of the upper arm, and a wiring inductance 202 is present between the inductance load 200 and the upper collector terminal 12a. The other terminal of the inductance load 200 is connected to the emitter terminal 11a of the upper arm.

  The upper collector terminal 12 a is connected to the high voltage side terminal of the high voltage power supply 201, and the wiring inductance 203 of the wiring exists between the upper collector terminal 12 a and the high voltage side terminal of the high voltage power supply 201. The low voltage side terminal of the high voltage power supply 201 is grounded together with the lower emitter terminal 11b of the lower arm.

  In the circuit of FIG. 2 described above, when the gate control signal is input to the upper gate terminal 10a of the upper arm, the gate voltage of the upper gate terminal 11a of the upper arm, the collector of the upper collector terminal 12a and the upper emitter terminal 11a The waveforms of the voltage between the emitter, the collector current of the upper collector terminal 12a, the voltage between the anode and the cathode of the diode 2b of the lower arm, and the current flowing to the diode 2b of the lower arm are schematically shown in FIG. Although the following description relates to the input of the gate terminal 10a of the upper arm, the same applies to the input of the gate terminal 10b of the lower arm.

  In FIG. 3, as shown in (a), the gate voltage G1 of the gate terminal 10a is turned on at time t1 from the "on steady state" in which the gate voltage G1 of the gate terminal 10a of the upper arm is stable in the on state. As shown in (b), the collector current of the collector terminal 12a of the upper arm decreases from time t1. On the other hand, as shown in (c), although the collector-emitter voltage increases, ΔV1 = transiently due to the time change rate dIc / dt of the current due to the decrease of the collector current and the wiring inductance 203 (inductance Ls1). The voltage of Ls1 × dIc / dt is superimposed on the voltage value Vcc of the power supply 201. Thus, in the transient state, the wiring inductance 203 is affected. When time t2 is reached after a predetermined time T1 at which the collector current decreases and decreases to the leakage current value, the collector-emitter voltage settles to the voltage value Vcc of the power supply 201, and the collector current also becomes a substantially constant value due to leakage current. Become.

  Here, between time t1 and time t2, as shown by (d), the current of the upper arm is commutated to the diode 2b of the lower arm to increase the current, and as shown by (e), The voltage between the anode and the cathode decreases, and when a predetermined time T1 is passed and time t2 is reached, the forward drop voltage becomes substantially constant.

  Thus, the collector current of the collector terminal 12b of the lower arm is affected in response to the change of the gate voltage of the upper arm. Similarly, the collector current of the collector terminal 12a of the upper arm is affected in response to the change of the gate voltage of the lower arm.

  Here, during the period from time t1 to time t2, an “on-off transient state” is established when the gate voltage G1 of the upper gate terminal 10a is switched from on to off. Also, after time t2, the "off steady state" is established.

  Next, as shown in (a), when time passes from the "off steady state" and the gate voltage G1 of the gate terminal 10a of the upper arm switches from off to on at time t3, as shown in (b) The collector current of the collector terminal 12a of the upper arm starts to increase, and a predetermined peak current Irp (this will be described later) is added and becomes approximately constant at time t4 after a predetermined time T2. On the other hand, the voltage between the collector and the emitter of the collector terminal 12a of the upper arm starts to decrease, and becomes approximately 0 V at time t4 after a predetermined time T2.

  In addition, during the period from time t3 to time t4, the current of the lower arm diode 2b decreases as shown by (d), and the carrier accumulated in the diode 2b generates a peak current having a recovery current Irp. This peak current Irp is to be added to the collector current of the upper arm.

  Further, as shown in (e), the voltage between the anode and the cathode of the diode 2b increases from time t3, and transiently ΔV2 = due to the temporal change rate dIrp / dt of the recovery current and the wiring inductance 202 (inductance value Ls2). The voltage of Ls2 × dIrp / dt is superimposed on the voltage value Vcc of the power supply 201. When reaching the time t4 after the predetermined time T2, since the temporal change rate dIrp / dt of the recovery current becomes 0, the voltage value Vcc of the power supply 201 becomes substantially constant. As described above, during the period from time t3 to time t4, an “off-on transient state” is established when the gate voltage G1 of the upper gate terminal 10a is switched from off to on. Also, after time t4, the "on steady state" is attained again.

  Thus, in the upper arm, "on steady state", "on-off transient state", "off steady state" and "off-on transient" corresponding to the change of the gate voltage G1 of the upper gate terminal 10a. It is classified into four states of "state". Similarly, in the lower arm, the "on steady state", "on-off transient state", "off steady state" and "off-on transient state" corresponding to the change of the gate voltage G2 of the lower gate terminal 10b. It is classified into four states.

  And in accordance with this, in the circuit model for simulation, the functional expressions relating to the collector-emitter voltage are "on steady-state voltage functional equation", "on-off transient voltage functional equation", "off steady-state voltage functional equation" and "off “On transient voltage function expression” is required. Furthermore, the functional expressions for the collector current also require “on steady-state current functional equation”, “on-off transient current function equation”, “off steady-state current equation” and “off-on transient current equation”.

  In addition to this, since the current of the diode of the other arm is affected corresponding to the operation based on the gate voltage of the one arm, the other arm is selected in the functional equation of the collector current of one arm. The information of the gate voltage of

  The circuit model for simulation shown in FIG. 4 is configured in consideration of the above description. What is important is that in this model, modeling is performed using a series of functional equations without distinction between IGBTs and diodes. Therefore, in the flowchart to be described later, no distinction is made between the IGBT and the diode, and a voltage function equation related to the collector-emitter voltage and a current function equation related to the collector current are selected.

  In FIG. 4, the upper arm model 30a is provided with the first upper gate terminal 20a (so-called regular gate terminal) of the upper arm, the second upper gate terminal 21a, the upper emitter terminal 22a, and the upper collector terminal 23a as terminals. There is. The lower arm model 30b is provided with a first lower gate terminal 20b (so-called regular gate terminal) of the lower arm, a second lower gate terminal 21b, a lower emitter terminal 22b, and a lower collector terminal 23b as terminals.

  Here, the first upper gate terminal 20a of the upper arm model 30a is connected to the second lower gate terminal 21b of the lower arm model 30b, and the second gate terminal 21a of the upper arm model 30a is the first of the lower arm model 30b. It is connected to the lower gate terminal 20b. That is, in addition to the regular gate terminals 20a and 20b of the respective arms, the gate terminals 21a and 21b of the other arm are provided. Thus, a functional expression of collector current of each arm is selected.

  In the upper arm model 30a, a functional equation regarding the collector-emitter voltage of the IGBT 1a is set. As described above, this functional equation is an on-state steady-state voltage function equation (Vson = f (t, Vg1)), an on-off transient voltage function equation (Vtron = f (t, Vg1)), an off-state voltage functional equation (Vsoff = F (t, Vg1)) and off-on transient voltage function formula (Vtroff = f (t, Vg1)). Here, t is time, and Vg1 is a gate voltage of the first upper gate terminal 20a.

  Further, in the upper arm model 30a, a functional equation regarding the collector current is set. As described above, this functional equation is an on-stationary current functional equation (Ison = f (t, Vg2)), an on-off transient current functional equation (Itron = f (t, Vg2)), an off-stationary current functional equation (Isoff) = F (t, Vg2) and off-on transient current function formula (Itroff = f (t, Vg2)). Here, t is time, and Vg2 is a gate voltage of the second upper gate terminal 21a (= first lower gate terminal 20b).

  Similarly, the lower arm model 30b is provided with a functional equation regarding the collector-emitter voltage. As described above, this functional equation is the on-state steady-state voltage function equation (Vson = f (t, Vg2)), the on-off transient voltage function equation (Vtron = f (t, Vg2)), the off-stationary voltage function equation (Vsoff = F (t, Vg2) and the off-on transient voltage function formula (Vtroff = f (t, Vg2)). Here, t is time, and Vg2 is a gate voltage of the first lower gate terminal 20b.

  Further, the lower arm model 30 b is provided with a functional equation regarding the collector current. As described above, this functional equation is an on-stationary current functional equation (Ison = f (t, Vg1)), an on-off transient current functional equation (Itron = f (t, Vg1)), an off-stationary current functional equation (Isoff) = F (t, Vg1)) and off-on transient current function formula (Itroff = f (t, Vg1)). Here, t is time, and Vg1 is a gate voltage of the second lower gate terminal 21b (= first upper gate terminal 20a).

  Each of the functional expressions described above can be obtained by an appropriate method, and for example, one obtained by approximating a waveform actually measured by a functional expression or one obtained by approximating a waveform obtained by device simulation by a functional expression It can be used.

  Next, a method of calculating a switching waveform using such a simulation circuit model will be described. In the following description, since the same calculation is performed for both the upper and lower arms, it will be described as the own arm and the other arm. However, since the regular gate voltage of the own arm is not the regular gate voltage of the other arm in the other arm but the gate voltage of the other arm, the selection of the functional equation is different.

  FIG. 5 shows a flowchart for selecting a functional expression of the self arm when the normal gate voltage of the self arm is switched from the “on state” to the “off state”. In this case, the functional expression of the collector-emitter voltage is selected because it is the normal gate voltage of its own arm.

«Step S10A»
In step S10A, the process proceeds to step S11A in order to set the time to 0 seconds and start the following calculation.

«Step S11A»
In step S11A, the gate voltage of its own arm is detected. In this case, for example, it is the gate voltage G1 of the first upper gate terminal 20a of FIG. When the detection of the gate voltage is completed, the process proceeds to step S12A.

«Step S12A»
In step S12A, it is determined whether the gate voltage of the self arm has changed from a high state to a low state. That is, it is determined whether the gate voltage is maintained in the "on state" or switched from on to off. If it is determined that the "on state" is continuing, the process proceeds to step S13A, and if it is determined that the "on state" is switched to the "off state", the process proceeds to step S14A.

«Step S13A»
In step S13A, since it is determined that the "on state" is maintained in step S12A, the on-state steady-state voltage functional expression (Vson = f (t, Vg1)) is used as it is.

«Step S14A»
In step S14A, it is determined whether or not the gate voltage has been switched from on to off and a predetermined time (for example, time T1 in FIG. 3) has passed or is in the process of passing. For example, it can be determined by measuring the time when the gate voltage falls below a predetermined threshold and comparing this time with the set time. This determination is made during the "on-off transient state" or whether the "off steady state" has been entered. And if predetermined time has not passed, it will transfer to step S15A, and if predetermined time has passed, it will transfer to step S16A. Although the gate voltage is used for this determination in this embodiment, it goes without saying that other parameters such as the collector current can be used besides this, and the same applies to the following embodiments.

«Step S15A»
In step S15A, since it is determined in step S14A that the "on-off transient state" is present, the on-off transient voltage functional equation (Vtron = f (t, Vg1)) is selected.

«Step S16A»
On the other hand, in step S16A, because it is determined in step S14A that the "off steady state" is established, the off steady state voltage functional expression (Vsoff = f (t, Vg1)) is selected.

«Step S17A»
In step S17A, the collector-emitter voltage at the current time t = ta is calculated based on the functional expressions selected in step S13A, step S15A and step S16A. When this calculation is completed, the process proceeds to step S18A.

«Step S18A»
In step S18A, next time t = ta + Δt is calculated to calculate the collector-emitter voltage at the next time. When this calculation is completed, the process proceeds to step S19A.

«Step S19A»
In step S19A, it is determined whether or not a preset calculation end time has been reached. If the calculation end time has not been reached, the process returns to step S11A, and the processes of step S11A to step S18A are repeated to calculate the collector-emitter voltage with each lapse of time. If it is determined in step S19A that the calculation end time has been reached, the process proceeds to step S20A.

«Step S20A»
In step S20A, assuming that all calculations have been completed, this calculation flow is ended and the process ends.

  On the other hand, FIG. 6 shows a flowchart for selecting a functional expression of the own arm when the gate voltage of the other arm is switched from the "on state" to the "off state" instead of the regular gate voltage of the own arm. In this case, since the gate voltages of the other arms are input, a functional equation of the collector current is selected.

«Step S10B»
In step S10B, which is the same as step 10A, the process proceeds to step S11B in order to set the time to 0 seconds and start the following calculation.

<< step S11 B >>
In step S11B, gate voltages of the other arms are detected. In this case, for example, it is the gate voltage G2 of the second upper gate terminal 21a of FIG. When the detection of the gate voltage is completed, the process proceeds to step S12B.

«Step S12B»
In step S12B, it is determined whether the gate voltage of the other arm has changed from the high state to the low state. That is, it is determined whether the gate voltage of the other arm is maintained in the "on state" or switched from on to off. If it is determined that the "on state" is continuing, the process proceeds to step S13B, and if it is determined that the "on state" is switched to the "off state", the process proceeds to step S14B.

«Step S13B»
In step S13B, since it is determined in step S12B that the "on state" is maintained, the on steady state current function equation (Ison = f (t, Vg2)) is used as it is.

«Step S14B»
In step S14B, it is determined whether the gate voltage has been switched from on to off and a predetermined time has passed or is in progress in the same manner as step S14A. This determination is made during the "on-off transient state" or whether the "off steady state" has been entered. And if predetermined time has not passed, it will transfer to step S15B, and if predetermined time has passed, it will transfer to step S16B.

«Step S15B»
In step S15B, since it is determined in step S14B that the "on-off transient state" is present, the on-off transient current function equation (Itron = f (t, Vg2)) is selected.

«Step S16B»
On the other hand, in step S16B, because it is determined in step S14B that the “off steady state” is established, the off steady state current function equation (Isoff = f (t, Vg2)) is selected.

«Step S17B»
In step S17B, the collector current at the current time t = ta is calculated based on the functions selected in step S13B, step S15B and step S16B. When this calculation is completed, the process proceeds to step S18B.

«Step S18B»
In step S18B, next time t = ta + Δt is calculated in order to calculate the collector current at the next time. When this calculation is completed, the process proceeds to step S19B.

«Step S19B»
In step S19B, it is determined whether or not a preset calculation end time has been reached. If the calculation end time has not been reached, the process returns to step S11B, and the processes of steps S11B to S18B are repeated to calculate the collector current for each elapsed time. If it is determined in step S19B that the calculation end time has been reached, the process proceeds to step S20B.

«Step S20B»
In step S20B, assuming that all calculations have been completed, this calculation flow is ended and the process ends.

  Although the case of calculating the collector-emitter voltage and the collector current of the own arm has been described in FIGS. 5 and 6, in the case of calculating the collector-emitter voltage and the collector current of the other arm, the opposite relationship is applied. The same calculation is performed. That is, when the collector-emitter voltage shown in FIG. 5 is calculated by the own arm, the normal gate voltage of the own arm is the other gate voltage of the other arm, so the collector current of FIG. Will be done. When the collector current shown in FIG. 6 is calculated by the own arm, the collector-emitter voltage of FIG. 5 is calculated by the other arm.

  Next, FIG. 7 shows a flowchart for selecting a functional expression of the own arm when the normal gate voltage of the own arm is switched from the “off state” to the “on state”. In this case, since the gate voltage of its own arm, a functional equation of the collector-emitter voltage is selected.

<< step S10 C >>
In step S10C, as in step S10A, the process proceeds to step S11C in order to set the time to 0 seconds and start the following calculation.

<< step S11 C >>
In step S11C, the gate voltage of the self arm is detected. In this case, for example, it is the gate voltage G1 of the first upper gate terminal 20a of FIG. When the detection of the gate voltage is completed, the process proceeds to step S12C.

<< step S12 C >>
In step S12C, it is determined whether the gate voltage of the self arm has changed from a low state to a high state. That is, it is determined whether the gate voltage is maintained in the "off state" or switched from off to on. If it is determined that the "off state" is continuing, the process proceeds to step S13C, and if it is determined that the off state is switched on, the process proceeds to step S14C.

«Step S13C»
In step S13C, because it is determined that the "off state" is maintained in step S12C, the off steady state voltage functional expression (Vsoff = f (t, Vg1)) is used as it is.

«Step S14C»
In step S14C, it is determined whether the gate voltage is switched from off to on and a predetermined time (for example, a predetermined time T2 in FIG. 3) has elapsed or is in the middle of the elapse. This can be determined, for example, by measuring the time when the gate voltage exceeds a predetermined threshold and comparing this time with the set time. This determination is made during the "off-on transient state" or whether the "on steady state" has been entered. And if predetermined time has not passed, it will transfer to step S15 C, and if predetermined time has passed, it will transfer to step S16C.

<< step S15 C >>
In step S15C, since it is determined that the "off-on transient state" is in step S14C, the off-on transient voltage functional equation (Vtroff = f (t, Vg1)) is selected.

«Step S16C»
On the other hand, in step S16C, since it is determined in step S14C that the "on steady state" is established, the on steady state voltage functional expression (Vson = f (t, Vg1)) is selected.

«Step S17C»
In step S17C, the collector-emitter voltage at the current time t = ta is calculated based on the functions selected in step S13C, step S15C and step S16C. When this calculation is completed, the process proceeds to step S18C.

«Step S18C»
In step S18C, next time t = ta + Δt is calculated to calculate a collector-emitter voltage at the next time. When this calculation is completed, the process proceeds to step S19C.

«Step S19C»
In step S19C, it is determined whether or not a preset calculation end time has been reached. If the calculation end time has not been reached, the process returns to step S11C, and the processes of steps S11C to S18C are repeated to calculate the collector-emitter voltage every time. If it is determined in step S19C that the calculation end time has been reached, the process proceeds to step S20C.

«Step S20C»
In step S20C, assuming that all calculations have been completed, this calculation flow is ended and the process ends.

  On the other hand, FIG. 8 shows a flowchart for selecting the functional equation of the own arm when the gate voltage of the other arm is switched from the “off state” to the “on state” instead of the regular gate voltage of the own arm. In this case, since the gate voltages of the other arms are input, a functional equation of the collector current is selected.

«Step S10D»
In step S10D, the process proceeds to step S11D in order to set the time to 0 second and start the following calculation as in step 10B.

<< step S11 D >>
In step S11D, gate voltages of other arms are detected. In this case, for example, it is the gate voltage G2 of the second upper gate terminal 21a of FIG. When the detection of the gate voltage is completed, the process proceeds to step S12D.

<< step S12D >>
In step S12D, it is determined whether the gate voltage of the other arm has changed from the low state to the high state. That is, it is determined whether the gate voltage is maintained in the "off state" or switched from off to on. If it is determined that the "off state" is continuing, the process proceeds to step S13D, and if it is determined that the off state is switched on, the process proceeds to step S14D.

«Step S13D»
In step S13D, since it is determined that the "off state" is maintained in step S12D, the off steady state current function equation (Isoff = f (t, Vg2)) is used as it is.

«Step S14D»
In step S14D, as in step S14C, it is determined whether the gate voltage is switched from on to off and a predetermined time has elapsed, or it is in the middle of the elapse. This determination is made during the "off-on transient state" or whether the "on steady state" has been entered. And if predetermined time has not passed, it will transfer to step S15D, and if predetermined time has passed, it will transfer to step S16D.

<< step S15 D >>
In step S15D, because it is determined that the "off-on transient state" is in step S14D, the off-on transient current function equation (Itroff = f (t, Vg2)) is selected.

<< step S16D >>
On the other hand, in step S16D, since it is determined in step S14D that the "on steady state" is present, the on steady state current function equation (Ison = f (t, Vg2)) is selected.

«Step S17D»
In step S17D, the collector current at the current time t = ta is calculated based on the functions selected in step S13D, step S15D and step S16D. When this calculation is completed, the process proceeds to step S18D.

«Step S18D»
In step S18D, next time t = ta + Δt is calculated to calculate the collector current at the next time. When this calculation is completed, the process proceeds to step S19D.

«Step S19D»
In step S19D, it is determined whether or not a preset calculation end time has been reached. If the calculation end time has not been reached, the process returns to step S11D, repeats the processes of steps S11D to S18D, and calculates the collector current for each elapsed time. If it is determined in step S19D that the calculation end time has been reached, the process proceeds to step S20D.

<< step S20D >>
In step S20D, assuming that all calculations have been completed, this calculation flow is ended and the process ends.

  As described in FIG. 5 and FIG. 6, when the collector-emitter voltage shown in FIG. 7 is calculated by the own arm, the normal gate voltage of the own arm is the other gate voltage of the other arm. In the other arm, the calculation of the collector current in FIG. 8 is performed. When the collector current shown in FIG. 8 is calculated by the own arm, the collector-emitter voltage of FIG. 7 is calculated by the other arm.

  As described above, according to the present invention, an electronic circuit in which two switching elements and two diodes connected in parallel are connected in series as one arm is modeled, and the collector-emitter voltage and collector current of each switching element are calculated. Each waveform is expressed as a functional expression, and the gate voltage of one arm and the other arm is input, and the functional expression of the collector-emitter voltage and the collector current is selected according to the gate voltage.

  According to this, the waveform of the collector-emitter voltage and the collector current can be accurately determined by selecting the functional equation of the collector-emitter voltage of the switching element and the collector current according to the gate voltage of one arm and the other arm. It is possible to reproduce in

  The present invention is not limited to the embodiments described above, but includes various modifications. For example, the embodiments described above are described in detail in order to explain the present invention in an easy-to-understand manner, and are not necessarily limited to those having all the configurations described. Also, part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. In addition, with respect to a part of the configuration of each embodiment, it is possible to add, delete, and replace other configurations.

  DESCRIPTION OF SYMBOLS 1a, 1b ... IGBT, 2a, 2b ... Diode, 10a, 10b ... Gate terminal, 11a, 11b ... Emitter terminal, 12a, 12b ... Collector terminal, 20a, 20b ... Normal gate terminal of the circuit model for simulation, 21a, 21b ... gate terminals of the other circuit of the simulation circuit model 22a, 22b ... emitter terminals of the simulation circuit model, 23a, 23b ... collector terminals of the simulation circuit model, 30a, 30b ... simulation circuit model.

Claims (3)

In a method, a computer calculates a switching waveform of a circuit model for simulation of an electronic circuit in which upper and lower arms are configured by connecting in series two arms in which a switching element and a diode are connected in parallel,
The computer
The respective waveforms of the collector-emitter voltage of the switching element of each arm and the collector current obtained by combining the current flowing through both the switching element and the diode are represented by functional expressions and modeled, and one arm And the collector-emitter voltage of the one arm is represented as a function of the gate voltage of the one arm, and the collector current of the one arm is represented as a function of the gate voltage of the other arm;
A gate terminal for inputting a regular gate voltage and a gate voltage of the other arm is provided in the modeled one arm, and a regular gate voltage and the one gate voltage are provided in the modeled other arm. Provide a gate terminal to input
Based on a change in gate voltage of the normal gate terminal of the one arm, a voltage functional expression of the collector-emitter voltage of the switching element of the one arm is selected, and based on the selected voltage functional expression Calculating the waveform of the collector-emitter voltage of the switching element;
Based on a change in gate voltage of the other gate terminal of the one arm, a current function expression of the collector current of the switching element of the one arm is selected, and the switching is performed based on the selected current function expression. Calculate the waveform of the collector current of the device
A calculation method of a switching waveform of a circuit model for simulation of an electronic circuit characterized by In claim 1,
The computer is
During a predetermined time after the input state of the gate voltage of the normal gate terminal of the one arm is switched, a voltage functional expression of a transient state of the collector-emitter voltage of the switching element of the one arm is obtained. After the lapse of the predetermined time, the steady-state voltage functional equation of the collector-emitter voltage of the switching device of the one arm is selected, and the switching equation of the switching device is selected based on these voltage functional equations. Calculate the waveform of collector-emitter voltage,
During the predetermined time after the input state of the gate voltage of the other gate terminal of the one arm is switched, a current function equation of the transient state of the collector current of the switching element of the one arm is selected After the predetermined time has elapsed, a steady-state current function expression of the collector current of the switching element of the one arm is selected, and a waveform of the collector current of the switching element is selected based on these current function expressions. calculate
A calculation method of a switching waveform of a circuit model for simulation of an electronic circuit characterized by In claim 2,
The computer is
When the gate voltage input to the normal gate terminal of the one arm changes from the on state to the off state, the on-off transient voltage function formula is selected, and the gate voltage changes from the off state to the on state Selects the off-on transient voltage function equation and calculates the waveform of the collector-emitter voltage of the switching element based on these voltage function equation,
When the gate voltage input to the other gate terminal of one arm changes from the on state to the off state, the on-off transient current function equation is selected, and when the gate voltage changes from the off state to the on state An off-on transient current function equation is selected, and the waveform of the collector current of the switching element is calculated based on these current function equations.
A calculation method of a switching waveform of a circuit model for simulation of an electronic circuit characterized by

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