JP6510128B1 - Tollgate data processing device, information processing device, setting method of lane terminal control mechanism of tollgate data processing device, setting method of terminal control mechanism of information processing device, and setting program - Google Patents

Abstract

An object of the present invention is to provide a tollgate data processing apparatus capable of reducing the development load of a dedicated lane terminal control mechanism (for example, a dedicated PCI expansion card) in a virtual environment. A tollgate data processing device according to an embodiment connects a central management system of a toll collection system to a roadside device and a lane terminal provided in a lane of the tollgate, and the tollgate data processing device controls lane terminals It comprises a mechanism, a storage unit, and a processor. A lane terminal control interface interfaces with the lane terminal. The storage unit stores a program. The processor sets a bit related to initial setting to the first register of the lane terminal control mechanism by the virtual BIOS on the virtual environment based on the program stored in the storage unit, and the terminal control mechanism driver on the virtual environment Thus, the bit related to the internal operation of the traffic lane terminal control mechanism is set in the second register of the traffic lane terminal control mechanism. [Selected figure] Figure 2

Description

  The embodiment of the present invention relates to a tollgate data processing device, an information processing device, a setting method of lane terminal control mechanism of the tollgate data processing device, a setting method of terminal control mechanism of the information processing device, and a setting program.

  As a toll collection system for toll roads such as expressways, ETC (Electronic Toll Collection System, hereinafter referred to as "ETC system") and toll tickets are used, which are collected by wireless communication between onboard communication device and roadside communication device. A magnetic card system is used.

  The toll collection system is roughly divided into a central (upper) central management system and each toll booth equipment (lower). Each tollgate facility includes a tollgate data processing device provided in a machine room or the like, a roadside device for performing start control and the like on a passing vehicle, and a lane terminal in a booth provided for each lane in which the vehicle travels. Equipped with

  Among these, the tollgate data processing device provided in the machine room of the tollgate is connected to the lane terminal and the roadside device, receives information from the lane terminal and the roadside device, and is connected to the central management system, the lane terminal and the roadside The information from the device is transmitted, and the central management system aggregates the information transmitted from the toll booth data processing device.

  The toll booth data processing apparatus is developed to communicate with the lane equipment (lane terminal) by means of a communication protocol developed specifically for this system. That is, the tollgate data processing apparatus includes a lane terminal control mechanism (hereinafter, referred to as “dedicated lane terminal control mechanism”) developed specifically for the present system. For example, the dedicated lane terminal control mechanism is a dedicated PCI (Peripheral Component Interconnect) expansion card.

  Generally, with servers or PCs, with the advancement of operating system (OS) virtualization technology, it is possible to operate legacy software assets in a legacy environment in a virtual environment, and the toll booth data described above The same applies to the processing apparatus. In order to directly access a PCI expansion card from a guest OS on a virtual environment, a technique called PCI pass-through (access not via the host OS) is required.

  In a virtual environment, a virtual BIOS exists on the host OS, and allows the guest OS to access the PCI expansion card. In order for the PCI expansion card to operate properly in a virtual environment, it is necessary to properly initialize the PCI expansion card from the virtual BIOS.

  Conventionally, in the setting related to the operation inside the card on the PCI expansion card, it is necessary for the PCI expansion card vendor to change the virtual BIOS which is free software and have the virtual BIOS community adopt it.

  General purpose PCI expansion cards aimed to be distributed to the market in large numbers, PCI expansion card vendors actively register in the virtual BIOS community, and general users can easily operate the PCI expansion cards in a virtual environment It is possible to

JP, 2008-004013, A JP 2001-344185 A Japanese Patent Publication No. 2015-518615 gazette

  In the toll booth data processing apparatus described above, the developers of the toll booth data processing apparatus change the virtual BIOS (setting related to the operation inside the card) in order to use a special (low versatility) PCI expansion card in a virtual environment. ), And it is necessary to register to the community of virtual BIOS. Such registration of the virtual BIOS with the community not only takes time to approve, but also bears the risk of being disapproved. As a result, the period from development to release may be prolonged, which may lead to an increase in the burden on developers.

  The object of the present invention is tollgate data processing device, information processing device, lane terminal of tollgate data processing device capable of reducing development load of dedicated lane terminal control mechanism (for example, dedicated PCI expansion card) in virtual environment A setting method of a control mechanism, a setting method of a terminal control mechanism of an information processing apparatus, and a setting program.

  The tollgate data processing apparatus according to the embodiment connects the central management system of the toll collection system to the roadside device and the lane terminal provided in the lane of the tollgate, and the tollgate data processing apparatus includes: lane terminal control mechanism; And a processor. A lane terminal control interface interfaces with the lane terminal. The storage unit stores a program. The processor sets a bit related to initial setting to the first register of the lane terminal control mechanism by the virtual BIOS on the virtual environment based on the program stored in the storage unit, and the terminal control mechanism driver on the virtual environment Thus, the bit related to the internal operation of the traffic lane terminal control mechanism is set in the second register of the traffic lane terminal control mechanism.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows an example of schematic structure of the toll collection system which concerns on embodiment. It is a block diagram which shows an example of a schematic structure of the tollgate data processing apparatus in the toll collection system which concerns on embodiment. It is a flowchart which shows the outline | summary of development of the tollgate data processor which concerns on embodiment. It is a flowchart which shows an example of the process for operating a PCI expansion card in a virtual environment in the tollgate data processing apparatus which concerns on embodiment. It is a block diagram which shows an example of schematic structure of the tollgate data processing apparatus as a comparative example. It is a flowchart which shows the outline | summary of development of the tollgate data processor of a comparative example.

  Hereinafter, an example of the toll collection system according to the embodiment will be described with reference to the drawings. In the present embodiment, the toll collection system is described as an example, but the present invention is not limited to the toll collection system, and can be applied to various information processing systems. Hereinafter, the toll collection system can be read as an information processing system.

FIG. 1 is a block diagram showing an example of a schematic configuration of a toll collection system according to the embodiment.
Toll roads are provided at entrances and exits of toll roads and the like to which the toll collection system is applied, and one or more lanes are provided at these entrances and exits.

  The toll collection system includes a start control bar for controlling the passage of the vehicle, and a roadside indicator provided at the side of the lane for displaying a guide such as a toll.

  The toll collection system receives tolls by wireless communication between an onboard unit (onboard unit loaded with an ETC card) mounted on a vehicle passing through the lane of a toll booth on a toll road and a roadside apparatus having an ETC antenna. If possible, open and close the start control bar to pass the vehicle. When wireless communication between the in-vehicle device and the roadside apparatus can not be performed, the ETC card and the lane terminal installed in the in-vehicle device receive a toll, for example, by reading data from the ETC card.

  As shown in FIG. 1, the toll collection system is roughly divided into a central (upper) central management system 1 and facilities of each toll booth (lower). The central management system 1 is also called a management station data processor. Each toll booth facility includes a toll plaza data processing device 2 provided in a machine room or the like. Furthermore, the toll collection system includes lane terminals 3 in a booth provided for each lane in which the vehicle travels at the toll station, and roadside devices 4 on the roadside outside the booth that performs start control and the like for passing vehicles. .

  When the toll collection system is read as an information processing system, the toll booth data processing device 2 can be read as an information processing device, and the lane terminal 3 can be read as a terminal device. The installation location is not limited.

  The central management system 1 is connected to the toll booth data processor 2 of each toll booth. The toll booth data processing device 2 of the predetermined toll booth is connected to the lane terminal 3 and the roadside device 4 provided in each lane of the same predetermined toll booth. The central management system 1 exchanges various data regarding toll collection with the toll booth data processing device 2 of each toll booth.

  The toll booth data processing device 2 communicates with the lane terminal 3 by a dedicated protocol via a dedicated communication board (a dedicated lane terminal control mechanism) to exchange various data. Further, the toll booth data processing device 2 communicates with the roadside device 4 in a general protocol (for example, TCP (transmission control protocol) / IP (internet protocol)) via a LAN (local area network) to exchange various data.

  For example, the central management system 1 transmits a toll table for each day, hour, and section, and the toll plaza data processing device 2 receives and stores the toll table. Further, the toll booth data processing device 2 transmits a toll table to the lane terminal 3.

  Lane terminal 3 is operated by a person in charge for handling payment to vehicles that do not use ETC such as cash or when there is a problem with payment by ETC communication (for example, failure to deliver ECT card, etc.) It is a clerk terminal. The lane terminal 3 receives and stores the toll table transmitted from the toll plaza data processing device 2. The lane terminal 3 receives settlement processing of tolls with cash, a credit card, or an ETC card associated with a credit card handed from the driver of a vehicle who is a user of a toll road, and based on the settlement result, etc. Control the opening and closing of the start control bar provided on the

  Further, charging data indicating the settlement result is transmitted to the toll station data processing device 2. Furthermore, the toll booth data processing device 2 transmits charging data to the central management system 1. The charging data corresponding to the cash settlement process includes an entrance toll gate ID, an exit toll gate ID, a settlement date, a settlement amount, and the like. The charge data corresponding to the settlement process by the credit includes a credit card number, an entrance toll gate ID, an exit toll gate ID, a settlement date, a settlement amount, and the like. The charging data corresponding to the settlement processing by the ETC card includes an ETC card number, an entrance toll gate ID, an exit toll gate ID, a settlement date, a settlement amount, and the like. The entrance toll gate ID is read from a pass ticket or an ETC card handed over by the driver or the like. Further, the exit tollgate ID is a tollgate ID in which the lane terminal 3 is installed, and the lane terminal 3 receives and stores the exit tollgate ID transmitted from the tollgate data processing device 2.

  The roadside device 4 is an ETC device equipped with an ETC antenna, and the roadside device 4 installed at the entrance toll booth communicates wirelessly with the on-board unit mounted on the vehicle passing through the lane of the toll booth by the ETC antenna. The entrance information including the place ID and the entrance date and time is transmitted.

  The in-vehicle device is loaded with an ETC card, and the in-vehicle device records entrance information on the ETC card. The roadside device 4 installed at the exit toll booth communicates wirelessly with the on-board unit mounted on the vehicle passing the lane of the toll booth via the ETC antenna, and the exit information including the exit toll booth ID and the date and time of participation It transmits and receives vehicle unit ID, ETC card ID, and entrance information. The on-board unit records exit information on the ETC card.

  The roadside device 4 transmits toll station data processing device 2 a traffic record including the entrance tollgate ID, the entrance date and time, the exit tollgate ID, and the date and time of participation. The toll plaza data processing device 2 calculates the toll based on the toll table and the passage record, and transmits to the central management system 1 billing data indicating the toll.

FIG. 2 is a block diagram showing an example of a schematic configuration of the tollgate data processing device 2 in the toll collection system according to the embodiment.
The tollgate data processing device 2 shown in FIG. 2 implements communication with the lane terminal 3 using a dedicated protocol, and uses a dedicated communication board (a dedicated lane terminal control mechanism 23). In addition, in the toll booth data processing apparatus 2, in order to perform application unification (commonization) with the current toll booth data processing apparatus, OS virtualization is performed, and an environment similar to the current toll booth data processing apparatus is constructed virtually. Do.

As shown in FIG. 2, the tollgate data processing device 2 includes a processor 21, a storage unit 22, a lane terminal control mechanism 23, and a communication interface 24.
The processor 21 and a program (host OS or the like) stored in the storage unit 22 cooperate with each other to control each unit. That is, the processor 21 operates based on the program stored in the storage unit 22, resets the register of the lane terminal control mechanism 23, writes a predetermined value to the register, and rewrites the predetermined value of the register.

  The storage unit 22 stores a host OS, a guest OS, a BIOS, and the like which are programs for setting predetermined bits in the lane terminal control mechanism. The processor 21 operates based on a program such as a host OS stored in the storage unit 22 or a guest OS on a virtual machine monitor of the host OS, writes a predetermined value to a register of the lane terminal control mechanism 23, and An environment (a virtual machine monitor including a virtual BIOS) is constructed, and a predetermined value is written to a register of the lane terminal control mechanism 23 by the virtual BIOS.

  The setting process of the lane terminal control mechanism 23 can be realized only by installing and executing programs such as the guest OS and the BIOS on the tollgate data processing apparatus 2 on the virtual machine monitor of the host OS. For example, the toll booth data processing device 2 can download these programs via the network, store the downloaded programs, and complete the installation of the programs. Alternatively, the toll plaza data processing device 2 can read these programs from the information storage medium, store the read programs, and complete the installation of these programs.

  The lane terminal control mechanism 23 is a bus interface for connecting a terminal device to the processor 21 (computer). Here, the case where the lane terminal control mechanism 23 is a PCI (Peripheral Component Interconnect) expansion card will be described. For example, the PCI expansion card is configured to receive two cards, and one card can communicate with each lane terminal 3 of 16 lanes. As described above, the tollgate data processing apparatus 2 implements communication with the lane terminal 3 using a dedicated protocol, and therefore, the dedicated lane terminal control mechanism 23 is used. That is, the PCI expansion card corresponding to the lane terminal control mechanism 23 is not a general-purpose card but a dedicated card.

  The lane terminal control mechanism 23 includes a PCI configuration register 231 having a plurality of registers, and a device specific space 232 having a plurality of registers. Although it has been described that the PCI expansion card corresponding to the lane terminal control mechanism 23 is a dedicated card, the PCI configuration register 231 is a general-purpose register provided on a general-purpose card, and the PCI configuration register 231 is accessed Can be realized by generally disclosed processing procedures. On the other hand, the device-specific space 232 is a unique register provided in a space unique to a dedicated card that is not found in general-purpose cards, and the procedure for accessing the device-specific space 232 is not generally disclosed. , Information for access (address information) is required.

  The PCI configuration register 231 includes a register (first register) 2311 related to the operation of the OS, and the device specific space 232 includes a register (second register) 2312 related to the internal operation of the lane terminal control mechanism. The PCI configuration register 231 includes a plurality of registers 2311 related to the operation of the OS, and the device specific space 232 includes a plurality of registers 2321 related to the internal operation of the lane terminal control mechanism.

  For example, the following four registers R1, R2, R3 and R4 will be listed as the registers 2321 related to the internal operation of the lane terminal control mechanism. Although a plurality of registers exist in addition to these four, in the present embodiment, the following four registers will be described, and the descriptions of the other registers will be omitted.

The register R1 (Control register) is a register for defining the internal operation of the firmware (FW) of the PCI expansion card.
The register R2 (ECC (error correction code) register) is a register for monitoring a memory failure state of the PCI expansion card.
The register R3 (LED (light emitting diode) register) is a register for monitoring a hardware fault condition other than the memory of the PCI expansion card, and outputting (notifying) a fault with the LED when a fault occurs.
The register R4 (reset / reconfiguration register) is a register in which the PCI expansion card is reset when the bit is set.

  The communication interface 24 is an interface that transmits and receives information by communication with the central management system 1 and the like.

FIG. 3 is a flowchart showing an outline of development of the toll booth data processing apparatus according to the embodiment.
As shown in FIG. 3, the developers of the tollgate data processing device design the lane terminal control mechanism (PCI expansion card) (step ST11) and the terminal control mechanism driver to correspond to the design of the PCI expansion card. It changes (step ST12). Thereafter, operation verification in the virtual environment is performed (step ST13), and development is completed. This enables product release regardless of the version of virtual BIOS. Next, operation verification in a virtual environment will be described.

FIG. 4 is a flowchart showing an example of processing for operating a PCI expansion card in a virtual environment in the tollgate data processing apparatus according to the embodiment.
The processor 21 initializes the first register 2311 related to the operation of the OS by the virtual BIOS. At the time of initialization, the processor 21 initializes the PCI configuration register 231 by the virtual BIOS. That is, the processor 21 accesses the register 2311 (base address register) related to the operation of the OS by the virtual BIOS, and sets a bit related to the initial setting. The initial setting includes access information (address) to the register 2321 related to the internal operation of the lane terminal control mechanism of the device specific space 232.

  Thereafter, the processor 21 starts the initialization process of the terminal control mechanism driver (step ST1301), and sets an error code (step ST1303) when executing the kernel dump process (step ST1302, YES) (step ST1303). finish. Kernel dump processing is a mechanism (hereinafter referred to as “kdump”) of dumping a crash of the core of the OS (hereinafter referred to as “kernel”) so that the contents of the memory of the storage unit 22 can be saved and analyzed later. Refers to the description about initialization of the terminal control mechanism driver at runtime. In the case of kdump kernel, it means ending the initialization process of the terminal control mechanism driver. The PCI expansion card has already been initialized by the initialization of the terminal control mechanism driver by the kernel in a state where an error occurs in the kernel and it can not be completely recovered (hereinafter referred to as "panic").

  When initializing with kdump kernel, it will be doubly initialized (prevented with FW in the current implementation), and that the physical address for managing the time of the kernel space notified to FW is different (this is countered with FW) There are two problems with this problem, which are dealt with in kdump kernel driver initialization.

  When the processor 21 does not execute the kernel dump process (step ST1302, NO), the terminal control mechanism driver refers to the access information in the register 2311 related to the operation of the OS, and the register 2321 related to the internal operation of the lane terminal control mechanism. To set the bit related to the internal operation of the lane terminal control mechanism. That is, the processor 21 maps the register 2321 relating to the internal operation of the lane terminal control mechanism to the kernel space by the terminal control mechanism driver (step ST1304). Thereby, the register 2321 related to the internal operation of the lane terminal control mechanism is mapped in the PCI configuration space. The processor 21 can access the register 2321 related to the internal operation of the lane terminal control mechanism by the terminal control mechanism driver by the mapping of this step ST1304.

  Here, the order of initial setting (first setting) of the PCI configuration register 231 by the virtual BIOS and setting (second setting) related to the internal operation of the lane terminal control mechanism by the terminal control mechanism driver will be supplemented. The first setting is a standard setting conforming to the PCI-Express (hereinafter referred to as PCIe) standard called PCI-SIG. The second setting is a setting unique to the dedicated lane terminal control mechanism 23 (dedicated PCI expansion card). For the second setting, the first setting will be implemented first. With such a setting order, maintenance is performed by processing with a terminal control mechanism driver having high affinity with the hardware of a dedicated PCI expansion card, without including unique settings in a general-purpose program (virtual BIOS). Can be enhanced.

  Also, by dividing the PCI configuration register 231 and the device specific space 232 into independent spaces, it is possible to clarify the function sharing. That is, it is possible to prevent careless handling of the specific process related to the dedicated terminal control function from the management function of PCle on the host OS side.

  The register 2321 related to the operation inside the lane terminal control mechanism of the device specific space 232 is an area managed by the FW of the lane terminal control mechanism, and the host OS operates on the register 2321 related to the operation inside the lane terminal control mechanism. (Virtual BIOS) can not read and write without permission.

  For example, the register R3 (LED register) of the device specific space 232 holds fault monitoring information of the lane terminal control hardware. When the guest OS restarts, the PCI configuration space is initialized, but the information of the device specific space 232 is not a target of initialization. Therefore, even if the PCI configuration space is initialized, the information of the device specific space 232 is retained. As described above, by dividing the PCI configuration register 231 and the device specific space 232 into independent spaces, it is possible to avoid a failure such as an unintended loss of information due to the initialization of the PCI configuration space.

  Again, we return to the flowchart description. The processor 21 accesses various registers related to the lane terminal control mechanism 23 (step ST1305), detects an error of the lane terminal control mechanism 23 (YES in step ST1306), sets an error code (step ST1307), finish. If the processor 21 does not detect an error of the lane terminal control 23 (NO in step ST1306), the FW of the lane terminal control 23 and the mailbox register for the interface of the terminal control driver are mapped to the kernel space (step ST 1308). This is the enable part 1 (enable for MSI / MSI-X interrupt) required for PCI pass-through.

  Furthermore, the processor 21 sets the kernel of the guest OS so that the lane terminal control mechanism 23 can perform DMA (direct memory access) transfer to physical memory of the guest OS by PCI pass-through (step ST1309). This is the enabling part 2 (DMA enabling) required for PCI pass-through.

  Further, the processor 21 sets an interrupt (step ST1310), and sets the INT × interrupt of the command register in the PCI configuration register 231 to be invalid (step ST1311) so that PCI pass-through can be performed. This is one of invalidation (INT × invalidation of interrupts) required for PCI pass-through.

  The processor 21 passes the initiative of the terminal control mechanism driver and the lane terminal control mechanism 23 to the lane terminal control mechanism 23. That is, the processor 21 sets the bus master by the command register in the PCI configuration register 231 so that the lane terminal control mechanism 23 can become the bus master (step ST1312). Further, the processor 21 waits for PCI reset of the lane terminal control mechanism 23 (step ST1313). At this point, the series of processes related to the initialization for causing the lane terminal control mechanism 23 to be used by the guest OS is ended (not the end of the guest OS).

Comparative Example
The comparative example will be described below. Here, the toll booth data processor 2a corresponding to the toll booth data processor 2 newly developed will be described. Although it is conceivable to develop as the toll booth data processing device 2a, the development load can be reduced by using the toll booth data processing device 2 as compared to the toll booth data processing device 2a. .

FIG. 5 is a block diagram showing an example of a schematic configuration of a tollgate data processing apparatus as a comparative example. The tollgate data processing device 2a shown in FIG. 5 will be described focusing on the differences from the tollgate data processing device 2 of the embodiment, and the description of the common points will be omitted as appropriate.
As shown in FIG. 5, the tollgate data processing device 2a includes a processor 21a, a storage unit 22a, a lane terminal control mechanism 23a, and a communication interface 24a.

  The lane terminal control mechanism 23a includes a PCI configuration register 231a. The PCI configuration register 231a includes a register (first register) 2311a related to the operation of the OS, and a register (second register) 2312a related to the internal operation of the lane terminal control mechanism. A plurality of first registers 2311 exist in the PCI configuration register 231a, and a plurality of registers 2321a related to the internal operation of the lane terminal control mechanism also exist. For example, four registers R1, R2, R3 and R4 can be mentioned as the registers 2322a related to the internal operation of the lane terminal control mechanism. The description of these four registers is omitted.

  When trying to realize the initial setting function of the lane terminal control mechanism 23a by newly developing a virtual BIOS corresponding to the dedicated lane terminal control mechanism 23a and realizing the newly developed virtual BIOS, the following (1) to (1) It is necessary to consider the matter of 3).

(1) It takes a long period of nearly one year for formal adoption by the newly developed virtual BIOS community.
(2) When it is discovered that the initial settings need to be added or corrected, the virtual BIOS community will not incorporate the correction into the target current version of virtual BIOS, making it difficult to continue development in the current version .
(3) In order to solve the above (1) or (2), it is also possible to create a unique virtual BIOS based on a standard virtual BIOS provided by the virtual BIOS community. However, since that time, it does not support the virtual BIOS community.

FIG. 6 is a flowchart showing an outline of development of the toll booth data processing apparatus of the comparative example.
As shown in FIG. 6, the developers of the tollgate data processing apparatus design the lane terminal control mechanism (PCI expansion card) (step ST21), and change the virtual BIOS in accordance with the designed lane terminal control mechanism. (Step ST22). The operation in the virtual environment is verified by the changed virtual BIOS (version_N) (step ST23), and the changed virtual BIOS is applied for registration in the virtual BIOS community (step ST24). Here, even if the virtual BIOS community accepts an application for registration of the virtual BIOS changed (step ST25), about one year will be spent during that time.

  In addition, when the version of virtual BIOS is updated (version _ N → version _ N + 1), the operation in the virtual environment is verified by the changed virtual BIOS (version _ N + 1) (step ST26), and the modified virtual BIOS Will apply for registration to the virtual BIOS community. Thus, it is expected that the development and release of the product will be prolonged.

  On the other hand, according to the tollgate data processing device 2 according to the embodiment described above, the development load of the dedicated lane terminal control mechanism (for example, the dedicated PCI expansion card) in the virtual environment can be reduced. That is, the items (1) to (3) mentioned in the comparative example can be resolved by the toll booth data processing apparatus 2 according to the embodiment described above.

  In virtualization, the burden on developers for preparing a virtual BIOS corresponding to a dedicated communication protocol is heavy, and a considerable amount of time is required from application of the virtual BIOS to registration. The tollgate data processing apparatus 2 according to the present embodiment rewrites the register 2321 related to the operation inside the lane terminal control mechanism of the device specific space 232 directly from the terminal control mechanism driver using the PCI pass-through technology. Thereby, communication between the tollgate data processing device 2 and the lane terminal 3 can be realized by the dedicated protocol while reducing the development load.

  While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

DESCRIPTION OF SYMBOLS 1 Central management system 2 2a Toll gate data processing device 3 Lane terminal 4 Roadside device 21 21a Processor 22 22a Storage part 23 23a Lane terminal control mechanism 24 24a Communication interface 231 231a ... PCI configuration register 232 ... Device specific space 2311 ... Register related to the operation of OS (first register)
2321 ... Register related to internal operation of lane terminal control mechanism (second register)
2311a: Register pertaining to the operation of the OS 2312a: register pertaining to the internal operation of the lane terminal control mechanism

Claims (14)

A toll booth data processing apparatus for connecting a central management system of a toll collection system and a roadside apparatus and a lane terminal provided on a lane of the toll booth,
A lane terminal control mechanism that is an interface with the lane terminal;
A storage unit for storing a program;
Based on the program stored in the storage unit, a bit related to the initial setting is set in the first register of the lane terminal control mechanism by the virtual BIOS on the virtual environment, and the lane control is performed by the terminal control mechanism driver on the virtual environment A processor for setting a bit related to the internal operation of the lane terminal control mechanism to a second register of the terminal control mechanism;
Equipped with
The lane terminal control mechanism is a PCI expansion card,
The processor sets a bit related to the initialization to the first general register included in the PCI configuration register of the PCI expansion card by the virtual BIOS.
The toll station data processing apparatus, wherein the processor sets a bit related to the internal operation to the second register dedicated to the PCI expansion card by a PCI expansion card driver corresponding to the PCI expansion card by PCI pass-through . The toll booth data processing apparatus according to claim 1 , wherein the PCI expansion card is a card corresponding to a dedicated communication protocol of the toll collection system.   The toll booth data processor according to claim 1, wherein the initial setting includes access information to the second register.   The PCI expansion card includes the PCI configuration register and device specific space which are independently divided.
  The toll booth data processing apparatus according to any one of claims 1 to 3, wherein the device specific space includes the second register. An information processing apparatus for connecting a central management system of an information processing system and a terminal device,
A terminal control mechanism that is an interface with the terminal device;
A storage unit for storing a program;
Based on the program stored in the storage unit, the virtual BIOS in the virtual environment sets a bit related to the initial setting to the first register of the terminal control mechanism, and the terminal control mechanism driver in the virtual environment performs the terminal control A processor for setting a bit related to the internal operation of the terminal control mechanism to a second register of the mechanism;
The terminal control mechanism is a PCI expansion card,
The processor sets a bit related to the initialization to the first general register included in the PCI configuration register of the PCI expansion card by the virtual BIOS.
The processor is an information processing apparatus for setting a bit related to the internal operation to the second register dedicated to the PCI expansion card by a PCI expansion card driver corresponding to the PCI expansion card by PCI pass-through . The information processing apparatus according to claim 5 , wherein the PCI expansion card is a card corresponding to a dedicated communication protocol of the information processing system.   The information processing apparatus according to claim 5, wherein the initial setting includes access information to the second register.   The PCI expansion card includes the PCI configuration register and device specific space which are independently divided.
  The information processing apparatus according to any one of claims 5 to 7, wherein the device specific space includes the second register. It is a setting method of a lane terminal control mechanism of a toll booth data processing apparatus connected to a central management system of a toll collection system and a roadside device and a lane terminal provided on a lane of the toll booth,
Based on the program stored in the storage unit of the lane terminal control mechanism, the virtual BIOS on the virtual environment sets a bit related to the initial setting to the first register of the lane terminal control mechanism,
The bit according to the internal operation of the lane terminal control mechanism is set in the second register of the lane terminal control mechanism by the lane terminal control mechanism driver on the virtual environment ,
The lane terminal control mechanism is a PCI expansion card,
The setting of the bit relating to the initial setting is to set the bit relating to the initial setting to the general purpose first register included in the PCI configuration register of the PCI expansion card by the virtual BIOS,
The setting of the bit relating to the internal operation is performed by setting the bit relating to the internal operation to the dedicated second register of the PCI expansion card by the PCI expansion card driver corresponding to the PCI expansion card by PCI pass-through. A method of setting a lane terminal control mechanism of a toll booth data processor.   The method according to claim 9, wherein the initial setting includes access information to the second register.   The PCI expansion card includes the PCI configuration register and device specific space which are independently divided.
  The method according to any one of claims 9 to 10, wherein the device specific space includes the second register. A method of setting a terminal control mechanism of an information processing apparatus applied to an information processing system, connected to a terminal device, and processing various data,
Setting a bit related to initial setting to the first register of the terminal control mechanism by the virtual BIOS on the virtual environment based on the program stored in the storage unit;
Setting a bit related to the internal operation of the terminal control mechanism in a second register of the terminal control mechanism by a terminal control mechanism driver on a virtual environment;
The terminal control mechanism is a PCI expansion card,
The setting of the bit relating to the initial setting is to set the bit relating to the initial setting to the general purpose first register included in the PCI configuration register of the PCI expansion card by the virtual BIOS,
The setting of the bit relating to the internal operation is performed by setting the bit relating to the internal operation to the dedicated second register of the PCI expansion card by the PCI expansion card driver corresponding to the PCI expansion card by PCI pass-through. A method of setting a terminal control mechanism of an information processing apparatus A program that is applied to a toll collection system and sets a tollgate data processing device that connects a central management system and a roadside device provided in a lane of a tollgate and a lane terminal,
A procedure for setting a bit related to initial setting to the first register of the lane terminal control mechanism by the virtual BIOS on the virtual environment of the lane terminal control mechanism;
A procedure for setting a bit relating to the internal operation of the lane terminal control mechanism to the second register of the lane terminal control mechanism by the lane terminal control mechanism driver on the virtual environment;
Is a setup program that causes a computer to execute
The lane terminal control mechanism is a PCI expansion card,
The setting of the bit relating to the initial setting is to set the bit relating to the initial setting to the general purpose first register included in the PCI configuration register of the PCI expansion card by the virtual BIOS,
The setting of the bit relating to the internal operation is performed by setting the bit relating to the internal operation to the dedicated second register of the PCI expansion card by the PCI expansion card driver corresponding to the PCI expansion card by PCI pass-through. There is a configuration program. A program for setting a terminal control mechanism of an information processing apparatus applied to an information processing system, connected to a terminal device, and processing various data,
A procedure for setting a bit related to initial setting to a first register of the terminal control mechanism by a virtual BIOS on a virtual environment;
A procedure for setting a bit related to an internal operation of the terminal control mechanism to a second register of the terminal control mechanism by a terminal control mechanism driver on a virtual environment;
Is a setup program that causes a computer to execute
The terminal control mechanism is a PCI expansion card,
The setting of the bit relating to the initial setting is to set the bit relating to the initial setting to the general purpose first register included in the PCI configuration register of the PCI expansion card by the virtual BIOS,
The setting of the bit relating to the internal operation is performed by setting the bit relating to the internal operation to the dedicated second register of the PCI expansion card by the PCI expansion card driver corresponding to the PCI expansion card by PCI pass-through. There is a configuration program.