JP6505012B2 - アクセラレーテッド処理デバイス内でネットワークメッセージを処理するための方法およびシステム - Google Patents
アクセラレーテッド処理デバイス内でネットワークメッセージを処理するための方法およびシステム Download PDFInfo
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- JP6505012B2 JP6505012B2 JP2015524869A JP2015524869A JP6505012B2 JP 6505012 B2 JP6505012 B2 JP 6505012B2 JP 2015524869 A JP2015524869 A JP 2015524869A JP 2015524869 A JP2015524869 A JP 2015524869A JP 6505012 B2 JP6505012 B2 JP 6505012B2
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- simd
- physical layer
- module
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- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0008—Modulated-carrier systems arrangements for allowing a transmitter or receiver to use more than one type of modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/60—Software-defined switches
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M1/00—Substation equipment, e.g. for use by subscribers
- H04M1/72—Mobile telephones; Cordless telephones, i.e. devices for establishing wireless links to base stations without route selection
- H04M1/724—User interfaces specially adapted for cordless or mobile telephones
- H04M1/72403—User interfaces specially adapted for cordless or mobile telephones with means for local support of applications that increase the functionality
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Human Computer Interaction (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mobile Radio Communication Systems (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/566,890 | 2012-08-03 | ||
| US13/566,890 US9319254B2 (en) | 2012-08-03 | 2012-08-03 | Methods and systems for processing network messages in an accelerated processing device |
| PCT/IB2013/002440 WO2014020450A2 (en) | 2012-08-03 | 2013-08-02 | Methods and systems for processing network messages in an accelerated processing device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015532798A JP2015532798A (ja) | 2015-11-12 |
| JP2015532798A5 JP2015532798A5 (enExample) | 2016-09-23 |
| JP6505012B2 true JP6505012B2 (ja) | 2019-04-24 |
Family
ID=50025466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015524869A Active JP6505012B2 (ja) | 2012-08-03 | 2013-08-02 | アクセラレーテッド処理デバイス内でネットワークメッセージを処理するための方法およびシステム |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9319254B2 (enExample) |
| EP (1) | EP2880900B1 (enExample) |
| JP (1) | JP6505012B2 (enExample) |
| KR (1) | KR101949999B1 (enExample) |
| CN (1) | CN104541542B (enExample) |
| IN (1) | IN2015DN00496A (enExample) |
| WO (1) | WO2014020450A2 (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9787457B2 (en) | 2013-10-07 | 2017-10-10 | Commscope Technologies Llc | Systems and methods for integrating asynchronous signals in distributed antenna system with direct digital interface to base station |
| US9843550B2 (en) * | 2015-11-29 | 2017-12-12 | International Business Machines Corporation | Processing messages in a data messaging system using constructed resource models |
| US20180007302A1 (en) | 2016-07-01 | 2018-01-04 | Google Inc. | Block Operations For An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register |
| US20180005346A1 (en) | 2016-07-01 | 2018-01-04 | Google Inc. | Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register |
| US10988274B2 (en) | 2017-02-07 | 2021-04-27 | Adhezion Biomedical, Llc | Packaging for adhesive compositions |
| US10963035B2 (en) * | 2017-10-11 | 2021-03-30 | Qualcomm Incorporated | Low power PCIe |
| US10740163B2 (en) * | 2018-06-28 | 2020-08-11 | Advanced Micro Devices, Inc. | Network packet templating for GPU-initiated communication |
| CN112528456B (zh) * | 2019-09-18 | 2024-05-07 | 曙光信息产业(北京)有限公司 | 一种异构节点计算系统及方法 |
| US11960813B2 (en) | 2021-08-02 | 2024-04-16 | Advanced Micro Devices, Inc. | Automatic redistribution layer via generation |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8364136B2 (en) | 1999-02-01 | 2013-01-29 | Steven M Hoffberg | Mobile system, a method of operating mobile system and a non-transitory computer readable medium for a programmable control of a mobile system |
| AU2003219812A1 (en) | 2002-02-19 | 2003-09-09 | Zyray Wireless, Inc. | Method and apparatus optimizing a radio link |
| US20050216700A1 (en) | 2004-03-26 | 2005-09-29 | Hooman Honary | Reconfigurable parallelism architecture |
| JP2008153833A (ja) * | 2006-12-15 | 2008-07-03 | Sony Corp | 無線通信装置及び無線通信方法 |
| WO2010097397A1 (en) * | 2009-02-24 | 2010-09-02 | Telefonaktiebolaget L M Ericsson (Publ) | Method and apparatus for allocating processing delays in multi-carrier systems |
| US8630592B2 (en) * | 2009-04-14 | 2014-01-14 | Qualcomm Incorporated | System and method for triggering a wireless connection |
| JP2011007683A (ja) * | 2009-06-26 | 2011-01-13 | Seiko Epson Corp | マルチパス信号信頼度判定方法、コード位相誤差算出方法、コード位相算出方法、位置算出方法及びマルチパス信号信頼度判定装置 |
| US8669990B2 (en) * | 2009-12-31 | 2014-03-11 | Intel Corporation | Sharing resources between a CPU and GPU |
| US8493992B2 (en) | 2010-02-04 | 2013-07-23 | Texas Instruments Incorporated | Interrelated WiFi and USB protocols and other application framework processes, circuits and systems |
| US20110302390A1 (en) * | 2010-06-05 | 2011-12-08 | Greg Copeland | SYSTEMS AND METHODS FOR PROCESSING COMMUNICATIONS SIGNALS fUSING PARALLEL PROCESSING |
| US20120246381A1 (en) * | 2010-12-14 | 2012-09-27 | Andy Kegel | Input Output Memory Management Unit (IOMMU) Two-Layer Addressing |
| US9606936B2 (en) * | 2010-12-16 | 2017-03-28 | Advanced Micro Devices, Inc. | Generalized control registers |
| US8719464B2 (en) * | 2011-11-30 | 2014-05-06 | Advanced Micro Device, Inc. | Efficient memory and resource management |
| US20130145051A1 (en) * | 2011-12-02 | 2013-06-06 | Andrew Kegel | Direct Device Assignment |
| US20130145055A1 (en) * | 2011-12-02 | 2013-06-06 | Andrew Kegel | Peripheral Memory Management |
| US20130262736A1 (en) * | 2012-03-30 | 2013-10-03 | Ati Technologies Ulc | Memory types for caching policies |
-
2012
- 2012-08-03 US US13/566,890 patent/US9319254B2/en active Active
-
2013
- 2013-08-02 KR KR1020157004713A patent/KR101949999B1/ko active Active
- 2013-08-02 WO PCT/IB2013/002440 patent/WO2014020450A2/en not_active Ceased
- 2013-08-02 EP EP13825412.3A patent/EP2880900B1/en active Active
- 2013-08-02 CN CN201380042538.2A patent/CN104541542B/zh active Active
- 2013-08-02 JP JP2015524869A patent/JP6505012B2/ja active Active
-
2015
- 2015-01-21 IN IN496DEN2015 patent/IN2015DN00496A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| IN2015DN00496A (enExample) | 2015-06-26 |
| JP2015532798A (ja) | 2015-11-12 |
| WO2014020450A3 (en) | 2014-05-30 |
| WO2014020450A2 (en) | 2014-02-06 |
| CN104541542B (zh) | 2018-11-23 |
| KR101949999B1 (ko) | 2019-02-19 |
| KR20150038284A (ko) | 2015-04-08 |
| CN104541542A (zh) | 2015-04-22 |
| US9319254B2 (en) | 2016-04-19 |
| US20140037027A1 (en) | 2014-02-06 |
| EP2880900A2 (en) | 2015-06-10 |
| EP2880900A4 (en) | 2016-03-23 |
| EP2880900B1 (en) | 2023-05-31 |
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