JP6491944B2 - Packet processing apparatus and program - Google Patents

Description

  The present invention relates to a device that performs packet transmission / reception processing, and particularly relates to a technique for performing packet transmission / reception processing using a general-purpose computer.

  As a conventional technique, an ICA for realizing “high throughput, low latency” packet transmission / reception processing using software on a general-purpose computer, which has been realized with dedicated hardware such as ATCA (Advanced Telecommunications Computing Architecture) and high-function edge routers. / O framework exists.

  This I / O framework eliminates kernel functions such as interrupt processing and occupies as many CPU cores as possible for packet processing on a general-purpose computer, thereby enabling high-speed packet processing. It is.

JP 2010-028708 A

  However, since the I / O framework technology needs to always use CPU resources, there are problems such as generation of heat, increase in CPU failure rate, and increase in power consumption.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a technique that enables appropriate CPU resource control in a computer that performs packet transmission / reception processing at high speed.

According to an embodiment of the present invention, a packet processing device configured by a computer including a network interface unit and an application,
First packet control means for reading packets from the network interface unit;
Second packet control means for notifying the application of the packet;
CPU control management means for assigning CPU resources to the first packet control means and assigning CPU resources to the second packet control means;
A packet processing device is provided.

  According to the embodiment of the present invention, there is provided a technique capable of appropriately performing CPU resource control in a computer that performs packet transmission / reception processing at high speed.

It is a figure which shows the structural example of the system which concerns on embodiment of this invention. 2 is a configuration diagram of a CPU control device 100. FIG. It is a figure for demonstrating the operation | movement outline | summary of CPU control. It is a figure which shows the example of the information managed by CPU management control part 131. It is a flowchart for demonstrating a packet control procedure. It is a flowchart for demonstrating a CPU control procedure. It is a figure which shows the example of a CPU utilization condition (before CPU control apparatus application). It is a figure which shows the example of a CPU utilization condition (after CPU control apparatus application).

  Embodiments of the present invention will be described below with reference to the drawings. The embodiment described below is only an example, and the embodiment to which the present invention is applied is not limited to the following embodiment.

(System configuration example)
In the present embodiment, a CPU control device 100 configured by a general-purpose computer is provided. FIG. 1 is a diagram illustrating an example of a system to which a CPU control device 100 according to the present embodiment is applied. Since the CPU control device 100 processes a packet, it may be referred to as a packet processing device.

  FIG. 1 shows an example of a telecommunications carrier network 10 composed of a number of routers including routers 1 to 3. In the example of FIG. 1, a telecommunications carrier network 10 is connected to a network 20 such as another business company. In addition, subscriber's home devices 4 and 5 are connected.

  In FIG. 1, routers 1 to 3 are shown as functions constituting the telecommunications carrier network 10, but in addition, the telecommunications carrier network 10 includes packet servers such as an access server and a content distribution server. Various functions for transmitting and receiving are provided.

  The CPU control device 100 according to the present embodiment implements each of the above functions constituting the telecommunications carrier network 10 as an application (program). By using the CPU control device 100 for implementing each of the above functions, the cost of capital investment and maintenance can be reduced, and the functions can be freely described with ordinary programs, so that functions specific to operating companies can be incorporated. It becomes feasible.

  Note that the use of the CPU control device 100 for realizing the functions constituting the telecommunications carrier network 10 is an example. The CPU control device 100 can be applied to various fields that perform packet transmission / reception, and its use is not particularly limited.

(Device configuration)
The CPU control device 100 has a configuration of a general-purpose computer as hardware. That is, the CPU control device 100 includes a CPU, a memory, a NIC (Network Interface Controller), and the like.

  The “CPU” described below regarding the functional configuration and operation of the CPU control device 100 may be a hardware CPU or a virtual CPU. In the present embodiment, the “CPU” is a unit for allocating calculation resources (in other words, a unit for controlling the operation rate). In this embodiment, the core (CORE) and “CPU” may be considered synonymous. That is, the core (CORE) described below may be replaced with “CPU”.

  FIG. 2 shows a functional configuration of the CPU control device 100 in the present embodiment. The configuration shown in FIG. 2 is a configuration of functions realized by cooperation of a program installed in the CPU control device 100, which is a computer, and hardware such as a CPU and a memory.

  As shown in FIG. 2, the CPU control apparatus 100 includes applications (APL) 141 and 142 and an I / O framework 110, and CPU control is performed between the applications 141 and 142 and the I / O framework 110. A unit 130 is provided.

  Each application is, for example, a program for causing a computer to realize functions such as routing control in the router configuring the telecommunications carrier network 10 described above. As described above, the I / O framework 110 is a functional unit that enables high-speed packet processing on a general-purpose computer by eliminating kernel functions such as interrupt processing. An example of the I / O framework is netmap. In the present embodiment, an embodiment in which the I / O framework 110 is used is shown, but the CPU control means according to the present invention can be applied to a configuration in which the I / O framework 110 is not used. is there.

  NICs 101 and 102 are connected to the I / O framework 110. The NIC queue 120 is a buffer (storage unit) that stores packets transmitted and received via the NIC. The NIC queue 120 and the NICs 101 and 102 may be referred to as NIC. In the example shown in FIG. 2, two APLs and two NICs are provided, but this is only an example.

  The CPU control unit 130 is a functional unit that controls packet transmission / reception processing for each CPU. The CPU control unit 130 includes a CPU control management unit 131, packet control units 132 to 134, and application (APL) queues 135 and 136. Here, three packet control units are shown and two APL queues are shown, but this is only an example.

  It is assumed that the CPU control management unit 131, the packet control unit 132, the packet control unit 133, and the packet control unit 134 are functional units assigned to one CPU. That is, the processing of each functional unit is realized by a program that is assigned to the corresponding CPU and executed by the CPU. The CPU control management unit and the packet control unit may be referred to as “CPU”, respectively.

  Note that assigning one CPU to one function unit is merely an example, and a plurality of function units may be assigned to one CPU, or one function unit may be assigned to a plurality of CPUs.

  In this embodiment, in order to control packet reception processing from the outside at high speed, processing for cutting packets from the NIC (more specifically, the NIC queue 120) (reaching processing), and notification of packets to the APL Each of the processes (notification processes) for performing the process is assigned to different CPUs, and one of the packet control units 132 to 134 corresponds to the CPU for the mowing process, and the other corresponds to the CPU for the notification process.

  A packet control unit that performs processing for notifying a packet to the APL has a notification IF (interface) (may be referred to as an APL-IF). The notification IF corresponds to a virtual socket, and its entity is, for example, an IP address (destination, transmission source, or both the destination and transmission source) and a port number (destination, transmission source, or transmission with the destination). And the identification information of the APL corresponding to them, and the information is set from the CPU control management unit 131, APL 141, APL 142, etc. to the corresponding packet control unit. A plurality of notification IFs may be assigned to a packet control unit (CPU) that performs processing for notifying a packet to the APL.

  The packet control unit reads the packet stored in the APL queue corresponding to itself, and performs an operation of notifying the packet to the APL of the notification IF corresponding to the header information (IP address, port number) of the packet. In the present embodiment, the APL queue may be provided for each packet control unit that performs packet notification processing, or may be provided for each APL (that is, for each APL-IF).

  Each packet control unit counts inflowing packets (reads from the queue), holds the count value, and pauses the operation of the CPU to which it is assigned based on the setting from the CPU control management unit 131. Including a function to perform control.

  The CPU control manager 131 determines the CPU pause time (pause time in each cycle) based on the packet count value for each CPU operating as a packet controller, and sets the pause time in the corresponding packet controller. Including the function to perform. Determining the CPU pause time based on the packet count value is an example. For example, the pause time may be determined by an external setting. As an external setting, there is an example in which a pause time is determined for each time zone. For example, in the night time zone, it is possible to perform control such as setting a pause time so that the CPU operation rate is low.

  In determining the CPU pause time based on the packet count value, the CPU control management unit 131 does not change the CPU pause time by changing the burst packet inflow amount. CPU) holds data (history) at a certain time interval of the counter value. Then, based on the history, the CPU control management unit 131 determines whether the current packet count value is a burst value or a continuous value, and continuously without using a burst value. The pause time is determined using the value. The CPU control management unit 131 may appropriately delete the history that is no longer used for determining the CPU pause time.

  With the functions described above, the CPU operating rate for packet control can be set to 100% when processing is desired at the fastest speed, and CPU resources can be allocated autonomously or in response to external instructions except during the busy period. It becomes possible. In other words, during a period other than the busiest period, it is possible to realize a control in which some resources of the CPU functioning as the packet control unit are used for other processing.

  The CPU control apparatus 100 according to the present embodiment can be realized by causing a computer to execute a program describing the processing contents described in the present embodiment. That is, the functions of the CPU control device 100 are realized by executing a program corresponding to processing executed in the device using hardware resources such as a CPU, a memory, and a hard disk built in the computer. Is possible. The above-mentioned program can be recorded on a computer-readable recording medium (portable memory or the like), stored, or distributed. It is also possible to provide the program through a network such as the Internet or electronic mail.

(Outline of operation of CPU control device 100)
Next, an outline of the operation of the CPU control device 100 will be described with reference to FIGS. The configuration shown in FIG. 3 corresponds to the configuration shown in FIG. 2, but more specifically shows the processing assigned to each packet control unit (CPU). .

  In the example of FIG. 3, APL01 to 03 are provided as applications, and NIC01 and NIC02 are provided as NICs. FIG. 3 also shows CORE (core) corresponding to each packet control unit. In the description of FIG. 3, the packet control unit is called CORE.

  As shown in FIG. 3, the relationship of APL-IF / CORE / NIC is defined in advance. Setting information for such a definition (referred to as relationship definition information) is held by the CPU control management unit 131. FIG. 4A shows an example of relationship definition information held by the CPU control management unit 131. The definition of FIG. 4A corresponds to FIG.

  As shown in FIG. 4A, NIC (N01) corresponds to CORE01, and NIC (N02) corresponds to CORE02 and CORE03.

  Further, APL-IF (S01) is associated as {CORE04, high, LEVEL2}. Here, APL-IF (S01) = {CORE04, high, LEVEL2} means that CORE04 is assigned with high priority to APL-IF (S01) when there are many packets. That is, if the level of the packet inflow amount to CORE04 is LEVEL2 or higher, CPU resources for low-priority APL-IF are not allocated, and CORE04 for APL01 is operated at a high operation rate and packet notification to APL01 is performed. Make it. Further, if the level of the packet inflow amount is LEVEL3 or less, the CPU resources on the APL02 and APL03 sides can be allocated.

  Further, the association is made as “APL-IF (S02) = {CORE04, low}, CORE05” and “APL-IF (S03) = {CORE04, low}, CORE05”. “APL-IF (S02) = {CORE04, low}, CORE05” is a packet notification process to the APL02. When the CORE05 normally performs the packet notification process and the CORE04 does not perform the high priority process, the CORE04 also notifies the APL02 of the packet. It shows that processing can be performed. The same applies to “APL-IF (S03) = {CORE04, low}, CORE05”.

  The CPU control management unit 131 further holds information on the control content of the CPU operation rate as setting information for each CPU (each CORE). FIG. 4B shows a part of the setting information. In FIG. 4B, for example, “LEVEL1 = 100% packet> = 1000 / sec” for CORE01 and CORE02 indicates that the number of inflowing packets (count value) is 1000 / second for each of CORE01 and CORE02. If there are more, the CORE is operated at 100% as LEVEL1. The same applies to other examples. In the example shown in FIG. 4B, the inflow amount is the number of packets per unit time, but this is only an example, and other amounts may be used. For example, a data amount (Mbyte or the like) per unit time may be used.

  The CPU control management unit 131 determines a pause time for each CPU based on the setting information and the packet count value. For example, if the operating rate is 50%, the CPU resource functioning as the packet control unit uses half of the total time for packet control, and rests the CPU for the remaining time. Alternatively, the remaining time may be assigned to processing other than packet control.

  With reference to FIG. 3, as an example, an operation example regarding the flow of packets from NIC (N01) to APL02 will be described.

  The CORE01 prunes the packet of NIC (N01) from the NIC queue, and stores the packet in the APL queue corresponding to the CORE (here, CORE05) that notifies the APL. Which APL queue the CORE01 selects is based on the setting from the CPU control management 131.

  For example, CORE01 holds information (IP address, port number, APL ID, etc.) of each notification IF by the setting from the CPU control management 131, and based on the setting information, the packet cut from the NIC queue is stored. And stored in the APL queue of the APL corresponding to the packet. CORE05 reads the packet from the APL queue and notifies APL02.

  In this embodiment, operations for controlling packet reception processing, which is an external factor, at high speed are mainly described. However, processing for transmitting packets to the outside can also be performed in the same manner as when receiving packets. It is.

(Detailed processing example of packet controller)
With reference to FIG. 5, an example of an operation procedure of the packet control unit when attention is paid to a certain packet control unit (CPU assigned to packet control) will be described.

  Each packet control unit (CPU) performs processing at a predetermined cycle. In step S101, the periodic process is started. The packet control unit acquires the CPU suspension period from the CPU control management unit 131 (step S102), and suspends the CPU for a predetermined period based on the information of the CPU suspension period (step S103). As already described, the pause period and pause timing are determined based on, for example, the packet count value and setting information indicating the relationship between the packet inflow amount and the CPU operating rate.

  If the packet control unit monitors the NIC after the pause (example: CORE01 set as “N01 = CORE01” in FIG. 4B) (Yes in step S104), the packet control unit A packet is read from the NIC queue 120 (step S105). When there is packet data (Yes in step S106), the packet control unit counts up the packet counter and updates the packet counter value.

  The packet control unit selects an APL queue based on the setting from the CPU control management unit 131 (step S108), and writes the packet to the APL queue (step S109).

  If the determination in step S104 is No, that is, if the target packet control unit performs APL notification processing (for example, CORE04 in FIG. 4B), the packet control unit corresponds to the corresponding APL queue. Packet reading is performed (step S111). If there is packet data (Yes in step S112), the packet counter value is updated (step S113). When the packet meets the APL notification condition (Yes in step S114), the packet is notified to the corresponding APL (step S115). In step S116, the periodic process ends.

  In step S111, the APL queue to be read is, for example, the APL queue of the APL corresponding to the APL-IF assigned to the packet control unit. The APL notification condition in step S114 is a condition as to whether or not the read packet corresponds to the IP address and port number of the APL-IF assigned to the packet control unit.

(Detailed processing example of CPU control management unit)
Next, an operation example of the CPU control management unit 131 will be described with reference to the flowchart of FIG. Here, first, the monitoring interval is set by setting from the outside (step S201). In the present embodiment, the suspension time of the CPU that operates as the CPU control management unit 131 is determined by the monitoring interval. For example, assuming that the monitoring interval is 100 and the time required for the monitoring process (steps S204 to S207 in FIG. 6) is 50, 50 is a pause period.

  In step S202, the periodic process is started. In step S203, the CPU control management unit 131 suspends its own CPU based on the monitoring interval.

  After the suspension, the CPU control management unit 131 reads the packet counter value for each CPU assigned as the packet control unit from each packet control unit (step S204), and the count value and setting information (example: FIG. 4B). ) To determine a pause time for each packet control unit (CPU) (step S205).

  As described above, the CPU control management unit 131 determines the suspension time based on the inflow amount within a certain period so that the CPU suspension time does not fluctuate due to the burst packet inflow increase.

  The CPU control management unit 131 writes the pause time for each new packet control unit (CPU) into, for example, a predetermined storage unit in the packet control unit (step S206), and a counter for each unnecessary packet control unit (CPU). The value history is deleted (step S207). In step S208, the periodic process ends.

(Effects of the embodiment)
FIG. 7 shows an example of a CPU usage situation when the CPU control according to the present embodiment is not applied.

  As shown in FIG. 7, when the CPU control is not applied, the operation rate of each CPU used for packet control is always 100%, and there is a lot of waste of power and the like. Even in the case of a system where the peak time is 13:00 to 18:00, CPU resources are wasted in other times such as at night. Even if it is desired to carry out heavy processing on a computer at night, the CPU resources are only available for two cores, so that there are restrictions on activities during the system off time.

  FIG. 8 shows an example of a CPU usage situation when the CPU control according to the present embodiment is applied.

  As shown in FIG. 8, when CPU control is applied, CPU allocation necessary for packet processing becomes possible, so that performance in the busiest period is not impaired, heat generation, CPU failure rate increase, power consumption The problem can be solved. At the system off time, the surplus CPU can be used for various purposes such as nighttime batch processing.

  As described above, according to the present embodiment, a packet processing apparatus configured by a computer including a network interface unit and an application, the first packet control means for reading a packet from the network interface unit And a second packet control means for notifying the application of the packet, a CPU resource allocation to the first packet control means, and a CPU resource allocation to the second packet control means A packet processing apparatus comprising: a control management unit.

  The processing of the first packet control means is assigned to one or more CPUs in the computer, the processing of the second packet control means is assigned to one or more CPUs in the computer, and the CPU control management For example, the means determines the CPU operation rate for each CPU based on the amount of packets flowing into the CPU.

  The CPU control management unit may set information of a notification interface for notifying the second packet control unit of a packet to the application.

  The present invention is not limited to the above-described embodiments, and various modifications and applications are possible within the scope of the claims.

1 to 3 routers 4 and 5 in-home equipment 10 telecommunications carrier network 20 network of other business company 100 CPU control devices 101 and 102 NIC
110 I / O framework 120 NIC queue 130 CPU control unit 131 CPU control management unit 132 to 134 Packet control unit 135, 136 Application (APL) queue 141, 142 Application (APL)

Claims (4)

A packet processing apparatus configured by a computer including a network interface unit and an application,
First packet control means for reading packets from the network interface unit;
Second packet control means for notifying the application of the packet;
CPU control management means for assigning CPU resources to the first packet control means and assigning CPU resources to the second packet control means;
A packet processing apparatus comprising: The processing of the first packet control means is assigned to one or more CPUs in the computer, the processing of the second packet control means is assigned to one or more CPUs in the computer,
The packet processing apparatus according to claim 1, wherein the CPU control management unit determines a CPU operation rate for each CPU based on a packet amount flowing into the CPU. The packet processing device according to claim 1, wherein the CPU control management unit sets information of a notification interface for notifying the application of a packet to the second packet control unit. .   The program for functioning a computer as each means in the packet processing apparatus of any one of Claims 1 thru | or 3.

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