JP6483838B2 - Semiconductor substrate, semiconductor substrate grinding method, and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor substrate, a semiconductor substrate grinding method, and a semiconductor device manufacturing method.

  The band gap of silicon carbide (SiC) is larger than the band gap of silicon (Si), and the electric field strength at which SiC breaks down is about 10 times higher than the electric field strength at which Si breaks down. For this reason, a semiconductor element made of SiC is applied to various semiconductor devices centering on a semiconductor device having a semiconductor element for high power use, that is, a power semiconductor device.

  As semiconductor elements made of SiC, Schottky Barrier Diodes (SBD) and MOSFETs (Metal Oxide Field Effect Transistors), which are unipolar elements, and pn diodes (PNDs) and insulated gate bipolar transistors (IGBTs), which are bipolar elements, are used. : Insulated Gate Bipolar Transistor).

  As a method of manufacturing a semiconductor device including such a semiconductor element made of SiC, when forming a semiconductor element on a semiconductor substrate as a single crystal substrate made of SiC, the upper surface (front surface) side or the lower surface (back surface) of the semiconductor substrate. ) Side may be polished or ground.

  US Patent Application Publication No. 2010/0093116 (Patent Document 1) incorporates a feature of incorporating an isotope element into a semiconductor device in a dimension profiling method of a semiconductor device on a silicon carbide substrate. A technique is disclosed in which the end point of a CMP (Chemical Mechanical Polishing) process is detected by measuring these dimensions.

US Patent Application Publication No. 2010/0093116

  In the semiconductor element included in the semiconductor device as the power semiconductor device described above, the loss in the on state, that is, the conduction loss, and the loss when switching between the on state and the off state, that is, the switching loss are within an appropriate range. It is desirable to adjust. For this purpose, it is desirable that the amount of carriers injected into the semiconductor layer included in the semiconductor element can be easily adjusted. For example, the amount of carriers injected into the semiconductor layer included in the semiconductor element can be easily increased. Is desirable.

  However, when the semiconductor element includes an n-type substrate as a single crystal substrate made of SiC, the impurity concentration in the n-type substrate is fixed to a constant value according to the specifications of the substrate as the single crystal substrate. Therefore, in a semiconductor element including an n-type substrate and a semiconductor layer formed on the n-type substrate, the amount of carriers injected from the n-type substrate into the semiconductor layer can be easily increased. Can not.

  On the other hand, a semiconductor device manufactured using a semiconductor substrate including a base and an n-type semiconductor layer formed on the base and having an n-type impurity concentration higher than the n-type impurity concentration in the base. A semiconductor element including an n-type semiconductor layer and a semiconductor layer formed on the n-type semiconductor layer is conceivable. In such a semiconductor element, the amount of carriers injected from the n-type semiconductor layer into the semiconductor layer formed on the n-type semiconductor layer can be easily increased.

  In the manufacturing process of a semiconductor device including such a semiconductor element, it is necessary to grind and remove the substrate from the lower surface (back surface) side of the semiconductor substrate. However, if the grinding amount is not accurately determined, the n-type semiconductor layer may be removed, or the n-type semiconductor layer may not be exposed on the lower surface of the semiconductor substrate.

  The object of the present invention is to accurately determine the amount of grinding when grinding the semiconductor substrate from the lower surface side in the manufacturing process of the semiconductor device that can easily adjust the amount of carriers injected into the semiconductor element. It is to provide a semiconductor substrate. An object of the present invention is to provide a semiconductor substrate grinding method and a semiconductor device manufacturing method capable of accurately determining a grinding amount when the semiconductor substrate is ground from the lower surface side.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor substrate according to a representative embodiment includes a base made of silicon carbide, a p-type first semiconductor layer formed on the base and made of silicon carbide, and formed on the first semiconductor layer and made of silicon carbide. an n-type second semiconductor layer; and a p-type third semiconductor layer formed on the second semiconductor layer and made of silicon carbide.

  The semiconductor substrate grinding method according to the representative embodiment includes a step of preparing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface opposite to the first surface, a base made of silicon carbide, and a p-type first formed of silicon carbide and formed on the first surface of the base. One semiconductor layer, an n-type second semiconductor layer formed on the first semiconductor layer and made of silicon carbide, and a p-type third semiconductor layer formed on the second semiconductor layer and made of silicon carbide. Have. In addition, the grinding method of the semiconductor substrate is such that a cross-sectional image of the semiconductor substrate is taken with a scanning electron microscope before the substrate is removed, and the luminance difference between the first semiconductor layer and the second semiconductor layer in the taken image. And determining the amount of grinding of the semiconductor substrate, and grinding the semiconductor substrate from the second surface side of the substrate with the determined amount of grinding to remove the substrate and the first semiconductor layer.

  In addition, a method for manufacturing a semiconductor device according to a representative embodiment includes a step of preparing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface opposite to the first surface, a base made of silicon carbide, and a p-type first formed of silicon carbide and formed on the first surface of the base. One semiconductor layer, an n-type second semiconductor layer formed on the first semiconductor layer and made of silicon carbide, and a p-type third semiconductor layer formed on the second semiconductor layer and made of silicon carbide. Have. The method for manufacturing a semiconductor device includes a step of forming semiconductor elements in the second semiconductor layer and the third semiconductor layer. Further, in the method for manufacturing the semiconductor device, an image of a cross section of the semiconductor substrate is picked up by a scanning electron microscope before the substrate is removed, and the luminance difference between the first semiconductor layer and the second semiconductor layer in the picked-up image. And determining the amount of grinding of the semiconductor substrate, and grinding the semiconductor substrate from the second surface side of the substrate with the determined amount of grinding to remove the substrate and the first semiconductor layer.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to a typical embodiment, when a semiconductor substrate is ground from the lower surface side in a semiconductor device manufacturing process in which the amount of carriers injected into a semiconductor element can be easily adjusted, the amount of grinding is accurately determined. be able to.

FIG. 10 is a cross-sectional view of a principal part of a semiconductor device of Comparative Example 1. 6 is a graph schematically showing a relationship between conduction loss and switching loss in the semiconductor device of Comparative Example 1; It is a graph which shows typically the relation between the position of the thickness direction in the n ⁻ type drift layer and the carrier density in the ON state of the pn diode. FIG. 10 is a cross-sectional view of main parts of a semiconductor device of Comparative Example 2. 6 is a cross-sectional view of a principal part of a semiconductor substrate of Comparative Example 2. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Comparative Example 2 during the manufacturing process thereof; FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Comparative Example 2 during the manufacturing process thereof; FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Comparative Example 2 during the manufacturing process thereof; FIG. FIG. 3 is a main-portion cross-sectional view of the semiconductor substrate of Embodiment 1; FIG. 3 is a main-portion cross-sectional view of the semiconductor substrate of Embodiment 1; 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. FIG. 10 is a plan view of the semiconductor device in First Embodiment during the manufacturing process thereof. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. FIG. 10 is a main-portion cross-sectional view of the semiconductor device of the modification example of the first embodiment during the manufacturing process; FIG. 10 is a main-portion cross-sectional view of the semiconductor device of the modification example of the first embodiment during the manufacturing process; FIG. 10 is a main-portion cross-sectional view of the semiconductor substrate of the second embodiment. FIG. 10 is a cross-sectional view of main parts of a semiconductor device of Comparative Example 3. 10 is a cross-sectional view of main parts of a semiconductor device of Comparative Example 4; FIG. 10 is a cross-sectional view of a principal part of a semiconductor substrate of Comparative Example 4. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Comparative Example 4 during the manufacturing process thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Comparative Example 4 during the manufacturing process thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Comparative Example 4 during the manufacturing process thereof. FIG. FIG. 10 is a main-portion cross-sectional view of the semiconductor substrate of the third embodiment. FIG. 10 is a main-portion cross-sectional view of the semiconductor substrate of the third embodiment. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof. FIG. 29 is an essential part cross-sectional view during a manufacturing step of the semiconductor device of the modified example of the third embodiment. FIG. 29 is an essential part cross-sectional view during a manufacturing step of the semiconductor device of the modified example of the third embodiment. FIG. 10 is a main-portion cross-sectional view of the semiconductor substrate of the fourth embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

  In addition, when showing a range as A-B in the following embodiment, it shall show A or more and B or less unless otherwise specified.

(Embodiment 1)
A semiconductor device, a semiconductor substrate, and a method for manufacturing a semiconductor device according to the first embodiment, which is an embodiment of the present invention, a semiconductor device according to comparative example 1 and a comparative example 2, and a semiconductor device according to comparative example 2 are manufactured. This will be explained in comparison with the method. In the first embodiment, an example in which a pn diode is formed as a semiconductor element will be described.

<Semiconductor Device of Comparative Example 1>
FIG. 1 is a cross-sectional view of a main part of the semiconductor device of Comparative Example 1. FIG. 2 is a graph schematically showing the relationship between conduction loss and switching loss in the semiconductor device of Comparative Example 1. FIG. 3 is a graph schematically showing the relationship between the position in the thickness direction and the carrier density in the n ⁻ type drift layer in the on state of the pn diode.

As shown in FIG. 1, the semiconductor device of Comparative Example 1 includes an n-type substrate 111, an n ⁻ -type drift layer 113b, a p-type semiconductor layer 114, an anode 115, and a cathode 116. The semiconductor device of Comparative Example 1 includes a pn diode as a rectifying element having an anode 115 and a cathode 116 as a semiconductor element that is a two-terminal element. The semiconductor substrate SB101 is formed by the n-type substrate 111, the n ⁻ -type drift layer 113b, and the p-type semiconductor layer 114.

The base 111 has an upper surface 111a and a lower surface 111b opposite to the upper surface 111a. An n ⁻ type drift layer 113b is formed on the upper surface 111a of the base 111, and a p type semiconductor layer 114 is formed on the n ⁻ type drift layer 113b. An anode 115 is formed on the p-type semiconductor layer 114. A cathode 116 is formed on the lower surface 111 b of the base 111.

The substrate 111 is a bulk substrate made of an n-type silicon carbide (SiC) single crystal. The n ⁻ type drift layer 113b is made of silicon carbide (SiC) as an n type semiconductor. The n ⁻ type drift layer 113b is formed on the base 111 by, for example, an epitaxial growth method. The p-type semiconductor layer 114 is made of silicon carbide (SiC) as a p-type semiconductor. The p-type semiconductor layer 114 is formed on the n ⁻ -type drift layer 113b by, for example, an epitaxial growth method.

In the semiconductor device of Comparative Example 1, when a voltage is applied between the anode 115 and the cathode 116 such that the potential of the anode 115 is lower than the potential of the cathode 116, that is, the p-type semiconductor layer 114 Consider a case where a voltage is applied in the reverse direction to the pn junction between the n ⁻ type drift layer 113b. In such a case, the breakdown voltage is secured by the depletion layer formed between the p-type semiconductor layer 114 and the n ⁻ -type drift layer 113b and the electric field formed in the depletion layer.

On the other hand, in the semiconductor device of Comparative Example 1, when a voltage is applied between the anode 115 and the cathode 116 such that the potential of the anode 115 is higher than the potential of the cathode 116, that is, a p-type semiconductor layer. Consider a case where a voltage is applied in the forward direction to the pn junction between 114 and the n ⁻ -type drift layer 113b. In such a case, the pn diode is turned on when the voltage exceeds a voltage equal to the built-in potential of the pn junction between the p-type semiconductor layer 114 and the n ⁻ -type drift layer 113b, that is, the built-in voltage. .

At this time, n ^- the p-type semiconductor layer 114 disposed on the anode 115 side with respect to the type drift layer 113b, n ^- holes flow into the type drift layer 113b, n ^- cathode for the type drift layer 113b 116 From the substrate 111 arranged on the side, electrons flow into the n ⁻ type drift layer 113b. As a result, n ^- -type drift layer 113b, n ^- electrons and holes accumulated at a higher density than the carrier density which is determined by the impurity concentration in the type drift layer 113b, i.e., injected, pn diode is turned on In this case, the resistance of the n ⁻ type drift layer 113b becomes low. This effect of storing or injecting electrons and holes at a density higher than the carrier density determined by the impurity concentration, that is, the effect of being injected is referred to as a minority carrier accumulation effect or a conductivity modulation effect. Due to the conductivity modulation effect, the on-resistance in the pn diode is lower than the on-resistance in the SBD.

In the pn diode using such a conductivity modulation effect, the amount of electrons and holes stored in the n ⁻ -type drift layer 113b, that is, the injection amount is controlled, and the loss in the on state, that is, the conduction loss and the on state. It is desirable to adjust the loss at the time of switching to the off state, that is, the switching loss at the time of switching to an appropriate range. Thus, conduction loss, and, as the switching loss can be adjusted to an appropriate range, n ^- inflow of electrons and holes flow into the type drift layer 113b, and, n ^- electrons and holes from the type drift layer 113b is It is necessary to design the amount of spilled water.

For example, when the accumulation amount of electrons and holes accumulated in the n ⁻ type drift layer 113b, that is, the amount of injected carriers is too large, the resistance of the n ⁻ type drift layer 113b becomes low and the conduction loss is small. In addition, since it is necessary to discharge the charge accumulated in the n ⁻ type drift layer 113b, the switching loss is large as shown in FIG. On the other hand, when the accumulation amount of electrons and holes accumulated in the n ⁻ type drift layer 113b, that is, the injection amount of carriers is too small, the switching loss is small, but the conduction loss is large as shown in FIG. That is, there is a trade-off relationship between conduction loss and switching loss, as shown in FIG.

In the semiconductor device of Comparative Example 1, the impurity concentration in the p-type semiconductor layer 114 and the thickness of the p-type semiconductor layer 114 can be adjusted. As a result, as shown in FIG. 3, the carrier density in the portion of the n ⁻ type drift layer 113b on the p-type semiconductor layer 114 side is changed from the carrier density in the specification A to the carrier density in the specification B, for example. Can be increased.

However, the impurity concentration in the substrate 111 is fixed to a constant value according to the specifications of the substrate 111 which is an n-type bulk substrate. Therefore, as shown in FIG. 3, in the on state of the pn diode, the carrier density in the portion on the base 111 side of the n ⁻ type drift layer 113b is between the carrier density in the specification A and the carrier density in the specification B. It cannot be changed.

That is, the semiconductor device of Comparative Example 1 has a problem that the amount of carriers injected into the pn diode from the cathode side is small. In addition, unlike the impurity concentration in each epitaxially grown semiconductor layer, the upper limit value of the impurity concentration in the base 111 as an n-type bulk substrate is about 1 × 10 ¹⁸ cm ⁻³ , so that the n ⁻ -type drift layer 113b includes a cathode. The injection amount of carriers injected from the side cannot be easily adjusted.

<Semiconductor Device of Comparative Example 2>
On the other hand, the semiconductor device of Comparative Example 2 can be considered as a semiconductor device that can easily adjust the carrier density in the portion of the n ⁻ type drift layer 113b opposite to the p-type semiconductor layer 114 side. FIG. 4 is a cross-sectional view of a main part of the semiconductor device of Comparative Example 2.

The semiconductor device of Comparative Example 2 is different from the semiconductor device of Comparative Example 1 in that it has an n-type semiconductor layer 113a instead of the n-type substrate 111 (see FIG. 1). In the semiconductor device of Comparative Example 2, by adjusting the impurity concentration in the n-type semiconductor layer 113a and the thickness of the n-type semiconductor layer 113a, the n ^- type drift layer 113b in the n ^- type drift layer 113b is turned on by adjusting the n ^- type drift layer 113b. The carrier density in the portion on the semiconductor layer 113a side can be easily adjusted.

The n-type semiconductor layer 113 is formed by the n-type semiconductor layer 113a and the n ⁻ -type drift layer 113b. Further, the semiconductor device of Comparative Example 2 has the same configuration as that of the semiconductor device of Embodiment 1 described with reference to FIG. 10 described later.

<Method for Manufacturing Semiconductor Device of Comparative Example 2>
FIG. 5 is a cross-sectional view of the main part of the semiconductor substrate of Comparative Example 2. 6 to 8 are main-portion cross-sectional views of the semiconductor device of Comparative Example 2 during the manufacturing process.

In the manufacturing process of the semiconductor device of Comparative Example 2, first, as shown in FIG. 5, a semiconductor substrate SB101 including a base 111 that is an n-type bulk substrate is prepared. The base 111 includes an upper surface 111a and a lower surface 111b opposite to the upper surface 111a. Further, the semiconductor substrate SB101 is formed on the n-type semiconductor layer 113a formed on the base 111, the n ⁻ type drift layer 113b formed on the n type semiconductor layer 113a, and the n ⁻ type drift layer 113b. a p-type semiconductor layer 114. The impurity concentration in the n-type semiconductor layer 113a is higher than the impurity concentration in the substrate 111.

  In the manufacturing process of the semiconductor device of Comparative Example 2, next, as shown in FIG. 6, the substrate 111 is ground by grinding the semiconductor substrate SB101 from the lower surface 111b (see FIG. 5) side of the substrate 111 (see FIG. 5). Remove. At this time, the grinding amount for grinding the semiconductor substrate SB101 is determined, and the semiconductor substrate SB101 is ground with the determined grinding amount.

Here, consider a case where the grinding amount for grinding the semiconductor substrate SB101 is not accurately determined and the thickness of the n-type semiconductor layer 113a is not sufficiently thick. In such a case, as shown in FIG. 7, the determined grinding amount may be larger than the appropriate grinding amount, and the n-type semiconductor layer 113a may be removed. Alternatively, as shown in FIG. 8, the determined grinding amount becomes smaller than the appropriate grinding amount, and the n-type semiconductor layer 113a (see FIG. 4) may not be exposed on the lower surface (back surface) of the semiconductor substrate SB101. . In addition, when the uniformity of the thickness of the n ⁻ type drift layer 113b or the substrate 111 in the upper surface 111a (see FIG. 5) of the substrate 111 is reduced, the n-type semiconductor layer 113a is formed in the upper surface 111a of the substrate 111. There is a possibility that a portion to be removed and a portion where the n-type semiconductor layer 113a is not exposed on the lower surface of the semiconductor substrate SB101 are mixed.

  Even when the grinding amount for grinding the semiconductor substrate SB101 is not accurately determined, if the thickness of the n-type semiconductor layer 113a is sufficiently thick, the n-type semiconductor layer 113a is not removed and the n-type semiconductor It is possible to perform appropriate grinding so that the layer 113a is exposed on the lower surface of the semiconductor substrate SB101. However, if the n-type semiconductor layer 113a is too thick, the manufacturing cost of the semiconductor substrate SB101 may increase.

  That is, in the semiconductor device of Comparative Example 2, although the amount of carriers injected into the pn diode from the cathode side can be easily adjusted, it is difficult to accurately determine the amount of grinding of the semiconductor substrate SB101. There is a problem that there is.

<Semiconductor substrate of Embodiment 1>
Next, the semiconductor substrate of Embodiment 1 which is one embodiment of the present invention will be described with reference to the drawings. The semiconductor substrate according to the first embodiment is a semiconductor substrate used for forming a pn diode in order to solve the above-described problems in Comparative Example 1 and Comparative Example 2, and is a substrate made of n-type silicon carbide. A semiconductor substrate in which a first p-type semiconductor layer, an n-type semiconductor layer, and a second p-type semiconductor layer are stacked.

  Hereinafter, a semiconductor substrate used for forming a pn diode will be described as an example. However, the semiconductor substrate as an embodiment of the present invention is not necessarily a semiconductor used for forming a pn diode, as will be described by exemplifying a semiconductor substrate used for forming an IGBT in the second embodiment. It is not limited to the substrate.

  FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate of the first embodiment.

As shown in FIG. 9, the semiconductor substrate SB1 of the first embodiment includes an n-type substrate 11, a p-type semiconductor layer 12, an n-type semiconductor layer 13a, an n ⁻ type drift layer 13b, and a p-type semiconductor. Layer 14.

The base 11 has an upper surface 11a as a first surface and a lower surface 11b as a second surface opposite to the upper surface 11a. A p-type semiconductor layer 12 is formed on the upper surface 11a of the substrate 11, an n-type semiconductor layer 13a is formed on the p-type semiconductor layer 12, an n ⁻ type drift layer 13b is formed on the n-type semiconductor layer 13a, and n ^A p-type semiconductor layer 14 is formed on the −-type drift layer 13b.

The substrate 11 is a bulk substrate made of, for example, silicon carbide (SiC) single crystal as an n-type semiconductor. The substrate 11 is formed by, for example, a sublimation method. The substrate 11 contains n-type impurities such as nitrogen (N) or phosphorus (P). The n-type impurity concentration in the substrate 11 can be set to, for example, about 1 × 10 ¹⁶ to 2 × 10 ¹⁹ cm ⁻³ . Further, the thickness of the substrate 11 can be set to about 100 to 1000 μm.

The p-type semiconductor layer 12 is made of, for example, silicon carbide (SiC) as a p-type semiconductor. The p-type semiconductor layer 12 is formed on the upper surface 11a of the base 11 by, for example, an epitaxial growth method. The p-type semiconductor layer 12 contains p-type impurities such as aluminum (Al) or boron (B). The p-type impurity concentration in the p-type semiconductor layer 12 can be set to about 1 × 10 ^{14 to} 5 × 10 ¹⁹ cm ⁻³ , for example. Moreover, the thickness of the p-type semiconductor layer 12 can be set to, for example, about 0.1 to 30 μm.

  As will be described later with reference to FIG. 11, the p-type semiconductor layer 12 is formed when the substrate 11 and the p-type semiconductor layer 12 are removed by grinding the semiconductor substrate SB1 from the lower surface 11b side of the substrate 11. This is a marker for taking an image of a cross section of SB1 with a scanning electron microscope (SEM) and determining an appropriate grinding amount. Therefore, when the thickness of the p-type semiconductor layer 12 is less than 0.1 μm, the thickness of the p-type semiconductor layer 12 is too thin and the p-type semiconductor layer 12 may not be observed with a scanning electron microscope. On the other hand, when the thickness of the p-type semiconductor layer 12 exceeds 30 μm, the thickness of the p-type semiconductor layer 12 is too thick, and the quality such as crystallinity of the p-type semiconductor layer 12 is deteriorated, or the p-type semiconductor There is a possibility that the time for epitaxially growing the layer 12 becomes long and the manufacturing time of the semiconductor substrate SB1 becomes long.

The n-type semiconductor layer 13a is made of silicon carbide (SiC) as an n-type semiconductor. The n-type semiconductor layer 13a is formed on the p-type semiconductor layer 12 by, for example, an epitaxial growth method. The n-type semiconductor layer 13a contains an n-type impurity such as nitrogen (N) or phosphorus (P). The n-type impurity concentration in the n-type semiconductor layer 13 can be set to, for example, about 1 × 10 ¹⁷ to 4 × 10 ²⁰ cm ⁻³ . Further, the thickness of the n-type semiconductor layer 13a can be set to, for example, about 0.5 to 30 μm.

As will be described later with reference to FIG. 10, the n-type semiconductor layer 13a is included in the pn diode formed using the semiconductor substrate SB1, and when the pn diode is in the on state, the n ⁻ type drift layer 13b includes electrons. Supply.

The n ⁻ type drift layer 13b is made of silicon carbide (SiC) as an n type semiconductor. The n ⁻ type drift layer 13b is formed on the n type semiconductor layer 13a by, for example, an epitaxial growth method. The n ⁻ type drift layer 13b contains an n type impurity such as nitrogen (N) or phosphorus (P). The n ^- type impurity concentration in the n ⁻ -type drift layer 13b can be made lower than the n-type impurity concentration in the n-type semiconductor layer 13a, for example, about 5 × 10 ^{13 to} 5 × 10 ¹⁶ cm ^−3. Can do. Further, the thickness of the n ⁻ type drift layer 13b can be set to about 10 to 300 μm, for example.

As will be described later with reference to FIG. 10, the n ⁻ -type drift layer 13b is included in a pn diode formed using the semiconductor substrate SB1, and electrons and holes flow when the pn diode is in an on state. Is a layer.

The p-type semiconductor layer 14 is a layer made of a p-type semiconductor. The p-type semiconductor layer 14 is formed on the n ⁻ -type drift layer 13b by, for example, an epitaxial growth method. The p-type semiconductor layer 14 contains a p-type impurity such as aluminum (Al) or boron (B). The p-type impurity concentration in the p-type semiconductor layer 14 can be set to, for example, about 5 × 10 ^{16 to} 5 × 10 ¹⁹ cm ⁻³ . Moreover, the thickness of the p-type semiconductor layer 14 can be set to, for example, about 0.2 to 20 μm.

As will be described later with reference to FIG. 10, the p-type semiconductor layer 14 is included in a pn diode formed using the semiconductor substrate SB1, and when the pn diode is in an on state, the p-type semiconductor layer 14 is positively connected to the n ⁻ -type drift layer 13b. Supply holes.

It is assumed that the n-type semiconductor layer 13 is formed by the n-type semiconductor layer 13a and the n ⁻ -type drift layer 13b. At this time, the semiconductor substrate SB1 of the first embodiment includes a base 11, a p-type semiconductor layer 12 formed on the upper surface 11a of the base 11, and an n-type semiconductor layer 13 formed on the p-type semiconductor layer 12. And a p-type semiconductor layer 14 formed on the n-type semiconductor layer 13. The n-type semiconductor layer 13 including the n-type semiconductor layer 13a and the n ⁻ -type drift layer 13b is formed on the p-type semiconductor layer 12 and is made of silicon carbide.

  As silicon carbide (SiC), a plurality of types of SiC having different crystal structures such as 3C-SiC, 4h-SiC, and 6h-SiC, that is, crystal polymorphs are known. Among these, the band gap of 4h-SiC is about 3.2 eV, which is larger than the band gap of SiC having other crystal structures. A single crystal substrate made of 4h-SiC can be manufactured more easily than a single crystal substrate made of SiC having another crystal structure. Therefore, in this Embodiment 1, although SiC is desirably 4h-SiC, it may have other crystal structures (the same applies to the following embodiments).

In the first embodiment, the example in which the base 11, the p-type semiconductor layer 12, the n-type semiconductor layer 13a, the n ⁻ -type drift layer 13b, and the p-type semiconductor layer 14 are all made of SiC has been described. However, any or all of the substrate 11, the p-type semiconductor layer 12, the n-type semiconductor layer 13a, the n ⁻ -type drift layer 13b, and the p-type semiconductor layer 14 are made of SiC such as gallium nitride (GaN) or gallium arsenide (GaAs). It may be made of a compound semiconductor other than the above (the same applies to the following embodiments).

<Semiconductor Device of First Embodiment>
FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate of First Embodiment. In FIG. 10, the structure of the peripheral portion of the semiconductor device, such as termination formed on both sides of the pn diode to ensure the breakdown voltage of the semiconductor device, and the structure of the electrode pad electrically connected to the anode, Is omitted.

As shown in FIG. 10, the semiconductor device of the first embodiment includes an n-type semiconductor layer 13a, an n ⁻ -type drift layer 13b, a p-type semiconductor layer 14, an anode 15, and a cathode 16. The semiconductor device of the first embodiment includes a pn diode as a rectifying element having an anode 15 and a cathode 16 as a semiconductor element that is a two-terminal element. The n-type semiconductor layer 13 is formed by the n-type semiconductor layer 13a and the n ⁻ -type drift layer 13b, and the semiconductor substrate SB1 is formed by the n-type semiconductor layer 13 and the p-type semiconductor layer 14. .

The n-type semiconductor layer 13a is made of silicon carbide (SiC) as an n-type semiconductor. The n ⁻ type drift layer 13b is made of silicon carbide (SiC) as an n type semiconductor. The n ⁻ type drift layer 13 b is formed on the n type semiconductor layer 3. The p-type semiconductor layer 14 is made of silicon carbide (SiC) as a p-type semiconductor. The p-type semiconductor layer 14 is formed on the n ⁻ type drift layer 13b.

As described with reference to FIG. 9, the n-type semiconductor layer 13 a supplies electrons to the n ⁻ -type drift layer 13 b when the pn diode is on. The n ⁻ -type drift layer 13b is a layer through which electrons and holes flow when the pn diode is in an on state. The p-type semiconductor layer 14 supplies holes to the n ⁻ -type drift layer 13b when the pn diode is in the on state.

  The anode 15 is formed on the p-type semiconductor layer 14. The anode 15 is made of, for example, titanium (Ti) or aluminum (Al).

The cathode 16 is formed under the n-type semiconductor layer 13a, that is, on the opposite side of the n ⁻ -type drift layer 13b with the n-type semiconductor layer 13a interposed therebetween. The cathode 16 is made of, for example, aluminum (Al).

In the semiconductor device of the first embodiment, the impurity concentration in the n-type semiconductor layer 13a and the thickness of the n-type semiconductor layer 13a can be adjusted. Thereby, the carrier density in the n ^- type drift layer 13b on the n-type semiconductor layer 13a side can be easily adjusted in the on state of the pn diode.

  Note that the semiconductor device of the first embodiment has the same configuration as that of the semiconductor device of Comparative Example 2 described with reference to FIG. 4 described above.

  In a semiconductor element included in a semiconductor device as a power semiconductor device, a loss in an on state, that is, a conduction loss, and a loss at the time of switching between an on state and an off state, that is, a switching loss are adjusted to an appropriate range. It is desirable. For example, by replacing the semiconductor element made of Si with a pn diode as a bipolar element made of SiC for each range of different breakdown voltages, the conduction loss and the switching loss of the power semiconductor device can be reduced.

When the breakdown voltage is less than 4.5 kV, the pn diode made of SiC has a built-in potential of about 2.7 V, which is about three times the built-in potential (built-in voltage) of the bipolar element made of Si. Therefore, the conduction loss of the pn diode made of SiC is higher than the conduction loss of the pn diode made of Si. However, if the breakdown voltage exceeds 6.5 kV, the resistance of the n ⁻ -type drift layer 13b does not increase much even if the breakdown voltage increases. Therefore, the conduction loss of the pn diode made of SiC is the conduction loss of the pn diode made of Si. It is expected to be lower than both of the conduction loss of SBD made of SiC. In the range where the withstand voltage exceeds 6.5 kV, the semiconductor device as the power semiconductor device according to the first embodiment is expected to be used in a transformer or a power transmission network or an SST (Solid State Transformer) in a high-speed railway. The

<Method for Manufacturing Semiconductor Device of First Embodiment>
11 and 13 to 15 are fragmentary cross-sectional views of the semiconductor device of First Embodiment during the manufacturing steps thereof. FIG. 12 is a plan view of the semiconductor device of First Embodiment during the manufacturing process thereof.

  Hereinafter, a manufacturing process of forming a pn diode as a semiconductor element on the semiconductor substrate SB1 after grinding the lower surface (back surface) of the semiconductor substrate SB1 will be described.

In the manufacturing process of the semiconductor device according to the first embodiment, first, as shown in FIG. 9, a semiconductor substrate SB1 including a base 11 that is an n-type bulk substrate is prepared. The semiconductor substrate SB1 includes a base 11, a p-type semiconductor layer 12, an n-type semiconductor layer 13a, an n ⁻ -type drift layer 13b, and a p-type semiconductor layer 14.

  In the manufacturing process of the semiconductor device according to the first embodiment, next, as shown in FIG. 11, the semiconductor substrate SB1 is ground from the lower surface 11b (see FIG. 9) side of the base 11 (see FIG. 9), thereby 11 and the p-type semiconductor layer 12 (see FIG. 9) are removed.

  In the step of grinding the semiconductor substrate SB1, before starting the grinding of the semiconductor substrate SB1, first, as shown in FIG. 12, a portion PT1 which is a part of the semiconductor substrate SB1 is cut along a cutting line LN1 to form a test piece. Is made. And as shown in FIG. 13, the cross section of the produced test piece is observed with a scanning electron microscope.

  At this time, the p-type semiconductor region such as the p-type semiconductor layer 12 is negatively charged, and the n-type semiconductor region such as the n-type substrate 11 and the n-type semiconductor layer 13a is positively charged. , For example, the p-type semiconductor region appears bright and the n-type semiconductor region appears dark due to the potential contrast. In other words, since the amount of secondary electrons emitted from the p-type semiconductor region is different from the amount of secondary electrons emitted from the n-type semiconductor region, the brightness in the p-type semiconductor region and the n-type semiconductor region The brightness in the semiconductor region is different. Thereby, the base | substrate 11 and the p-type semiconductor layer 12 can be distinguished clearly, and the p-type semiconductor layer 12 and the n-type semiconductor layer 13a can be distinguished clearly.

Therefore, the thickness TH11, which is the sum of the thicknesses of the substrate 11 and the p-type semiconductor layer 12, can be accurately measured, and the n-type semiconductor layer 13a, the n ⁻ -type drift layer 13b, and the p-type semiconductor layer 14 can be measured. The thickness TH12, which is the sum of the thicknesses, can be accurately measured. A desired grinding amount (equal to the thickness TH11) for grinding the semiconductor substrate SB1 can be accurately determined.

  That is, in the semiconductor substrate grinding method of the first embodiment, before starting the grinding of the semiconductor substrate SB1, an image of a cross section of the semiconductor substrate SB1 is taken with a scanning electron microscope. Then, based on the luminance difference (contrast) between the p-type semiconductor layer 12 and the n-type semiconductor layer 13a in the captured image, that is, the difference in brightness between the p-type semiconductor layer 12 and the n-type semiconductor layer 13a, A grinding amount for grinding the semiconductor substrate SB1 is determined.

  Note that the substrate 11 may not be an n-type semiconductor, as long as at least the p-type semiconductor layer 12 and the n-type semiconductor layer 13a can be clearly distinguished. For example, silicon carbide (SiC) as a p-type semiconductor may be used. ) A bulk substrate made of a single crystal may be used.

  In the step of grinding the semiconductor substrate SB1, next, the substrate 11 and the p-type semiconductor layer 12 are removed by grinding the semiconductor substrate SB1 from the lower surface 11b side of the substrate 11 with the determined grinding amount.

  As described above when describing the manufacturing process of the semiconductor device of Comparative Example 2, the grinding amount for grinding the semiconductor substrate SB1 is not accurately determined, and the thickness of the n-type semiconductor layer 13a is Consider the case where it is not thick enough. In such a case, when the semiconductor substrate SB1 is ground from the lower surface 11b side of the base 11, the n-type semiconductor layer 13a is removed or the n-type semiconductor layer 13a is removed from the lower surface (back surface) of the semiconductor substrate SB1. May not be exposed.

  However, according to the manufacturing process of the semiconductor device of the first embodiment, the grinding amount for grinding the semiconductor substrate SB1 can be accurately adjusted in the manufacturing process of the semiconductor device in which the injection amount of carriers injected into the semiconductor element can be easily adjusted. Can be determined. Therefore, the semiconductor substrate SB1 is accurately ground from the lower surface 11b side of the base 11 so that the n-type semiconductor layer 13a is not removed and the n-type semiconductor layer 13a is exposed on the lower surface (back surface) of the semiconductor substrate SB1. Can be ground.

In addition, even when the uniformity of the thickness of the n ⁻ type drift layer 13b or the base body 11 in the upper surface 11a of the base body 11 is reduced, the portion of the upper surface 11a of the base body 11 where the n-type semiconductor layer 13a is removed; It is possible to prevent or suppress the n-type semiconductor layer 13a from being mixed with a portion that is not exposed on the lower surface of the semiconductor substrate SB1. Thereby, the characteristics of the pn diode as a semiconductor element formed in the n-type semiconductor layer 13 a, the n ⁻ -type drift layer 13 b and the p-type semiconductor layer 14 are prevented or suppressed from changing in the upper surface 11 a of the base body 11. be able to.

  Furthermore, since it is not necessary to increase the thickness of the n-type semiconductor layer 13a, the manufacturing cost of the semiconductor substrate SB1 can be reduced.

  In the method described above, an image of a cross section of the semiconductor substrate SB1 is taken with a scanning electron microscope before starting the grinding of the semiconductor substrate SB1. However, after starting the grinding of the semiconductor substrate SB1, as shown in FIG. 14, an image of a cross section of the semiconductor substrate SB1 may be taken with a scanning electron microscope in a state where a part of the base 11 remains. . Even in such a case, the base 11 and the p-type semiconductor layer 12 can be clearly distinguished, and the p-type semiconductor layer 12 and the n-type semiconductor layer 13a can be clearly distinguished. Therefore, it is possible to accurately measure the thickness TH13 which is the sum of the thicknesses of the remaining portion of the substrate 11 and the p-type semiconductor layer 12. Then, a desired grinding amount (equal to the thickness TH13) for grinding the remaining portion of the substrate 11 and the p-type semiconductor layer 12 can be accurately determined.

  After determining the grinding amount, the accuracy of the grinding amount is improved as the absolute value of the grinding amount by which the semiconductor substrate SB1 is ground is smaller. Therefore, after starting the grinding of the semiconductor substrate SB1, for example, after grinding is performed until the actual grinding amount becomes about 80% of the appropriate grinding amount, an image of the cross section of the semiconductor substrate SB1 is taken by the scanning electron microscope. By doing so, the precision of the grinding amount can be further improved.

  That is, in the method for grinding a semiconductor substrate according to the first embodiment, an image of a cross section of the semiconductor substrate SB1 may be taken with a scanning electron microscope before the substrate 11 is removed. Then, based on the luminance difference (contrast) between the p-type semiconductor layer 12 and the n-type semiconductor layer 13a in the captured image, that is, the difference in brightness between the p-type semiconductor layer 12 and the n-type semiconductor layer 13a, What is necessary is just to determine the grinding amount which grinds semiconductor substrate SB1.

  At this time, in the method for measuring the thickness of the semiconductor substrate according to the first embodiment, an image of a cross section of the semiconductor substrate SB1 is taken with a scanning electron microscope before the base 11 is removed. Then, based on the luminance difference (contrast) between the p-type semiconductor layer 12 and the n-type semiconductor layer 13a in the captured image, that is, the difference in brightness between the p-type semiconductor layer 12 and the n-type semiconductor layer 13a, The sum of the thicknesses of the substrate 11 and the p-type semiconductor layer 12 is measured.

  In the manufacturing process of the semiconductor device according to the first embodiment, a pn diode as a semiconductor element is formed next.

  In the step of forming the pn diode, first, as shown in FIG. 15, the anode 15 is formed on the p-type semiconductor layer 14. As the anode 15, the anode 15 made of, for example, titanium (Ti) or aluminum (Al) is formed on the p-type semiconductor layer 14 by, for example, vapor deposition or sputtering. As a result, the anode 15 electrically connected to the p-type semiconductor layer 14 is formed.

  Although not shown in FIG. 15, peripheral portions of the semiconductor device, such as terminations formed on both sides of the pn diode to ensure the breakdown voltage of the semiconductor device, and electrode pads electrically connected to the anode , May be formed.

As shown in FIG. 15, impurities are implanted into the lower surface (rear surface) of the n-type semiconductor layer 13a, that is, the portion of the n-type semiconductor layer 13a opposite to the n ⁻ -type drift layer 13b by, for example, ion implantation. The n-type semiconductor layer 16a may be formed by performing a heat treatment to activate the implanted impurities. The n-type semiconductor layer 16a reduces the contact resistance between the n-type semiconductor layer 13a and the cathode 16 (see FIG. 10).

Next, as shown in FIG. 10, the cathode 16 is formed under the n-type semiconductor layer 13a, that is, on the opposite side of the n ⁻ -type drift layer 13b with the n-type semiconductor layer 13a interposed therebetween. For example, the cathode 16 made of aluminum (Al) or the like is formed on the lower surface of the n-type semiconductor layer 13a by, for example, vapor deposition or sputtering. As a result, a cathode 16 electrically connected to the n-type semiconductor layer 13a is formed, and a pn diode as a semiconductor element is formed in the n-type semiconductor layer 13 and the p-type semiconductor layer 14 of the semiconductor substrate SB1. As described above, the semiconductor device of the first embodiment can be manufactured.

  When the semiconductor device of the first embodiment is manufactured by the manufacturing process described above, the impurity concentration in the n-type semiconductor layer 13a can be made higher than the impurity concentration in the n-type substrate 11, for example. At this time, the amount of carriers injected from the cathode side into the pn diode, that is, the amount of injected electrons can be easily increased, and the conduction loss can be reduced as compared with the semiconductor device of Comparative Example 1.

  Alternatively, when the semiconductor device of the first embodiment is manufactured by the manufacturing process described above, the impurity concentration in the n-type semiconductor layer 13a can be made lower than the impurity concentration in the n-type substrate 11, for example. At this time, the amount of carriers injected from the cathode side into the pn diode, that is, the amount of injected electrons can be easily reduced, and the switching loss can be reduced as compared with the semiconductor device of Comparative Example 1.

  In the technique disclosed in Patent Document 1, the upper surface (front surface) of the semiconductor substrate is polished and planarized by a CMP method. On the other hand, in the first embodiment, the lower surface (back surface) of the semiconductor substrate is ground. In the first embodiment, the grinding amount for grinding the lower surface of the semiconductor substrate is much larger than the grinding amount for polishing the upper surface of the semiconductor substrate in the technique disclosed in Patent Document 1. Furthermore, in the technique disclosed in Patent Document 1, since the isotope element is contained in the semiconductor element, the manufacturing process of the semiconductor device becomes complicated. Therefore, when performing the manufacturing process of the semiconductor device according to the first embodiment, it is possible to easily detect the end point when grinding the lower surface of the semiconductor substrate as compared with the case where the technique disclosed in Patent Document 1 is used. (The same applies to the following embodiments).

<Modification of Manufacturing Method of Semiconductor Device of First Embodiment>
In the manufacturing process described above, after the lower surface (back surface) of the semiconductor substrate SB1 is ground, a pn diode is formed on the semiconductor substrate SB1. On the other hand, in the manufacturing process of the modified example described below, a portion other than the cathode 16 of the pn diode is formed on the upper surface (front surface) of the semiconductor substrate SB1, and then the lower surface (back surface) of the semiconductor substrate SB1 is ground.

  16 and 17 are main-portion cross-sectional views during the manufacturing process of the semiconductor device according to the modification of the first embodiment.

  Also in the manufacturing process of the present modification, first, as in the manufacturing process of the first embodiment, as shown in FIG. 9, a semiconductor substrate SB1 including a base 11 that is an n-type bulk substrate is prepared.

  In the manufacturing process of the present modification, next, unlike the first embodiment, as shown in FIG. 16, a portion of the pn diode as the semiconductor element on the upper surface side of the semiconductor substrate SB1 is formed. Specifically, the anode 15 is formed on the p-type semiconductor layer 14. About the process of forming this anode 15, it can carry out similarly to the process of forming the anode 15 in the manufacturing process of Embodiment 1. FIG. As a result, a portion of the pn diode on the upper surface side of the semiconductor substrate SB1 is formed in the p-type semiconductor layer 14.

  In the manufacturing process of the present modification, next, as shown in FIG. 17, the semiconductor substrate SB1 is ground from the lower surface 11b (see FIG. 16) side of the base 11 (see FIG. 16) to thereby form the base 11 and the p-type semiconductor. Layer 12 (see FIG. 16) is removed. About the process of grinding this semiconductor substrate SB1, it can carry out similarly to the process of grinding semiconductor substrate SB1 in the manufacturing process of Embodiment 1. FIG.

In the manufacturing process of this modification, next, as shown in FIG. 10, the cathode 16 is formed below the n-type semiconductor layer 13a, that is, on the opposite side of the n ⁻ -type drift layer 13b with the n-type semiconductor layer 13a interposed therebetween. . About the process of forming this cathode 16, it can carry out similarly to the process of forming the cathode 16 in the manufacturing process of Embodiment 1. FIG. As a result, a portion of the pn diode on the lower surface side of the semiconductor substrate SB1 is formed in the n-type semiconductor layer 13a. As described above, a semiconductor device similar to the semiconductor device of the first embodiment can be manufactured.

  In the manufacturing process of this modification, a portion other than the cathode 16 of the pn diode is formed on the upper surface (front surface) of the semiconductor substrate SB1, and then the lower surface (back surface) of the semiconductor substrate SB1 is ground. Thus, a portion other than the cathode 16 of the pn diode can be formed using the thick semiconductor substrate SB1 before being ground. Therefore, when forming a part other than the cathode 16 in the pn diode, it is possible to more reliably prevent the semiconductor substrate SB1 from being damaged.

(Embodiment 2)
In the first embodiment, the example in which the p-type semiconductor layer 12 is directly formed on the substrate 11 as the semiconductor substrate SB1 has been described. On the other hand, in the second embodiment, an example will be described in which the p-type semiconductor layer 12 is formed on the base 11 via the buffer layer as the semiconductor substrate SB1.

  Note that the semiconductor substrate, the semiconductor device, and the method for manufacturing the semiconductor substrate according to the second embodiment are the same as those in the first embodiment except that the p-type semiconductor layer 12 is formed on the base 11 via a buffer layer. The semiconductor substrate, the semiconductor device, and the method for manufacturing the semiconductor substrate can be the same, and the description of the same parts as those in the first embodiment is omitted.

  FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate of the second embodiment.

As shown in FIG. 18, also in the second embodiment, as in the first embodiment, the semiconductor substrate SB1 includes an n-type substrate 11, a p-type semiconductor layer 12, an n-type semiconductor layer 13a, and an n ^{− type.} And a p-type semiconductor layer 14.

On the other hand, in the second embodiment, unlike the first embodiment, an n-type semiconductor layer 25 as a buffer layer is interposed between the base 11 and the p-type semiconductor layer 12. That is, the n-type semiconductor layer 25 is formed on the base 11, and the p-type semiconductor layer 12 is formed on the base 11 via the n-type semiconductor layer 25. The n-type semiconductor layer 25 prevents or suppresses continuous formation of crystal defects such as basal plane dislocations formed in the substrate 11 made of silicon carbide (SiC) in the p-type semiconductor layer 12. Therefore, the formation of the n-type semiconductor layer 25 can improve the characteristics of the pn diode as a semiconductor element formed in the n-type semiconductor layer 13a, the n ⁻ -type drift layer 13b, and the p-type semiconductor layer 14.

The n-type semiconductor layer 25 is made of silicon carbide (SiC) as an n-type semiconductor. The n-type semiconductor layer 25 is formed on the base 11 by, for example, an epitaxial growth method. The n-type semiconductor layer 25 contains an n-type impurity such as nitrogen (N) or phosphorus (P). The n-type impurity concentration in the n-type semiconductor layer 25 can be set to about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ , for example. Further, the thickness of the n-type semiconductor layer 25 can be set to, for example, about 0.5 to 30 μm.

  In the second embodiment, the n-type semiconductor layer is removed when the substrate 11 and the p-type semiconductor layer 12 are removed by grinding the semiconductor substrate SB1 from the lower surface 11b side of the substrate 11 in the manufacturing process of the semiconductor device. 25 is also removed.

(Embodiment 3)
The manufacturing method of the semiconductor device, the semiconductor substrate, and the semiconductor device of the third embodiment which is an embodiment of the present invention is the same as that of the semiconductor device of comparative example 3 and comparative example 4, and the manufacturing of the semiconductor device of comparative example 4. This will be explained in comparison with the method. Note that in Embodiment 3, an example in which an IGBT is formed as a semiconductor element will be described.

<Semiconductor Device of Comparative Example 3>
FIG. 19 is a cross-sectional view of main parts of the semiconductor device of Comparative Example 3.

As shown in FIG. 19, the semiconductor device of Comparative Example 3 includes an n-type substrate 131, a p-type semiconductor layer 134a, a p ⁻ -type drift layer 134b, an n-type semiconductor region 135, and a p-type semiconductor region 136. A gate insulating film 137, a gate electrode 138, an interlayer insulating film 139, an opening 140, an emitter electrode 141, and a collector electrode 142. The semiconductor device of Comparative Example 3 includes a p-channel IGBT having a gate electrode 138, an emitter electrode 141, and a collector electrode 142 as a semiconductor element as a three-terminal element. The n-type substrate 131, the p-type semiconductor layer 134a, and the p ⁻ -type drift layer 134b form a semiconductor substrate SB103.

The base 131 has an upper surface 131a and a lower surface 131b opposite to the upper surface 131a. A p-type semiconductor layer 134a is formed on the upper surface 131a of the base 131, and a p ⁻ -type drift layer 134b is formed on the p-type semiconductor layer 134a. p ^- n-type semiconductor region 135 is formed in the upper portion of the type drift layer 134b, a p-type semiconductor region 136 is formed in the upper portion of the n-type semiconductor region 135, p ^- -type drift layer 134b and the p-type semiconductor region 136 A gate electrode 138 is formed on the n-type semiconductor region 135 sandwiched between the gate insulating films 137 with a gate insulating film 137 interposed therebetween. An interlayer insulating film 139 covering the gate electrode 138 is formed on the semiconductor substrate SB103, and an opening 140 reaching the n-type semiconductor region 135 and the p-type semiconductor region 136 through the interlayer insulating film 139 is formed in the interlayer insulating film 139. An emitter electrode 141 formed in contact with the n-type semiconductor region 135 and the p-type semiconductor region 136 is formed in the opening 140 and on the interlayer insulating film 139. A collector electrode 142 is formed on the lower surface 131 b of the base 131.

The base 131 is a bulk substrate made of n-type silicon carbide (SiC) single crystal. The p-type semiconductor layer 134a is made of silicon carbide (SiC) as a p-type semiconductor. The p-type semiconductor layer 134a is formed on the base 131 by, for example, an epitaxial growth method. The p ⁻ type drift layer 134b is formed on the p type semiconductor layer 134a by, for example, an epitaxial growth method.

In such an IGBT, with a voltage applied between the collector electrode 142 and the emitter electrode 141, a necessary voltage is applied to the gate electrode 138 to turn on the IGBT. At this time, an inversion layer is formed in the n-type semiconductor region 135 near the gate insulating film 137, and holes flow from the p-type semiconductor region 136 into the p ⁻ -type drift layer 134b through the inversion layer. At this time, electrons flow from the n-type substrate 131 to the p ⁻ -type drift layer 134b. As a result, p ^- -type drift layer 134b, the above-mentioned conductivity modulation effect, p ^- the electrons and holes are accumulated at a higher density than the carrier density which is determined by the impurity concentration in the type drift layer 134b, When the IGBT is on, the resistance of the n ⁻ type drift layer 113b is low.

Even in such an IGBT, the switching loss and the conduction loss vary depending on the amount of electrons and holes accumulated in the p ⁻ type drift layer 134b, that is, the amount of carriers injected, and there is a trade-off between the conduction loss and the switching loss. The OFF relationship is the same as in the case of the pn diode described in the first embodiment with reference to FIGS.

In the semiconductor device of Comparative Example 3, the carrier density in the p ⁻ type drift layer 134b can be easily adjusted in the on state of the IGBT by adjusting the impurity concentration in the p type semiconductor region 136 and the n type semiconductor region 135, for example. Can do. However, since the impurity concentration in the base 131 is fixed to a constant value according to the specifications of the base 131, which is an n-type bulk substrate, the carrier density in the p ⁻ type drift layer 134b cannot be easily adjusted.

That is, the semiconductor device of Comparative Example 3 has a problem that the amount of carriers injected into the IGBT from the collector side is small. Further, since the upper limit value of the impurity concentration in the base 131 as an n-type bulk substrate is about 1 × 10 ¹⁸ cm ⁻³ , the amount of carriers injected into the p ⁻ -type drift layer 134b from the collector side can be easily increased. Can not be adjusted.

<Semiconductor Device of Comparative Example 4>
On the other hand, the semiconductor device of Comparative Example 4 is conceivable as a semiconductor device that can easily adjust the carrier density in the p ⁻ -type drift layer 134b. FIG. 20 is a cross-sectional view of main parts of the semiconductor device of Comparative Example 4.

The semiconductor device of Comparative Example 4 is different from the semiconductor device of Comparative Example 3 in that an n-type semiconductor layer 133 is provided instead of the n-type substrate 131 (see FIG. 19). In the semiconductor device of Comparative Example 4, by adjusting the impurity concentration in the n-type semiconductor layer 133 and the thickness of the n-type semiconductor layer 133, the carrier density in the p ⁻ -type drift layer 134b in the on state of the IGBT is It can be adjusted easily.

The p-type semiconductor layer 134 is formed by the p-type semiconductor layer 134a and the p ⁻ -type drift layer 134b. Further, the semiconductor device of Comparative Example 4 has a configuration similar to that of the semiconductor device of Embodiment 3 described with reference to FIG.

<Method for Manufacturing Semiconductor Device of Comparative Example 4>
FIG. 21 is a cross-sectional view of main parts of a semiconductor substrate of Comparative Example 4. 22 to 24 are fragmentary cross-sectional views of the semiconductor device of Comparative Example 4 during the manufacturing process.

In the manufacturing process of the semiconductor device of Comparative Example 4, first, as shown in FIG. 21, a semiconductor substrate SB103 including a base 131 that is an n-type bulk substrate is prepared. The base 131 includes an upper surface 131a and a lower surface 131b opposite to the upper surface 131a. The semiconductor substrate SB103 includes an n-type semiconductor layer 133 formed on the base 131, a p-type semiconductor layer 134a formed on the n-type semiconductor layer 133, and a p ⁻ formed on the p-type semiconductor layer 134a. Type drift layer 134b. The impurity concentration in the n-type semiconductor layer 133 is higher than the impurity concentration in the substrate 131.

  In the manufacturing process of the semiconductor device of Comparative Example 4, next, as shown in FIG. 22, the substrate 131 is ground by grinding the semiconductor substrate SB103 from the lower surface 131b (see FIG. 21) side of the substrate 131 (see FIG. 21). Remove. At this time, a grinding amount for grinding the semiconductor substrate SB103 is determined, and the semiconductor substrate SB103 is ground with the determined grinding amount.

  Here, a case where the grinding amount for grinding the semiconductor substrate SB103 is not accurately determined and the thickness of the n-type semiconductor layer 133 is not sufficiently thick will be considered. In such a case, as shown in FIG. 23, the determined grinding amount may be larger than an appropriate grinding amount, and the n-type semiconductor layer 133 may be removed. Alternatively, as shown in FIG. 24, the determined grinding amount becomes smaller than the appropriate grinding amount, and the n-type semiconductor layer 133 (see FIG. 21) may not be exposed on the lower surface (back surface) of the semiconductor substrate SB103. . Further, when the thickness uniformity of the p-type semiconductor layer 134 or the base 131 in the upper surface 131a (see FIG. 21) of the base 131 (see FIG. 21) decreases, the n-type in the top 131a of the base 131. There is a possibility that a portion where the semiconductor layer 133 is removed and a portion where the n-type semiconductor layer 133 is not exposed on the lower surface of the semiconductor substrate SB103 are mixed.

  Even if the grinding amount for grinding the semiconductor substrate SB103 is not accurately determined, if the thickness of the n-type semiconductor layer 133 is sufficiently thick, the n-type semiconductor layer 133 is not removed and the n-type semiconductor The layer 133 can be appropriately ground so as to be exposed on the lower surface of the semiconductor substrate SB103. However, if the n-type semiconductor layer 133 is too thick, the manufacturing cost of the semiconductor substrate SB103 may increase.

  That is, in the semiconductor device of Comparative Example 4, although the amount of carriers injected into the IGBT from the collector side can be easily adjusted, it is difficult to accurately determine the amount of grinding of the semiconductor substrate SB103. There is a problem.

<Semiconductor substrate of Embodiment 3>
Next, the semiconductor substrate of Embodiment 3 which is one embodiment of the present invention will be described with reference to the drawings. The semiconductor substrate according to the third embodiment is a semiconductor substrate used for forming an IGBT in order to solve the above-described problems in Comparative Example 3 and Comparative Example 4, and is on a substrate made of n-type silicon carbide. And a semiconductor substrate in which a first p-type semiconductor layer, an n-type semiconductor layer, and a second p-type semiconductor layer are stacked.

  FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate of Third Embodiment.

As shown in FIG. 25, the semiconductor substrate SB3 of the third embodiment includes an n-type substrate 31, a p-type semiconductor layer 32, an n-type semiconductor layer 33, a p-type semiconductor layer 34a, and a p ⁻ -type drift. A layer 34b.

The base 31 has an upper surface 31a as a first surface and a lower surface 31b as a second surface opposite to the upper surface 31a. A p-type semiconductor layer 32 is formed on the upper surface 31 a of the base 31, an n-type semiconductor layer 33 is formed on the p-type semiconductor layer 32, a p-type semiconductor layer 34 a is formed on the n-type semiconductor layer 33, and p-type A p ⁻ type drift layer 34b is formed on the semiconductor layer 34a.

The base 31 is a bulk substrate made of, for example, a silicon carbide (SiC) single crystal as an n-type semiconductor. The base 31 is formed by, for example, a sublimation method. The base 31 contains n-type impurities such as nitrogen (N) or phosphorus (P). The n-type impurity concentration in the substrate 31 can be set to, for example, about 1 × 10 ¹⁶ to 2 × 10 ¹⁹ cm ⁻³ . Further, the thickness of the base 31 can be set to about 100 to 1000 μm.

The p-type semiconductor layer 32 is made of, for example, silicon carbide (SiC) as a p-type semiconductor. The p-type semiconductor layer 32 is formed on the upper surface 31a of the base 31 by, for example, an epitaxial growth method. The p-type semiconductor layer 32 contains a p-type impurity such as aluminum (Al) or boron (B). The p-type impurity concentration in the p-type semiconductor layer 32 can be set to, for example, about 1 × 10 ^{14 to} 5 × 10 ¹⁹ cm ⁻³ . Moreover, the thickness of the p-type semiconductor layer 32 can be set to, for example, about 0.1 to 30 μm.

  As will be described later with reference to FIG. 27, the p-type semiconductor layer 32 is formed by removing the substrate 31 and the p-type semiconductor layer 32 by grinding the semiconductor substrate SB3 from the lower surface 31b side of the substrate 31. This is a marker for determining an appropriate grinding amount by taking an image of a cross section of SB3 with a scanning electron microscope. Therefore, when the thickness of the p-type semiconductor layer 32 is less than 0.1 μm, the thickness of the p-type semiconductor layer 32 may be too thin to observe the p-type semiconductor layer 32 with a scanning electron microscope. On the other hand, when the thickness of the p-type semiconductor layer 32 exceeds 30 μm, the thickness of the p-type semiconductor layer 32 is too thick and the quality such as crystallinity of the p-type semiconductor layer 32 is deteriorated, or the p-type semiconductor There is a possibility that the time for epitaxially growing the layer 32 becomes long and the manufacturing time of the semiconductor substrate SB3 becomes long.

The n-type semiconductor layer 33 is made of silicon carbide (SiC) as an n-type semiconductor. The n-type semiconductor layer 33 is formed on the p-type semiconductor layer 32 by, for example, an epitaxial growth method. The n-type semiconductor layer 33 contains an n-type impurity such as nitrogen (N) or phosphorus (P). The n-type impurity concentration in the n-type semiconductor layer 33 can be set to about 1 × 10 ¹⁷ to 4 × 10 ²⁰ cm ⁻³ , for example. Further, the thickness of the n-type semiconductor layer 33 can be set to, for example, about 0.5 to 30 μm.

As will be described later with reference to FIG. 26, the n-type semiconductor layer 33 is included in the IGBT formed using the semiconductor substrate SB3, and supplies electrons to the p ⁻ -type drift layer 34b when the IGBT is in the on state. To do.

The p-type semiconductor layer 34a is a layer made of a p-type semiconductor. The p-type semiconductor layer 34a is formed on the n-type semiconductor layer 33 by, for example, an epitaxial growth method. The p-type semiconductor layer 34a contains a p-type impurity such as aluminum (Al) or boron (B). The p-type impurity concentration in the p-type semiconductor layer 34a can be, for example, about 4 × 10 ¹⁵ to 1 × 10 ¹⁹ cm ⁻³ . Moreover, the thickness of the p-type semiconductor layer 34a can be set to, for example, about 0.5 to 20 μm.

As will be described later with reference to FIG. 26, the p-type semiconductor layer 34a is included in the IGBT formed using the semiconductor substrate SB3, and when a voltage corresponding to a withstand voltage is applied to the IGBT, the p ⁻ -type drift layer is formed. The depletion layer extending from 34b is terminated. The p-type semiconductor layer 34a is also referred to as a field stop layer.

The p ⁻ type drift layer 34b is a layer made of a p type semiconductor. The p ⁻ type drift layer 34b is formed on the p type semiconductor layer 34a by, for example, an epitaxial growth method. The p ⁻ type drift layer 34b contains a p type impurity such as aluminum (Al) or boron (B). The p ^- type impurity concentration in the p ⁻ -type drift layer 34b is, for example, about 5 × 10 ¹³ to 1 × 10 ¹⁶ cm ⁻³ and lower than the p-type impurity concentration in the p-type semiconductor layer 34a. Can do. Further, the thickness of the p ⁻ type drift layer 34b can be set to about 10 to 300 μm, for example.

As will be described later with reference to FIG. 26, the p ⁻ type drift layer 34b is included in an IGBT formed using the semiconductor substrate SB3, and is a layer through which electrons and holes flow when the IGBT is in an on state. There is a function similar to that of the p ⁻ -type drift layer 13b in the first embodiment.

It is assumed that the p-type semiconductor layer 34 is formed by the p-type semiconductor layer 34a and the p ⁻ -type drift layer 34b. At this time, the semiconductor substrate SB3 according to the third embodiment includes a base 31, a p-type semiconductor layer 32 formed on the upper surface 31a of the base 31, and an n-type semiconductor layer 33 formed on the p-type semiconductor layer 32. And a p-type semiconductor layer 34 formed on the n-type semiconductor layer 33. The p-type semiconductor layer 34 including the p-type semiconductor layer 34a and the p ⁻ -type drift layer 34b is formed on the n-type semiconductor layer 33 and is made of silicon carbide.

<Semiconductor Device of Third Embodiment>
FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate of the third embodiment.

As shown in FIG. 26, the semiconductor device of the third embodiment includes an n-type semiconductor layer 33, a p-type semiconductor layer 34a, a p ⁻ -type drift layer 34b, an n-type semiconductor region 35, and a p-type semiconductor region. 36, a gate insulating film 37, a gate electrode 38, an interlayer insulating film 39, an opening 40, an emitter electrode 41, and a collector electrode 42.

The semiconductor device of the third embodiment includes a p-channel IGBT having a gate electrode 38, an emitter electrode 41, and a collector electrode 42 as a semiconductor element as a three-terminal element. The IGBT controls the current flowing between the emitter electrode 41 and the collector electrode 42 by controlling the voltage applied to the gate electrode 38 to switch between the on state and the off state. Further, a p-type semiconductor layer 34a, p ^- -type drift layer 34b, p-type semiconductor layer 34 is formed by an n-type semiconductor layer 33, a p-type semiconductor layer 34a, p ^- -type drift layer 34b, the A semiconductor substrate SB3 is formed.

The n-type semiconductor layer 33 is made of silicon carbide (SiC) as an n-type semiconductor. The p-type semiconductor layer 34a is made of silicon carbide (SiC) as a p-type semiconductor. The p-type semiconductor layer 34 a is formed on the n-type semiconductor layer 33. The p ⁻ type drift layer 34b is made of silicon carbide (SiC) as a p type semiconductor. The p ⁻ type drift layer 34b is formed on the p type semiconductor layer 34a.

As described with reference to FIG. 25, the n-type semiconductor layer 33 supplies electrons to the p ⁻ -type drift layer 34b when the IGBT is on. The p-type semiconductor layer 34a is also referred to as a field stop layer, and terminates a depletion layer extending from the p ⁻ -type drift layer 34b when a voltage corresponding to a withstand voltage is applied to the IGBT. The p ⁻ -type drift layer 34b is a layer through which electrons and holes flow when the IGBT is on.

p ^- n-type semiconductor region 35 is formed in the upper portion of the type drift layer 34b, p-type semiconductor region 36 is formed in the upper portion of the n-type semiconductor region 35, p ^- -type drift layer 34b and the p-type semiconductor region 36 A gate electrode 38 is formed on the n-type semiconductor region 35 sandwiched between the layers via a gate insulating film 37. The gate insulating film 37 is made of, for example, a silicon oxide (SiO ₂ ) film. The gate electrode 38 is made of, for example, a polysilicon film in which a p-type impurity such as boron (B) is diffused at a high concentration.

An interlayer insulating film 39 that covers the gate electrode 38 is formed on the semiconductor substrate SB3. The interlayer insulating film 39 is made of, for example, a silicon oxide (SiO ₂ ) film.

  An opening 40 is formed in the interlayer insulating film 39 so as to penetrate the interlayer insulating film 39 and reach the n-type semiconductor region 35 and the p-type semiconductor region 36. The n-type semiconductor region is formed in the opening 40 and on the interlayer insulating film 39. An emitter electrode 41 in contact with 35 and the p-type semiconductor region 36 is formed. The emitter electrode 41 is made of, for example, titanium (Ti) or aluminum (Al).

  A collector electrode 42 is formed on the lower surface 31 b of the base 31. The collector electrode 42 is made of, for example, aluminum (Al).

In the semiconductor device of the third embodiment, the impurity concentration in the n-type semiconductor layer 33 and the thickness of the n-type semiconductor layer 33 can be adjusted. Thereby, the carrier density in the p ⁻ -type drift layer 34b can be easily adjusted in the ON state of the IGBT.

  The semiconductor device according to the third embodiment has the same configuration as that of the semiconductor device according to the comparative example 4 described with reference to FIG.

The IGBT provided in the semiconductor device of the third embodiment has a gate insulating film 37 on the n-type semiconductor region 35 sandwiched between the p ⁻ -type drift layer 34 b and the p-type semiconductor region 36. A so-called planar type IGBT in which a gate electrode 38 is formed. However, in the semiconductor device of the third embodiment, the gate electrode 38 is formed on the surface of the n-type semiconductor region 35 sandwiched between the p ⁻ -type drift layer 34 b and the p-type semiconductor region 36 via the gate insulating film 37. Should just be formed. Therefore, in the IGBT provided in the semiconductor device of the third embodiment, the gate insulating film 37 is provided on the side surface of the n-type semiconductor region 35 sandwiched between the p ⁻ -type drift layer 34 b and the p-type semiconductor region 36. A so-called trench gate type IGBT in which the gate electrode 38 is formed may be used.

  As described above in the first embodiment, in the semiconductor element included in the semiconductor device as the power semiconductor device, it is desirable to adjust the conduction loss and the switching loss to appropriate ranges. For example, by replacing a semiconductor element made of Si with an IGBT as a bipolar element made of SiC for each range of different breakdown voltages, conduction loss and switching loss of the power semiconductor device can be reduced.

  As described above in the first embodiment, in the range where the breakdown voltage exceeds 6.5 kV, the conduction loss of the IGBT made of SiC is either the conduction loss of the IGBT made of Si or the conduction loss of the MOSFET made of SiC. Is expected to be lower. In such a range where the withstand voltage exceeds 6.5 kV, the semiconductor device as the power semiconductor device of the third embodiment is expected to be used in a transformer, a power transmission network, or an SST in a high-speed railway.

<Method for Manufacturing Semiconductor Device of Third Embodiment>
27 to 30 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of Third Embodiment.

  In the following, a manufacturing process for forming an IGBT as a semiconductor element on the semiconductor substrate SB1 after grinding the lower surface (back surface) of the semiconductor substrate SB1 will be described.

In the manufacturing process of the semiconductor device according to the third embodiment, first, as shown in FIG. 25, a semiconductor substrate SB3 including a base 31 that is an n-type bulk substrate is prepared. The semiconductor substrate SB3 includes a base 31, a p-type semiconductor layer 32, an n-type semiconductor layer 33, a p-type semiconductor layer 34a, and a p ⁻ -type drift layer 34b.

  In the manufacturing process of the semiconductor device according to the third embodiment, next, as shown in FIG. 27, the semiconductor substrate SB3 is ground from the lower surface 31b (see FIG. 25) side of the base 31 (see FIG. 25). 31 and the p-type semiconductor layer 32 (see FIG. 25) are removed.

  In the step of grinding the semiconductor substrate SB3, before starting the grinding of the semiconductor substrate SB3, first, as shown in FIG. 12, a portion PT3 which is a part of the semiconductor substrate SB3 is cut along a cutting line LN3 to form a test piece. Is made. And as shown in FIG. 28, the cross section of the produced test piece is observed with a scanning electron microscope.

  At this time, the p-type semiconductor regions such as the p-type semiconductor layer 32 are negatively charged, and the n-type semiconductor regions such as the n-type substrate 31 and the n-type semiconductor layer 33 are positively charged. , For example, the p-type semiconductor region appears bright and the n-type semiconductor region appears dark due to the potential contrast. Thereby, the base 31 and the p-type semiconductor layer 32 can be clearly distinguished, and the p-type semiconductor layer 32 and the n-type semiconductor layer 33 can be clearly distinguished.

Therefore, the thickness TH31, which is the sum of the thicknesses of the base 31 and the p-type semiconductor layer 32, can be accurately measured, and the n-type semiconductor layer 33, the p-type semiconductor layer 34a, and the p ⁻ -type drift layer 34b The thickness TH32, which is the sum of the thicknesses, can be accurately measured. Then, a desired grinding amount (equal to the thickness TH31) for grinding the semiconductor substrate SB3 can be accurately determined.

  That is, in the semiconductor substrate grinding method of the third embodiment, an image of a cross section of the semiconductor substrate SB3 is taken with a scanning electron microscope before starting the grinding of the semiconductor substrate SB3. Then, based on the luminance difference (contrast) between the p-type semiconductor layer 32 and the n-type semiconductor layer 33 in the captured image, that is, the difference in brightness between the p-type semiconductor layer 32 and the n-type semiconductor layer 33, A grinding amount for grinding the semiconductor substrate SB3 is determined.

  Note that the substrate 31 may not be an n-type semiconductor, as long as at least the p-type semiconductor layer 32 and the n-type semiconductor layer 33 can be clearly distinguished. For example, silicon carbide (SiC) as a p-type semiconductor is used. ) A bulk substrate made of a single crystal may be used.

  In the step of grinding the semiconductor substrate SB3, the base 31 and the p-type semiconductor layer 32 are then removed by grinding the semiconductor substrate SB3 from the lower surface 31b side of the base 31 with the determined grinding amount.

  As described above when describing the manufacturing process of the semiconductor device of Comparative Example 4, the amount of grinding of the semiconductor substrate SB3 is not accurately determined, and the thickness of the n-type semiconductor layer 33 is Consider the case where it is not thick enough. In such a case, when the semiconductor substrate SB3 is ground from the lower surface 31b side of the base 31, the n-type semiconductor layer 33 is removed or the n-type semiconductor layer 33 is removed from the lower surface (back surface) of the semiconductor substrate SB3. May not be exposed.

  However, according to the manufacturing process of the semiconductor device of the third embodiment, the grinding amount for grinding the semiconductor substrate SB3 can be accurately adjusted in the manufacturing process of the semiconductor device in which the injection amount of carriers injected into the semiconductor element can be easily adjusted. Can be determined. Therefore, the semiconductor substrate SB3 is accurately ground from the lower surface 31b side of the base 31 so that the n-type semiconductor layer 33 is not removed and the n-type semiconductor layer 33 is exposed on the lower surface (back surface) of the semiconductor substrate SB3. Can be ground.

In addition, even when the thickness uniformity of the p-type semiconductor layer 34 or the base 31 in the upper surface 31a of the base 31 is reduced, the n-type semiconductor layer 33 is removed from the upper surface 31a of the base 31 and n It is possible to prevent or suppress the mixing of the portion where the mold semiconductor layer 33 is not exposed on the lower surface of the semiconductor substrate SB3. Thereby, it is prevented or suppressed that the characteristics of the IGBT as the semiconductor element formed in the n-type semiconductor layer 33, the p-type semiconductor layer 34a, and the p ⁻ -type drift layer 34b vary in the upper surface 31a of the base 31. be able to.

  Moreover, since it is not necessary to increase the thickness of the n-type semiconductor layer 33, the manufacturing cost of the semiconductor substrate SB3 can be reduced.

  In the method described above, an image of a cross section of the semiconductor substrate SB3 is taken with a scanning electron microscope before starting the grinding of the semiconductor substrate SB3. However, after starting the grinding of the semiconductor substrate SB3, as shown in FIG. 29, an image of a cross section of the semiconductor substrate SB3 may be taken with a scanning electron microscope in a state where a part of the base 31 remains. . Even in such a case, the base 31 and the p-type semiconductor layer 32 can be clearly distinguished, and the p-type semiconductor layer 32 and the n-type semiconductor layer 33 can be clearly distinguished. Therefore, the thickness TH33, which is the sum of the thicknesses of the remaining portion of the base 31 and the p-type semiconductor layer 32, can be accurately measured. Then, a desired grinding amount (equal to the thickness TH33) for grinding the remaining portion of the substrate 11 and the p-type semiconductor layer 32 can be accurately determined.

  After determining the grinding amount, the accuracy of the grinding amount is improved as the absolute value of the grinding amount by which the semiconductor substrate SB1 is ground is smaller. Therefore, after starting the grinding of the semiconductor substrate SB3, for example, after grinding until the actual grinding amount becomes about 80% of the appropriate grinding amount, an image of the cross section of the semiconductor substrate SB3 is taken by the scanning electron microscope. By doing so, the precision of the grinding amount can be further improved.

  That is, in the method for grinding a semiconductor substrate according to the third embodiment, an image of a cross section of the semiconductor substrate SB3 may be taken with a scanning electron microscope before the base 31 is removed. Then, based on the luminance difference (contrast) between the p-type semiconductor layer 32 and the n-type semiconductor layer 33 in the captured image, that is, the difference in brightness between the p-type semiconductor layer 32 and the n-type semiconductor layer 33, What is necessary is just to determine the grinding amount which grinds semiconductor substrate SB3.

At this time, in the method for measuring the thickness of the semiconductor substrate according to the third embodiment, an image of a cross section of the semiconductor substrate SB3 is taken with a scanning electron microscope before the base 31 is removed. Then, based on the luminance difference (contrast) between the p-type semiconductor layer 32 and the n-type semiconductor layer 33 in the captured image, that is, the difference in brightness between the p-type semiconductor layer 32 and the n-type semiconductor layer 33, The sum of the thicknesses of the substrate 31 and the p-type semiconductor layer 32 is measured.
In the manufacturing process of the semiconductor device of the third embodiment, next, an IGBT as a semiconductor element is formed.

In the step of forming the IGBT, first, as shown in FIG. 30, an n-type semiconductor region 35 is formed. For example, n-type impurities such as phosphorus (P) or arsenic (As) are introduced into the upper layer portion of the p ⁻ -type drift layer 34b by, for example, an ion implantation method using a patterned resist film as a mask. As a result, an n-type semiconductor region 35 is formed in the upper layer portion of the p ⁻ -type drift layer 34b.

  Next, as shown in FIG. 30, a p-type semiconductor region 36 is formed. For example, p-type impurities such as aluminum (Al) or boron (B) are introduced into the upper layer portion of the n-type semiconductor region 35 by, for example, ion implantation using a patterned resist film as a mask. As a result, a p-type semiconductor region 36 is formed in the upper layer portion of the n-type semiconductor region 35.

Next, as shown in FIG. 30, a gate insulating film 37 and a gate electrode 38 are formed. For example, the gate insulating film 37 made of silicon oxide (SiO ₂ ) or the like is formed on the semiconductor substrate SB3 by, for example, a CVD (Chemical Vapor Deposition) method. Further, a gate electrode 38 made of, for example, polycrystalline silicon (polysilicon) is formed on the gate insulating film 37 by, for example, a CVD method. Then, the gate electrode 38 and the gate insulating film 37 are patterned. As a result, the gate electrode 38 is formed on the n-type semiconductor region 35 between the p-type semiconductor region 36 and the p ⁻ -type drift layer 34 b via the gate insulating film 37.

In addition to the case where the planar type IGBT shown in FIG. 30 is formed, including the case where the trench gate type IGBT is formed, the portion sandwiched between the p type semiconductor region 36 and the p ⁻ type drift layer 34b is included. A gate electrode 38 may be formed on the surface of the n-type semiconductor region 35 with a gate insulating film 37 interposed therebetween.

Next, as shown in FIG. 30, an interlayer insulating film 39 is formed. For example, an interlayer insulating film 39 made of silicon oxide (SiO ₂ ) or the like is formed on the semiconductor substrate SB3 so as to cover the gate electrode 38, for example, by a CVD method.

  Next, as shown in FIG. 30, an opening 40 is formed. An opening 40 is formed in the interlayer insulating film 39 so as to penetrate the interlayer insulating film 39 and reach the n-type semiconductor region 35 and the p-type semiconductor region 36. At the bottom of the opening 40, the n-type semiconductor region 35 and the p-type semiconductor region 36 are exposed.

  Next, as shown in FIG. 32, an emitter electrode 41 is formed. For example, the emitter electrode 41 made of titanium (Ti) or aluminum (Al) is deposited on the inside of the opening 40 and on the interlayer insulating film 39 by, for example, vapor deposition or sputtering. Form. Thereby, the emitter electrode 41 electrically connected to the n-type semiconductor region 35 and the p-type semiconductor region 36 is formed.

  Also, as shown in FIG. 30, impurities are implanted into the lower surface (rear surface) of the n-type semiconductor layer 33, that is, the portion of the n-type semiconductor layer 33 opposite to the p-type semiconductor layer 34a by, for example, ion implantation. The n-type semiconductor layer 42a may be formed by performing heat treatment to activate the implanted impurities. The n-type semiconductor layer 42a reduces the contact resistance between the n-type semiconductor layer 33 and the collector electrode 42 (see FIG. 26).

  Next, as shown in FIG. 26, a collector electrode 42 is formed under the n-type semiconductor layer 33, that is, on the opposite side of the p-type semiconductor layer 34a with the n-type semiconductor layer 33 interposed therebetween. For example, a collector electrode 42 made of aluminum (Al) or the like is formed on the lower surface of the n-type semiconductor layer 33 by, for example, vapor deposition or sputtering. As a result, a collector electrode 42 electrically connected to the n-type semiconductor layer 33 is formed, and an IGBT as a semiconductor element is formed on the semiconductor substrate SB3. As described above, the semiconductor device of the third embodiment can be manufactured.

  When manufacturing the semiconductor device of the third embodiment by the manufacturing process described above, the impurity concentration in the n-type semiconductor layer 33 can be made higher than the impurity concentration in the n-type substrate 31, for example. At this time, the amount of carriers injected into the IGBT from the collector side, that is, the amount of injected electrons can be easily increased, and the conduction loss can be reduced as compared with the semiconductor device of Comparative Example 3.

  Alternatively, when the semiconductor device of the third embodiment is manufactured by the manufacturing process described above, the impurity concentration in the n-type semiconductor layer 33 can be made lower than the impurity concentration in the n-type substrate 11, for example. At this time, the amount of carriers injected into the IGBT from the collector side, that is, the amount of injected electrons can be easily reduced, and the switching loss can be reduced as compared with the semiconductor device of Comparative Example 3.

<Modification of Manufacturing Method of Semiconductor Device of Third Embodiment>
In the manufacturing process described above, after the lower surface (back surface) of the semiconductor substrate SB3 was ground, the IGBT was formed on the semiconductor substrate SB3. On the other hand, in the manufacturing process of the modified example described below, after a portion other than the collector electrode 42 of the IGBT is formed on the upper surface (front surface) of the semiconductor substrate SB3, the lower surface (back surface) of the semiconductor substrate SB3 is ground.

  31 and 32 are cross-sectional views of relevant parts in the manufacturing process of the semiconductor device according to the modification of the third embodiment.

  Also in the manufacturing process of the present modification, first, as in the manufacturing process of the third embodiment, as shown in FIG. 25, a semiconductor substrate SB3 including a base 31 that is an n-type bulk substrate is prepared.

  In the manufacturing process of the present modification, next, unlike the third embodiment, as shown in FIG. 31, a portion on the upper surface side of the semiconductor substrate SB3 is formed in the IGBT as the semiconductor element. Specifically, the n-type semiconductor region 35, the p-type semiconductor region 36, the gate insulating film 37, the gate electrode 38, the interlayer insulating film 39, the opening 40 and the emitter electrode 41 are formed. About the process of forming each part, it can carry out similarly to the process of forming each part in the manufacturing process of Embodiment 3. As a result, a portion of the IGBT on the upper surface side of the semiconductor substrate SB3 is formed in the p-type semiconductor layer 34.

  In the manufacturing process of the present modification, next, as shown in FIG. 32, the semiconductor substrate SB1 is ground from the lower surface 31b (see FIG. 31) side of the base 31 (see FIG. 31), so that the base 31 and the p-type semiconductor are obtained. Layer 32 (see FIG. 31) is removed. The process of grinding the semiconductor substrate SB3 can be performed in the same manner as the process of grinding the semiconductor substrate SB3 in the manufacturing process of the third embodiment.

  In the manufacturing process of the present modification, next, as shown in FIG. 26, the collector electrode 42 is formed under the n-type semiconductor layer 33, that is, on the opposite side of the p-type semiconductor layer 34a with the n-type semiconductor layer 33 interposed therebetween. . The step of forming the collector electrode 42 can be performed in the same manner as the step of forming the collector electrode 42 in the manufacturing process of the third embodiment. As a result, a portion of the IGBT on the lower surface side of the semiconductor substrate SB3 is formed in the n-type semiconductor layer 33. As described above, a semiconductor device similar to the semiconductor device of the third embodiment can be manufactured.

  In the manufacturing process of this modification, after forming a portion of the IGBT other than the collector electrode 42 on the upper surface (front surface) of the semiconductor substrate SB3, the lower surface (back surface) of the semiconductor substrate SB3 is ground. Thereby, parts other than collector electrode 42 among IGBT can be formed using thick semiconductor substrate SB3 before grinding. Therefore, the semiconductor substrate SB3 can be more reliably prevented from being damaged when a portion other than the collector electrode 42 is formed in the IGBT.

(Embodiment 4)
In the third embodiment, the example in which the p-type semiconductor layer 32 is directly formed on the base 31 as the semiconductor substrate SB3 has been described. On the other hand, in the fourth embodiment, an example will be described in which the p-type semiconductor layer 32 is formed on the base 31 via the buffer layer as the semiconductor substrate SB3.

  Note that the semiconductor substrate, semiconductor device, and semiconductor substrate manufacturing method of the fourth embodiment are the same as those of the third embodiment except that the p-type semiconductor layer 32 is formed on the base 31 via a buffer layer. The semiconductor substrate, the semiconductor device, and the method for manufacturing the semiconductor substrate can be the same, and the description of the same parts as those of the third embodiment is omitted.

  FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate of the fourth embodiment.

As shown in FIG. 33, also in the fourth embodiment, as in the third embodiment, the semiconductor substrate SB3 includes an n-type substrate 31, a p-type semiconductor layer 32, an n-type semiconductor layer 33, and a p-type. The semiconductor layer 34 and the p ⁻ type drift layer 34 b are included.

On the other hand, in the fourth embodiment, unlike the third embodiment, an n-type semiconductor layer 45 as a buffer layer is interposed between the base 31 and the p-type semiconductor layer 32. That is, the n-type semiconductor layer 45 is formed on the base 31, and the p-type semiconductor layer 32 is formed on the base 31 via the n-type semiconductor layer 45. The n-type semiconductor layer 45 prevents or suppresses continuous formation of crystal defects such as basal plane dislocations formed in the base 31 made of silicon carbide (SiC) in the p-type semiconductor layer 32. Therefore, the formation of the n-type semiconductor layer 45 can improve the characteristics of the IGBT as a semiconductor element formed in the n-type semiconductor layer 33, the p-type semiconductor layer 34a, and the p ⁻ -type drift layer 34b.

The n-type semiconductor layer 45 is made of silicon carbide (SiC) as an n-type semiconductor. The n-type semiconductor layer 45 is formed on the base 31 by, for example, an epitaxial growth method. The n-type semiconductor layer 45 contains an n-type impurity such as nitrogen (N) or phosphorus (P). The n-type impurity concentration in the n-type semiconductor layer 45 can be, for example, about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . Further, the thickness of the n-type semiconductor layer 25 can be set to, for example, about 0.5 to 30 μm.

  In the fourth embodiment, in the semiconductor device manufacturing process, the n-type semiconductor layer is removed when the base 31 and the p-type semiconductor layer 32 are removed by grinding the semiconductor substrate SB3 from the lower surface 31b side of the base 31. 45 is also removed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a semiconductor substrate, a semiconductor substrate grinding method, and a semiconductor device manufacturing method.

11 Substrate 11a Upper surface 11b Lower surface 12 p-type semiconductor layer 13, 13a n-type semiconductor layer 13b n ^- type drift layer 14 p-type semiconductor layer 15 Anode 16 cathode 16a n-type semiconductor layer 31 Base 31a upper surface 31b lower surface 32 p-type semiconductor layer 33 n-type semiconductor layer 34, 34a p-type semiconductor layer 34b p ^- type drift layer 35 n-type semiconductor region 36 p-type semiconductor region 37 gate insulating film 38 gate electrode 39 interlayer insulating film 40 opening 41 emitter electrode 42 collector electrode 42a n-type Semiconductor layer LN1, LN3 Cut line PT1, PT3 portion SB1, SB3 Semiconductor substrate TH11, TH12, TH13 thickness TH31, TH32, TH33 thickness

Claims (14)

A substrate made of silicon carbide;
A p-type first semiconductor layer formed on the substrate and made of silicon carbide;
An n-type second semiconductor layer formed on the first semiconductor layer and made of silicon carbide;
A p-type third semiconductor layer formed on the second semiconductor layer and made of silicon carbide;
I have a,
The second semiconductor layer includes
An n-type fifth semiconductor layer formed on the first semiconductor layer and made of silicon carbide;
An n-type sixth semiconductor layer formed on the fifth semiconductor layer and made of silicon carbide;
Including
A semiconductor substrate, wherein an n-type impurity concentration in the sixth semiconductor layer is lower than an n-type impurity concentration in the fifth semiconductor layer. A substrate made of silicon carbide;
A p-type first semiconductor layer formed on the substrate and made of silicon carbide;
An n-type second semiconductor layer formed on the first semiconductor layer and made of silicon carbide;
A p-type third semiconductor layer formed on the second semiconductor layer and made of silicon carbide;
I have a,
The third semiconductor layer includes
A p-type seventh semiconductor layer formed on the second semiconductor layer and made of silicon carbide;
A p-type eighth semiconductor layer formed on the seventh semiconductor layer and made of silicon carbide;
Including
The semiconductor substrate, wherein the p-type impurity concentration in the eighth semiconductor layer is lower than the p-type impurity concentration in the seventh semiconductor layer. The semiconductor substrate according to claim 1 or 2 ,
An n-type fourth semiconductor layer formed on the substrate and made of silicon carbide;
The first semiconductor layer is a semiconductor substrate formed on the base via the fourth semiconductor layer. The semiconductor substrate according to claim 1 or 2 ,
The thickness of the said 1st semiconductor layer is a semiconductor substrate which is 0.1-30 micrometers. (A) a first surface and a second surface opposite to the first surface, a base made of silicon carbide, and a p-type made of silicon carbide formed on the first surface of the base A first semiconductor layer; an n-type second semiconductor layer formed on the first semiconductor layer and made of silicon carbide; and a p-type third semiconductor layer formed on the second semiconductor layer and made of silicon carbide. And a step of preparing a semiconductor substrate having
(B) removing the base and the first semiconductor layer by grinding the semiconductor substrate from the second surface side of the base;
Have
In the step (b), an image of a cross section of the semiconductor substrate is taken with a scanning electron microscope before the substrate is removed, and the brightness of the first semiconductor layer and the second semiconductor layer in the taken image Based on the difference, a grinding amount for grinding the semiconductor substrate is determined, and the semiconductor substrate is ground from the second surface side of the base body with the determined grinding amount, whereby the base body and the first semiconductor layer are separated. A method for grinding a semiconductor substrate to be removed. In the grinding method of the semiconductor substrate according to claim 5 ,
The semiconductor substrate has an n-type fourth semiconductor layer formed on the substrate and made of silicon carbide,
The first semiconductor layer is formed on the base via the fourth semiconductor layer,
In the step (b), the semiconductor substrate is ground from the second surface side of the base body, thereby removing the base body, the fourth semiconductor layer, and the first semiconductor layer. In the grinding method of the semiconductor substrate according to claim 5 ,
The second semiconductor layer includes
An n-type fifth semiconductor layer formed on the first semiconductor layer and made of silicon carbide;
An n-type sixth semiconductor layer formed on the fifth semiconductor layer and made of silicon carbide;
Including
A method for grinding a semiconductor substrate, wherein an n-type impurity concentration in the sixth semiconductor layer is lower than an n-type impurity concentration in the fifth semiconductor layer. In the grinding method of the semiconductor substrate according to claim 5 ,
The third semiconductor layer includes
A p-type seventh semiconductor layer formed on the second semiconductor layer and made of silicon carbide;
A p-type eighth semiconductor layer formed on the seventh semiconductor layer and made of silicon carbide;
Including
A method for grinding a semiconductor substrate, wherein a p-type impurity concentration in the eighth semiconductor layer is lower than a p-type impurity concentration in the seventh semiconductor layer. (A) a first surface and a second surface opposite to the first surface, a base made of silicon carbide, and a p-type made of silicon carbide formed on the first surface of the base A first semiconductor layer; an n-type second semiconductor layer formed on the first semiconductor layer and made of silicon carbide; and a p-type third semiconductor layer formed on the second semiconductor layer and made of silicon carbide. And a step of preparing a semiconductor substrate having
(B) removing the base and the first semiconductor layer by grinding the semiconductor substrate from the second surface side of the base;
(C) forming a semiconductor element on the second semiconductor layer and the third semiconductor layer;
Have
In the step (b), an image of a cross section of the semiconductor substrate is taken with a scanning electron microscope before the substrate is removed, and the brightness of the first semiconductor layer and the second semiconductor layer in the taken image Based on the difference, a grinding amount for grinding the semiconductor substrate is determined, and the semiconductor substrate is ground from the second surface side of the base body with the determined grinding amount, whereby the base body and the first semiconductor layer are separated. A method of manufacturing a semiconductor device to be removed. In the manufacturing method of the semiconductor device according to claim 9 ,
The semiconductor substrate has an n-type fourth semiconductor layer formed on the substrate and made of silicon carbide,
The first semiconductor layer is formed on the base via the fourth semiconductor layer,
In the step (b), the semiconductor substrate is ground from the second surface side of the base to remove the base, the fourth semiconductor layer, and the first semiconductor layer. In the manufacturing method of the semiconductor device according to claim 9 ,
The second semiconductor layer includes
An n-type fifth semiconductor layer formed on the first semiconductor layer and made of silicon carbide;
An n-type sixth semiconductor layer formed on the fifth semiconductor layer and made of silicon carbide;
Including
The n-type impurity concentration in the sixth semiconductor layer is lower than the n-type impurity concentration in the fifth semiconductor layer,
The semiconductor element is a diode;
The diode is
An anode electrically connected to the sixth semiconductor layer;
A cathode electrically connected to the second semiconductor layer;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 9 ,
The third semiconductor layer includes
A p-type seventh semiconductor layer formed on the second semiconductor layer and made of silicon carbide;
A p-type eighth semiconductor layer formed on the seventh semiconductor layer and made of silicon carbide;
Including
The p-type impurity concentration in the eighth semiconductor layer is lower than the p-type impurity concentration in the seventh semiconductor layer,
The semiconductor element is an insulated gate bipolar transistor;
The insulated gate bipolar transistor is:
An n-type first semiconductor region formed in an upper layer portion of the eighth semiconductor layer;
A p-type second semiconductor region formed in an upper layer portion of the first semiconductor region;
A gate electrode formed on a surface of the first semiconductor region in a portion sandwiched between the second semiconductor region and the eighth semiconductor layer via a gate insulating film;
An emitter electrode electrically connected to the first semiconductor region and the second semiconductor region;
A collector electrode electrically connected to the second semiconductor layer;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 9 ,
In the step (c), the semiconductor element is formed after the step (b). In the manufacturing method of the semiconductor device according to claim 9 ,
The step (c)
(C1) forming a first portion of the semiconductor element in the third semiconductor layer before the step (b);
(C2) after the step (b), forming a second portion of the semiconductor element in the second semiconductor layer;
A method for manufacturing a semiconductor device, comprising:

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