JP6477248B2 - 演算処理装置及び演算処理装置の処理方法 - Google Patents

演算処理装置及び演算処理装置の処理方法 Download PDF

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JP6477248B2
JP6477248B2 JP2015104724A JP2015104724A JP6477248B2 JP 6477248 B2 JP6477248 B2 JP 6477248B2 JP 2015104724 A JP2015104724 A JP 2015104724A JP 2015104724 A JP2015104724 A JP 2015104724A JP 6477248 B2 JP6477248 B2 JP 6477248B2
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instruction
entry
stored
arithmetic
output
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JP2016218855A5 (enExample
JP2016218855A (ja
Inventor
亮平 岡崎
亮平 岡崎
秋月　康伸
康伸 秋月
猛一 田端
猛一 田端
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Fujitsu Ltd
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Fujitsu Ltd
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Publication of JP2016218855A5 publication Critical patent/JP2016218855A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
JP2015104724A 2015-05-22 2015-05-22 演算処理装置及び演算処理装置の処理方法 Active JP6477248B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015104724A JP6477248B2 (ja) 2015-05-22 2015-05-22 演算処理装置及び演算処理装置の処理方法
US15/068,692 US9965283B2 (en) 2015-05-22 2016-03-14 Multi-threaded processor interrupting and saving execution states of complex instructions of a first thread to allow execution of an oldest ready instruction of a second thread

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015104724A JP6477248B2 (ja) 2015-05-22 2015-05-22 演算処理装置及び演算処理装置の処理方法

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JP2016218855A JP2016218855A (ja) 2016-12-22
JP2016218855A5 JP2016218855A5 (enExample) 2018-02-15
JP6477248B2 true JP6477248B2 (ja) 2019-03-06

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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
JP2023135511A (ja) * 2022-03-15 2023-09-28 富士通株式会社 演算処理装置及び演算処理方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6567839B1 (en) 1997-10-23 2003-05-20 International Business Machines Corporation Thread switch control in a multithreaded processor system
US6237081B1 (en) * 1998-12-16 2001-05-22 International Business Machines Corporation Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor
KR101086792B1 (ko) * 2007-06-20 2011-11-25 후지쯔 가부시끼가이샤 명령 실행 제어 장치 및 명령 실행 제어 방법
EP2159689A4 (en) * 2007-06-20 2011-01-05 Fujitsu Ltd INSTRUCTION MANAGEMENT CONTROL AND INSTRUCTION MANUAL CONTROL PROCEDURES
US20130297910A1 (en) * 2012-05-03 2013-11-07 Jared C. Smolens Mitigation of thread hogs on a threaded processor using a general load/store timeout counter
US20140181484A1 (en) * 2012-12-21 2014-06-26 James Callister Mechanism to provide high performance and fairness in a multi-threading computer system
US20160011874A1 (en) * 2014-07-09 2016-01-14 Doron Orenstein Silent memory instructions and miss-rate tracking to optimize switching policy on threads in a processing device

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US9965283B2 (en) 2018-05-08
US20160342415A1 (en) 2016-11-24
JP2016218855A (ja) 2016-12-22

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