JP6460869B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semi-conductor device.

  2. Description of the Related Art Conventionally, there is known a semiconductor device that includes a cell portion having a source electrode layer and a gate pad portion having a gate pad electrode layer, and the source electrode layer and the gate pad electrode layer are connected via a Zener diode ( For example, see Patent Document 1.)

  As shown in FIG. 13, a conventional semiconductor device 900 includes a cell portion R1 having a source electrode layer 928 (first electrode layer) formed on one surface of a semiconductor substrate 910, and a semiconductor substrate 910 on one surface. And a gate pad portion R2 having the formed gate pad electrode layer 940. An n-type first semiconductor layer 951 formed along the outer edge of the gate pad portion R2 and electrically connected to the source electrode layer 928 and an outer edge of the gate pad portion R2 are formed on the outer edge of the gate pad portion R2. And an n-type second semiconductor layer 952 formed on the gate pad portion R2 side of the first semiconductor layer 951 and electrically connected to the gate pad electrode layer 940, the first semiconductor layer 951, and the first semiconductor layer 951 A zener diode 950 having a p-type third semiconductor layer 953 formed between the two semiconductor layers 952 is formed, and the source electrode layer 928 and the gate pad electrode layer 940 are connected via the zener diode 950. . The Zener diode 950 is formed in a region corresponding to four sides of the quadrangular shape constituting the outer edge of the gate pad portion R2, and is formed on the surface of the semiconductor substrate 910 via the field insulating layer 938. .

  According to the conventional semiconductor device 900, since the source electrode layer 928 and the gate pad electrode layer 940 are connected via the Zener diode 950, the voltage applied to the gate insulating layer 976 in the cell portion R1 when static electricity occurs. Can be lowered, and the ESD tolerance can be increased.

JP 2009-43953 A

  Incidentally, in recent years, in the field of semiconductor device technology, there is a demand for a semiconductor device that satisfies the demand for downsizing of electronic equipment. However, in order to satisfy such a requirement, in the conventional semiconductor device 900, if the planar area occupied by the Zener diode 950 in the semiconductor device is reduced, the pn junction area of the Zener diode 950 is reduced, resulting in the Zener diode 950 being reduced. Since the amount of current flowing through the diode 950 is reduced, there is a problem that the voltage applied to the gate insulating layer 976 is increased when static electricity is generated, and the ESD tolerance is reduced.

  Therefore, the present invention has been made to solve such a problem, and even when the planar area occupied by the Zener diode in the semiconductor device is made smaller than the conventional one, the ESD resistance is unlikely to be smaller than the conventional one. An object is to provide a semiconductor device. Moreover, it aims at providing the manufacturing method of the semiconductor device for manufacturing such a semiconductor device.

[1] A semiconductor device of the present invention includes a cell portion having a first electrode layer formed on one surface of a semiconductor substrate and a gate pad portion having a gate pad electrode layer formed on one surface of the semiconductor substrate. A first conductive type first semiconductor formed at least part of the outer edge of the gate pad portion along the outer edge of the gate pad portion and electrically connected to the first electrode layer A first conductivity type second layer formed on the gate pad portion side of the first semiconductor layer along the outer edge of the gate pad portion and electrically connected to the gate pad electrode layer. A Zener diode having a semiconductor layer and a second conductive type third semiconductor layer formed between the first semiconductor layer and the second semiconductor layer is formed, and the first electrode layer and the gate pad electrode layer are formed. But the Zena A semiconductor device connected via a diode, wherein the semiconductor device includes a trench region in which a trench is formed in the semiconductor substrate along a direction perpendicular to an outer edge of the gate pad portion, and the trench The non-trench regions that are not formed have a concavo-convex structure formed alternately along the outer edge of the gate pad portion, and the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer include the concavo-convex structure. The height positions of the upper surfaces of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are continuously formed throughout, and the height position of one surface of the semiconductor substrate is also the trench region. It is characterized by being higher than.

[2] In the semiconductor device of the present invention, the length from the height position of one surface of the semiconductor substrate to the height position of the bottom of the trench is the length of one surface of the semiconductor substrate in the trench region. The length from the height position to the height position of the upper surface of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, and the height position of one surface of the semiconductor substrate in the non-trench region It is preferable that the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are longer than any of the lengths up to the height position of the upper surface.

[3] In the semiconductor device of the present invention, in the Zener diode, a fourth first conductivity type formed on the third semiconductor layer side between the third semiconductor layer and the second semiconductor layer. It is preferable that at least one set of the semiconductor layer and the second conductive type fifth semiconductor layer formed on the second semiconductor layer side is formed along a direction perpendicular to the outer edge of the gate pad portion. .

[4] In the semiconductor device of the present invention, the length from the height position of one surface of the semiconductor substrate to the height position of the bottom of the trench is the length of one surface of the semiconductor substrate in the trench region. The length from the height position to the height position of the upper surface of the fourth semiconductor layer and the fifth semiconductor layer, and the height position of one surface of the semiconductor substrate in the non-trench region, the fourth semiconductor layer And the length to the height position of the upper surface of the fifth semiconductor layer is preferably longer.

[5] In the semiconductor device of the present invention, the width of the trench is preferably in the range of 0.3 μm to 0.7 μm.

[6] In the semiconductor device of the present invention, the semiconductor device includes a gate electrode layer embedded in a gate trench formed on one surface of the semiconductor substrate via a gate insulating layer in the cell portion. It is preferable that the depth of the trench and the depth of the gate trench are the same.

[7] In the semiconductor device of the present invention, the semiconductor device is a planar type semiconductor device having a gate electrode layer formed on the semiconductor substrate via a gate insulating layer in the cell portion, and the cell Preferably, the thickness of the gate electrode layer in the portion and the thickness of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the non-trench region are the same.

[8] In the semiconductor device of the present invention, each of the gate electrode layer, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer has a first conductivity type in a polysilicon layer formed in a lump. It is preferably formed by introducing an impurity or a second conductivity type impurity.

[9] A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device according to any one of [1] to [8], in which at least one of the outer edges of the gate pad portion. Forming a trench in the semiconductor substrate along a direction perpendicular to the outer edge of the region where the gate pad portion is to be formed, and a non-trench in which the trench is formed and in which the trench is not formed The concavo-convex structure forming step for forming the concavo-convex structure in which the regions are alternately formed along the outer edge of the gate pad portion, and the height position of the upper surface is continuous throughout the concavo-convex structure and also in the trench region. After forming the polysilicon layer so as to be higher than the height position of one surface of the semiconductor substrate, the polysilicon layer is disposed along the outer edge of the gate pad portion. Forming a Zener diode having the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer by introducing a first conductivity type impurity or a second conductivity type impurity into each of the regions; It is characterized by including in this order.

  According to the semiconductor device of the present invention, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are continuously formed over the entire uneven structure, and the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are formed. Since the height position of the upper surface of the semiconductor substrate is higher than the height position of one surface of the semiconductor substrate also in the trench region, not only between the height position of one surface of the semiconductor substrate to the upper surface of each semiconductor layer, A pn junction is also formed in the trench. Therefore, even when the planar area occupied by the Zener diode in the semiconductor device is smaller than the conventional area, the pn junction area of the Zener diode is not smaller than the conventional area, so that the amount of current flowing through the Zener diode is difficult to be reduced. When static electricity occurs, the voltage applied to the gate insulating layer is difficult to increase. As a result, the semiconductor device of the present invention is a semiconductor device in which the ESD resistance is less likely to be smaller than that in the past even when the planar area occupied by the Zener diode in the semiconductor device is smaller than that in the past.

  According to the method for manufacturing a semiconductor device of the present invention, the polyhedral structure is formed so that the height position of the upper surface is higher than the height position of one surface of the semiconductor substrate continuously throughout the entire concavo-convex structure and also in the trench region. After forming the silicon layer, the first semiconductor layer, the second semiconductor layer, and the second semiconductor layer are introduced by introducing a first conductivity type impurity or a second conductivity type impurity into predetermined regions of the polysilicon layer along the outer edge of the gate pad portion, respectively. In order to include a Zener diode forming step of forming a Zener diode having a third semiconductor layer, in the manufactured semiconductor device, not only from the height position of one surface of the semiconductor substrate to the upper surface of each semiconductor layer, A pn junction of a Zener diode is also formed in the trench. Therefore, even when the planar area occupied by the Zener diode in the semiconductor device is smaller than the conventional area, the pn junction area of the Zener diode is not smaller than the conventional area, so that the amount of current flowing through the Zener diode is difficult to be reduced. When static electricity occurs, the voltage applied to the gate insulating layer is difficult to increase. As a result, it is possible to manufacture a semiconductor device in which the ESD resistance is less likely to be smaller than that in the past even when the planar area occupied by the Zener diode in the semiconductor device is smaller than that in the past.

  Further, according to the method for manufacturing a semiconductor device of the present invention, in the Zener diode forming step, after forming a polysilicon layer in which impurities are easily diffused, the first conductivity type impurity or the predetermined region in the polysilicon layer is formed. Since the second conductivity type impurity is introduced, the first conductivity type impurity or the second conductivity type impurity can be diffused to the vicinity of the bottom of the trench, and the pn junction surface of the Zener diode is also formed at the bottom of the trench. be able to.

1 is a diagram for explaining a semiconductor device 100 according to a first embodiment. 1A is a plan view of the semiconductor device 100, FIG. 1B is an enlarged view of a region surrounded by a broken line in FIG. 1A, and FIG. 1C is a plan view of FIG. It is CC sectional drawing, FIG.1 (d) is AA sectional drawing of Fig.1 (a). In FIG. 1, the unevenness on the upper surfaces of the source electrode layer 128 and the gate pad electrode layer 140 is not shown (the same applies to FIGS. 2, 6 to 8, and FIGS. 10 to 12). In addition, the field insulating layer 138 and the interlayer insulating layer 142 are formed by stacking a plurality of insulating layers. However, in order to simplify the description, the insulating layers are collectively illustrated without being distinguished (hereinafter, FIG. 2 to 8 and FIGS. 10 to 12). FIG. 3 is a diagram for explaining a main part of the semiconductor device 100 according to the first embodiment. 2A is a schematic perspective view of the BB cross section of FIG. 1B, and FIG. 2B is a CC cross sectional view of FIG. 1B (cross section of the trench region 162). 2C is a sectional view taken along the line DD of FIG. 1B (a sectional view of the non-trench region 164). In FIG. 2, the illustration of the internal structure of the semiconductor substrate is omitted. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment. 3A-1 to 3D-1 and FIGS. 3A-2 to 3D-2 are process diagrams. 3A-1 to 3D-1 are cross-sectional views of the concavo-convex structure 160 (trench region 162) in each process, and FIGS. 3A-2 to 3D-2. These are sectional views of cell part R1 in each process. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIGS. 4A-1 to 4C-1 and FIGS. 4A-2 to 4C-2 are process diagrams. 4 (a-1) to 4 (c-1) are cross-sectional views of the concavo-convex structure 160 (trench region 162) in each step, and FIGS. 4 (a-2) to 4 (c-2). These are sectional views of cell part R1 in each process. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. 5A-1 to FIG. 5C-1 and FIG. 5A-2 to FIG. 5C-2 are process diagrams. 5 (a-1) to 5 (c-1) are cross-sectional views of the concavo-convex structure 160 (trench region 162) in each step, and FIGS. 5 (a-2) to 5 (c-2). These are sectional views of cell part R1 in each process. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIGS. 6A-1 to 6C-1 and FIGS. 6A-2 to 6C-2 are process diagrams. 6 (a-1) to 6 (c-1) are cross-sectional views of the concavo-convex structure 160 (trench region 162) in each step, and FIGS. 6 (a-2) to 6 (c-2). These are sectional views of cell part R1 in each process. FIG. 6 is an enlarged cross-sectional view of a main part in a semiconductor device 101 according to a second embodiment. In FIG. 7, the internal structure of the semiconductor substrate is not shown. FIG. 6 is a diagram for explaining a semiconductor device 102 according to a third embodiment. 8A is a cross-sectional view showing the Zener diode 150 in the semiconductor device 102, and FIG. 8B is a cross-sectional view showing the cell portion R1 in the semiconductor device 102. 10 is a plan view for explaining a semiconductor device 103 according to Modification 1. FIG. FIG. 11 is a diagram for illustrating a main part of a semiconductor device 104 according to Modification 2. FIG. 10A is a cross-sectional view showing the trench region 162 in the semiconductor device 104, and FIG. 10B is a cross-sectional view showing the non-trench region 164 in the semiconductor device 104. In FIG. 10, the illustration of the internal structure of the semiconductor substrate is omitted. FIG. 11 is a diagram for explaining a semiconductor device 105 according to Modification 3. 11A is a cross-sectional view showing the Zener diode 150 in the semiconductor device 105, and FIG. 11B is a cross-sectional view showing the cell portion R1 in the semiconductor device 105. FIG. 10 is a view for explaining a semiconductor device 106 according to Modification 4; 12A is a cross-sectional view showing the Zener diode 150 in the semiconductor device 106, and FIG. 12B is a cross-sectional view showing the cell portion R1 in the semiconductor device 106. It is a figure shown in order to demonstrate the conventional semiconductor device 900. 13A is a plan view of the semiconductor device 900, and FIG. 13B is a cross-sectional view taken along the line AA in FIG. 13A. In FIG. 13, reference numeral 912 indicates a low resistance semiconductor layer, reference numeral 914 indicates a drift layer, reference numeral 936 indicates a conductor layer, reference numeral 938 indicates a field insulating layer, and reference numerals 942 and 980 indicate interlayer insulating layers. , 972 indicates a base region, 974 indicates an n-type diffusion region, 976 indicates a gate insulating layer, and 978 indicates a gate electrode layer.

  Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device of the present invention will be described based on embodiments shown in the drawings.

[Embodiment 1]
1. Configuration of Semiconductor Device 100 According to Embodiment 1 A semiconductor device 100 according to Embodiment 1 has a source electrode layer 128 (first electrode layer) formed on one surface of a semiconductor substrate 110, as shown in FIG. A cell portion R1 and a gate pad portion R2 having a gate pad electrode layer 140 formed on one surface of the semiconductor substrate 110 are provided, and the source electrode layer 128 and the gate pad electrode layer 140 are connected via a Zener diode 150. ing.

  As illustrated in FIG. 1A, the semiconductor device 100 according to the first embodiment further includes a gate finger 144 formed at a position surrounding the cell portion R1. The gate finger 144 is connected to the gate pad electrode layer 140.

  As shown in FIG. 1D, the cell portion R1 includes a first conductivity type (n-type) low-resistance semiconductor layer 112, an n-type drift layer 114 formed on the low-resistance semiconductor layer 112, a drift A second conductivity type (p-type) base region 116 formed on the surface of the layer 114; a plurality of gate trenches 118 formed by opening the base region 116 and reaching the drift layer 114; An n-type diffusion region (source region 120) formed and partially exposed to the inner peripheral surface of the gate trench 118; and a gate insulating layer 122 formed on the inner peripheral surface of the gate trench 118; The gate electrode layer 124 filled in the gate trench 118 through the gate insulating layer 122 and the source region 1 in a state where the gate electrode layer 124 is insulated through the interlayer insulating layer 126. 0 and has a source electrode layer 128 are formed on the surfaces of the base region 116, and a drain electrode layer 130 formed on the surface of the low-resistance semiconductor layer 112. The depth of the gate trench 118 is, for example, 1.2 μm.

  As shown in FIG. 1A, the gate pad portion R2 is formed in a state of protruding from the outer edge of the cell portion R1 to the cell portion R1 side. The shape of the gate pad portion R2 is a quadrangular shape. As shown in FIG. 1C, the gate pad portion R2 includes a low-resistance semiconductor layer 112, a drift layer 114 formed on the low-resistance semiconductor layer 112, and a p-type diffusion formed on the surface of the drift layer 114. A region 134, a conductor layer 136 formed over the drift layer 114 via the field insulating layer 138, an interlayer insulating layer 142 formed over the conductor layer 136, and the gate electrode layer 124 And a gate pad electrode layer 140 connected to each other.

  The gate electrode layer 124, the conductor layer 136, and conductor layers 135 and 137 described later are formed by introducing n-type impurities into polysilicon. The source electrode layer 128, the gate pad electrode layer 140, and the gate finger 144 are all made of metal (for example, aluminum).

  In the semiconductor device 100 according to the first embodiment, as shown in FIGS. 1B and 2, the trenches 166 are formed in the semiconductor substrate 110 at a predetermined pitch along a direction perpendicular to the outer edge of the gate pad portion R <b> 2. The semiconductor device 100 according to the first embodiment is formed in a separated state. The trench region 162 in which the trench 166 is formed (see FIG. 2B) and the non-trench region in which the trench 166 is not formed. 164 (see FIG. 2C) has a concavo-convex structure 160 formed alternately along the outer edge of the gate pad portion R2. An insulating layer 168 is formed on the surface of the uneven structure 160.

  The width of the trench region 162 (the width of the trench 166) is, for example, in the range of 0.3 μm to 0.7 μm. Note that the above range is a range of the width of the trench region 162 when the insulating layer 168 is not formed.

  The width of the non-trench region 164 (the interval between adjacent trenches 166) is preferably shorter, for example, shorter than the width of the trench region 162.

  The depth of the trench 166 (the depth from the height position of one surface of the semiconductor substrate 110 to the bottom of the trench 166) can be set to an appropriate depth that is not filled with the insulating layer 168. It exists in the range of 5 micrometers-2 micrometers, Preferably it exists in the range of 1.0 micrometer-1.5 micrometers, for example, is 1.2 micrometers.

  As shown in FIG. 1A, the Zener diode 150 is formed along the outer edge of the gate pad portion R2. Specifically, the gate pad portion R2 is formed in a region corresponding to two sides of the rectangular shape constituting the outer edge, and the Zener diode is formed in a region corresponding to four sides of the rectangular shape. Compared to the conventional semiconductor device 900 (see FIG. 13A), the planar area occupied by the Zener diode 150 in the semiconductor device is smaller.

  As shown in FIG. 1C, the Zener diode 150 is formed on the p-type diffusion region 134 with an insulating layer 168 interposed therebetween.

  As shown in FIGS. 1B and 1C, the Zener diode 150 is formed along the outer edge of the gate pad portion R2, and is electrically connected to the source electrode layer 128 through the conductor layer 135. The n-type first semiconductor layer 151 and the gate pad electrode layer formed along the outer edge of the gate pad portion R2 and on the gate pad portion R2 side of the first semiconductor layer 151 via the conductor layer 137 140 includes an n-type second semiconductor layer 152 electrically connected to the semiconductor layer 140, and a p-type third semiconductor layer 153 formed between the first semiconductor layer 151 and the second semiconductor layer 152. The Zener diode 150 is formed between the third semiconductor layer 153 and the second semiconductor layer 152 on the n-type fourth semiconductor layer 154 and the second semiconductor layer 152 side formed on the third semiconductor layer 153 side. One set of the p-type fifth semiconductor layer 155 is formed along a direction perpendicular to the outer edge of the gate pad portion R2.

  That is, the Zener diode 150 includes an n-type first semiconductor layer 151, a p-type third semiconductor layer 153, an n-type fourth semiconductor layer 154, and a p-type from the cell part R1 side to the gate pad part R2 side. The fifth semiconductor layer 155 and the n-type second semiconductor layer 152 are arranged in the order of the so-called npnpn structure Zener diode.

  As shown in FIG. 2, the first semiconductor layer 151, the second semiconductor layer 152, the third semiconductor layer 153, the fourth semiconductor layer 154, and the fifth semiconductor layer 155 are continuously formed over the entire concavo-convex structure 160. . Therefore, the area of the pn junction surface of the Zener diode 150 is larger than the junction area of the pn junction surface of the Zener diode when there is no trench. The height positions of the top surfaces of the first semiconductor layer 151, the second semiconductor layer 152, the third semiconductor layer 153, the fourth semiconductor layer 154, and the fifth semiconductor layer 155 are not only in the non-trench region 164, The trench region 162 is also higher than the height position of one surface of the semiconductor substrate 110.

  The length from the height position of one surface of the semiconductor substrate 110 to the height position of the bottom of the trench 166 is the first semiconductor layer 151, the first semiconductor layer 151 from the height position of one surface of the semiconductor substrate 110 in the trench region 162. 2 semiconductor layer 152, third semiconductor layer 153, fourth semiconductor layer 154, or length to the height position of the upper surface of fifth semiconductor layer 155, and height of one surface of semiconductor substrate 110 in non-trench region 164 It is longer than any of the lengths from the position to the height position of the upper surface of the first semiconductor layer 151, the second semiconductor layer 152, the third semiconductor layer 153, the fourth semiconductor layer 154, or the fifth semiconductor layer 155.

  The gate electrode layer 124, the conductor layers 135, 136, and 137, the first semiconductor layer 151, the second semiconductor layer 152, the third semiconductor layer 153, the fourth semiconductor layer 154, and the fifth semiconductor layer 155 are collectively formed. Each of the polysilicon layers (polysilicon layer 150 ′ described later) is formed by introducing n-type impurities or p-type impurities into predetermined regions.

2. Method for Manufacturing Semiconductor Device According to First Embodiment Next, a method for manufacturing the semiconductor device 100 according to the first embodiment (a method for manufacturing a semiconductor device according to the first embodiment) will be described along each step.

(1) Preparation Step of Semiconductor Base 110 First, a semiconductor base 110 is prepared in which an n-type low-resistance semiconductor layer 112 and an n-type drift layer 114 having a lower concentration than the low-resistance semiconductor layer 112 are stacked (FIG. 3 ( a-1) and FIG. 3 (a-2).)

(2) Step of forming p-type diffusion region 134 Next, a mask (not shown) having an opening in a region corresponding to the p-type diffusion region 134 is formed, and p-type impurities (for example, boron) are passed through the mask. Ion implantation is performed to introduce a p-type impurity into a region corresponding to the p-type diffusion region 134.

  Next, after removing the mask, the semiconductor substrate 110 is heat-treated in an oxygen gas-containing atmosphere to perform a p-type impurity diffusion annealing process to form a p-type diffusion region 134. At this time, the surfaces of the drift layer 114 and the p-type diffusion region 134 are thermally oxidized, and the field insulating layer 138 is formed. Next, the field insulating layer 138 in the entire region of the cell portion R1 and a predetermined region of the gate pad portion R2 is removed by etching (see FIGS. 3B-1 and 3B-2).

(3) Step of Forming Gate Trench 118 and Uneven Structure 160 Next, a trench 166 is formed in the semiconductor substrate 110 along the direction perpendicular to the outer edge of the region where the gate pad portion R2 is to be formed. Thus, the concavo-convex structure 160 is formed in which the trench regions 162 in which the trenches 166 are formed and the non-trench regions 164 in which the trenches 166 are not formed are alternately formed along the outer edge of the gate pad portion R2.

  Specifically, first, a mask M1 having an opening in a region corresponding to a region where the gate trench 118 and the trench 166 are formed is formed. Next, the drift layer 114 and the p-type diffusion region 134 are opened by an etching method using the mask M1, thereby forming the gate trench 118 and the trench 166 (see FIGS. 3C-1 and 3C-2). .)

  Next, the mask M1 is removed, and the surface of the drift layer 114 and the p-type diffusion region 134 is thermally oxidized by performing a heat treatment of the semiconductor substrate 110 in an oxygen gas-containing atmosphere, so that the gate insulating layer 122 is formed in the cell portion R1. And an insulating layer 168 is formed in the gate pad portion R2 (see FIGS. 3D-1 and 3D-2).

(4) Step of Forming Gate Electrode Layer 124 and Conductor Layer 136 Next, the first main surface side (one surface) so that the inside of the gate trench 118 and the trench 166 of the semiconductor substrate 110 can be completely filled with polysilicon. A polysilicon layer 150 ′ is formed on the entire surface of the side by a deposition method (CVD method, sputtering method, etc.) (see FIGS. 4A-1 and 4A-2). At this time, the polysilicon layer 150 ′ is continuous over the entire concavo-convex structure 160, and in the trench region 162, as in the case of the non-trench region 164, the height position of the upper surface is one of the semiconductor substrates 110. It becomes higher than the height position of the surface.

(5) Step of forming source region 120, base region 116, and Zener diode 150 Next, after forming a mask M2 in a region where the Zener diode 150 is to be formed, an n-type impurity (for example, phosphorus) is introduced over the entire surface ( (Refer FIG.4 (b-1) and FIG.4 (b-2).). Next, after removing the mask M2, the semiconductor substrate 110 is heat-treated in an oxygen gas-containing atmosphere to perform an n-type impurity activation annealing process to form the gate electrode layer 124 and the conductor layer 136 ′. (See FIGS. 4 (c-1) and 4 (c-2).)

  Next, a mask M3 is formed in which regions corresponding to all the regions of the cell portion R1 and regions corresponding to predetermined regions of the gate pad portion R2 are opened. Next, the gate electrode layer 124 is etched back by an etching method using the mask M3, and a predetermined region of the conductor layer 136 ′ is opened (see FIGS. 5A-1 and 5A-2). Thus, the conductor layers 135, 136, and 137 are obtained.

  Next, after removing the mask M3, the semiconductor substrate 110 is subjected to thermal oxidation, whereby impurities on the surfaces of the conductor layers 135, 136, 137, the polysilicon layer 150 ′, and the gate electrode layer 124 are formed in a subsequent process. An insulating layer 139 for preventing the out diffusion (outward diffusion) is formed.

  Next, p-type impurities are introduced throughout the cell portion R1 and the gate pad portion R2 (see FIGS. 5B-1 and 5B-2). Next, a base region 116 is formed by performing activation annealing of p-type impurities in an oxygen gas-containing atmosphere. At this time, the polysilicon layer 150 ′ is in a state where a p-type impurity is introduced (polysilicon layer 150 ″).

  Next, a mask M4 having an opening in a region corresponding to the source region 120, the first semiconductor layer 151, the second semiconductor layer 152, and the fourth semiconductor layer 154 is formed, and the source region 120 and the first semiconductor are formed using the mask M4. An n-type impurity is introduced into regions corresponding to the layer 151, the second semiconductor layer 152, and the fourth semiconductor layer 154 (see FIGS. 5C-1 and 5C-2).

  Next, after removing the mask M4, the semiconductor substrate 110 is heat-treated in an oxygen gas-containing atmosphere to perform activation annealing of the n-type impurity, thereby performing the source region 120 and the first semiconductor layer 151 of the Zener diode 150. Then, the second semiconductor layer 152 and the fourth semiconductor layer 154 are formed. At this time, portions of the polysilicon layer 150 ′ into which the n-type impurity is not introduced become the third semiconductor layer 153 and the fifth semiconductor layer 155 (FIGS. 6A-1 and 6A-2). reference.).

(6) Formation Step of Interlayer Insulating Layers 126, 142 Next, an insulating layer made of PSG having a thickness of 1000 nm, for example, is formed on the entire surface of the first main surface side of the semiconductor substrate 110 by the CVD method. Next, in the cell portion R1, a portion other than the portion to be the interlayer insulating layer 126, and in the gate pad portion R2, the conductor layer 135 connected to the first semiconductor layer 151 and the source electrode layer 128 are in contact. Masks having openings respectively in a portion where the conductor layer 137 connected to the gate pad electrode layer 140 is in contact with the second semiconductor layer 152 and a portion where the conductor layer 136 is in contact with the gate pad electrode layer 140 (FIG. And an insulating layer is opened by an etching method using the mask (see FIGS. 6B-1 and 6B-2). Thereby, the interlayer insulating layers 126 and 142 are formed.

(7) Step of Forming Source Electrode Layer 128 and Gate Pad Electrode Layer 140 Next, a metal layer made of aluminum is formed from above the surface on the first main surface side of the semiconductor substrate 110 by sputtering or vapor deposition. Next, the metal layer in a region other than the region to be the source electrode layer 128, the gate pad electrode layer 140, and the gate finger 144 is removed by an etching method to form the source electrode layer 128, the gate pad electrode layer 140, and the gate finger 144. To do. The thicknesses of the source electrode layer 128, the gate pad electrode layer 140, and the gate finger 144 are, for example, 4 μm.

  Next, a drain electrode layer 130 is formed by forming a metal film made of a multilayer metal film such as Ti—Ni—Au on the second main surface side surface of the semiconductor substrate 110 (the surface of the low resistance semiconductor layer 112). (See FIGS. 6 (c-1) and 6 (c-2).)

  By performing the above steps, the semiconductor device 100 according to the first embodiment can be manufactured.

3. Effects of Semiconductor Device 100 and Semiconductor Device Manufacturing Method According to First Embodiment According to the semiconductor device 100 according to the first embodiment, the first semiconductor layer 151, the second semiconductor layer 152, the third semiconductor layer 153 (and the fourth semiconductor) The first semiconductor layer 151, the second semiconductor layer 152, and the third semiconductor layer 153 (and the fourth semiconductor layer 154 and the fifth semiconductor layer 155). Since the height position of the upper surface of the semiconductor layer 155) is higher than the height position of one surface of the semiconductor substrate 110 also in the trench region 162, the first semiconductor layer 151 starts from the height position of one surface of the semiconductor substrate 110. , Trenches as well as between the second semiconductor layer 152 and the third semiconductor layer 153 (and the fourth semiconductor layer 154 and the fifth semiconductor layer 155). Also so that the pn junction is formed in 66. Therefore, even when the planar area occupied by the Zener diode 150 in the semiconductor device is smaller than the conventional area, the pn junction area of the Zener diode 150 is not smaller than the conventional area, so that the amount of current flowing through the Zener diode 150 is small. It is difficult to increase the voltage applied to the gate insulating layer 122 when static electricity is generated. As a result, the semiconductor device 100 according to the first embodiment is a semiconductor device in which the ESD tolerance is less likely to be smaller than that in the past even when the planar area occupied by the Zener diode 150 in the semiconductor device is smaller than that in the past.

  Further, according to the semiconductor device 100 according to the first embodiment, the length from the height position of one surface of the semiconductor substrate 110 to the height position of the bottom of the trench 166 is one of the semiconductor substrates 110 in the trench region 162. From the surface height position of the first semiconductor layer 151 to the height position of the top surface of the first semiconductor layer 151, the second semiconductor layer 152, and the third semiconductor layer 153, and the length of one surface of the semiconductor substrate 110 in the non-trench region 164 Since the length from the height position to the height position of the top surface of each of the first semiconductor layer 151, the second semiconductor layer 152, and the third semiconductor layer 153 is longer, the flatness occupied by the Zener diode 150 in the semiconductor device is longer. Even when the area is made smaller than before, the pn junction area of the Zener diode 150 does not become smaller than before. Hardly the amount of current flowing through the de-150 is reliably reduced, the voltage applied to the gate insulating layer 122 is hardly becomes reliably high when the static electricity is generated.

  In addition, according to the semiconductor device 100 according to the first embodiment, the n-type fourth semiconductor layer 154 and the fourth semiconductor layer 154 formed on the third semiconductor layer 153 side between the third semiconductor layer 153 and the second semiconductor layer 152. 2 Since a pair of p-type fifth semiconductor layers 155 formed on the semiconductor layer 152 side is formed along a direction perpendicular to the outer edge of the gate pad portion R2, the Zener diode is of npnpn type. A Zener diode is formed, and the Zener diode can have a higher Zener voltage than an npn-type Zener diode.

  Further, according to the semiconductor device 100 according to the first embodiment, the length from the height position of one surface of the semiconductor substrate 110 to the height position of the bottom of the trench 166 is one of the semiconductor substrates 110 in the trench region 162. The length from the height position of the surface of the semiconductor substrate 110 to the height position of the upper surface of the fourth semiconductor layer 154 and the fifth semiconductor layer 155 and the height position of one surface of the semiconductor substrate 110 in the non-trench region 164 to the fourth height. Since the length of the upper surface of the semiconductor layer 154 and the fifth semiconductor layer 155 is longer than both, the plane area occupied by the Zener diode 150 in the semiconductor device is much smaller than in the past. However, since the pn junction area of the Zener diode 150 is not smaller than the conventional one, the amount of current flowing through the Zener diode 150 is more reliably small. Hardly, voltage applied to the gate insulating layer 122 is less likely be more reliably high when the static electricity is generated.

  In addition, according to the semiconductor device 100 according to the first embodiment, since the width of the trench 166 is in the range of 0.3 μm to 0.7 μm, in the process of forming the Zener diode 150, the trench 166 reaches the deepest portion of the trench 166. Silicon can be filled, and the entire trench 166 can be filled with polysilicon.

  Here, the width of the trench 166 (the width of the trench region 162) is set to 0.3 μm or more. When the width of the trench 166 (the width of the trench region 162) is less than 0.3 μm, the Zener diode 150 is changed. This is because it is difficult to fill polysilicon into the deepest portion of the trench 166 in the process of forming, and the width of the trench 166 (the width of the trench region 162) is set to 0.7 μm or less. This is because it is difficult to fill the entire trench 166 with polysilicon when the width of the region 162 exceeds 0.7 μm. From this viewpoint, the width of the trench 166 (the width of the trench region 162) is preferably in the range of 0.6 μm to 0.65 μm.

  Further, according to the semiconductor device 100 according to the first embodiment, since the depth of the trench 166 and the depth of the gate trench 118 are the same, the trench 166 and the gate trench 118 can be formed at a time. Therefore, a semiconductor device with high productivity can be obtained as compared with the case where the trench 166 and the gate trench 118 are formed in separate steps.

  Also, according to the semiconductor device 100 according to the first embodiment, the gate electrode layer 124, the first semiconductor layer 151, the second semiconductor layer 152, the third semiconductor layer 153, the fourth semiconductor layer 154, the fifth semiconductor layer 155, and the conductive The body layers 135, 136, and 137 are formed by introducing n-type impurities or p-type impurities into predetermined regions of the polysilicon layer 150 ′ formed in a lump, so that the polysilicon layer 150 is formed. Compared with the case where 'is formed in a separate process, a semiconductor device with higher productivity is obtained.

  According to the method for manufacturing a semiconductor device according to the first embodiment, the height position of the upper surface is higher than the height position of one surface of the semiconductor substrate 110 continuously throughout the entire concavo-convex structure 160 and also in the trench region 162. After the polysilicon layer 150 ′ is formed so as to be higher, n-type impurities or p-type impurities are respectively introduced into predetermined regions of the polysilicon layer 150 ′ along the outer edge of the gate pad portion R2. In the manufactured semiconductor device, the semiconductor device includes a Zener diode forming step of forming the Zener diode 150 having the layer 151, the second semiconductor layer 152, and the third semiconductor layer 153 (and the fourth semiconductor layer 154 and the fifth semiconductor layer 155). The first semiconductor layer 151, the second semiconductor layer 152, and the third semiconductor layer from the height position of one surface of the semiconductor substrate 110. 53 but only until the upper surface of the (as well as the fourth semiconductor layer 154 and the fifth semiconductor layer 155), it is possible to pn junction of the Zener diode 150 is formed in the trench 166. Therefore, even when the planar area occupied by the Zener diode 150 in the semiconductor device is smaller than the conventional area, the pn junction area of the Zener diode 150 is not smaller than the conventional area, so that the amount of current flowing through the Zener diode 150 is small. It is difficult to increase the voltage applied to the gate insulating layer 122 when static electricity is generated. As a result, even when the planar area occupied by the Zener diode 150 in the semiconductor device is smaller than that in the conventional case, the ESD resistance is less likely to be smaller than that in the conventional device, and the semiconductor device can be manufactured.

  In addition, according to the method for manufacturing a semiconductor device according to the first embodiment, in the Zener diode formation step, after forming the polysilicon layer 150 ′ that easily diffuses impurities, each of the predetermined regions of the polysilicon layer 150 ′ is formed. Since the n-type impurity or the p-type impurity is introduced, the n-type impurity or the p-type impurity can be diffused to the vicinity of the bottom of the trench 166, and the pn junction surface of the Zener diode 150 is also formed at the bottom of the trench 166. can do.

[Embodiment 2]
The semiconductor device 101 according to the second embodiment basically has the same configuration as that of the semiconductor device 100 according to the first embodiment. However, the semiconductor device 100 according to the first embodiment is that the Zener diode is a Zener diode having an npnpnpn structure. It is different from the case of. That is, the Zener diode 150a in the semiconductor device 101 according to the second embodiment is formed on the third semiconductor layer 153 side between the third semiconductor layer 153 and the second semiconductor layer 152, as shown in FIG. Two sets of the n-type fourth semiconductor layer and the p-type fifth semiconductor layer formed on the second semiconductor layer 152 side are formed along the direction perpendicular to the outer edge of the gate pad portion R2. Therefore, in the semiconductor device 101 according to the second embodiment, the Zener diode 150a includes the first semiconductor layer 151, the third semiconductor layer 153, the fourth semiconductor layer 154, from the cell part R1 side to the gate pad part R2 side. The fifth semiconductor layer 155, the sixth semiconductor layer 156 (second set of fourth semiconductor layers), the seventh semiconductor layer 157 (second set of fifth semiconductor layers), and the second semiconductor layer 152 are arranged in this order. .

  As described above, the semiconductor device 101 according to the second embodiment differs from the semiconductor device 100 according to the first embodiment in that the Zener diode is a Zener diode having an npnpnpn structure, but the first semiconductor layer 151 and the second semiconductor layer The layer 152, the third semiconductor layer 153, the fourth semiconductor layer 154, the fifth semiconductor layer 155, the sixth semiconductor layer 156, and the seventh semiconductor layer 157 are continuously formed over the entire uneven structure 160, and the first semiconductor layer 151, the height positions of the top surfaces of the second semiconductor layer 152 and the third semiconductor layer 153, the fourth semiconductor layer 154, the fifth semiconductor layer 155, the sixth semiconductor layer 156, and the seventh semiconductor layer 157 also in the trench region 162. Since the height position of one surface of the semiconductor substrate 110 is higher, the first semiconductor layer 151 starts from the height position of one surface of the semiconductor substrate 110. Not only between the second semiconductor layer 152, the third semiconductor layer 153, the fourth semiconductor layer 154, the fifth semiconductor layer 155, the sixth semiconductor layer 156, and the seventh semiconductor layer 157, but also in the trench 166 pn A bond will be formed. Therefore, even if the planar area occupied by the Zener diode 150a in the semiconductor device is smaller than the conventional area, the pn junction area of the Zener diode 150a does not have to be smaller than the conventional area, so that the Zener diode 150a flows. The amount of current is difficult to decrease, and the voltage applied to the gate insulating layer 122 is difficult to increase when static electricity is generated. As a result, the semiconductor device 101 according to the second embodiment is a semiconductor device in which the ESD tolerance is less likely to be smaller than the conventional one even when the planar area occupied by the Zener diode 150a in the semiconductor device is smaller than the conventional one.

  In addition, according to the semiconductor device 101 according to the second embodiment, in the Zener diode 150a, the n-type first formed on the third semiconductor layer 153 side between the third semiconductor layer 153 and the second semiconductor layer 152. 4 pairs of the fourth semiconductor layer and the p-type fifth semiconductor layer formed on the second semiconductor layer 152 side are arranged in two sets (the fourth semiconductor layer 154 and the fifth semiconductor layer 154 along the direction perpendicular to the outer edge of the gate pad portion R2). The semiconductor layer 155 and the sixth semiconductor layer 156 and the seventh semiconductor layer 157) are formed, so that the Zener diode becomes an npnpnpn type Zener diode, and the Zener voltage can be further increased. it can.

  The semiconductor device 101 according to the second embodiment has the same configuration as that of the semiconductor device 100 according to the first embodiment except that the Zener diode is a Zener diode having an npnpnpn structure. The device 100 has a corresponding effect among the effects of the device 100.

[Embodiment 3]
The semiconductor device 102 according to the third embodiment basically has the same configuration as that of the semiconductor device 100 according to the first embodiment, but the semiconductor device according to the first embodiment is not a trench type semiconductor device but a planar type semiconductor device. Different from the case of the apparatus 100. That is, the semiconductor device 102 according to the third embodiment includes a planar semiconductor device having a gate electrode layer 178 formed on the semiconductor substrate 110 via the gate insulating layer 176, as shown in FIG. It is.

  In the semiconductor device 102 according to the third embodiment, the cell unit R1 includes a low resistance semiconductor layer 112, a drift layer 114 formed on the low resistance semiconductor layer 112, and a p-type base formed on the surface of the drift layer 114. The gate formed on the region 172, the n-type diffusion region 174 formed on the surface of the base region 172, and the base region 172 sandwiched between the n-type diffusion region 174 and the drift layer 114 via the gate insulating layer 176 A source electrode layer 128 formed in contact with the surfaces of the n-type diffusion region 174 and the base region 172 in a state in which the electrode layer 178 and the gate electrode layer 178 are insulated via the interlayer insulating layer 180; and a low-resistance semiconductor layer And a drain electrode layer 130 formed on the surface of 112.

  In the semiconductor device 102 according to the third embodiment, the gate electrode layer 178 in the cell portion R1, the conductor layers 135, 136, and 137 in the gate pad portion R2, the first semiconductor layer 151, the second semiconductor layer 152, and the third semiconductor layer 153. The fourth semiconductor layer 154 and the fifth semiconductor layer 155 are formed by introducing n-type impurities or p-type impurities into predetermined regions of the polysilicon layer formed in a lump. Therefore, the thickness of the gate electrode layer 178 in the cell portion R1 is such that the first semiconductor layer 151, the second semiconductor layer 152, the third semiconductor layer 153, and the fourth semiconductor in the non-trench region 164 (see FIG. 2C). The thickness is the same as the thickness of the layer 154, the fifth semiconductor layer 155, and the conductor layers 135, 136, and 137.

  As described above, the semiconductor device 102 according to the third embodiment is different from the semiconductor device 100 according to the first embodiment in that the semiconductor device 102 is not a trench type semiconductor device but a planar type semiconductor device. The second semiconductor layer 152, the third semiconductor layer 153, the fourth semiconductor layer 154, and the fifth semiconductor layer 155 are continuously formed over the entire concavo-convex structure 160, and the first semiconductor layer 151, the second semiconductor layer 152, and the third semiconductor layer 152 are formed. Since the height positions of the upper surfaces of the semiconductor layer 153, the fourth semiconductor layer 154, and the fifth semiconductor layer 155 are higher than the height position of one surface of the semiconductor substrate 110 also in the trench region 162, the semiconductor according to the first embodiment. As in the case of the device 100, the first semiconductor layer 151, the second semiconductor layer 152, the third semiconductor layer 153, from the height position of one surface of the semiconductor substrate 110, 4 not only until the upper surface of the semiconductor layer 154 and the fifth semiconductor layer 155, so that the pn junction is also formed in the trench 166. Therefore, even when the planar area occupied by the Zener diode 150 in the semiconductor device is smaller than the conventional area, the pn junction area of the Zener diode 150 is not smaller than the conventional area, so that the amount of current flowing through the Zener diode 150 is small. It is difficult to increase the voltage applied to the gate insulating layer 176 when static electricity is generated. As a result, the semiconductor device 102 according to the third embodiment is a semiconductor device in which the ESD tolerance is less likely to be smaller than that in the past even when the planar area occupied by the Zener diode 150 in the semiconductor device is smaller than that in the past.

  In addition, according to the semiconductor device 102 according to the third embodiment, the thickness of the gate electrode layer 178 in the cell portion R1, and the first semiconductor layer 151, the second semiconductor layer 152, the third semiconductor layer 153, and the first semiconductor layer 151 in the non-trench region 164. Since the thicknesses of the fourth semiconductor layer 154, the fifth semiconductor layer 155, and the conductor layers 135, 136, and 137 are the same, the gate electrode layer 178, the first The semiconductor layer 151, the second semiconductor layer 152, the third semiconductor layer 153, the fourth semiconductor layer 154, the fifth semiconductor layer 155, and the conductor layers 135, 136, and 137 can be formed, respectively, and the polysilicon layer 150 ′ can be formed. The semiconductor device has higher productivity than the case where it is formed in a separate process.

  The semiconductor device 102 according to the third embodiment has the same configuration as that of the semiconductor device 100 according to the first embodiment except that the semiconductor device 102 is not a trench type semiconductor device but a planar type semiconductor device. The semiconductor device 100 has a corresponding effect among the effects of the semiconductor device 100.

  As mentioned above, although this invention was demonstrated based on said embodiment, this invention is not limited to said embodiment. The present invention can be implemented in various modes without departing from the spirit thereof, and for example, the following modifications are possible.

(1) The number, material, shape, position, size, and the like of the constituent elements described in the above embodiments are exemplifications, and can be changed within a range not impairing the effects of the present invention.

(2) In each of the above embodiments, the Zener diodes are formed on the two sides of the outer edge of the gate pad portion R2, but the present invention is not limited to this. A Zener diode may be formed on one side of the outer edge of the gate pad portion R2. In this case, it is possible to obtain an effect that the plane area occupied by the Zener diode in the semiconductor device can be made smaller than before.

(3) In each of the above embodiments, the Zener diode is formed on two sides of the outer edge of the gate pad portion R2, but the present invention is not limited to this. Zener diodes may be formed on three or more sides of the outer edge of the gate pad portion R2 (see the semiconductor device 103 according to Modification 1 in FIG. 9). In this case, the current capacity of the Zener diode can be increased as compared with the conventional semiconductor device, and as a result, an effect that the ESD tolerance can be increased can be obtained.

(4) In the first embodiment, one set of the fourth semiconductor layer and the fifth semiconductor layer is formed between the third semiconductor layer 153 and the second semiconductor layer 152. In the second embodiment, Although the two sets are formed, three or more sets may be formed between the third semiconductor layer 153 and the second semiconductor layer 152, or the sets may not be formed (see FIG. (See the semiconductor device 104 according to the second modification example 10). In this way, the Zener voltage can be adjusted by adjusting the number of pairs of the fourth semiconductor layer and the fifth semiconductor layer.

(5) In each of the above embodiments, a MOSFET is used as a semiconductor device, but the present invention is not limited to this. As the semiconductor device, an appropriate semiconductor device such as an IGBT (see the semiconductor device 105 according to Modification 3 in FIG. 11 and the semiconductor device 106 according to Modification 4 in FIG. 12), a thyristor, or a triac can be used. When an IGBT is used as a semiconductor device, as shown in FIGS. 11 and 12, a p-type low-resistance semiconductor layer 112a is provided instead of an n-type low-resistance semiconductor layer, and an emitter electrode is used instead of a source electrode layer. A layer 128a is provided, and a collector electrode layer 130a is provided instead of the drain electrode layer.

(6) In Embodiments 1 and 2 and Modifications 2 and 3, the trench 166 and the gate trench 118 are formed together, but the trench 166 and the gate trench 118 may be formed separately.

(7) In Embodiments 1 and 2 and Modifications 2 and 3, the depth of the trench 166 and the depth of the gate trench 118 are the same, but the depth of the trench 166 and the depth of the gate trench 118 are different. The depth may be any.

  100, 101, 102, 103, 104, 105, 106 ... semiconductor device, 110, 110a ... semiconductor substrate, 112, 112a ... low resistance semiconductor layer, 114 ... drift layer, 116, 172 ... base region, 118 ... gate trench, 120, 174 ... n-type diffusion region (source region, emitter region), 122, 176 ... gate insulating layer, 124, 178 ... gate electrode layer, 128 ... source electrode layer, 128a ... emitter electrode layer, 130 ... drain electrode layer, 130a ... collector electrode layer, 134 ... p-type diffusion region, 135, 136, 137 ... conductor layer, 138 ... field insulating layer, 139, 168 ... insulating layer, 140 ... gate pad electrode layer, 126, 142, 180 ... interlayer Insulating layer, 144... Gate finger, 150, 150a, 150b, 150c... Zener die 150 ′... Polysilicon layer, 150 ″... Polysilicon layer (with p-type impurity introduced), 151 and 151b... First semiconductor layer, 152 and 152b... Second semiconductor layer, 153 and 153b. 3 semiconductor layers, 154, 154b ... fourth semiconductor layer, 155, 155b ... fifth semiconductor layer, 156 ... sixth semiconductor layer, 157 ... seventh semiconductor layer, 160 ... uneven structure, 162 ... trench region, 164 ... non-trench Region, 166 ... trench, R1 ... cell part, R2 ... gate pad part

Claims (7)

A cell portion having a first electrode layer formed on one surface of the semiconductor substrate;
A gate pad portion having a gate pad electrode layer formed on one surface of the semiconductor substrate,
A first semiconductor layer of a first conductivity type formed along an outer edge of the gate pad portion and electrically connected to the first electrode layer on at least a part of the outer edge of the gate pad portion; A second semiconductor layer of a first conductivity type formed along the outer edge of the gate pad portion and on the gate pad portion side of the first semiconductor layer and electrically connected to the gate pad electrode layer; A Zener diode having a second conductivity type third semiconductor layer formed between the first semiconductor layer and the second semiconductor layer is formed;
The first electrode layer and the gate pad electrode layer are connected via the Zener diode,
In the semiconductor device, a trench region in which a trench is formed in the semiconductor substrate along a direction perpendicular to an outer edge of the gate pad portion, and a non-trench region in which the trench is not formed are outer edges of the gate pad portion. Having a concavo-convex structure formed alternately along
The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are formed continuously over the entire concavo-convex structure,
A semiconductor device is manufactured in which the height positions of the upper surfaces of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are higher than the height position of one surface of the semiconductor substrate also in the trench region. A method of manufacturing a semiconductor device for
The trench is formed by forming the trench in the semiconductor substrate along a direction perpendicular to an outer edge of a region where the gate pad portion is to be formed on at least a part of an outer edge of the gate pad portion. A concavo-convex structure forming step for forming the concavo-convex structure in which the trench region and the non-trench region where the trench is not formed are alternately formed along the outer edge of the gate pad portion;
After forming the polysilicon layer so that the height position of the upper surface is higher than the height position of one surface of the semiconductor substrate, continuously over the entire concavo-convex structure and also in the trench region, The first semiconductor layer, the second semiconductor layer, and the third semiconductor are introduced by introducing a first conductivity type impurity or a second conductivity type impurity into predetermined regions of the polysilicon layer along the outer edge of the gate pad portion, respectively. A zener diode forming step of forming the zener diode having a layer in this order,
The gate electrode layer, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer that are formed in the cell portion are each formed with a first conductivity type impurity or a second impurity in the polysilicon layer that is collectively formed. A method for manufacturing a semiconductor device, wherein the semiconductor device is formed by introducing conductive impurities. In the manufacturing method of the semiconductor device according to claim 1 ,
The length from the height position of one surface of the semiconductor substrate to the height position of the bottommost portion of the trench is from the height position of one surface of the semiconductor substrate in the trench region to the first semiconductor layer, The first semiconductor layer and the second semiconductor from the length to the height position of the upper surface of the second semiconductor layer and the third semiconductor layer and the height position of one surface of the semiconductor substrate in the non-trench region A method of manufacturing a semiconductor device, characterized in that it is longer than both the layer and the length to the height position of the upper surface of the third semiconductor layer. In the manufacturing method of the semiconductor device according to claim 1 or 2 ,
In the Zener diode, the first conductive type fourth semiconductor layer formed on the third semiconductor layer side and the second semiconductor layer side are formed between the third semiconductor layer and the second semiconductor layer. A method for manufacturing a semiconductor device, wherein at least one set of the second conductive type fifth semiconductor layers is formed along a direction perpendicular to the outer edge of the gate pad portion. In the manufacturing method of the semiconductor device according to claim 3 ,
The length from the height position of one surface of the semiconductor substrate to the height position of the bottom of the trench is from the height position of one surface of the semiconductor substrate in the trench region to the fourth semiconductor layer and the The length to the height position of the upper surface of the fifth semiconductor layer and the height of the upper surfaces of the fourth semiconductor layer and the fifth semiconductor layer from the height position of one surface of the semiconductor substrate in the non-trench region A method for manufacturing a semiconductor device, characterized by being longer than either of the lengths to the position. In the manufacturing method of the semiconductor device in any one of Claims 1-4 ,
The width of the trench is in the range of 0.3 μm to 0.7 μm. In the manufacturing method of the semiconductor device in any one of Claims 1-5 ,
The semiconductor device is a trench type semiconductor device having a gate electrode layer embedded in a gate trench formed on one surface of the semiconductor substrate through a gate insulating layer in the cell portion,
The method of manufacturing a semiconductor device, wherein the depth of the trench and the depth of the gate trench are the same. In the manufacturing method of the semiconductor device in any one of Claims 1-5 ,
The semiconductor device is a planar type semiconductor device having a gate electrode layer formed on the semiconductor substrate via a gate insulating layer in the cell portion,
The method of manufacturing a semiconductor device, wherein the thickness of the gate electrode layer in the cell portion is the same as the thickness of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the non-trench region. .

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