JP6451499B2 - Amplifier and amplifier control method - Google Patents

Description

  The present invention relates to an amplifier and a method for controlling the amplifier.

  An RF power amplifier system having an RF source, a DC voltage source, a bridge circuit, and a switch driver is known (see Patent Document 1). The RF source provides a train of RF pulses where each pulse has a fixed amplitude and duration and exhibits a fixed frequency RF period. The bridge circuit includes a first transistor switch and a second transistor switch. The first transistor switch connects a DC voltage source across the load to allow DC current to flow through the load in a first direction when on. The second transistor switch connects a DC voltage source across the load to allow DC current to flow through the load in the second direction when on. The switch driver sends an RF pulse to drive the first and second transistor switches on and off at a frequency that depends on the frequency of the RF pulse when enabled, and the current from the DC voltage source passes through the load. Flow alternately in the first and second directions. The driver control circuit provides them with a turn-on signal and selectively provides them to the switch driver to enable the switch driver to send RF pulses to the transistor switch. The switch driver includes first and second logic gates each connected to the first and second transistor switches. The first and second inductive operating circuits are respectively inserted between the first logic gate and the first transistor switch and between the second logic gate and the second transistor switch.

  Further, a switch mode power amplifier configured to amplify and add a plurality of signal inputs integrally is known (see Patent Document 2). The switch mode power amplifier comprises an input component for each of a plurality of input signals, an output resonator component, and a transformer component in between. The transformer component includes a plurality of serially connected input and output windings. Each input component comprises one of the input windings and a plurality of active devices. The active device is configured to be alternately switched by the input signal to provide an amplified signal corresponding to the input signal of the input winding and a low impedance. The output winding provides a sum signal corresponding to the sum of the amplified signals.

  A digital amplifier having a switching unit, a low-pass filter, and a mute unit is known (see Patent Document 3). The switching means outputs a drive signal by switching an operating voltage composed of a DC voltage based on an input signal in a pulse width modulation format. The low pass filter outputs an audio signal by inputting a drive signal and passing a signal component in an audible frequency band of the drive signal. The mute means is configured such that the resistance value can be increased or decreased in steps between the output end of the switching means for outputting the drive signal and the input end of the low-pass filter to which the drive signal is input.

JP 2001-267849 A JP 2005-512375 A JP 2005-117091 A

  The transformer has a primary side inductor and a secondary side inductor, and a voltage is generated in the secondary side inductor in accordance with a voltage applied to the primary side coil. In an amplifier using a transformer, a transistor is connected to a primary inductor. If a current flows through the secondary inductor during a period in which the transistor is off, a voltage is generated in the primary inductor, a high voltage is applied to the transistor, and the transistor may be destroyed.

  An object of the present invention is to provide an amplifier and a method for controlling the amplifier that can prevent the transistor from being damaged by applying a high voltage to the transistor.

  The amplifier separates the input signal into an amplitude component and a phase component, and outputs a plurality of bit signals and the phase component signal corresponding to the amplitude component, and a plurality of amplifications that input the phase component signal Each of the plurality of amplification units inputs one bit signal different from each other in the plurality of bit signals, and each of the plurality of amplification units is complementary based on the signal of the phase component. First and second transistors operating in common, a primary-side inductor and a secondary-side inductor, wherein the primary-side inductor is connected between the drain and source of the second transistor, and the one bit A plurality of amplifying units having a bias circuit for controlling gate bias voltages of the first and second transistors according to a signal; The secondary inductor of the transformer is connected in series, the first and second transistors are connected in series with each other, and the bias circuit has a case where the one bit signal has a first value. Includes applying a first gate bias voltage for turning on the first transistor to the gate of the first transistor, and a second gate bias for turning on the second transistor. When a voltage is applied to the gate of the second transistor and the one bit signal has a second value, a third gate bias voltage for turning off the first transistor is applied to the first transistor. A fourth gate bias voltage applied to the gate of the first transistor to turn on the second transistor is applied to the gate of the second transistor. It is applied to the door.

  By turning on the second transistor, destruction of the second transistor due to application of a high voltage to the second transistor can be prevented.

FIG. 1 is a diagram illustrating a configuration example of an amplifier according to the first embodiment. FIG. 2 is a diagram illustrating a configuration example of an amplifier according to a comparative example. FIG. 3 is a diagram illustrating a configuration example of an amplifier according to the second embodiment.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of an amplifier according to the first embodiment. The amplifier includes a signal processing unit 101, a plurality of amplification units AMP1 to AMPn, and a load 104. The signal processing unit 101 includes an amplitude component processing unit 102 and a phase component processing unit 103, which separates the input signal IN into an amplitude component (envelope component) and a phase component, and a plurality of bit signals A1 to An corresponding to the amplitude component. And a phase component signal PH.

  The amplitude component processing unit 102 extracts an amplitude component from the input signal IN and outputs a plurality of bit signals A1 to An corresponding to the amplitude component. The bit signals A1 to An are binary signals of “0” or “1”, respectively. For example, the amplitude component processing unit 102 controls the number of “1” bit signals among the plurality of bit signals A1 to An in accordance with the magnitude of the amplitude component. That is, the number of “1” bit signals among the plurality of bit signals A1 to An represents the magnitude of the amplitude component. The larger the amplitude component, the larger the number of “1” bit signals among the plurality of bit signals A1 to An. The n bit signals A1 to An are input to the n amplification units AMP1 to AMPn, respectively.

  The phase component processing unit 103 extracts the phase component of the input signal IN by removing the amplitude component from the input signal IN, and outputs the phase component signal PH. The phase component signal PH is input to n amplification units AMP1 to AMPn. For example, in the case of a mobile phone, the input signal IN is phase-modulated at several MHz in a high-frequency signal in a frequency band of 1 GHz to 5 GHz. In this case, the phase component signal PH is a signal that is phase-modulated at several MHz, and the bit signals A1 to An are output to the bias circuits B1 to Bn at several MHz.

  Each of the n amplification units AMP1 to AMPn inputs one different bit signal in the n number of bit signals A1 to An. Further, the n amplification units AMP1 to AMPn receive the phase component signal PH.

  The n amplification units AMP1 to AMPn include inverters I1 to In, first capacitors CA1 to CAn, second capacitors CB1 to CBn, bias circuits B1 to Bn, and first transistors TA1 to TAn, respectively. And second transistors TB1 to TBn and transformers TR1 to TRn. The amplification units AMP1 to AMPn are class D amplification units. Transformers TR1 to TRn have primary side inductors LA1 to LAn and secondary side inductors LB1 to LBn, respectively.

  Each of the inverters I1 to In outputs a signal inverted with respect to the phase component signal PH. The first capacitors CA1 to CAn are connected between the output terminals of the inverters I1 to In and the gates of the first transistors TA1 to TAn, respectively. The second capacitors CB1 to CBn are connected between the node of the phase component signal PH output from the signal processing unit 101 and the gates of the second transistors TB1 to TBn, respectively.

  The bias circuits B1 to Bn control the gate bias voltages of the first transistors TA1 to TAn and the second transistors TB1 to TBn, respectively, according to the bit signals A1 to An. By providing the first capacitors CA1 to CAn and the second capacitors CB1 to CBn, the bias circuits B1 to Bn can supply the gate bias voltage.

  The power supply potential node Vdd is connected to the drains of the first transistors TA1 to TAn, respectively. The sources of the first transistors TA1 to TAn are connected to the drains of the second transistors TB1 to TBn, respectively. The sources of the second transistors TB1 to TBn are connected to a reference potential node (ground potential node). That is, the first transistors TA1 to TAn and the second transistors TB1 to TBn are connected in series between the power supply potential node Vdd and the reference potential node, respectively. The sizes of the first transistors TA1 to TAn and the second transistors TB1 to TBn are the same in all the amplification units AMP1 to AMPn.

  Transformers TR1 to TRn include primary side inductors LA1 to LAn and secondary side inductors LB1 to LBn, respectively. The primary inductors LA1 to LAn are connected between the drains and sources of the second transistors TB1 to TBn, respectively. Secondary inductors LB1-LBn are connected in series between output node OUT and the reference potential node. The load 104 is connected between the output node OUT and the reference potential node. The transformers TR1 to TRn may be constituted by individual parts using a high magnetic permeability material, or may be constituted by a spiral wiring on a semiconductor chip together with the amplification units AMP1 to AMPn.

  The first transistors TA1 to TAn and the second transistors TB1 to TBn are, for example, high electron mobility transistors (HEMT) having a stacked structure of AlGaN and GaN, and have a threshold voltage of −2V. For example, the power supply potential node Vdd is 50V. When the sources of the first transistors TA1 to TAn and the second transistors TB1 to TBn are on, the interconnection point between the sources of the first transistors TA1 to TAn and the drains of the second transistors TB1 to TBn is 25V. is there.

  Each of the bias circuits B1 to Bn supplies a first gate bias voltage for turning on the first transistors TA1 to TAn when the bit signals A1 to An are the first value “1”. A first gate bias voltage is applied to the gates of the first transistors TA1 to TAn, and a second gate bias voltage for turning on the second transistors TB1 to TBn is applied to the gates of the second transistors TB1 to TBn. The first gate bias voltage is, for example, 24V. The second gate bias voltage is, for example, -1V. Each of the second transistors TB1 to TBn is turned on when the gate bias voltage is −1V. Each of the first transistors TA1 to TAn is turned on when the gate bias voltage is 24V.

  On the other hand, each of the bias circuits B1 to Bn has a third gate for turning off the first transistors TA1 to TAn when the bit signals A1 to An are the second value “0”. A bias voltage is applied to the gates of the first transistors TA1 to TAn, and a fourth gate bias voltage for turning on the second transistors TB1 to TBn is applied to the gates of the second transistors TB1 to TBn. The third gate bias voltage is −2V or less, for example −2V. The fourth gate bias voltage is, for example, 1V to −1V, preferably 1V. The second transistors TB1 to TBn are turned on when the gate bias voltage is 1V to −1V, respectively. The first transistors TA1 to TAn are each turned off when the gate bias voltage is −2V.

  For example, when the bit signals A1 to A3 are “1” and the bit signals A4 to An are “0”, the first transistors TA1 to TA3 and the second transistors TB1 to TB3 are turned on, The transistors TA4 to TAn are turned off, and the second transistors TB4 to TBn are turned on.

  When the first transistors TA1 to TA3 and the second transistors TB1 to TB3 are turned on, the first transistors TA1 to TA3 and the second transistors TB1 to TB3 each function as an inverter. That is, the first transistors TA1 to TA3 and the second transistors TB1 to TB3 respectively obtain the signals obtained by inverting and amplifying the phase component signal PH, and the sources of the first transistors TA1 to TA3 and the second transistors TB1 to TBn. Output to the interconnection point of the drains. The first transistors TA1 to TA3 and the second transistors TB1 to TB3 operate complementarily based on the phase component signal PH, respectively.

  On the other hand, when the first transistors TA4 to TAn are turned off and the second transistors TB4 to TBn are turned on, the sources of the first transistors TA1 to TA3 and the drains of the second transistors TB1 to TBn are turned on. The interconnection point is approximately 0V.

  In the transformers TR1 to TRn, voltages corresponding to the drain voltages of the second transistors TB1 to TBn are generated in the secondary side inductors LB1 to LBn, respectively. For example, the secondary side inductors LB1 to LB3 generate signals obtained by inverting and amplifying the phase component signal PH. On the other hand, the voltage generated in the secondary side inductors LB4 to LBn is 0V. As a result, a signal on which signals generated by the secondary side inductors LB1 to LB3 are superimposed is output to the output node OUT. That is, a signal on which signals amplified by the three amplification units AMP1 to AMP3 are superimposed is output to the output node OUT.

  Similarly, when the n bit signals A1 to An are “1”, the first transistors TA1 to TAn and the second transistors TB1 to TBn are turned on. In this case, the output node OUT outputs a signal on which the signal inverted and amplified by the n amplification units AMP1 to AMPn is superimposed. Since the bit signals A1 to An are signals corresponding to the amplitude signal of the input signal IN, a signal amplified according to the amplitude component of the input signal IN is output to the output node OUT. As a result, a signal amplified according to the phase component and amplitude component of the input signal IN is output to the output node OUT. That is, a signal obtained by amplifying the input signal IN is output to the output node OUT.

  The signal amplification factor can also be increased by connecting an inductor between the power supply potential node Vdd and the drains of the first transistors TA1 to TAn and adjusting the impedance of the amplification units AMP1 to AMPn.

  The amplifier according to the present embodiment can be used for a digital wireless communication apparatus such as a mobile phone, a smartphone, and a wireless local area network. In digital wireless communication devices, digital modulation schemes such as QPSK and 16QAM are employed to increase transmission capacity and frequency utilization efficiency, and the amplitude component and phase component of the transmission signal vary greatly. Usually, an amplifier capable of outputting power that is 4 to 10 times larger than the average transmission power is used as a transmission amplifier so that distortion does not occur with respect to such a signal with large fluctuation.

  Next, the case where the amplifier is a general amplifier that directly amplifies the input signal IN without separating the input signal IN into an amplitude component and a phase component will be described. In a general amplifier, the efficiency of the amplifier is maximized at an operating point where the output power is maximum, and the efficiency is decreased at an operating point where the output power is low. When a general amplifier is used in a region where the average output power is low (backoff operation region), the efficiency becomes low.

  On the other hand, the amplifier of FIG. 1 of the present embodiment can always operate the amplification units AMP1 to AMPn in a state of maximum efficiency, and can achieve the maximum efficiency at every amplitude level of the input signal IN. There is.

  FIG. 2 is a diagram illustrating a configuration example of an amplifier according to a comparative example. The amplifier of FIG. 2 is obtained by deleting the inverters I1 to In, the first capacitors CA1 to CAn, and the first transistors TA1 to TAn from the amplifier of FIG. Here, a case where the bit signal A1 is “0” and the bit signals A2 to An are “1” will be described. In this case, the transistor TB1 is turned off and the transistors TB2 to TBn are turned on. As a result, amplified signals are generated in the secondary inductors LB2 to LBn. Then, a current flows through the series connection of the secondary inductors LB1 to LBn, and a voltage corresponding to the amplified signal is generated at the output node OUT. At this time, since the transistor TB1 is in an off state, when a large current flows through the secondary inductor LB1, a high voltage is generated in the primary inductor LA1 due to the counter electromotive force. Accordingly, a high voltage is applied between the drain and source of the transistor TB1, and the transistor TB1 may be destroyed.

  On the other hand, in the amplifier of FIG. 1 of this embodiment, when the bit signal A1 is “0”, the first transistor TA1 is turned off and the second transistor TB1 is turned on as described above. . As a result, the on-resistance between the drain and source of the second transistor TB1 is almost 0Ω, so that even if a large current flows through the secondary inductor LB1, a high voltage is applied between the drain and source of the second transistor TB1. Not applied. Therefore, according to this embodiment, the destruction of the second transistor TB1 can be prevented.

  In the present embodiment, as described above, when the bit signals A1 to An have the first value “1”, the bias circuits B1 to Bn are connected to the gates of the second transistors TB1 to TBn by “− A second gate bias voltage of “1 V” is applied to turn on the second transistors TB1 to TBn. On the other hand, when the bit signals A1 to An are the second value “0”, the bias circuits B1 to Bn are connected to the gates of the second transistors TB1 to TBn and the fourth gate of “1V”. A bias voltage is applied to turn on the second transistors TB1 to TBn. Thus, the fourth gate bias voltage is preferably higher than the second gate bias voltage. That is, in the second transistors TB1 to TBn, the on-resistance when the fourth gate bias voltage is applied is smaller than the on-resistance when the second gate bias voltage is applied. Accordingly, when a fourth gate bias voltage is applied to the gates of the second transistors TB1 to TB4, a high voltage is prevented from being applied between the drains and sources of the second transistors TB1 to TBn, The effect that can prevent the destruction of the second transistors TB1 to TBn works more strongly.

Note that the first transistors TA1 to TAn and the second transistors TB1 to TBn are not limited to the HEMT having a stacked structure of AlGaN and GaN, and may be constituted by transistors using Si or a compound semiconductor, for example. Compound semiconductor transistors include GaAs-based MES field effect transistors, HEMTs, and stacked layers of AlGaN and In _x Ga _1-x N (0 <= x <1) using nitride semiconductors, HEMTs, InAlN, and In _x Ga. _1-x N (0 <= x <1) HEMT, InAlGaN and In _x Ga _1-x N (0 <= x <1) HEMT, insulated gate transistor, ZnO, MnO, etc. There are transistors including oxide semiconductors.

  In addition, the first transistors TA1 to TAn and the second transistors TB1 to TBn can be formed of CMOS transistors on a silicon substrate. That is, the second transistors TB1 to TBn can be constituted by n-channel MOS field effect transistors, the inverters I1 to In can be eliminated, and the first transistors TA1 to TAn can be constituted by p-channel field effect transistors. In this case, the same operation as described above can be performed.

  However, in the case of a CMOS transistor on a silicon substrate, a parasitic diode (body diode) is formed between the drain and source of the second transistors TB1 to TBn, so that the second transistors TB1 to TBn are not necessarily destroyed.

  On the other hand, as described above, when the first transistors TA1 to TAn and the second transistors TB1 to TBn are transistors using a nitride semiconductor such as HEMT, the parasitic diode is not formed. Therefore, there is a high possibility that the second transistors TB1 to TBn are destroyed. Therefore, when the first transistors TA1 to TAn and the second transistors TB1 to TBn are transistors using nitride semiconductors, the present embodiment has an effect of preventing the destruction of the second transistors TB1 to TBn. Become prominent.

  In the above description, the case where the sizes of the first transistors TA1 to TAn and the second transistors TB1 to TBn are the same in all the amplification units AMP1 to AMPn has been described. However, the present invention is not limited to this. The sizes of the first transistors TA1 to TAn and the second transistors TB1 to TBn may be different for each of the amplification units AMP1 to AMPn. For example, the size ratio of the first transistors TA1 to TAn and the second transistors TB1 to TBn can be set to 1: 2: 4: 8: 16:... Between the amplification units AMP1 to AMPn. As a result, the transformers TR1 to TRn output signals having sizes corresponding to the sizes of the first transistors TA1 to TAn and the second transistors TB1 to TBn, respectively, so that the amplifier outputs a high resolution amplified signal. Can be output to node OUT. For example, when the first transistors TA1 to TAn and the second transistors TB1 to TBn are HEMTs having a stacked structure of AlGaN and GaN, the gate widths of the first transistor TA1 and the second transistor TB1 are set to 200 μm. The gate width of the transistor TA2 and the second transistor TB2 can be 200 μm × 2, and the gate width of the first transistor TA3 and the second transistor TB3 can be 200 μm × 4. In that case, the amplifier can amplify and transmit the output power of about 200 W in increments of 1 W with respect to the input signal IN in the 1 GHz to 5 GHz band.

(Second Embodiment)
FIG. 3 is a diagram illustrating a configuration example of an amplifier according to the second embodiment. The amplifier of FIG. 3 differs from the amplifier of FIG. 1 in the connection destinations of the primary side inductors LA1 to LAn. Hereinafter, differences of the present embodiment (FIG. 3) from the first embodiment (FIG. 1) will be described. The primary side inductors LA1 to LAn are connected between the drains and sources of the first transistors TA1 to TAn, respectively.

  Each of the bias circuits B1 to Bn supplies a third gate bias voltage for turning on the first transistors TA1 to TAn when the bit signals A1 to An are the second value “0”. A first gate bias voltage is applied to the gates of the first transistors TA1 to TAn, and a fourth gate bias voltage for turning off the second transistors TB1 to TBn is applied to the gates of the second transistors TB1 to TBn.

  When the first transistors TA1 to TAn are turned on, the on-resistance between the drain and the source of the first transistors TA1 to TAn is approximately 0Ω, respectively. As a result, even when a large current flows through the secondary inductor LB1, a high voltage is not applied between the drain and source of the first transistor TA1, so that the breakdown of the first transistor TA1 can be prevented.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

101 Signal processing unit 102 Amplitude component processing unit 103 Phase component processing unit 104 Loads AMP1 to AMPn Amplifying units B1 to Bn Bias circuits I1 to In Inverters CA1 to CAn First capacitors CB1 to CBn Second capacitors TA1 to TAn First Transistors TB1 to TBn Second transistors TR1 to TRn Transformers LA1 to LAn Primary inductors LB1 to LBn Secondary inductors

Claims (15)

A signal processing unit that separates an input signal into an amplitude component and a phase component, and outputs a plurality of bit signals corresponding to the amplitude component and a signal of the phase component;
A plurality of amplification units for inputting the signal of the phase component;
Each of the plurality of amplification units inputs one bit signal different from each other in the plurality of bit signals,
Each of the plurality of amplification units includes:
First and second transistors operating complementarily based on the signal of the phase component;
A transformer including a primary inductor and a secondary inductor, wherein the primary inductor is connected between a drain and a source of the second transistor;
A bias circuit for controlling gate bias voltages of the first and second transistors according to the one bit signal;
The secondary inductors of the transformers in the plurality of amplification units are connected in series;
The first and second transistors are connected in series with each other;
The bias circuit includes:
When the one bit signal has a first value, a first gate bias voltage for turning on the first transistor is applied to the gate of the first transistor, and the second transistor is turned on. Applying a second gate bias voltage for turning on the transistor to the gate of the second transistor;
When the one bit signal has the second value, a third gate bias voltage for turning off the first transistor is applied to the gate of the first transistor, and the second transistor An amplifier, wherein a fourth gate bias voltage for turning on a transistor is applied to a gate of the second transistor.   The amplifier according to claim 1, wherein the fourth gate bias voltage has a voltage value different from that of the second gate bias voltage.   The on-resistance of the second transistor when the fourth gate bias voltage is applied is smaller than the on-resistance when the second gate bias voltage is applied. The described amplifier. Each of the plurality of amplification units includes:
A first capacitor connected between the signal processing unit and a gate of the first transistor;
The amplifier according to claim 1, further comprising: a second capacitor connected between the signal processing unit and a gate of the second transistor.   The amplifier according to claim 1, further comprising a load connected to the secondary inductor of the transformer in the plurality of amplification units.   The amplifier according to any one of claims 1 to 5, wherein the first and second transistors are connected in series between a power supply potential node and a reference potential node.   7. The amplifier according to claim 6, wherein each of the plurality of amplification units further includes an inductor connected between a series connection of the first and second transistors and the power supply potential node.   8. The amplifier according to claim 6, wherein the first transistor is connected to the power supply potential node side, and the second transistor is connected to the reference potential node side.   8. The amplifier according to claim 6, wherein the first transistor is connected to the reference potential node side, and the second transistor is connected to the power supply potential node side. The gate of the first transistor inputs a signal inverted with respect to the signal of the phase component,
The amplifier according to claim 1, wherein a signal of the phase component is input to a gate of the second transistor. The gate of the first transistor inputs the signal of the phase component,
10. The amplifier according to claim 1, wherein a signal inverted with respect to the signal of the phase component is input to the gate of the second transistor. 11.   The amplifier according to claim 1, wherein the first and second transistors have the same size in the plurality of amplification units.   The amplifier according to any one of claims 1 to 11, wherein the sizes of the first and second transistors are different for each of the amplification units.   The amplifier according to any one of claims 1 to 13, wherein the first and second transistors are transistors using a nitride semiconductor. A signal processing unit that separates an input signal into an amplitude component and a phase component, and outputs a plurality of bit signals corresponding to the amplitude component and a signal of the phase component;
A method for controlling an amplifier having a plurality of amplification units for inputting a signal of the phase component,
Each of the plurality of amplification units inputs one bit signal different from each other in the plurality of bit signals,
Each of the plurality of amplification units includes:
First and second transistors operating complementarily based on the signal of the phase component;
A transformer including a primary inductor and a secondary inductor, wherein the primary inductor is connected between a drain and a source of the second transistor;
A bias circuit for controlling gate bias voltages of the first and second transistors according to the one bit signal;
The secondary inductors of the transformers in the plurality of amplification units are connected in series;
The first and second transistors are connected in series with each other;
The control method is:
When the one bit signal has a first value, the bias circuit applies a first gate bias voltage for turning on the first transistor to the gate of the first transistor. Applying a second gate bias voltage for turning on the second transistor to the gate of the second transistor;
When the one bit signal has a second value, the bias circuit applies a third gate bias voltage for turning off the first transistor to the gate of the first transistor. A method of controlling an amplifier, comprising applying a fourth gate bias voltage for turning on the second transistor to the gate of the second transistor.

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