JP6445487B2 - OR operation apparatus and OR operation method - Google Patents

Description

  The present invention relates to a quantum calculation technique, and more particularly to a technique for calculating a logical sum function.

When the number of input digits is n, there is no initialization auxiliary qubit, one uninitialized auxiliary qubit, and the OR function x ₁ ∨... ∨x _n is calculated in O (n) calculation steps. A method of configuring a quantum circuit to be calculated is known (see, for example, Non-Patent Document 1). FIG. 17 shows an example when n = 7, and in addition to the input qubits of states (quantum states) | x ₁ >,..., | X _n > and output qubits of state | y>, any state | A ₁ > uninitialized auxiliary qubits are used.

Barenco, CH Bennett, R. Cleve, DP DiVincenzo, N. Margolus, P. Shor, T. Sleator, JA Smolin, and H. Weinfurter, “Elementary gates for quantum computation,” Phys. Rev. A, Vol. 52 No 5, pp. 3457-3467, 1995.

  The larger the number of calculation steps, the longer the calculation time of the quantum circuit. In addition, the physical feasibility decreases as the number of calculation steps increases. Therefore, in order to simultaneously realize high physical feasibility and short calculation time, it is better to reduce the number of calculation steps. In the conventional method, a logical sum function is performed in O (n) calculation steps, and there is a problem in physical feasibility and the length of calculation time.

  An object of the present invention is to calculate a logical sum function with fewer calculation steps than before.

で表される状態｜φ_ｋ〉を生成し、当該状態｜φ_１〉…｜φ_ｍ〉からφ_１，…，φ_ｍの論理和を表す状態を生成する。ただし、ｎが２以上の整数であり、ｗが１≦ｗ≦ｎを満たす整数であり、ｘ_ｗ∈｛０，１｝であり、｜ｘ｜＝ｘ_１＋…＋ｘ_ｎであり、ｃｅｉｌ（・）が（・）の天井関数であり、ｍ＝ｃｅｉｌ（ｌｏｇ_２（ｎ＋１））であり、ｋが１≦ｋ≦ｍを満たす整数である。 x _1, ..., in order to calculate the logical sum of _{x n,} the initial state is _{| x 1>, ..., |} x n> n inputs qubit _X 1 is a, ..., _{X n,} the initial state | y> using one output qubit Y, an initialization auxiliary qubit, and an uninitialized auxiliary qubit,

Generates phi _k>, the state | | state expressed in φ _1> ... | from φ _m> φ _1, ..., and generates a status indicating a logical sum of phi _m. However, n is an integer of 2 or more, w is an integer satisfying 1 ≦ w ≦ n, x _w ε {0, 1}, | x | = x ₁ +... + X _n , ceil ( ·) Is the ceiling function of (·), m = ceil (log ₂ (n + 1)), and k is an integer satisfying 1 ≦ k ≦ m.

With initialization auxiliary qubit and uninitialized auxiliary _qubit, x 1, ..., calculate phi ₁ of the logical sum of x _n, ..., it is to result in the calculation of the logical sum of phi _m, less than conventional The logical sum function can be calculated in the calculation step.

FIG. 1 is a block diagram illustrating a functional configuration of a logical sum operation device according to an embodiment. 2A and 2B are block diagrams illustrating the configuration of auxiliary qubits. FIG. 3 is an example of a quantum circuit that performs a logical sum operation of this embodiment. FIG. 4 is an example of a quantum circuit that performs a logical sum operation of this embodiment. FIG. 5 is an example of a quantum circuit that performs a logical sum operation of this embodiment. 6A represents a NOT operation, FIG. 6B represents a CNOT operation, FIG. 6C represents a Hadamard operation, and FIG. 6D represents a z-Toffoli operation. FIG. 8 shows a quantum circuit that performs a 5-Toffoli operation. FIG. 7 shows a quantum circuit that performs a 3-Toffoli operation. FIG. 9A shows the control V calculation, and FIG. 9B shows the reverse calculation of the control V calculation. FIG. 10 shows the p-fanout operation. FIG. 11 shows an example of a quantum circuit that performs a 9-fanout operation. 12A shows the (p, q) -phase shift operation, and FIG. 12B shows the inverse operation of the (p, q) -phase shift operation. FIG. 13 shows an example of a quantum circuit that performs a (9, q) -phase shift operation. FIG. 14A is a flowchart for explaining the entire processing of this embodiment. FIG. 14B is a flowchart for explaining details of step S1 in FIG. 14A. FIG. 15 is a flowchart for explaining details of step S (s). FIG. 16 is a flowchart for explaining details of step S2. FIG. 17 shows an example of a conventional quantum circuit that calculates a logical sum function.

を出力する関数を意味する。ただし、ｎが１以上の整数であり、１≦ｗ≦ｎを満たす整数ｗに対し、ｘ_ｗは０または１（ｘ_ｗ∈｛０，１｝）であり、｜ｘ｜＝ｘ_１＋…＋ｘ_ｎである。例えばｎは２以上の整数であり、特に本形態ではｎが３以上の整数のときに効果が高い。以下では、論理積関数も扱うが、この関数は入力ビット列ｘがｎ個のビットｘ_１，…，ｘ_ｎからなる列のとき、

を出力する。 Embodiments of the present invention will be described below.
[Definition]
First, terms used in the embodiment are defined.
The logical sum function is a function having a set of all finite bit sequences of length 1 or more as a domain and {0, 1} as a range, and an input bit sequence x is n bits x ₁ ,..., X _For a sequence of _n ,

Means a function that outputs However, n is an integer of 1 or more, and for an integer w satisfying 1 ≦ w ≦ n, x _w is 0 or 1 (x _w ε {0, 1}), and | x | = x ₁ +. + _Xn . For example, n is an integer of 2 or more, and in this embodiment, the effect is particularly high when n is an integer of 3 or more. In the following, a logical product function is also handled, but this function is used when the input bit string x is a string composed of n bits x ₁ ,..., X _n .

Is output.

は２を法とする加算（排他的論理和）を表し、記載表記の制約上、本形態ではこれを（＋）と表記することもある。任意のα∈｛０，１｝に対し、α（＋）１（αにNOT演算を適用した値）を

と記述する。このとき

という関係が成り立つことは容易に確認できる。

Represents an addition modulo 2 (exclusive OR), and in the present embodiment, this may be expressed as (+) due to the limitation of description. For any α∈ {0,1}, α (+) 1 (value obtained by applying NOT operation to α)

Is described. At this time

It can be easily confirmed that this relationship holds.

When the number of input digits is n, the quantum circuit for calculating the logical sum function has n input qubits and one output qubit, and any x ₁ ,..., X _n , y∈ {0 , 1}, if the initial state of the input qubit is | x ₁ >... | X _n > and the initial state of the output qubit is | y>, by applying all basic operations constituting the quantum circuit, , the state of the input qubit is not changed, the state of the output qubit has a _{y (+) x 1 ∨ ...} ∨x n (2 modulo, obtained by adding _{x 1} ∨ ··· _{∨x n} to y value Of the quantum circuit. A quantum circuit that calculates a logical product function is similarly defined. That is, the quantum circuit for calculating a logical product function, having n input qubit and one output qubits, any x _1, ..., x _n, with respect y∈ {0,1}, the input When the initial state of the qubit is | x ₁ >... | X _n > and the initial state of the output qubit is | y>, the state of the input qubit is obtained by applying all the basic operations that constitute the quantum circuit. It is a quantum circuit that does not change and the state of the output qubit is | y (+) x ₁ ∧... ∧x _n >. “State” is synonymous with “quantum state”, and “initial state” is synonymous with “initial quantum state”.

The quantum circuit can have auxiliary qubits in addition to the input qubits and the output qubits, and the auxiliary qubits are classified into initialized auxiliary qubits and uninitialized auxiliary qubits. The initializing auxiliary qubit is defined as an initial state of | 0>, and the uninitialized auxiliary qubit is permitted when the initial state is either | 0> or | 1>. When the quantum circuit that calculates the logical sum function has u initialization auxiliary qubits and q uninitialized auxiliary qubits (where u and q are positive integers), the initial state of the entire initialization qubit Is | 0> ... | 0>, but the initial state of the entire uninitialized auxiliary qubit is | a ₁ > ... | a _{q for} any a ₁ ,..., A _q ε {0, 1}. It is assumed that these states do not change after all basic operations constituting the quantum circuit are applied. That is, the auxiliary qubit may be in any state during the calculation, but it is requested that the auxiliary qubit must return to the initial state after the calculation is completed.

  In a quantum circuit, one calculation step is a group of basic operations that can be executed in parallel in the quantum circuit. However, basic operations on different qubits (one qubit operation such as NOT operation and Hadamard operation and two qubit operation such as CNOT operation) can be executed in parallel. Therefore, in a quantum circuit that calculates a logical sum function in λ calculation steps, the basic operations included in the quantum circuit are classified into λ groups, and in each group, all the operations can be executed in parallel. It is.

  As shown in FIG. 6A, the NOT operation X is an operation for one qubit in an arbitrary state | χ>, and the state of this qubit is set to | χ (+) 1> (where χ∈ {0, 1}, χ (+) 1 = χ + 1 mod 2).

  As shown in FIG. 6B, the CNOT operation is an operation on one control bit in an arbitrary state | χ> and one target bit in an arbitrary state | γ>. The state of the control bit after the CNOT operation is | χ>, and the state of the target bit is | χ (+) γ> (where χ, γ∈ {0,1}, χ (+) γ = χ + γ mod 2).

にする（ただし、χ∈｛０，１｝）。 As shown in FIG. 6C, the Hadamard operation (transformation) is an operation on one qubit in an arbitrary state | χ>, and the state of this qubit is changed.

(Where χ∈ {0,1}).

As shown in FIG. 6D, the z-Toffoli operation is performed with z-1 control bits (where z is an integer of 3 or more) in an arbitrary state | χ ₁ >,..., | Χ _z-1 >, and This is an operation for one target bit in an arbitrary state | γ>. z-Toffoli operation after the z-1 pieces of control bits in the state each of | χ _1>, ..., | a χ _z-1>, the state of the target bit _{| γ (+) χ 1 ...} χ z _-1 is a> _{(where, χ 1, ..., χ z} -1, .χ 1 ... χ z-1 is chi ₁ is γ∈ {0,1}, ..., is the product of the χ _z-1, represents the logical product of χ ₁ ,..., χ _z−1 ). z-Toffoli operation, note that the input digits are quantum circuit for calculating a logical product function χ ₁ ∧ ... ∧χ _z-1 of z-1. The z-Toffoli operation can be calculated by a quantum circuit composed of 3-Toffoli operations. For example, the 5-Toffoli operation can be calculated by a quantum circuit including the 3-Toffoli operation illustrated in FIG. Four control bits in any state | χ ₁ >,..., | Χ ₄ >, one target bit in any state | γ>, and any state | a ₁ >, | a ₂ > By applying this quantum circuit to two uninitialized auxiliary qubits, a 5-Toffoli operation can be performed. The said four states of the control bits after each operation | χ _1>, ..., | a chi _4>, the state of the target bit | γ (+) χ _{1 ...} a chi _4>, the 2 The states of the uninitialized auxiliary qubits are | a ₁ > and | a ₂ >, respectively. As illustrated in FIG. 8, the 3-Toffoli operation can be calculated by a quantum circuit including a CNOT operation, a control V operation, and an inverse operation of the control V operation. By applying this quantum circuit to two control bits in an arbitrary state | χ ₁ > and | χ ₂ > and one target bit in an arbitrary state | γ>, a 3-Toffoli operation is performed. It can be carried out. The states of the two control bits after this calculation are | χ ₁ > and | χ ₂ >, respectively, and the state of the target bit is | γ (+) χ ₁ χ ₂ >.

As shown in FIG. 9A, the control V operation is an operation on one control bit in an arbitrary state | χ> and one target bit in an arbitrary state | γ> (where χ, γ ∈ {0, 1}). The state of the control bit after the control V calculation is | χ>, and the state of the target bit is as follows. However, i represents an imaginary unit.

As shown in FIG. 9B, the inverse operation of the control V is an operation on one control bit in an arbitrary state | χ> and one target bit in an arbitrary state | γ> (provided that χ , Γ∈ {0, 1}). The state of the control bit after the control V calculation is | χ>, and the state of the target bit is as follows.

As shown in FIG. 10, the p-fanout operation includes one control bit in an arbitrary state | γ> and _p−1 bits in any state | χ ₁ >,..., | Χ _p-1 >. (Where p is an integer equal to or greater than 2). The state of the control bit after the p-fanout operation is | γ>, and the states of the p−1 target bits are | χ ₁ (+) γ>,..., | χ _p-1 (+) γ, respectively. (Where γ, χ ₁ ,..., Χ _p−1 ε {0, 1}).

From the quantum circuit described in Reference 1 (C. Moore, “Quantum circuits: fanout, parity, and counting,” arXiv: quant-ph / 9903046, 1999.), it has no auxiliary qubit and O (logp ) A quantum circuit that performs p-fanout operations in a single calculation step can be easily configured. As an example, a quantum circuit that performs a p-fanout operation when p = 2 ^κ +1 (where κ is an integer equal to or greater than 1) will be described (note that when κ = 0, the p-fanout operation is a CNOT operation). From a quantum circuit consisting of only one CNOT operation). Prepare the following qubits.
・ One control bit Γ
P-1 target bits _{１ 1} , ..., Χ _p-1
The initial state of Γ is | γ>, and the initial states of Χ ₁ , ..., Χ _p-1 are | χ ₁ >, ..., | χ _p-1 >, respectively. However, γ, χ ₁ ,..., Χ _p−1 ε {0, 1}. This initial state | γ> | χ ₁ >,..., | Χ _p-1 > is converted to | γ> | χ ₁ (+) γ>,..., | Χ _p-1 (+) γ>, p-fanout The quantum circuit which performs an operation is shown. This quantum circuit consists only of CNOT operations. Processing by this quantum circuit is as follows.

を制御ビットとし、

を標的ビットとしたCNOT演算を適用する。ただし、ｊは０≦ｊ≦２^κ−Ｌ−１を満たす整数であり、これら２^κ−Ｌ個のCNOT演算は並列に適用される。
＜ステップII＞次に量子回路はΓ制御ビットとし、Χ_１を標的ビットとしたCNOT演算を適用する。
＜ステップIII＞次に量子回路はステップIの逆演算を適用する。すなわち量子回路は、Ｌ＝κ，κ−１，κ−２，…，１についてκから１まで降順に、次の処理を実行する。

を制御ビットとし、

を標的ビットとしたCNOT演算を適用する。ただし、ｊは０≦ｊ≦２^κ−Ｌ−１を満たす整数であり、これら２^κ−Ｌ個のCNOT演算は並列に適用される。 <Step I> The quantum circuit executes the following processing in ascending order from 1 to κ for L = 1, 2, 3,.

Is a control bit,

Apply CNOT operation using as the target bit. However, j is an integer satisfying 0 ≦ j ≦ 2 ^κ−L −1, and these 2 ^κ−L CNOT operations are applied in parallel.
<Step II> next quantum circuit is a Γ control bits, applies the CNOT operation that target bit chi _1.
<Step III> Next, the quantum circuit applies the inverse operation of Step I. That is, the quantum circuit executes the following processing in descending order from κ to 1 for L = κ, κ-1, κ-2,.

Is a control bit,

Apply CNOT operation using as the target bit. However, j is an integer satisfying 0 ≦ j ≦ 2 ^κ−L −1, and these 2 ^κ−L CNOT operations are applied in parallel.

  The quantum circuit when κ = 3 (9-fanout) is as shown in FIG.

If p can not be represented by p = 2 ^kappa +1, quantum circuit that performs p-fanout operation is constructed as follows. First, a quantum circuit that executes the above-described steps I to III with p = p ′ for the minimum p ′ that satisfies p <p ′ = ^2κ + 1 is configured. However, κ is an integer of 1 or more. This quantum circuit has qubits Γ, _{１ 1} ,..., _{Ｐ p′−1} . Next, all the operations applied to any quantum bit of Χp, Χp + 1,..., Ｐp′ ₋₁ are deleted. This is the desired quantum circuit. For example, delete the case of p = 8, p '= 9 (κ = 3) becomes, in the circuit of FIG. 11, chi The assigned two CNOT operation on ₈ (included in the first step and the last step) The result is a quantum circuit that performs an 8-fanout operation.

As described above, a quantum circuit that performs a p-fanout operation for an arbitrary p does not have auxiliary qubits. Since κ corresponding to p ′ satisfies κ ≦ ceil (log ₂ p), the number of calculation steps of this quantum circuit is O (log ₂ p).

である。 Also, as shown in FIG. 12A, the (p, q) -phase shift operation is performed with p−1 control bits in an arbitrary state | χ ₁ >,..., | Χ _p−1 >, and an arbitrary state | a p qubit operations on one target bit in the chi _{p> (However, χ 1, ..., χ p} -1, χ p ∈ {0,1}, p is an integer of 2 or more, q is It is an integer of 1 or more). (p, q) -The state of the p-1 control bits and one target bit after the phase shift operation is

It is.

From the quantum circuit described in Non-Patent Document 1, a quantum circuit that does not have auxiliary qubits and performs a (p, q) -phase shift operation in O (p) calculation steps is one (2 , q) -phase shift operation, two (2, q + 1) -phase shift operations, and two (p-1) -Toffoli operations. For example, a quantum circuit that executes a (p, 9) -phase shift operation when p = 9 is as shown in FIG. This 8-Toffoli operation removes all NOT operations in the first and last operation steps of the quantum circuit of FIG. 17, and changes the state of the input qubits | x ₁ >,..., | X ₇ > to | χ ₁ >,. | replaced with chi _7>, output qubit state | y> a | replaced by chi _9>, uninitialized auxiliary quantum bit states | can be calculated by substitution quantum circuit chi _8> | a a _1> .

である。 As shown in FIG. 12B, the inverse operation of (p, q) -phase shift is performed by p-1 control bits in an arbitrary state | χ ₁ >,..., | Χ _p-1 > and an arbitrary state. P qubit operation for one target bit in | χ _p > (where χ ₁ ,..., Χ _p−1 , χ _p ε {0, 1}, p is an integer of 2 or more, q Is an integer of 1 or more). The state of the p-1 control bits and one target bit after the inverse operation of (p, q) -phase shift is

It is.

[Embodiment]
Next, the outline of the embodiment will be described with reference to the drawings.
<Configuration>
As illustrated in FIG. 1 and FIG. 2, the logical sum operation device 1 of this embodiment includes a quantum operation unit 11 including operation units 1101 to 1110, a quantum operation unit 12 including operation units 1211 to 1214, and n input quantum Bits X ₁ ,..., X _n , 1 output qubit Y, m initialization auxiliary qubits I (1),..., I (m), nm (m + 3) / 2 uninitialized auxiliary quanta Has a bit. n is an integer greater than or equal to 2, but when n is an integer greater than or equal to 3, the reduction effect of a calculation step is remarkable. m = ceil (log ₂ (n + 1)), and ceil (•) represents the ceiling function of (•). A set of uninitialized auxiliary qubits consists of subsets A (1),..., A (m), B (1),. The subset A (k) consists of n uninitialized auxiliary qubits A ₁ (k),..., A _n (k) (FIG. 2A). However, k is an integer (k = 1, ..., m) satisfying 1≤k≤m. The subset B (k) is composed of k subsets B (k, 1),..., B (k, k), and the subset B (k, r) is n uninitialized auxiliary qubits B _1. (K, r),..., B _n (k, r) (FIG. 2B). Here, r is an integer satisfying 1 ≦ r ≦ k (r = 1,..., K). That is, the subset B (k) includes kn uninitialized auxiliary quantum bits B ₁ (k, r),..., B _n (k, r) (where 1 ≦ k ≦ m, 1 ≦ r ≦ k). Consists of.

  The OR operation device 1 can be realized using a known quantum computer. For example, when an ion trap quantum computer is used, a quantum bit is realized using the ground state and excited state of the ion, and each calculation is performed by arranging the ions on a straight line. A 1-qubit unitary operation including a Hadamard operation is realized by a laser beam aimed at individual ions, and a CNOT operation, which is a 2-qubit operation, is similarly realized. A general 2-qubit operation is realized by combining a 1-qubit operation and a CNOT operation.

<Processing>
An outline of processing for obtaining the logical sum x ₁ ∨... ∨x _n by applying the above-described logical sum function (formula (1)) to the input bit string x composed of _n bits x ₁ ,. However, x _w ε {0, 1}, and w is an integer that satisfies 1 ≦ w ≦ n.

で表される状態｜φ_ｋ〉を生成する。ただし、｜ｘ｜＝ｘ_１＋…＋ｘ_ｎである（ステップＳ１）。 As illustrated in FIG. 14A, first, the quantum operation unit 11 (first quantum operation unit) has n input qubits X ₁ ,..., X whose initial states are | x ₁ >, ..., | x _n >. _n , one output qubit Y whose initial state is | y>, an initialization auxiliary qubit, and an uninitialized auxiliary qubit, and k = 1,..., m

A state | φ _k > represented by However, | x | = x ₁ +... + X _n (step S1).

Next, quantum computing unit 12 (second quantum computation part), the state | φ _1> ... | from φ _m> φ _1, ..., to produce a state representing a logical sum of phi _m. In other words, a quantum operation is performed on the state | φ ₁ >... | Φ _m > to generate a state representing the logical sum of φ ₁ ,..., Φ _m (step S2).

Here, a state is obtained in step _{S1 | φ 1> ... | φ} 1 corresponding to phi _m>, ..., state representing a logical sum φ ₁ ∨ ... ∨φ _m of phi _{m is,} x 1, ..., _{x n} Is _equal to the state representing x ₁ ∨... ∨x _n . For example, when n = 3, m = 2, and in step S1, the following two 1-qubit states are generated.

It can be easily confirmed that these have the following properties (for example, Reference 2: P. Hoyer and R. Spalek, “Quantum fan-out is powerful,” Theory of Computing, Vol. 1, pp. 81-103. , 2005.).
When x ₁ ∨x ₂ ∨x ₃ = 1 (at least one of x ₁ , x ₂ , x ₃ is 1), at least in the above two states (formula (2) (3)) One is | 1>.
When x ₁ ∨x ₂ ∨x ₃ = 0 (all of x ₁ , x ₂ , and x ₃ are 0), the above two states (formulas (2) and (3)) are all | 0>.
Therefore, the calculation of x ₁ ∨x ₂ ∨x ₃ is reduced to a calculation for obtaining a logical sum of the states | φ ₁ > and | φ ₂ >, that is, a state representing the logical sum φ ₁ ∨φ ₂ . Therefore, the state in step S2 | φ _1> ... | from φ _m> φ _1, ..., to produce a state representing a logical sum of phi _m, to obtain the operation result of _{x 1 ∨x 2 ∨x 3} it can.

In this embodiment, using the initialization auxiliary qubit and uninitialized auxiliary qubit, x _1, ..., calculate phi ₁ of the logical sum of x _n, ..., it is to result in the calculation of the logical sum of phi _m, The logical sum function can be calculated with fewer calculation steps than before.

<Details of Step S1>
Details of Step 1 will be described.
The next qubit is used (FIGS. 1, 2A and 2B).
N input qubits X ₁ ,..., X _n
・ One output qubit Y
-M initialization auxiliary qubits I (1), ..., I (m)
・ Nm (m + 3) / 2 uninitialized auxiliary qubits (the structure of the uninitialized auxiliary qubits is as described above)

The initial state is as follows.
The initial states of X ₁ ,..., X _n are | x ₁ >, ..., | x _n >, respectively.
The initial state of Y is | y>
The initial states of I (1),..., I (m) are | 0>,.
For any _{1 ≦ k ≦ m, A 1} (k), ..., the initial state of _A n (k), respectively _{| a 1 (k)>,} ..., | a n (k)>
For any 1 ≦ k ≦ m and 1 ≦ r ≦ k, the initial states of B ₁ (k, r),..., B _n (k, r) are | b ₁ (k, r)>,. | B _n (k, r)>

In order to facilitate the description of the circuit configuration, when the states of all qubits are illustrated, the states of X ₁ ,..., X _n are described first, and thereafter, for each k in order from k = 1 to m, A ₁ (k),..., _An (k) state, I (k) state, B (k, 1),..., B (k, k) state. Is described. The state of B (k, r) for any 1 ≦ r ≦ k is described in the order of the state of B ₁ (k, r),..., B _n (k, r). In step S1, the state of I (k) (where 1 ≦ k ≦ m) becomes | φ _k >, and the states of other qubits do not change. For example, when n = 3, m = 2, three input qubits X ₁ , X ₂ , X ₃ , one output qubit Y, two initialization auxiliary qubits I (1), I (2), 15 uninitialized auxiliary qubits A ₁ (1), A ₂ (1), A ₃ (1), A ₁ (2), A ₂ (2), A ₃ (2), B ₁ (1,1), B ₂ (1,1), B ₃ (1,1), B ₁ (2,1), B ₂ (2,1), B ₃ (2,1), B ₁ The states of (2, 2), B ₂ (2, 2), and B ₃ (2, 2) are described in the order described above.
| X ₁ > | x ₂ > | x ₃ > | a ₁ (1)> | a ₂ (1)> | a ₃ (1)> | 0> | b ₁ (1,1)> | b ₂ (1 , 1)> | b ₃ (1,1)> | a ₁ (2)> | a ₂ (2)> | a ₃ (2)> | 0> | b ₁ (2,1)> | b ₂ ( 2, 1)> | b ₃ (2,1)> | b ₁ (2,2)> | b ₂ (2,2)> | b ₃ (2,2)> | y>

This state becomes the next state by the process of step S1.
| X ₁ > | x ₂ > | x ₃ > | a ₁ (1)> | a ₂ (1)> | a ₃ (1)> | φ ₁ > | b ₁ (1,1)> | b ₂ ( 1, 1)> | b ₃ (1,1)> | a ₁ (2)> | a ₂ (2)> | a ₃ (2)> | φ ₂ > | b ₁ (2,1)> | b ₂ (2,1)> | b ₃ (2,1)> | b ₁ (2,2)> | b ₂ (2,2)> | b ₃ (2,2)> | y>

  As illustrated in FIG. 14, step S1 includes m stages S (1),..., S (m) (steps S11-1 to S11-m), and S (1),. Run in order. That is, if s ′ is an integer satisfying 2 ≦ s ′ ≦ m, the stage S (s ′) is executed after the stage S (s′−1).

≪Details of Stage S (s) ≫
Details of the stage S (s) will be described with reference to FIGS. However, s is an integer satisfying 1 ≦ s ≦ m. However, FIG. 3 is an example of n = 3, m = 2, and s = 1, and FIG. 4 is an example of n = 3, m = 2, and s = 2.

  First, the calculation unit 1101 (first calculation unit) applies Hadamard calculation to I (k (s)) for s ≦ k (s) ≦ m (step S111-s).

Then calculating unit 1102 (second calculation unit) is, for s ≦ k (s) ≦ m , and control bits _{I (k (s)),} B 1 (k (s), s), ..., B n The (n + 1) -fanout operation with (k (s), s) as the target bit is applied in parallel (step S112-s).

When s ≧ 2, the arithmetic unit 1103 (third arithmetic unit) then sets A _j (k (s)) as a control bit for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, and B _j S-fanout operation with (k (s), 1),..., B _j (k (s), s−1) as target bits is applied in parallel. When s = 1, the calculation unit 1103 does not apply any calculation (step S113-s).

When s = 1, the operation unit 1104 (fourth operation unit) then sets A _j (k (s)) as a control bit for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, and B _j An inverse operation of (s + 1, k (s) -s + 1) -phase shift operation with (k (s), s) as a target bit is applied in parallel. When s ≧ 2, the arithmetic unit 1104 determines that A _j (k (s)) and B _j (k (s), 1),..., B for s ≦ k (s) ≦ m and 1 ≦ j ≦ n. _j (k (s), s-1) is a control bit and B _j (k (s), s) is a target bit. The inverse operation is applied in parallel (step S114-s).

Next, for 1 ≦ j ≦ n, the operation unit 1105 (fifth operation unit) uses X _j as a control bit, and A _j (s), A _j (s + 1),..., A _j (m) as target bits. The (m-s + 2) -fanout operation is applied in parallel (step S115-s).

When s = 1, the operation unit 1106 (sixth operation unit) then sets A _j (k (s)) as a control bit for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, and B _j The (s + 1, k (s) -s + 1) -phase shift operation with (k (s), s) as the target bits is applied in parallel. When s ≧ 2, the calculation unit 1106 determines that A _j (k (s)) and B _j (k (s), 1),..., B for s ≦ k (s) ≦ m and 1 ≦ j ≦ n. (s + 1, k (s) -s + 1) -phase shift operation with _j (k (s), s-1) as control bits and _Bj (k (s), s) as target bits Apply in parallel (step S116-s).

Next, for 1 ≦ j ≦ n, the operation unit 1107 (seventh operation unit) uses X _j as a control bit, and A _j (s), A _j (s + 1),..., A _j (m) as target bits. The (m-s + 2) -fanout calculation is performed (step S117-s: same as step S115-s).

When s ≧ 2, the operation unit 1108 (eighth operation unit) then sets A _j (k (s)) as a control bit for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, and B _j S-fanout operation with (k (s), 1),..., B _j (k (s), s−1) as target bits is applied in parallel. When s = 1, the calculation unit 1108 does not apply any calculation (step S118-s: same as step S113-s).

Then calculating unit 1109 (ninth arithmetic unit) is, for s ≦ k (s) ≦ m , and control bits _{I (k (s)),} B 1 (k (s), s), ..., B n The (n + 1) -fanout operation with (k (s), s) as the target bit is applied in parallel (step S119-s: same as step S112-s).

  Next, the calculation unit 1101 (first calculation unit) applies Hadamard calculation to I (k (s)) for s ≦ k (s) ≦ m (step S120-s: same as step S111-s).

As described above, the states of the m initialization auxiliary qubits I (1),..., I (m) become | φ ₁ >, ..., | φ _m > (the reason will be described later).

<Details of Step S2>
Details of step 2 will be described with reference to FIGS. However, FIG. 5 is an example of n = 3 and m = 2.

  After step S1 described above, first, the calculation unit 1211 (the eleventh calculation unit) applies the NOT calculation X to I (k) in parallel for 1 ≦ k ≦ m (step S21).

Next, the arithmetic unit 1212 (the twelfth arithmetic unit) applies (m + 1) -Toffoli arithmetic in parallel with I (1),..., I (m) as control bits and Y as a target bit. The (m + 1) -Toffoli operation can be calculated by a quantum circuit obtained by removing the NOT operation of the first and last calculation steps from the quantum circuit that calculates the logical sum function x ₁ ∨... ∨x _n (where n = m). (For example, refer nonpatent literature 1). Such a quantum circuit uses one uninitialized auxiliary qubit, but any qubit other than the control bit and target bit of the (m + 1) -Toffoli operation (for example, input qubit X ₁ ) Should correspond to this uninitialized auxiliary qubit (step S22).

  Next, the calculation unit 1213 (the thirteenth calculation unit) applies the NOT calculation X to Y, and in parallel with this, performs the same calculation as step S21, that is, the NOT calculation X to I (k) for 1 ≦ k ≦ m. Apply (step S23).

  Next, the calculation unit 1214 (fourteenth calculation unit) applies the reverse calculation RS (m),..., RS (1) of the stages S (1),. However, the inverse operation RS (s) is an inverse operation of the stage S (s), and the inverse operation RS (s′−1) of the inverse operation RS (s ′) is an integer s ′ that satisfies 2 ≦ s ′ ≦ m. Will be executed later. That is, the quantum circuit starting from the quantum circuit that executes the inverse operation RS (m) of the stage S (m) is applied in order to the quantum circuit that executes the inverse operation RS (1) of the stage S (1). The quantum circuit that executes the inverse operation RS (s) of each stage S (s) is obtained by replacing each gate with its inverse operation in the quantum circuit of each stage S (s) and reversing the order of application. is there. Each inverse operation of H and CNOT is itself. Also, note that the inverse operation of the inverse operation for a certain operation is the original operation (step S24).

The NOT operation X to be applied to Y in operation and step 23 to step _{S22, | φ 1>, ...} , | φ m> logical sum is calculated with respect to, Y is the logical sum _{x 1} ∨ ... _{∨x n} The state to be expressed is | y (+) x ₁ ∨... 表 す x _n >. In step S23, the same operation as in step S21 is applied to return the state of I (k) to | φ _k >, and the states of qubits other than Y are changed to the output state of step S1. Return. Accordingly, in step 24, the state of the qubits other than Y is returned to the initial state. Note that step S1 applies no operation to Y.

<Reason why | φ ₁ >,..., | Φ _m > is correctly generated in Step S1>
The reason why | φ ₁ >,..., | Φ _m > is correctly generated in step S1 will be described. For simplicity, the case of n = 3 (and hence m = 2) will be described.

ただし、α＝−ａ_１（１）（１−２ｂ_１（１，１））−ａ_２（１）（１−２ｂ_２（１，１））−ａ_３（１）（１−２ｂ_３（１，１））である。さらにステップＳ１１６−ｓ終了後、状態は次のようになる。

ただし、β＝ｘ_１−２（ａ_１（１）（＋）ｂ_１（１，１））ｘ_１＋ｘ_２−２（ａ_２（１）（＋）ｂ_２（１，１））ｘ_２＋ｘ_３−２（ａ_３（１）（＋）ｂ_３（１，１））ｘ_３である。さらに、ステージＳ（１）（ステップＳ１１−１）終了後、状態は次のようになる。

ここで、βの中の２の倍数の項が

の値に影響しないことに注意する。実際、

であり、βの中の２の倍数である他の項も同様に計算され、

となる。従って、式（４）の最終状態は次と等しい。

これは所望の量子状態

である（式（２））。 About ≪ ｜ φ ₁ ≫
As illustrated in FIG. 3, the preparation of | φ ₁ > is completed at stage S (1) (step S11-1). For simplicity, only the state changes of I (1) and B ₁ (1,1), B ₂ (1,1), B ₃ (1,1) are described. These initial states are | 0> | b ₁ (1,1)> | b ₂ (1,1)> | b ₃ (1,1)>. After step S114-s, the state is as follows. become.

However, α = −a ₁ (1) (1-2b ₁ (1,1))-a ₂ (1) (1-2b ₂ (1,1))-a ₃ (1) (1-2b ₃ ( 1, 1)). Further, after step S116-s ends, the state becomes as follows.

However, β = x ₁ -2 (a ₁ (1) (+) b ₁ (1,1)) x ₁ + x ₂ -2 (a ₂ (1) (+) b ₂ (1,1)) x ₂ + X ₃ -2 (a ₃ (1) (+) b ₃ (1,1)) x ₃ . Further, after stage S (1) (step S11-1), the state is as follows.

Where the term of multiples of 2 in β is

Note that it does not affect the value of. In fact,

And the other terms that are multiples of 2 in β are computed similarly,

It becomes. Therefore, the final state of equation (4) is equal to:

This is the desired quantum state

(Equation (2)).

ただし、η＝ｘ_１−２（ａ_１（２）（＋）ｂ_１（２，１））ｘ_１＋ｘ_２−２（ａ_２（２）（＋）ｂ_２（２，１））ｘ_２＋ｘ_３−２（ａ_３（２）（＋）ｂ_３（２，１））ｘ_３である。｜φ_１〉の場合と異なり、ηの中の２の倍数の項が

の値に影響しないとは言えないことに注意する。これは、ｅの指数部分の値の分母が２ではなく、２^２であるからである。ステージＳ（２）（ステップＳ１１−２）による状態変化は、ステージＳ（１）（ステップＳ１１−１）と同様であり、Ｉ（２）の状態は次のようになる。

ただし、δ＝ｘ_１−２^２（ａ_１（２）（＋）ｂ_１（２，１））（ａ_１（２）（＋）ｂ_１（２，２））ｘ_１＋ｘ_２−２^２（ａ_２（２）（＋）ｂ_２（２，１））（ａ_２（２）（＋）ｂ_２（２，２））ｘ_２＋ｘ_３−２^２（ａ_３（２）（＋）ｂ_３（２，１））（ａ_３（２）（＋）ｂ_３（２，２））ｘ_３である。δの中の２^２の倍数の項が

の値に影響しないことは、｜φ_１〉を用意する場合に、βの中の２の倍数の項が

の値に影響しなかったことと同様である。従って、この状態は所望の状態

と等しい。 About ≪ ｜ φ ₂ ≫
As illustrated in FIGS. 3 and 4, | φ ₂ > is completely prepared in stages S (1) (step S11-1) and S (2) (step S11-2). The state change by stage S (1) (step S11-1) is the same as in the case of | φ ₂ >, and the state of I (2) after stage S (1) is as follows.

However, η = x ₁ -2 (a ₁ (2) (+) b ₁ (2,1)) x ₁ + x ₂ -2 (a ₂ (2) (+) b ₂ (2,1)) x ₂ + X ₃ −2 (a ₃ (2) (+) b ₃ (2,1)) x ₃ . Unlike the case of | φ ₁ >, the term of multiples of 2 in η is

Note that this does not affect the value of. This is not the denominator 2 of the value of the exponent part of e, because a 2 ^2. The state change by stage S (2) (step S11-2) is the same as that of stage S (1) (step S11-1), and the state of I (2) is as follows.

However, δ = x ₁ −2 ² (a ₁ (2) (+) b ₁ (2,1)) (a ₁ (2) (+) b ₁ (2,2)) x ₁ + x ₂ −2 ² (A ₂ (2) (+) b ₂ (2,1)) (a ₂ (2) (+) b ₂ (2,2)) x ₂ + x ₃ −2 ² (a ₃ (2) (+) _{b 3 (2,1)) (a} 3 (2) (+) b 3 (2,2)) is _{x 3.} The term of multiple of ^{2 in} δ is

Does not affect the value of, when | φ ₁ > is prepared, the term of multiples of 2 in β

This is the same as not affecting the value of. Therefore, this state is the desired state

Is equal to

<Number of auxiliary qubits and calculation steps>
As described above, the quantum circuit for calculating the logical sum function of this embodiment has m = ceil (log ₂ (n + 1)) = O (logn) initialization auxiliary qubits, and nm (m + 3) / 2 = It has O (n (log ₂ n) ² ) uninitialized auxiliary qubits.

Consider the number of calculation steps of this quantum circuit. For an arbitrary 1 ≦ s ≦ m, the number of calculation steps of the stage S (s) is as follows.
Step S111-s: 1
Step S112-s: O (log ₂ (n + 1))
Step S113-s: O (log ₂ s)
Step S114-s: O (s + 1)
Step S115-s: O (log ₂ (ms + 2))
Steps S116-s to S120-s: Same as Steps S111-s to S115-s Since s ≦ m = O (log ₂ n), the number of steps in the stage S (s) is O (log ₂ n). Thus, the number of steps in step S1 is O (mlog ₂ n) = O ((log ₂ n) ² ).

Step S2 is as follows.
Step S21: 1
Step 22: O (m + 1)
Step 23: 1
Step 24: Same as Step S1 Accordingly, the number of calculation steps in Step S2 is O ((log ₂ n) ² ), and the number of steps in the whole quantum circuit of this embodiment is O ((log ₂ n) ² ). Become.

<Features of this embodiment>
It is physically difficult to realize a large number of initialization auxiliary qubits, but it is easier to realize a large number of uninitialized auxiliary qubits compared to initialization auxiliary qubits. Also, the calculation time becomes longer as the number of calculation steps of the quantum circuit is larger. Therefore, in order to achieve high physical feasibility and short calculation time at the same time, it is better to reduce the number of initialization auxiliary qubits and the number of calculation steps at the same time, even if many uninitialized auxiliary qubits are used. Good. Even if many uninitialized auxiliary qubits are used, the number of initialized auxiliary qubits and the number of calculation steps are simultaneously expressed by a logarithmic polynomial (O ((log ₂ n) ^c ), where c is a constant greater than or equal to 0). A method for constructing such a small quantum circuit has not been known.

In the quantum circuit of this embodiment, O (n (log ₂ n) ² ) uninitialized auxiliary qubits and O (log ₂ n) initialized auxiliary qubits are used, and O ((log ₂ n) ² ) Calculate the logical sum function in one calculation step. Thereby, high physical feasibility and short calculation time can be realized simultaneously.

[Other variations]
In addition, this invention is not limited to the above-mentioned embodiment. The various processes described above are not only executed in time series according to the description, but may also be executed in parallel or individually as required by the processing capability of the apparatus that executes the processes. Needless to say, other modifications are possible without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 OR operation apparatus 11 Quantum operation part 12 Quantum operation part

Claims (8)

n is an integer of 2 or more, w is an integer satisfying 1 ≦ w ≦ n, x _w ε {0, 1}, | x | = x ₁ +... + x _n , ceil (·) Is the ceiling function of (·), m = ceil (log ₂ (n + 1)), k is an integer satisfying 1 ≦ k ≦ m,
N input qubits X ₁ ,..., X _n whose initial state is | x ₁ >,..., | X _n >, one output qubit Y whose initial state is | y>, and initialization auxiliary quanta. Bit, and uninitialized auxiliary qubit,

A first quantum operation unit that generates a state represented by | φ _k >;
The state | φ _1> ... | from φ _m> φ _{1, ...,} a second quantum computing section for generating a state representing a logical sum of phi _m,
A logical sum operation device. The logical sum operation device according to claim 1,
An OR operation device, wherein n is an integer of 3 or more. The logical sum operation device according to claim 1 or 2,
I (1),..., I (m) are m initialization auxiliary qubits, and a set of nm (m + 3) / 2 uninitialized auxiliary qubits is a subset A (1), , A (m), B (1),..., B (m), and the subset A (k) includes n uninitialized auxiliary qubits A ₁ (k) _,. k), and the subset B (k) is composed of k subsets B (k, 1),..., B (k, k), and r is an integer satisfying 1 ≦ r ≦ k, A subset B (k, r) consists of n said uninitialized auxiliary qubits B ₁ (k, r),..., B _n (k, r);
The first quantum arithmetic unit includes first to tenth arithmetic units, executes m stages S (1),..., S (m), and s is an integer satisfying 1 ≦ s ≦ m, s ′ is an integer satisfying 2 ≦ s ′ ≦ m, and the stage S (s ′) is executed after the stage S (s′−1),
The initial states of the initialization auxiliary qubits I (1),..., I (m) are | 0>,..., | 0>, and the uninitialized auxiliary qubits A ₁ (k) _,. The initial state of (k) is | a ₁ (k)>,..., | _An (k)>, and the uninitialized auxiliary quantum bits B ₁ (k, r),..., B _n (k, r ) Is the initial state of | b ₁ (k, r)>,..., | B _n (k, r)>,
In the stage S (s),
The first calculation unit applies Hadamard calculation to I (k (s)) for s ≦ k (s) ≦ m;
The second calculation unit for s ≦ k (s) ≦ m , and control bits _{I (k (s)),} B 1 (k (s), s), ..., B n (k (s), Perform (n + 1) -fanout operation with s) as the target bit,
When the third arithmetic unit is s ≧ 2, for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, A _j (k (s)) is a control bit, and B _j (k (s) , 1),..., B _j (k (s), s−1) is used as a target bit to perform an s-fanout operation,
The fourth arithmetic unit is
When s = 1, for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, A _j (k (s)) is a control bit and B _j (k (s), s) is a target bit. (S + 1, k (s) -s + 1)-reverse the phase shift operation,
When s ≧ 2, for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, A _j (k (s)) and B _j (k (s), 1),..., B _j (k ( s), s-1) are control bits, and B _j (k (s), s) is a target bit. ,
In the fifth arithmetic unit, for 1 ≦ j ≦ n, X _j is a control bit and A _j (s), A _j (s + 1),..., A _j (m) is a target bit (m−s + 2) Perform -fanout operation,
The sixth arithmetic unit is
When s = 1, for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, A _j (k (s)) is a control bit and B _j (k (s), s) is a target bit. (S + 1, k (s) -s + 1) -phase shift operation,
When s ≧ 2, for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, A _j (k (s)) and B _j (k (s), 1),..., B _j (k ( (s + 1, k (s) -s + 1) -phase shift operation with s), s-1) as control bits and B _j (k (s), s) as target bits,
In the case where 1 ≦ j ≦ n, the seventh arithmetic unit uses X _j as a control bit and A _j (s), A _j (s + 1),..., A _j (m) as target bits (m−s + 2) Perform -fanout operation,
When the eighth arithmetic unit is s ≧ 2, for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, A _j (k (s)) is a control bit, and B _j (k (s) , 1),..., B _j (k (s), s−1) is used as a target bit to perform an s-fanout operation,
Said ninth computing unit for s ≦ k (s) ≦ m , and control bits _{I (k (s)),} B 1 (k (s), s), ..., B n (k (s), Perform (n + 1) -fanout operation with s) as the target bit,
The tenth operation unit applies a Hadamard operation to I (k (s)) for s ≦ k (s) ≦ m. The logical sum operation device according to claim 3,
The second quantum operation unit includes eleventh to fourteen operation units,
The eleventh operation unit applies a NOT operation to I (k) for 1 ≦ k ≦ m,
The twelfth calculation unit applies (m + 1) -Toffoli calculation with I (1),..., I (m) as control bits and Y as a target bit,
The thirteenth operation unit applies a NOT operation to I (k) and Y for 1 ≦ k ≦ m,
The fourteenth operation unit performs inverse operations RS (m), ..., RS (1),
The inverse operation RS (s) is an inverse operation of the stage S (s), and the inverse operation RS (s′−1) is executed after the inverse operation RS (s ′). n is an integer of 2 or more, w is an integer satisfying 1 ≦ w ≦ n, x _w ε {0, 1}, | x | = x ₁ +... + x _n , ceil (·) Is the ceiling function of (·), m = ceil (log ₂ (n + 1)), k is an integer satisfying 1 ≦ k ≦ m,
The first quantum operation unit has n input qubits X ₁ ,..., X _n whose initial state is | x ₁ >,..., | X _n >, and one output quantum whose initial state is | y>. Using bit Y, initialized auxiliary qubit, and uninitialized auxiliary qubit,

A first quantum operation step for generating a state | φ _k > represented by:
Second quantum computation unit, the state | φ _1> ... | from φ _m> φ _{1, ...,} a second quantum computation step of generating a state representing a logical sum of phi _m,
A logical sum operation method. The logical sum operation method according to claim 5,
A logical OR operation method, wherein n is an integer of 3 or more. A logical sum operation method according to claim 5 or 6,
I (1),..., I (m) are m initialization auxiliary qubits, and a set of nm (m + 3) / 2 uninitialized auxiliary qubits is a subset A (1), , A (m), B (1),..., B (m), and the subset A (k) includes n uninitialized auxiliary qubits A ₁ (k) _,. k), and the subset B (k) is composed of k subsets B (k, 1),..., B (k, k), and r = 1,. (K, r) consists of n said uninitialized auxiliary qubits B ₁ (k, r),..., B _n (k, r),
The first quantum arithmetic unit includes first to tenth arithmetic units, executes m stages S (1),..., S (m), and s is an integer satisfying 1 ≦ s ≦ m, s ′ is an integer satisfying 2 ≦ s ′ ≦ m, and the stage S (s ′) is executed after the stage S (s′−1),
The initial states of the initialization auxiliary qubits I (1),..., I (m) are | 0>,..., | 0>, and the uninitialized auxiliary qubits A ₁ (k) _,. The initial state of (k) is | a ₁ (k)>,..., | _An (k)>, and the uninitialized auxiliary quantum bits B ₁ (k, r),..., B _n (k, r ) Is the initial state of | b ₁ (k, r)>,..., | B _n (k, r)>,
In the stage S (s),
The first calculation unit applies Hadamard calculation to I (k (s)) for s ≦ k (s) ≦ m;
The second calculation unit for s ≦ k (s) ≦ m , and control bits _{I (k (s)),} B 1 (k (s), s), ..., B n (k (s), Perform (n + 1) -fanout operation with s) as the target bit,
When the third arithmetic unit is s ≧ 2, for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, A _j (k (s)) is a control bit, and B _j (k (s) , 1),..., B _j (k (s), s−1) is used as a target bit to perform an s-fanout operation,
The fourth arithmetic unit is
When s = 1, for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, A _j (k (s)) is a control bit and B _j (k (s), s) is a target bit. (S + 1, k (s) -s + 1)-reverse the phase shift operation,
When s ≧ 2, for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, A _j (k (s)) and B _j (k (s), 1),..., B _j (k ( s), s-1) are control bits, and B _j (k (s), s) is a target bit. ,
In the fifth arithmetic unit, for 1 ≦ j ≦ n, X _j is a control bit and A _j (s), A _j (s + 1),..., A _j (m) is a target bit (m−s + 2) Perform -fanout operation,
The sixth arithmetic unit is
When s = 1, for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, A _j (k (s)) is a control bit and B _j (k (s), s) is a target bit. (S + 1, k (s) -s + 1) -phase shift operation,
When s ≧ 2, for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, A _j (k (s)) and B _j (k (s), 1),..., B _j (k ( (s + 1, k (s) -s + 1) -phase shift operation with s), s-1) as control bits and B _j (k (s), s) as target bits,
In the case where 1 ≦ j ≦ n, the seventh arithmetic unit uses X _j as a control bit and A _j (s), A _j (s + 1),..., A _j (m) as target bits (m−s + 2) Perform -fanout operation,
When the eighth arithmetic unit is s ≧ 2, for s ≦ k (s) ≦ m and 1 ≦ j ≦ n, A _j (k (s)) is a control bit, and B _j (k (s) , 1),..., B _j (k (s), s−1) is used as a target bit to perform an s-fanout operation,
Said ninth computing unit for s ≦ k (s) ≦ m , and control bits _{I (k (s)),} B 1 (k (s), s), ..., B n (k (s), Perform (n + 1) -fanout operation with s) as the target bit,
The tenth operation unit applies a Hadamard operation to I (k (s)) for s ≦ k (s) ≦ m. The logical sum operation method according to claim 7,
The second quantum operation unit includes eleventh to fourteen operation units,
The eleventh operation unit applies a NOT operation to I (k) for 1 ≦ k ≦ m,
The twelfth calculation unit applies (m + 1) -Toffoli calculation with I (1),..., I (m) as control bits and Y as a target bit,
The thirteenth operation unit applies a NOT operation to I (k) and Y for 1 ≦ k ≦ m,
The fourteenth operation unit performs inverse operations RS (m), ..., RS (1),
The inverse operation RS (s) is an inverse operation of the stage S (s), and the inverse operation RS (s′−1) is executed after the inverse operation RS (s ′).

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