JP6441251B2 - Integrated circuit - Google Patents

Description

  Embodiments described herein relate generally to an integrated circuit.

  The programmable logic switch is an element that is used in an FPGA (Field Programmable Gate Array) or the like that needs to reconfigure a logic operation circuit or a wiring circuit, and switches the logic switch on and off based on data held in a memory. Conventionally, a volatile memory such as an SRAM is used as the memory. Since this volatile memory loses data when the power is turned off, it is necessary to write the data to the memory again when the power is supplied.

  As one of the architectures of the FPGA, there is one in which wiring for connection to a logic block or the like is an antifuse. Unlike an FPGA using an SRAM or the like, data cannot be rewritten, but an unexpected data change can be prevented by using an OTP (One Time Programmable) memory element.

  For example, the configuration of a cross-point type array using transistors as OTP memory elements includes a gate control line to which the gates of memory elements arranged in the same row are connected, and sources and drains of transistors arranged in the same column. The active area line to be connected has a cross structure, and a write pulse is applied from one end of the gate control line via a high-voltage PMOS transistor, and 0 V is applied via a column selection transistor connected to the active area line of the memory element to be written. Put in. At this time, since the write voltage Vprg is applied to the source terminal of the row selection transistor connected to the other end of the gate control line, there is a possibility that the lifetime of the row selection transistor is shorter than that of a transistor that performs a normal logic operation. is there.

  There is known a redundancy structure in which when a memory element is erroneously destroyed, the memory element in the column to which the memory element belongs is discarded and replaced with an extra prepared column of memory elements. In this memory having a redundancy structure, even if a defective row selection transistor remains connected to a memory column, the row selection transistor can be used even when there is a read signal deterioration or two or more defective row selection transistors due to leakage. There is a possibility that an erroneous read path is formed through the gate line, causing malfunction.

US Patent Application Publication No. 2011/0298054 US Patent Application Publication No. 2007/0183181

  The present embodiment provides an integrated circuit including a memory circuit that can suppress malfunction.

  The integrated circuit according to the present embodiment is arranged in a plurality of first wirings, a plurality of second wirings intersecting with the plurality of first wirings, and an intersection region of the first wiring and the second wiring, A plurality of memory elements having a first terminal and a second terminal, wherein the first terminal is electrically connected to a corresponding first wiring, and the second terminal is electrically connected to a corresponding second wiring. And a plurality of fuse elements arranged corresponding to the plurality of second wirings, each having a third terminal and a fourth terminal, the second terminal corresponding to the third terminal. A plurality of fuse elements electrically connected to each other and a plurality of first transistors arranged corresponding to the plurality of fuse elements, wherein one of the source and drain of the first transistor corresponds to the first of the fuse elements. Electrically connected to 4 terminals It includes a plurality of first transistors, and a third wiring which is electrically connected to a gate of said plurality of first transistors, and a current detection circuit for detecting a current flowing through the third wiring.

1 is a circuit diagram showing an integrated circuit according to a first embodiment. The figure which shows an example of the voltage applied to the wiring at the time of the write-in operation | movement in the integrated circuit of 1st Embodiment, read-out operation, and the fracture | rupture operation | movement of a fuse element. The flowchart which shows the isolation | separation direction of a defective transistor. The flowchart which shows the isolation | separation method of a defective transistor. A circuit diagram explaining write-in operation in an integrated circuit of a 2nd embodiment. A circuit diagram explaining reading operation in an integrated circuit of a 2nd embodiment. The circuit diagram explaining the fracture | rupture operation | movement of the fuse element in the integrated circuit of 2nd Embodiment. The top view which shows an example of the fuse element used in the integrated circuit of 2nd Embodiment. A circuit diagram showing an integrated circuit by a 3rd embodiment. A circuit diagram explaining write-in operation in an integrated circuit of a 3rd embodiment. A circuit diagram explaining read-out operation in an integrated circuit of a 3rd embodiment. The circuit diagram explaining the fracture | rupture operation | movement of the fuse element in the integrated circuit of 3rd Embodiment. The top view which shows an example of the fuse element used in the integrated circuit of 3rd Embodiment. The top view which shows the 1st example of the layout of the fuse element in the integrated circuit of 3rd Embodiment. The top view which shows the 2nd example of the layout of the fuse element in the integrated circuit of 3rd Embodiment. The top view which shows the 3rd example of the layout of the fuse element in the integrated circuit of 3rd Embodiment. A circuit diagram showing an integrated circuit by a 4th embodiment. A circuit diagram explaining write-in operation in an integrated circuit of a 4th embodiment. A circuit diagram explaining read-out operation in an integrated circuit of a 4th embodiment. The circuit diagram explaining the fracture | rupture operation | movement of the fuse element in the integrated circuit of 4th Embodiment. The circuit diagram which shows the 2nd example of a current detection circuit. The circuit diagram which shows the 3rd example of a current detection circuit. Sectional drawing which shows a resistance change memory element.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
An integrated circuit according to the first embodiment is shown in FIG. The integrated circuit according to the first embodiment is used in, for example, a memory array circuit of a multi-input multi-output MUX (multiplexer) circuit, and includes a memory array having memory elements 10 ₁₁ to 10 ₃₃ arranged in a 3 × 3 array. It has. Each memory element 10 _ij (i, j = 1, 2, 3) is a MOS transistor. The memory cells 10 _1j , 10 _2j , and 10 _3j in the j-th (j = 1, 2, 3) column have their sources and drains connected to the wiring 20 _j , respectively. The wiring 20 _j (j = 1, 2, 3) is connected to the input terminal of the inverter 22 _j via the column selection transistor 24 _j . The inverter 22 _j (j = 1, 2, 3) has an input terminal connected to the word line WL _j . The column selection transistor 24 _j (j = 1, 2, 3) has a gate connected to the wiring 25.

The gates of the memory elements 10 _i1 , 10 _i2 , 10 _{i3 in the} i-th (i = 1, 2, 3) row are connected to the wiring 30 _i . One end of the wiring 30 _i (i = 1, 2, 3) is connected to the drain of the high breakdown voltage p-channel MOS transistor 32 _i , and the other end is connected to one terminal of the fuse element 34 _i . The transistor 32 _i (i = 1, 2, 3) has a source connected to the bit line BL _i and a gate connected to the wiring 33. The other terminal of the fuse element 34 _i (i = 1, 2, 3) is connected to the source of the row selection transistor 36 _i . The row selection transistor 36 _i (i = 1, 2, 3) has a drain connected to the input terminal of the inverter 38 _i and a gate connected to the wiring 37. The output terminal of the inverter 38 _i (i = 1, 2, 3) is connected to the output wiring Out _i .

The word lines WL _{1 to} WL ₃ and the wiring 25 are driven by a driver 42, and the bit lines BL _{1 to} BL ₃ and the wirings 33 and 37 are driven by a driver 46. In the present embodiment, a current detection circuit 50 and a control circuit 60 are provided, and the current detection circuit 50 detects a current flowing through the wiring 37. The control circuit 60 controls the driver 42 and the driver 46 to perform a write operation or a read operation, finds a defective row selection transistor based on the result detected by the current detection circuit 50, and selects the defective row. The fuse element connected to the transistor is broken.

(Write operation)
Writing, the case of writing to the memory device 10 ₁₁ for example. In this case, the driver 46 applies the voltage Von1 to the wiring 33 to turn on the transistors 32 _{1 to} 32 ₃ . Further, the driver 42 applies the voltage Von2 to the wiring 25 to turn on the column selection transistors 24 _{1 to} 24 ₃ . Further, the driver 46 applies a voltage Von3 to the wiring 37 to turn on the row selection transistors 36 _{1 to} 36 ₃ . In this state, applying a write voltage (program voltage) Vprg to the bit line BL _1, applying a respective write inhibit voltage Vinh1 to the bit line _BL 2, BL _3. Further, 0V to the wiring 20 _1, lines ₂₀ 2, as the 20 ₃ write inhibit voltage Vinh1 is applied, the driver 42 drives the word line WL1, the word line WL _2, and the word line WL _3. Thus, the gate of the memory device 10 ₁₁ for writing, between the source and drain, the write voltage Vprg is applied, writing is performed. On the other hand, a voltage (= Vprg−Vinh1) lower than the program voltage Vprg is applied between the respective gates of the memory elements 10 ₁₂ , 10 ₁₃ and the respective sources and drains, and the memory elements 10 ₂₁ , A voltage (Vinh1) lower than the program voltage Vprg is applied between the respective gates of 10 ₃₁ and the respective sources and drains, and the gates and the sources of the memory elements 10 ₂₂ , 10 ₂₃ , 10 ₃₂ , 10 ₃₃ A voltage (0 V) lower than the program voltage is applied between the drain and the drain, and writing is not performed. An example of the applied voltage at this time is shown in FIG. In the integrated circuit of this embodiment, as in the case of the memory element in the first row, writing is performed in at most one memory element in the memory element in the second row and the memory element in the third row.

(Read operation)
When reading is performed, the driver 46 applies a voltage Voff1 to the wiring 33 to turn off the transistors 32 _{1 to} 32 ₃ . Further, the driver 42 applies the voltage Von2 to the wiring 25 to turn on the column selection transistors 24 _{1 to} 24 ₃ . Further, the driver 46 applies a voltage Von3 to the wiring 37 to turn on the row selection transistors 36 _{1 to} 36 ₃ . The voltage applied to the bit lines BL ₁ , BL ₂ , and BL ₃ is Voff ₁ , and Voff ₁ is also applied to the substrates of the transistors 32 _{1 to} 32 ₃ . In this state, the driver 42 drives the word lines WL ₁ , WL ₂ , and WL ₃ , applies read voltages Vread ₁ , Vread ₂ , and Vread ₃ to the wirings 20 ₁ , 20 ₂ , and 20 ₃ , respectively, and performs reading. An example of the applied voltage at the time of reading is shown in FIG. Read signal is sent from the memory element fuse element ₃₄ 1-34 _3, the row select transistor ₃₆ 1-36 _3, and the inverter ₃₈ 1-38 ₃ through the output line _{Out 1, Out 2, Out 3} .

In the integrated circuit of the thus-configured present embodiment, the current detection circuit 50 for detecting a current flowing through the wiring 37 connected to the gate of the row select transistor 36 _{1-36 3} provided further row select transistor 36 ₁ to 36 _{by 3} to connect to the drains provided fuse elements ₃₄ 1 to 34 _3, the row select transistor ₃₆ 1 to 36 integrated circuits to not use the line containing the row select transistor caused bad of ₃ It has been separated from.

Here, the memory element of the integrated circuit is an OTP memory element by a transistor using oxide film destruction. In this case, the wirings 30 ₁ to 30 ₃ and the wirings 20 _{1 to} 20 ₃ intersect with each other, and a cross point structure in which a memory element is provided in the intersecting region is obtained. A write pulse (write voltage) is applied from one end of each of the wirings 30 ₁ to 30 ₃ via high-breakdown-voltage p-channel MOS transistors 32 _{1 to} 32 ₃ to write information, for example, the wiring 20 of the memory element 10 ₁₁ put a 0V through the column select transistor 24 ₁ to _1. At this time, the write voltage Vprg is applied to the source terminal of the transistor 32 ₁ is connected to the other end of the wiring 30 _1, the row select transistor 36 ₁ of life than transistor for normal logic operation is shorter Is concerned. As defects may occur at this time, there is a current leakage between the gate and the source of the row select transistor 36 _1. If it remains causing the failure is row select transistor 36 ₁ is connected to the memory column, the readout signal degradation by current leakage, or the row selection if there is more than one defective row select transistor transistor 36 ₁ There is a possibility that an erroneous read path is formed through the gate line, causing malfunction. From this background, in this embodiment, the defective row selection transistor is separated.

  There are two cases in which the defective transistor is separated: a) when the presence or absence of aging is confirmed at the time of reading, and b) when the breakdown that occurs at the time of writing is detected.

  First, a procedure for confirming the presence or absence of aged deterioration at the time of reading will be described with reference to FIG. The presence or absence of this aging is performed every certain period.

In this case, the voltage Von3 is applied by the driver 46 to the wiring 37 to which each gate is connected so that the row selection transistors 36 _{1 to} 36 ₃ are turned on at the time of reading. For example, writing is performed to the three OTP memory elements _{10 11,} 10 22, _{20 33,} and current leakage occurs due to aging between the gate and the source of the row select transistor 36 _2. In this case, to confirm the presence or absence of current increase in current detection circuit 50 for monitoring the current value provided to the gate line 37 of the row select transistor 36 ₂ (steps S1, S2 in FIG. 3). Here, if the detected current value is equal to that before writing or the signal level is equivalent to that when the read signal is turned off, the process proceeds to step S3 and normal operation is performed. However, if an increase in leakage current is found from this detection result, the leakage location is identified (step S4). The defective part can be identified by sequentially performing the reading paths one by one.

In the present embodiment, since the number of output terminals (that is, the number of row selection transistors 36 _{1 to} 36 ₃ ) is three, the destruction location of the row selection transistors 36 _{1 to} 36 ₃ is specified through three paths. Perform the operation. For example, when performing a check as to the presence of a row select transistor 36 ₁ defect, since the memory element 10 ₁₁ has been performed a write inputs an input signal to the word line WL _1, the other word lines WL ₂ , WL ₃ are left floating. Further, the output wiring Out ₁ is set to 0 V, and the other output wirings Out ₂ and Out ₃ are set to be floating. Thus, the presence or absence of the row select transistor 36 ₁ defect, i.e. confirmation of the presence or absence of leakage current takes place.

The transistors 36 ₂ and 36 ₃ are similarly checked for the presence or absence of leakage current. Failure of the transistors in the process so far, for example, the row select transistor 36 ₂ is identified.

Subsequently, in order to disable the transistor 36 ₂ defective, for blocking the signal path between the word line WL ₂ and the output terminal Out _2, row-direction ends of the memory array and a row select transistor 36 ₂ cut fuse element 34 ₂ in the source terminal (step S5 in FIG. 3). An example of the applied voltage at this time is shown in FIG. That is, if to break the fuse element 34 _2, the voltage Von1 is applied to the wiring 33 by the driver 46, to turn on the transistors ₃₂₁ to 323. Further, the driver 42 applies a voltage Von2 to the wiring 25 to turn on the column selection transistors 24 _{1 to} 24 ₃ . Further, the voltage applied to the wiring 37 by the driver 46 is set to 0 V, and the row selection transistors 36 _{1 to} 36 ₃ are turned off. Further, a voltage Vf_break applied bit line BL ₂ by the driver 46, the other bit line _BL 1, BL ₃ and floating. On the other hand, the driver 42 drives the word lines WL1, WL2, and WL3, and applies the write inhibit voltage Vinh2 to the wirings 20 ₁ , 20 ₂ , and 20 ₃ , respectively. Thus, the voltage Vf_break is applied to the fuse element 34 _2, are broken.

Then, after failure of the row select transistor, the fuse element 34 _2, for example the row selection transistor 36 ₂ is connected broken, the process returns to step S1, performs normal read operation, flows through the gate wiring line select transistor at this time The current is monitored again to determine whether or not it is a normal value (steps S1 and S2 in FIG. 3). If it is a normal value, it shifts to a normal operation mode (step S3 in FIG. 3). If there is still a problem, identification of the defective row selection transistor is performed again (step S4 in FIG. 3). This checking procedure can be used regardless of the scale of the multi-input multi-output MUX circuit, and can also cope with a case where there are a plurality of defective row selection transistors.

  Next, with reference to FIG. 4, a procedure for detecting destruction that occurs during writing will be described.

Writing to the memory element is performed row by row, and the gate current of the row direction selection transistor at this time is monitored by the current detection circuit 50 (step S11 in FIG. 4). It is determined whether or not the detected current is normal (step S12). If normal, the process returns to step S11 to perform the next writing. If the detected current is not normal, it is determined that the row selection transistor in the same row as the memory element that performed writing when the leakage current increases, and the fuse element in the row to which the row selection transistor is connected is broken ( Step S12 in FIG. For example, writes to the second row of the memory device 10 _22, this time the leakage current If detected by the current detecting circuit 50 to have increased, breaking the fuse element 34 _2. The fuse element is broken in the same manner as described above. Then, return to step S11 and repeat the same operation,
Therefore, a flow of finding a row having a defective transistor is unnecessary as compared with the flow executed at the time of reading.

  Also, the fuse breakage does not change due to the difference in timing for specifying the position of the failure selection transistor. Any flow can be similarly implemented.

  Examples of the fuse element used here are shown in FIGS. FIG. 3 shows a four-terminal control fuse, and FIG. 4 shows a two-terminal control fuse. The case of using the four-terminal control fuse shown in FIG. 3 will be described later. Further, the two-terminal fuse shown in FIG. 4 is illustrated here assuming a poly-Si fuse, but a metal fuse, a diode junction breakdown, or the like is also possible.

  As described above, according to the first embodiment, the memory element in the row to which the defective row selection transistor is connected can be separated from the memory element array, and the memory circuit that can suppress malfunction is provided. Integrated circuits can be provided.

In the first embodiment and each embodiment described later, the gate of the memory element is connected to a corresponding wiring among the wirings 30 ₁ to 30 ₃ , and the source and drain are correspondences among the wirings 20 _{1 to} 20 _3. Was connected to the wiring. The gate may be connected to the corresponding wiring among the wirings 30 ₁ to 30 ₃ , and one of the source and the drain may be connected to the corresponding wiring among the wirings 20 _{1 to} 20 ₃ . The gate may be connected to a corresponding wiring among the wirings 20 _{1 to} 20 ₃ , and one of the source and the drain may be connected to a corresponding wiring among the wirings 30 ₁ to 30 ₃ .

(Second Embodiment)
An integrated circuit according to the second embodiment will be described with reference to FIGS. FIG. 5 is a diagram for explaining a write operation in the integrated circuit of the second embodiment, FIG. 6 is a diagram for explaining a read operation, FIG. 7 is a diagram for explaining an operation for breaking the fuse element, and FIG. 8 is an example of the fuse element. FIG. The integrated circuit of the second embodiment has a configuration in which the current detection circuit 50 is replaced with a current detection circuit 50A in the integrated circuit of the first embodiment shown in FIG. In FIGS. 5 to 7, the drivers 42 and 46 shown in FIG. 1 are not shown in order to simplify the description.

  The current detection circuit 50A includes a resistor 52 arranged in series with the wiring 37, an amplifier circuit 54 that detects and amplifies the potential difference between both ends of the resistor 52, and a reference value based on the potential difference detected by the amplifier circuit 54. And a comparison circuit 56 for comparing and determining whether or not the current flowing through the wiring 37 is normal. The control circuit 60 controls the drivers 42 and 46 shown in FIG. 1 so as to break the fuse element based on the determination result in the comparison circuit 56. The value of the resistor 52 is adjusted according to the current range to be detected. The resistor 52 may be replaced with a transistor.

(Write operation)
The voltages applied to the respective wirings during the write operation in the integrated circuit of the second embodiment are as shown in FIG. The write operation is basically the same as that described in the first embodiment. For example, when writing to the memory element _{10 11,} the program voltage Vprg is applied to the bit line BL _1, to adjust the voltage applied to the wiring 33 to the transistor 32 ₁ is turned on. Furthermore, in order to write the memory element _1011, the word line WL ₁ by the driver _42, drives the WL 2, WL _3, respectively to the wiring _{20 1,} 20 2, 20 _3, and applies 0V, the write inhibit voltage Vinh1 . At this time, since there is no need for current sensing, row select transistor 36 ₁ may be in the off state even in the on state.

(Read operation)
The voltages applied to the wirings during the read operation in the integrated circuit of the second embodiment are as shown in FIG. At this time, in order to turn off the transistors 32 _{1 to} 32 ₃ , a voltage Voff1 is applied to the wiring 33 and the bit lines BL _{1 to} BL ₃ and the substrate. Further, since the read signal is input from the word lines WL _{1 to} WL ₃ , a voltage Von 2 (> 0 V) is applied to the wiring 25 in order to turn on the column selection transistors 24 _{1 to} 24 ₃ . Further, in order to turn on the row select transistor ₃₆ 1-36 ₃ applies a voltage Von3 (> 0V) to the wiring 37. Voltage Von3 the gate voltage of the row select transistor ₃₆ 1-36 ₃ in consideration of the amount of voltage drop by the resistor 52 is adjusted to be VDD voltage. Then, during the signal reading heading operation, the current flowing through the resistor 52 is simultaneously detected by the current detection circuit 50A. This operation is performed for each output path.

(Breaking operation of fuse element)
The voltage applied to each wiring when performing the breaking operation of the fuse element in the integrated circuit of the second embodiment is as shown in FIG. Incidentally, FIG. 7, row select transistor 36 ₂ is poor, showing voltages applied to the wiring in the case of breaking the fuse element 34 _2. The fuse element is broken after the location of the row selection transistor performing the defective operation is determined by the current detection operation. If failure is confirmed row select transistor has an example row select transistor 36 _2, the fuse element to break becomes 34 _2.

In the second embodiment, the fuse elements 34 _{1 to} 34 ₃ are two-terminal elements, and the fuse elements can be broken by flowing a current of a certain level or more. An example of the two-terminal fuse element is shown in FIG. The fuse element 34 includes two terminals 34a and 34b and a path 34c made of, for example, polysilicon that is disposed between the terminals 34a and 34b and connects the terminals 34a and 34b. Each terminal is provided with at least one contact 34d for connecting one of the wirings 30 ₁ to 30 _{3 and} a corresponding one of the row selection transistors 36 _{1 to} 36 ₃ .

If to break the fuse element 34 _2, a sufficient voltage Vf_break to flow the amount of current required to break bit line BL ₂ is applied by the driver 46 shown in FIG. 1, the full open or fuse even if the gate voltage of the p-channel transistor element 34 ₂ is required to a value enough to ensure a sufficient current to rupture. The current path for breaking the fuse element is to enter the voltage from the bit line BL _2, through the fuse element 34 _2, omission to the poor state row select transistor 36 _{and second} gate, applied to the wiring 37 The current flows into the wiring 37 by setting the voltage to be 0V. Row select transistor 36 _2, since it is able to pass between the gate and source at this point, so that the path flowing a current for such fracture is present.

Row select transistor 36 ₂ which caused the problem by breaking the fuse element 34 ₂ is disconnected from the memory row, the memory device ₁₀₁₂ connected to the wiring 30 _2, 10 22, _{10 23} programmed not to use.

  As described above, according to the second embodiment, the memory element in the row to which the defective row selection transistor is connected can be separated from the memory element array, and the memory circuit that can suppress malfunction is provided. Integrated circuits can be provided.

(Third embodiment)
An integrated circuit according to the third embodiment will be described with reference to FIGS. 9 is a circuit diagram showing the integrated circuit of the third embodiment, FIG. 10 is a diagram for explaining the write operation in the integrated circuit of the third embodiment, FIG. 11 is a diagram for explaining the read operation, and FIG. It is a figure explaining the operation to make.

Integrated circuit of the third embodiment, the integrated circuit of the second embodiment shown in FIG. 5 has a configuration obtained by replacing the fuse element ₃₄ 1-34 ₃ the fuse element ₃₅ 1-35 ₃ respectively. 9 to 12, the drivers 42 and 46 shown in FIG. 1 are not shown for the sake of simplicity.

The fuse element 35 _i (i = 1, 2, 3) is a MOS transistor, and its source and drain are connected to a common wiring 38 and its gate is connected to a wiring 30 _i in the memory cell array.

(Write operation)
The voltages applied to the respective wirings during the write operation in the integrated circuit of the third embodiment are as shown in FIG. The write operation is basically the same as that described in the first embodiment. For example, when writing to the memory element _{10 22,} the program voltage Vprg is applied to the bit line BL _2, adjusts the voltage applied to the wiring 33 to the transistor 32 ₂ is turned on. In FIG. 10, the voltage Vcomp <b> 1 (for example, 0 V) is applied to the wiring 33. At this time, the substrate voltage of the transistor 32 ₂ is programmed to the above voltage Vprg. Note that the write inhibit voltage Vinh is applied to the other bit lines BL ₁ and BL ₃ . Furthermore, in order to write to the memory element _{10 22,} the source and the drain of the memory element _{10 22} 0V is applied to the connected wires 20 _2, it is applied to the write inhibit voltage Vinh (> 0V) to the other lines 201, 203 Thus, the driver 42 drives the word lines WL ₁ , WL ₂ , WL ₃ .

The fuse elements 35 _{1 to} 35 ₃ also apply a write inhibit voltage Vinh (> 0 V) to the wiring 38 connected to the source and drain in order to prevent breakage. Note that the voltage Vcomp2 is applied to the wiring 37 so that the row selection transistors 36 _{1 to} 36 ₃ are turned on. At this time, the output wirings Out _{1 to} Out ₃ are set in a floating state.

(Read operation)
The voltage applied to each wiring during the read operation in the integrated circuit of the third embodiment is as shown in FIG. At this time, in order to turn off the transistors 32 _{1 to} 32 ₃ , the voltage Voff 2 is applied to the wiring 33 and the bit lines BL _{1 to} BL ₃ and the substrate. Further, since the read signal is input from the word lines WL _{1 to} WL ₃ , a voltage Von 2 (> 0 V) is applied to the wiring 25 in order to turn on the column selection transistors 24 _{1 to} 24 ₃ . Further, in order to turn on the row select transistor ₃₆ 1-36 ₃ applies a voltage Von3 (> 0V) to the wiring 37. This voltage Von3 the gate voltage of the row select transistor ₃₆ 1-36 ₃ in consideration of the amount of voltage drop by the resistor 52 is adjusted to be VDD voltage. Then, during the signal reading heading operation, the current flowing through the resistor 52 is simultaneously detected by the current detection circuit 50A. This operation is performed for each output path.

(Fuse breaking action)
The voltage applied to each wiring when performing the breaking operation of the fuse element in the integrated circuit of the third embodiment is as shown in FIG. Incidentally, FIG. 12, row select transistor 36 ₂ is poor, showing voltages applied to the wiring in the case of breaking the fuse element 35 _2. The fuse element is broken after the location of the row selection transistor performing the defective operation is determined by the current detection operation. If failure is confirmed row select transistor has an example row select transistor 36 _2, the fuse element to break becomes 34 _2.

In the third embodiment, the fuse elements 35 _{1 to} 35 ₃ are 4-terminal elements. An example fuse element having four terminals is a transistor-type fuse element as shown in FIG. 13, and includes a source 35a and a drain 35b spaced apart from the semiconductor layer 35j, and a semiconductor layer between the source 35a and the drain 35b. A gate 35c disposed above, a gate insulating layer 35d disposed between the gate 35c and the semiconductor layer 35j, and terminals 35e and 35f disposed at both ends of the gate 35c are provided. Contacts 35g are disposed on the source 35a and the drain 35b, respectively, and contacts 35h and 35i are disposed on the terminals 35e and 35f, respectively. Contacts 35g arranged on the source 35a and the drain 35b are connected to the wiring 38 shown in FIG. The contact 35h arranged at the terminal 35e is connected to one of the corresponding wirings 30 ₁ to 30 ₃ shown in FIG. 12, and the contact 35i arranged at the terminal 35f is connected to the row selection transistors 36 _{1 to} 36 ₃ . It is connected to the drain of one of the corresponding transistors.

  In addition to the breakdown of the gate insulating layer 35d, the fuse element 35 causes a current of a certain level or more to flow between the gate 35c and the source 35a formed by the breakdown of the gate insulating layer 35d and between the gate 35c and the drain 35b. As a result, the gate 35c is broken to serve as a fuse.

If to break the fuse element 35 _2, a sufficient voltage Vprg2 to flow the amount of current required to break is applied to the bit line BL _2, the voltage applied to the gate of the transistor 32 ₂ full opening or the fuse element 35 ₂ It is necessary to set a value sufficient to ensure a sufficient current for breaking, for example, Vcomp1 (for example, 0 V). The path of the current for the fuse element 35 _{and second} fracture receives the voltage from the bit line BL _2, through the leak path due to breakdown of the gate insulating layer from the gate of the fuse element 35 _2, and the fuse element 35 ₂ Source Connected to the wiring 38 connected to the drain. Here 0V is applied to the wiring 38, the current flowing between the bit line BL ₂ through the fuse element 35 ₂ and the wiring 38, breaking the gate of the fuse element 35 _2.

Such row select transistor 36 ₂ which caused the problem by breaking the fuse element 35 ₂ in the disconnected from the memory cell array, the memory device ₁₀ 21 connected to the wiring 30 _2, 10 22, _{10 23} not to use To program.

  In the third embodiment, the case where the OTP memory element utilizing the breakdown of the gate insulating layer is used as the memory array of the multi-input multi-output MUX has been described. However, even when a resistance change type memory element in which a resistance change layer is disposed between two electrodes is used as a cross-point type memory array, a defective selection transistor can be isolated by the same operation as described above. .

(Example layout of transistor type fuse element)
Next, first to third examples of the layout of the four-terminal transistor type fuse element used in the third embodiment are shown in FIGS. 14 to 16, respectively. Each is an array of three rows of memory elements and fuse elements, with two memory element columns and one fuse element column. Here, wirings 30 ₁ to 30 ₃ are gate wirings made of polysilicon, reference numerals 12 _{2 to} 12 ₃ indicate active areas serving as a source and a drain of the memory element, and reference numeral 14 indicates transistor type fuse elements 35 _{1 to} 35 _3. Indicates the active area. Here, the memory transistor 10 ₁₂ , 10 ₁₃ , 10 ₂₂ , 10 ₂₃ , 10 ₃₂ , 10 ₃₃ in which the intersecting region between the active areas 12 ₂ , 12 ₃ and the gate wirings 30 ₁ to 30 ₃ is a memory element is active Intersection regions between the area 14 and the gate wirings 30 ₁ to 30 ₃ become transistor type fuse elements 35 _{1 to} 35 ₃ .

The transistor type fuse elements 35 _{1 to} 35 ₃ shown in FIG. 14 have a gate width (Wf) wider than the gate width (Wm) of the memory transistors 1012 to 1033. That is, Wf> Wm.

Further, the transistor-type fuse elements 35 _{1 to} 35 ₃ shown in FIG. 15 have a structure that promotes gate breakage by narrowing a part of the polysilicon wiring between the memory element array and the fuse element.

Further, the transistor type fuse elements 35 _{1 to} 35 ₃ shown in FIG. 16 have a structure that promotes gate breakage by slitting a part of the polysilicon wiring between the memory element array and the fuse element. .

  As described above, according to the third embodiment, the memory element in the row to which the defective row selection transistor is connected can be separated from the memory element array, and the memory circuit that can suppress malfunction is provided. Integrated circuits can be provided.

In the third embodiment, the gate of the fuse element 35 is connected to the corresponding wiring among the wirings 30 ₁ to 30 ₃ , and the source and drain are connected to the wiring 38. The gate may be connected to the corresponding wiring among the wirings 30 ₁ to 30 ₃ , and one of the source and the drain may be connected to the wiring 38. Further, the gate may be connected to the wiring 38, and one of the source and the drain may be connected to a corresponding wiring among the wirings 30 ₁ to 30 ₃ .

(Fourth embodiment)
An integrated circuit according to the fourth embodiment will be described with reference to FIGS. 17 is a circuit diagram showing the integrated circuit of the fourth embodiment, FIG. 18 is a diagram for explaining the write operation in the integrated circuit of the fourth embodiment, FIG. 19 is a diagram for explaining the read operation, and FIG. It is a figure explaining the operation to make.

In the integrated circuit of the fourth embodiment, the first terminal of the fuse element 34 _i (i = 1, 2, 3) is connected to the wiring 37 in the integrated circuit of the second embodiment shown in FIG. a structure connected to a gate of the corresponding row select transistor 36 _i has a. In the fourth embodiment, the fuse element 34 _i (i = 1, 2, 3) is broken using the same method as that described in the third embodiment.

(Write operation)
The voltages applied to the respective wirings during the write operation in the integrated circuit of the fourth embodiment are as shown in FIG. The write operation is basically the same as that described in the first embodiment. For example, the bit when writing to the memory element _{10 22,} in order to turn on transistor 32 _2, which applies a voltage Vcomp1 (for example, 0V) to the wiring 33, is connected to the row containing the memory device _{10 22} for writing the line BL ₂ for applying a write voltage Vprg. At this time, the substrate voltage of the transistor 32 ₂ is set to more than Vprg. Further, 0V is applied to the wiring 20 ₂ the source and drain of the memory device _{10 22} are connected, the wiring ₂₀ 1, as 20 ₃ to the write inhibit voltage Vinh (> 0V) is applied, the word line by the driver 42 WL ₁ , WL ₂ , WL ₃ are driven. The fuse elements 34 _{1 to} 34 ₃ also apply Vcomp2 (> 0 V) to the wiring 37 to prevent breakage. At this time, the output wirings Out _{1 to} Out ₃ are set in a floating state.

(Read operation)
The voltage applied to each wiring during the read operation in the integrated circuit of the fourth embodiment is as shown in FIG. At this time, in order to turn off the transistors 32 _{1 to} 32 ₃ , the voltage Voff 2 is applied to the wiring 33 and the bit lines BL _{1 to} BL ₃ and the substrate. Further, since the read signal is input from the word lines WL _{1 to} WL ₃ , a voltage Von 2 (> 0 V) is applied to the wiring 25 in order to turn on the column selection transistors 24 _{1 to} 24 ₃ . Further, in order to turn on the row select transistor ₃₆ 1-36 ₃ applies a voltage Von3 (> 0V) to the wiring 37. This voltage Von3 the gate voltage of the row select transistor ₃₆ 1-36 ₃ in consideration of the amount of voltage drop by the resistor 52 is adjusted to be VDD voltage. Then, during the signal reading heading operation, the current flowing through the resistor 52 is simultaneously detected by the current detection circuit 50A. This operation is performed for each output path.

(Fuse breaking action)
The voltage applied to each wiring when performing the breaking operation of the fuse element in the integrated circuit of the fourth embodiment is as shown in FIG. Incidentally, FIG. 20 is a row select transistor 36 ₂ is poor, showing voltages applied to the wiring in the case of breaking the fuse element 34 _2. The fuse element is broken after the location of the row selection transistor performing the defective operation is determined by the current detection operation. If failure is confirmed row select transistor has an example row select transistor 36 _2, the fuse element to break becomes 34 _2.

  In the fourth embodiment, a defective row selection transistor is treated as a fuse element, and the same fuse breaking method as that in the third embodiment is used.

For example, if to break the fuse element 34 _2, by applying a sufficient voltage Vprg2 bit line BL ₂ for supplying a current amount required for breaking, voltage full opening or a fuse element applied to the gate of the transistor 32 ₂ 34 _It is necessary to set it to a value that can secure a sufficient current for breaking ₂ (for example, Vcomp1 (for example, 0 V)). The path of the current for the fuse element 34 _{and second} fracture inputs a voltage from the bit line BL _2. The current path for breaking the fuse element 34 _2, via the already leak path current leakage occurs between the gate and the drain by and are the row select transistor 36 ₂ which becomes defective, 0V to the wiring 37 fuse element 34 ₂ is broken by applying a. Thus, by a floating state to the row select transistor 36 ₂ which gate is broken, sufficient signal can not pass is the wiring Out ₂ via a row select transistor 36 _2. Therefore, after breaking the fuse element 34 _2, the row select transistor 36 ₂ which caused the defect is separated from the memory cell array, the memory device ₁₀ 21 connected to the wiring 30 _2, 10 22, _{10 23} programmed not to use .

  In the fourth embodiment, the case where the OTP memory element utilizing the breakdown of the gate insulating layer is used as the memory array of the multi-input multi-output MUX has been described. However, even when a resistance change type memory element in which a resistance change layer is disposed between two electrodes is used as a cross-point type memory array, a defective selection transistor can be isolated by the same operation as described above. .

  As described above, according to the fourth embodiment, the memory element in the row to which the defective row selection transistor is connected can be separated from the memory element array, and the memory circuit that can suppress malfunction is provided. Integrated circuits can be provided.

(Other examples of current detection circuit)
Next, a second example of the current detection circuit used in the first to fourth embodiments is shown in FIG. This current detection circuit 50B includes resistors 53a and 53b connected in series between the first terminal of the resistor 52 and the ground GND in the current detection circuit 50A of the first example of the second embodiment shown in FIG. Resistors 53 c and 53 d connected in series are provided between the second terminal of the resistor 52 and the output terminal of the amplifier 54. The voltage divided by the resistors 53a and 53b is input to the positive input terminal of the amplifier 54, and the voltage divided by the resistors 53c and 53d is input to the negative input terminal of the amplifier 54.

  Similarly to the current detection circuit 50A of the first example, the current detection circuit 50B of the second example configured as described above can confirm whether or not the current flowing through the wiring 37 has increased.

  Next, FIG. 22 shows a third example of the current detection circuit used in the first to fourth embodiments. The current detection circuit 50C is a current mirror that detects a current flowing through the wiring 37 instead of the resistor 52, the amplification circuit, and the comparison circuit 56 in the current detection circuit 50A of the first example of the second embodiment shown in FIG. The circuit 51, the fuse element 55, and the comparator 57 are provided. The fuse element 55 is disposed between the output terminal of the current mirror circuit 51 and the positive input terminal of the comparator 57. The output of the comparator 57 is sent to the control circuit 60.

  Similarly to the current detection circuit 50A of the first example, the current detection circuit 50B of the third example configured as described above can confirm whether or not the current flowing through the wiring 37 has increased.

In the first to fourth embodiments, the case where the multi-input multi-output MUX memory array uses the OTP memory element utilizing the destruction of the oxide film has been described. However, as shown in FIG. 23, as the cross-point type memory array, the resistance change type memory element 70 in which the resistance change layer 76 is arranged between the two electrodes 72 and 74 is used, as described above. With this operation, the defective selection transistor can be isolated. In this case, the electrode 72 is connected to a corresponding one of the wirings 20 _{1 to} 20 ₃ , and the electrode 74 is connected to a corresponding one of the wirings 30 ₁ to 30 ₃ .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the invention described in the claims and equivalents thereof as well as included in the scope and gist of the invention.

10 ₁₁ to 10 ₃₃ ... Memory element, 20 _{1 to} 20 ₃ ... Column wiring, 22 _{1 to} 22 ₃ ... Inverter, 24 _{1 to} 24 ₃ ... Column selection transistor, 25. 30 ₁ to 30 ₃ ... Row wiring, 32 _{1 to} 32 ₃ ... High breakdown voltage p-channel MOS transistor, 33... Wiring, 34 _{1 to} 34 ₃ ... Fuse element, 35 _{1 to} 35 _3. Transistor type fuse element, 36 _{1 to} 36 ₃ ... Row selection transistor, 37... Wiring, 38 _{1 to} 38 ₃ ... Inverter, 42... Driver, 46. ..Current detection circuit, 52... Resistor, 54... Amplification circuit, 56... Comparison circuit, 60... Control circuit, 70. ..Electrodes, 76 ... resistance _Layer, BL 1 _{to BL} 3 ... bit _lines, WL 1 _{to WL} 3 ... word lines, 57 ... comparator, 51 ... current mirror

Claims (8)

A plurality of first wires;
A plurality of second wirings intersecting with the plurality of first wirings;
A plurality of memory elements, each having a first terminal and a second terminal, wherein the first terminal is electrically connected to the corresponding first wiring; A plurality of memory elements connected and electrically connected to corresponding second wirings of the second terminals;
A plurality of fuse elements arranged corresponding to the plurality of second wirings, each having a third terminal and a fourth terminal, wherein the third terminal is electrically connected to the corresponding second wiring. A plurality of fuse elements;
A plurality of first transistors arranged corresponding to the plurality of fuse elements, wherein one of a source and a drain of the first transistor is electrically connected to a fourth terminal of the corresponding fuse element; One transistor,
A third wiring electrically connected to the gates of the plurality of first transistors;
A current detection circuit for detecting a current flowing in the third wiring;
Integrated circuit with. A plurality of first wires;
A plurality of second wirings intersecting with the plurality of first wirings;
A plurality of memory elements, each having a first terminal and a second terminal, wherein the first terminal is electrically connected to the corresponding first wiring; A plurality of memory elements connected and electrically connected to corresponding second wirings of the second terminals;
A plurality of first transistors arranged corresponding to the plurality of second wirings, wherein one of the source and drain of the first transistor is electrically connected to the corresponding second wiring. When,
A plurality of fuse elements arranged corresponding to the plurality of first transistors, each having a third terminal and a fourth terminal, wherein the third terminal is electrically connected to the gate of the corresponding first transistor. A plurality of fuse elements,
A third wiring electrically connected to a fourth terminal of the plurality of fuse elements;
A current detection circuit for detecting a current flowing in the third wiring;
Integrated circuit with.   The integrated circuit according to claim 1, wherein the fuse element includes a fourth wiring and terminals connected to both ends of the fourth wiring.   The fuse element is a MOS transistor, and at least one of a gate and a source and a drain of each MOS transistor is electrically connected to a corresponding second wiring, and the other is connected to a source of the first transistor. The integrated circuit of claim 1, wherein the integrated circuit is electrically connected to one of the drains. A plurality of second transistors arranged corresponding to the plurality of second wirings and having a higher breakdown voltage than the first transistor, wherein each second transistor is electrically connected to a second wiring corresponding to one of a source and a drain. A plurality of second transistors positioned between the corresponding first transistor and the corresponding second transistor; and
A plurality of third transistors arranged corresponding to the plurality of first wirings, each of the third transistors having a plurality of third transistors, one of which is electrically connected to the corresponding first wiring. A transistor,
The integrated circuit according to claim 1, further comprising: A driver for controlling gates of the first to third transistors and controlling voltages applied to the first to third wirings;
When the current detected by the current detection circuit is different from a predetermined value, at least one of the plurality of first transistors is determined to be defective, and the fuse element corresponding to the first transistor determined to be defective is broken. A control circuit for controlling the driver,
The integrated circuit according to claim 5 , further comprising:   The memory element is a transistor, and one of a gate and at least one of a source and a drain is electrically connected to a corresponding first wiring, and the other is electrically connected to a corresponding second wiring. An integrated circuit according to any one of claims 1 to 6.   The memory element is a resistance change memory element including first and second electrodes, and a resistance change layer disposed between the first electrode and the second electrode. The integrated circuit according to claim 1, wherein the integrated circuit is electrically connected to a corresponding first wiring, and the second electrode is electrically connected to a corresponding second wiring.

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