JP6428167B2 - Database server, relocation method, and relocation program - Google Patents

Description

  The present invention relates to a database server that can relocate data distributed to a plurality of processors, a relocation method, and a relocation program.

  When a processor is added to a database server composed of a plurality of processors, it is necessary to rearrange the data distributed and arranged in each processor. Patent Document 1 discloses an invention relating to a database server capable of rearranging data arranged in a distributed manner on a plurality of processors.

  Below, the method of patent document 1 is demonstrated easily.

  The database server is composed of a plurality of processors. Each processor holds a host DB and a conversion DB.

  The host DB stores a record in which a hash value, key information, and data (for example, an ID of a database host that stores information related to key information) are associated with each other. The hash value is obtained by converting the key information into a certain range of values by applying a hash function to the key information. By applying the hash function to the key information, all the key information is classified into one of a certain range of hash values.

  The conversion DB indicates in which processor host DB the record of each hash value is stored. For all hash values, a PUID (Processor Unit ID) that identifies the processor is stored in association with each other.

  As described above, in the database server of Patent Document 1, records relating to key information are distributed and stored in the host DB of each processor. When key information is input to the database server, the processor in charge of processing calculates a hash value from the input key information, and acquires a PUID associated with the hash value from the conversion DB. If the PUID is its own, data corresponding to the hash value and key information is acquired from its own host DB. If the PUID is from another processor, the corresponding processor is notified of the hash value, and a request is made to transmit data corresponding to the hash value and key information. In this way, the host DB search process can be performed in parallel by each processor corresponding to the hash value. Therefore, it is possible to acquire a record relating to key information at a high speed from a large number of distributed records.

  Also, when a processor is added to the database server, the method of Patent Document 1 imports a new conversion DB from an external file, and rearranges the records in the host DB of each processor according to the new conversion DB and the old conversion DB. Is going.

Japanese Patent No. 5084310

  Patent Document 1 describes a rearrangement method according to a new conversion DB and an old conversion DB. However, specifically, how to associate each hash value with each processor (PUID) in the new conversion DB, in other words, a method for creating the new conversion DB is not described.

  As a method for creating a new conversion DB, a simple method may be a method of assigning each processor in order of hash values. For example, FIG. 15 shows a case where a processor with PUID c is newly added to two processors with PUIDs a and b. In the example of FIG. 15, in the old conversion DB, the PUIDs are associated in the order of hash values in the order of a, b, a, b, and in the new conversion DB, the associations are performed in the order of a, b, c, a, b, c. Yes. However, with such a method, a state occurs in which records are moved between existing processors as in the case where the hash values in FIG. 15 are “011” and “100” (shaded portions in FIG. 15). . When a processor is added, moving a record between existing processors is a wasteful movement and increases the load and time for rearrangement. In addition, since it is assumed that relocation processing is performed during service operation, the resources necessary for record relocation are minimized in order to secure sufficient computer resources necessary for service operation. It is desirable to avoid useless record movement.

  An object of the present invention is to provide a database server, a rearrangement method, and a rearrangement program that can eliminate data movement between existing processors and perform data rearrangement at a higher speed.

  In order to solve the above-described problem, the database server of the present invention refers to a record in which a plurality of processors, key information, a hash value derived from the key information and data are associated with each other, and is referred to by each of the processors. A record storage unit that stores the different record for each processor based on the hash value, and for each of the hash values, processor identification information that identifies each hash value and the processor that refers to the record of the hash value And a first processor information storage unit that stores first processor information, each of which communicates with another processor or another device, and the processor newly Processor addition including the processor identification information of the added processor when added to The processor identification of the processor to which the processor identification information associated with the hash value as a part of the first processor information is added when the processor addition notification is received. The second processor information replaced with the information is generated, and the record referred to by the processor added from the record storage unit referred to by the own processor based on the first processor information and the second processor information And a storage control unit that rearranges the records in the storage unit.

  The processor information generation device of the present invention includes: processor information in which a hash value and processor identification information that identifies a processor that can refer to a record of the hash value are associated with each other; and the processor identification information of the processor to be added A processor information communication unit that receives input and outputs the newly generated processor information, and adds the processor identification information associated with the hash value that is part of the processor information to the processor identification information of the processor And a processor information generation unit for generating new replaced processor information.

  In the relocation method of the present invention, a record in which a plurality of processors, key information, a hash value derived from the key information and data are associated with each other is referred to by each of the processors, and based on the hash value. In a database server comprising a record storage unit for storing the record that differs for each processor, when each of the processors receives a processor addition notification including processor identification information that identifies the added processor, all the Regarding the hash value, the processor associated with a part of the hash value of the first processor information in which each hash value is associated with the processor identification information of the processor that refers to the record of the hash value The processor identification information of the processor to which identification information has been added To the record storage unit referenced by the processor added from the record storage unit referenced by the own processor based on the first processor information and the second processor information. The record is rearranged.

  The processor information generation method of the present invention includes processor information in which a hash value is associated with processor identification information that identifies a processor that can refer to the record of the hash value, and the processor identification information of the processor to be added. The new processor information is generated by replacing the processor identification information associated with the hash value of a part of the processor information with the processor identification information of the processor to be added.

  Also, the relocation program of the present invention refers to a record in which a plurality of processors, key information, a hash value derived from the key information, and data are associated with each other, and is referred to by each of the processors, and based on the hash value A record storage unit that stores the different records for each processor, and for each of the hash values, each hash value is associated with processor identification information that identifies the processor that refers to the record of the hash value. A first processor information storage unit that stores first processor information is added to a computer that communicates with another processor or another device and is newly added to the computer. A communication function for receiving a processor addition notification including the processor identification information of the processor; Second processor information obtained by replacing the processor identification information associated with the hash value, which is a part of the first processor information, with the processor identification information of the added processor when receiving a sesser addition notification Based on the first processor information and the second processor information, the record is rearranged from the record storage unit referenced by the own processor to the record storage unit referenced by the processor. A memory control function is realized.

  In addition, the processor information generation program of the present invention provides processor information that associates a hash value with processor identification information that identifies a processor that can reference a record of the hash value, and the processor identification of the processor to be added. A processor information communication function for receiving input of information and outputting the newly generated processor information; and the processor of the processor for adding the processor identification information associated with the hash value as part of the processor information A processor information generation function for generating new processor information replaced with identification information is realized.

  The database server, the rearrangement method, and the rearrangement program according to the present invention can eliminate data movement between existing processors and perform data rearrangement at a higher speed.

It is a figure which shows the structural example of the database server of 1st embodiment of this invention. It is a figure which shows the example of the record of 1st embodiment of this invention. It is a figure which shows the example of the processor information of 1st embodiment of this invention. It is a figure which shows the operation example of the processor of the database server of 1st embodiment of this invention. It is a figure which shows the operation example of the processor of the database server of 2nd embodiment of this invention. It is a figure which shows the example of the production | generation method of the 2nd processor information of 3rd embodiment of this invention. It is a figure which shows the specific example 1 of 3rd embodiment of this invention. It is a figure which shows the specific example 1 of 3rd embodiment of this invention. It is a figure which shows the specific example 2 of 3rd embodiment of this invention. It is a figure which shows the specific example 3 of 3rd embodiment of this invention. It is a figure which shows the specific example 4 of 3rd embodiment of this invention. It is a figure which shows the specific example 5 of 3rd embodiment of this invention. It is a figure which shows the specific example 6 of 3rd embodiment of this invention. It is a figure which shows the example of the production | generation method of the 2nd processor information of 4th embodiment of this invention. It is a figure which shows the example of a simple method.

  First, a first embodiment of the present invention will be described.

  FIG. 1 shows a configuration example of the database server according to the first embodiment of the present invention.

  The database server 1 includes a plurality of processors 10. In the example of FIG. 1, it is comprised from three processors 10a, 10b, and 10c with PUID a, b, and c. The number of processors 10 constituting the database server 1 is not limited as long as it is one or more. Each processor transmits and receives information to and from other processors in the database server 1 and other devices outside the database server 1.

  The processor 10 includes a communication unit 11, a storage control unit 12, a record storage unit 13, and a first processor information storage unit 14.

  The communication unit 11 is a part that communicates with other processors in the database server 1 and other devices outside the database. The storage control unit 12 is a part that controls information stored in the record storage unit 13 and the first processor information storage unit 14.

  The record storage unit 13 stores a record in which hash values, key information, and data are associated with each other. The hash value is obtained by converting the key information into a certain range of values by applying a hash function to the key information. By applying the hash function to the key information, all the key information is classified into one of a certain range of hash values.

  FIG. 2 shows an example of records stored in the record storage unit 13. For example, a subscriber ID is stored in the key information. Then, the hash value and data resulting from applying the hash function to one key information “aaa @ zzz” are stored as a record. In the example of FIG. 2, the hash value corresponding to the key information “aaa @ zzz” is “010”, and the data is “2”. The data in this example indicates which DB host ID stores the data corresponding to the subscriber ID.

  The first processor information storage unit 14 is a part for storing processor information indicating which processor's host DB stores a record of each hash value. For all hash values, a PUID that identifies the processor is stored in association with each other.

  FIG. 3 shows an example of the processor information. The correspondence relationship between the hash value and the PUID is described. For example, a record corresponding to the hash values “000” and “011” indicates that the processor having the PUID is a. In the case of the processor information of FIG. 3, the record of the hash value “010” is stored in the example of the record of FIG.

  In the configuration example of FIG. 1, the record storage unit 13 and the first processor information storage unit 14 are provided in the processor 10, but these can also be provided in the database server 1 outside the processor 10. . In this case, the record storage unit 13 is configured such that there is one or more record storage units 13 that can be referred from each processor, and that there is one processor corresponding to each record storage unit 13. As for the first processor information storage unit 14, since the processor information is common to all the processors, only one processor information storage unit 14 is provided in the database server 1, and the same first processor information storage unit 14 is referred to by all the processors. You may comprise.

  By configuring the database server 1 as described above, it is possible to eliminate data movement between existing processors and perform data relocation at a higher speed.

  Next, FIG. 4 shows an example of the operation of the processor 10 of the database server 1 in the configuration example of FIG.

  The processor 10 receives a relocation instruction to the database server 1 from an operation panel of the database server 1 or another control terminal connected to the database server 1 and starts a relocation operation. First, the processor 10 generates new second processor information from the processor information stored in the first processor information storage unit 14 (S101). The second processor information is new processor information when the processor information (correspondence between hash value and PUID) is changed, such as when the number of processors is changed. At this time, in the case of adding a processor to the database server, the second processor information in which the processor identification information associated with the hash value that is part of the first processor information is replaced with the processor identification information of the processor to be added. Is generated.

  Based on the processor information (first processor information) and the second processor information in the first processor information storage unit 14, the records are rearranged from the record storage unit of the own processor to the record storage unit of the added processor. (S102).

  As described above, in the first embodiment of the present invention, when adding a processor, the processor identification of the processor to which the processor identification information associated with a part of hash values of the first processor information is added. New processor information replaced with information is generated. Therefore, it is possible to eliminate data movement between existing processors and perform data relocation at a higher speed.

  Next, a second embodiment of the present invention will be described. In the first embodiment, new processor information is generated by each processor. However, in this embodiment, the host processor generates new processor information and distributes it to other processors.

  A configuration example of the database server is as shown in FIG. 1 as in the first embodiment. In this embodiment, one of the plurality of processors operates as a master processor that controls other processors.

  An example of the operation of this embodiment is shown in FIG. (A) is an operation example of the master processor, and (b) is an operation example of a processor other than the master processor.

  First, when receiving a rearrangement instruction, the master processor generates new second processor information from the processor information in the first processor information storage unit 14 (S201). At this time, when adding a processor, second processor information is generated by replacing the processor identification information associated with a part of hash values of the first processor information with the processor identification information of the processor to be added.

  Next, the generated second processor information is distributed to other processors. Processors other than the master processor receive second processor information from the master processor (S204).

  Then, in each processor, the records in the record storage unit of each processor are rearranged based on the processor information in the first processor information storage unit 14 and the second processor information (S203, S205).

  As described above, also in the second embodiment of the present invention, when adding a processor, the processor identification of a processor that adds processor identification information associated with a hash value that is part of the first processor information. New processor information replaced with information is generated. Therefore, it is possible to eliminate data movement between existing processors and perform data relocation at a higher speed.

  Next, a third embodiment of the present invention will be described. In this embodiment, a method for generating new processor information performed in the first and second embodiments will be specifically described.

  FIG. 6 shows an example of a new processor information generation method according to this embodiment. This operation is performed in step S101 in FIG. 4 or step S201 in FIG. In the present embodiment, it is assumed that each processor is periodically assigned to each hash value in the processor information in the first processor information storage unit.

  First, let x be the allocation period of processor information (first processor information) in the first processor information storage unit, and y be the number of processors to be added. Also, PI is prepared as a working array, and PI2 is prepared as a storage array for the generated new processor information (second processor information). The size of the work array PI is x, and the size of the second processor information storage array is x × (x + y).

  Next, the allocation period x of the first processor information is compared with the number y of added processors (S301). When x is greater than or equal to y, y is the shift amount s. When x is less than y, x is repeatedly subtracted from y until x is less than or equal to x, and the result of the subtraction is defined as the shift amount s (S302 to S305). ). Then, the PUID (x pieces) for one cycle of the first processor information is stored in the work array PI (S306).

  Next, x contents of the work array PI are additionally copied to the second processor information storage array PI2, and y PUIDs of the processors to be added are added (S307).

  Next, the contents of the working array PI are cyclically shifted by the shift amount s in the head direction (the shifted and overflowed portion is stored in the empty portion) (S308). When the cyclically shifted work array PI returns to the original PI (PI of S306) (S309), the PUID stored in PI2 is stored as one cycle and periodically stored as second processor information (S310). ). If the cyclically shifted work array PI has not returned to the original PI (S309), x contents of the work array PI are additionally copied to the second processor information storage array PI2, and the processor to be added is further copied. Y PUIDs are added (S307).

  Even when steps S301 and S303 to S305 are not provided, that is, regardless of the magnitude relationship between x and y, the same second processor information can be obtained even if y is the shift amount s. Therefore, steps S301 and S303 to S305 can be deleted.

  In step S309, it is confirmed whether or not the working array PI has returned to the original PI. However, since the size of PI is x and returns to the original after x cyclic shifts, the number of cyclic shifts is counted. The number of times may be confirmed.

  The above is an example of a method for generating new processor information in the present embodiment. In this way, when adding a processor, new processor information can be generated so that there is no movement of records from the existing processor to the existing processor. Therefore, it is possible to eliminate data movement between existing processors and perform data relocation at a higher speed.

  Next, a specific example of the generation of new processor information in the present embodiment will be illustrated.

  First, specific example 1 describes a case where a processor with PUID c is added to two processors with PUIDs a and b.

  7 and 8 show examples of generation of processor information in the first specific example. In the first processor information, processors are assigned in the order of hash values in the order of abab. At this time, the processor allocation period x is two. The number of processors y to be added is 1. When x and y are compared, since x is greater than or equal to y, the shift amount s is 1 (= y) (S301 to S302). Next, the PUID for one period of the first processor information is stored in the work array PI (S306). FIG. 8A shows the PI at this time. A and b are stored in PI. Next, as in the part (1) of PI2 in FIG. 8, PI is copied to PI2, and PUID = c (shaded part) of the processor to be added is added (S307). Next, the working array PI is cyclically shifted in the head direction by the shift amount s = 1 (S308). FIG. 8B shows the PI at this time. As in the part (2) of PI2 in FIG. 8, this PI is additionally copied to PI2, and PUID = c of the processor to be added is further added (S307). When PI is further cyclically shifted by the shift amount s, the original working array PI is restored as shown in FIG. Since the PI has returned to the original PI (S309), the PI2 at this time is stored as one cycle and periodically stored as second processor information (S310).

  The processor information generated as described above is the second processor information in FIG. Thus, when adding a processor, new processor information can be generated so that there is no movement of records between existing processors by cyclically shifting the number of processors to which the work array PI is added. it can. Therefore, it is possible to eliminate data movement between existing processors and perform data relocation at a higher speed.

  Next, as a third specific example, FIG. 9 illustrates a generation example of processor information when a processor having a PUID of d is added to three processors having a PUID of a, b, and c. Further, as a fourth specific example, FIG. 10 illustrates a generation example of processor information when a processor having a PUID of e is added to four processors having a PUID of a, b, c, and d. Since the description of the operation is the same as in the first specific example, the description thereof is omitted. 9 and 10 also show that relocation between existing processors can be eliminated.

  Next, as specific example 4, an example of generating processor information when two processors with PUIDs d and e are added to three processors with PUIDs a, b, and c will be described.

  FIG. 11 shows an example of generation of processor information in specific example 4. In the first processor information, the processors are allocated in the order of abbcc... In the order of hash values. At this time, the processor allocation period x is three. The number of processors y to be added is 2. When x and y are compared, since x is greater than or equal to y, the shift amount s is 2 (= y) (S301 to S302). Next, the PUID for one period of the first processor information is stored in the work array PI (S306). FIG. 11 (1) shows the PI at this time. A, b, and c are stored in PI. Next, as in the part (1) of PI2 in FIG. 11, PI is copied to PI2, and PUID = d and e of the processor to be added are added (shaded part) (S307). Next, the working array PI is cyclically shifted in the head direction by the shift amount s = 2 (S308). FIG. 11 (2) shows the PI at this time. As in the part (2) of PI2 in FIG. 11, this PI is additionally copied to PI2, and PUID = d and e of the processor to be added are further added (S307). Further, when the PI is cyclically shifted by the shift amount s, the result is as shown in FIG. 11 (3) (S308). Then, as in the part (3) of PI2 in FIG. 11, this PI is additionally copied to PI2, and PUID = d and e of the processor to be added are further added (S307). Further, when the PI is cyclically shifted by the shift amount s, the original working array PI is returned as shown in FIG. 11 (4) (S308). Since the PI has returned to the original PI (S309), the PI2 at this time is stored as one cycle and periodically stored as second processor information (S310).

  As described above, also in this specific example, when adding a processor, a new processor is added so that there is no movement of records between existing processors by cyclically shifting the number of processors to which the working array PI is added. Information can be generated. Therefore, it is possible to eliminate data movement between existing processors and perform data relocation at a higher speed.

  Next, as specific example 5, an example of generating processor information when three processors with PUIDs c, d, and e are added to two processors with PUIDs a and b will be described. This specific example is an example in which the number of processors to be added is larger than the processor allocation period of the first processor information.

  FIG. 12 shows an example of generation of processor information in the specific example 5. First, in the first processor information, processors are assigned in the order of abab... In the order of hash values. At this time, the processor allocation period x is two. The number y of processors to be added is three. When x and y are compared, since x is less than y, x is subtracted from y, and the shift amount s becomes 1 (= y−x) (S301, S303 to S305). Next, the PUID for one period of the first processor information is stored in the work array PI (S306). FIG. 12 (1) shows the PI at this time. The PUIDs of existing processors, a and b are stored in the PI. Next, as in the part (1) of PI2 in FIG. 12, PI is copied to PI2, and PUID = c, d, and e of the processor to be added are added (S307). Next, the working array PI is cyclically shifted in the head direction by the shift amount s = 1 (S308). FIG. 12 (2) shows the PI at this time. As shown in the part (2) of PI2 in FIG. 12, this PI is additionally copied to PI2, and PUID = c, d, and e of the processor to be added are added (S307). When the PI is further cyclically shifted by the shift amount s, the original working array PI is restored as shown in FIG. Since the PI has returned to the original PI (S309), the PI2 at this time is stored as one cycle and periodically stored as second processor information (S310). Here, the shift amount is 1 (= y−x), but y (= 3) may be used as the shift amount regardless of the magnitude relationship between x and y. This is because an array having a size of 2 can obtain the same result regardless of whether the shift amount is 1 or 3.

  As described above, also in this specific example, when adding a processor, a new processor is added so that there is no movement of records between existing processors by cyclically shifting the number of processors to which the working array PI is added. Information can be generated. Therefore, it is possible to eliminate data movement between existing processors and perform data relocation at a higher speed.

  As described above, in the third embodiment, when a processor is added, a cyclic shift is performed by the number of processors to which the work array PI is added. As a result, new processor information can be generated so that there is no movement of records between existing processors. Therefore, it is possible to eliminate data movement between existing processors and perform data relocation at a higher speed.

  Next, a fourth embodiment of the present invention will be described. In this embodiment, a specific example of a second processor information generation method different from the third embodiment will be described. In the present embodiment, the same second processor information as in the third embodiment is obtained.

  FIG. 14 shows an example of a method for generating new processor information according to this embodiment. This operation is performed in step S101 in FIG. 4 or step S201 in FIG.

  First, let z be the number of existing processors and y be the number of processors to be added. Also, PI2 is prepared as a storage array for the generated new processor information (second processor information).

  Then, the first processor information is copied to the array PI2 (S401). At this time, all the first processor information is copied to PI2 instead of one cycle. Next, z pieces are skipped from the top of PI2, and y pieces of PUIDs of processors to be subsequently added are overwritten (S402). This is repeated until the end of PI2 (S403). When the end of PI2 is reached, PI2 is set as second processor information (S404).

  When the first processor information is periodically assigned, the period of the second processor information is xx (x + y), and thus the size of PI2 can be xx (x + y). At this time, the number of skips in step S402 is the period x of the first processor information, and in step 404, PI2 is periodically stored as the second processor information.

  By doing in this way, the same second processor information as in the third embodiment can be obtained in the fourth embodiment. That is, the same results as those of the specific examples 1 to 6 can be obtained.

  As described above, in the fourth embodiment, only the PUID of the processor to be added is overwritten on the first processor information. As a result, new processor information can be generated so that there is no movement of records between existing processors. Therefore, it is possible to eliminate data movement between existing processors and perform data relocation at a higher speed.

  Furthermore, although the third embodiment is based on the premise that the first processor information is periodically configured, the fourth embodiment is also applied to the case where the first processor information is not periodic. be able to.

  As another embodiment, the generation of the second processor information described in the third or fourth embodiment can be executed by another device connected to the database server without performing it inside the processor. is there. In this case, the second processor information generated by the external device is transferred to each processor of the database server by some means, and the records are rearranged based on the first processor information and the second processor information.

  Each of the above-described embodiments is a preferred embodiment of the present invention, and various modifications can be made without departing from the scope of the present invention.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
Multiple processors,
A record storage unit that stores the record that is referred to by each of the processors and stores the record different for each processor based on the hash value, with respect to the record that associates the key information and the hash value and data derived from the key information.
For all the hash values, a first processor information storage unit that stores first processor information in which each hash value is associated with processor identification information that identifies the processor that refers to the record of the hash value When,
With
Each of the processors
A communication unit that communicates with another processor or another device and receives a processor addition notification including the processor identification information of the added processor when the processor is newly added;
When the processor addition notification is received, the second processor replaces the processor identification information associated with the hash value of a part of the first processor information with the processor identification information of the added processor Information is generated, and based on the first processor information and the second processor information, the record is rearranged from the record storage unit referenced by the own processor to the record storage unit referenced by the processor And a storage control unit.

(Appendix 2)
One of the plurality of processors functions as a master processor,
The database server according to appendix 1, wherein the storage control unit of the master processor distributes the second processor information to the processors via the communication unit.

(Appendix 3)
The storage control unit further includes the first processor when the processor identification information of the first processor information is periodically assigned to each hash value in the generation of the second processor information. An array of the processor identification information for one cycle of information is cyclically shifted in the head direction of the hash value by the number of added processors, and the result of the cyclic shift and the processor identification information of the added processor are obtained. The database server according to appendix 1 or appendix 2, wherein the database server is alternately stored as the second processor information.

(Appendix 4)
Further, in the generation of the second processor information, the storage control unit periodically assigns the number of the existing processors or the processor identification information of the first processor information to each hash value. The first processor information period is set as the skip number, the first processor information is copied to the second processor information, and the processor identification of the skip number is compared with the second processor information. The database server according to appendix 1 or appendix 2, wherein skipping of information and overwriting of the processor identification information of the added processor are repeated.

(Appendix 5)
The processor information newly generated by accepting input of processor information in which a hash value and processor identification information for identifying a processor that can refer to the record of the hash value are associated with the processor identification information of the processor to be added Processor information communication unit for outputting,
A processor information generation unit that generates new processor information, in which the processor identification information associated with the hash value of a part of the processor information is replaced with the processor identification information of the processor to be added. A processor information generation device.

(Appendix 6)
In the generation of the new processor information, the processor information generation unit further includes one cycle of the processor information when the processor identification information of the processor information is periodically assigned to each hash value. The array of the processor identification information is repeatedly cyclically shifted in the head direction of the hash value by the number of the added processors, and the result of the cyclic shift and the processor identification information of the added processor are alternately used for the new processor. The processor information generation device according to appendix 5, wherein the processor information generation device is stored as information.

(Appendix 7)
In the generation of the new processor information, the processor information generation unit is further configured to periodically allocate the number of the existing processors or the processor identification information of the processor information to each hash value. The processor of the processor in which the cycle of the processor information is set as a skip number, the processor information is copied to the new processor information, and the skip number of the processor identification information is added to the new processor information. The processor information generation device according to appendix 5, wherein the identification information is repeatedly overwritten.

(Appendix 8)
A record in which a plurality of processors, key information, a hash value derived from the key information, and data are associated with each other is referred to by each of the processors, and the record different for each processor is stored based on the hash value In a database server comprising a record storage unit,
Each of the processors
The processor identification information of the processor that refers to each hash value and the record of the hash value for all the hash values when a processor addition notification including processor identification information that identifies the added processor is received. Generating second processor information in which the processor identification information associated with a part of the hash values is replaced with the processor identification information of the added processor. Based on the first processor information and the second processor information, the record is rearranged from the record storage unit referred to by the own processor to the record storage unit referred to by the processor. Placement method.

(Appendix 9)
One of the plurality of processors functions as a master processor,
The relocation method according to appendix 8, wherein the master processor distributes second processor information to the processors.

(Appendix 10)
Furthermore, in the generation of the second processor information, when the processor identification information of the first processor information is periodically assigned to each hash value, one cycle of the first processor information The number of the processors to which the array of processor identification information is added is repeatedly cyclically shifted in the head direction of the hash value, and the result of the cyclic shift and the processor identification information of the added processor are alternately used for the second processor. 10. The rearrangement method according to appendix 8 or appendix 9, wherein the rearrangement method is stored as information.

(Appendix 11)
Further, in the generation of the second processor information, when the number of the existing processors or the processor identification information of the first processor information is periodically assigned to each hash value, the first processor information is generated. The first processor information is copied to the second processor information, and the number of skips of the processor identification information is added to the second processor information. The relocation method according to appendix 8 or appendix 9, wherein the processor identification information of the processor is repeatedly overwritten.

(Appendix 12)
From the processor information in which a hash value and processor identification information for identifying a processor that can refer to the record of the hash value are associated with each other, and the processor identification information of the processor to be added, the hash value of a part of the processor information A new processor information is generated by replacing the processor identification information associated with the processor identification information of the processor to be added.

(Appendix 13)
Furthermore, in the generation of the new processor information, when the processor identification information of the processor information is periodically assigned to each hash value, an array of the processor identification information for one cycle of the processor information is obtained. The number of added processors is repeatedly cyclically shifted in the head direction of the hash value, and the result of the cyclic shift and the processor identification information of the added processor are alternately stored as the new processor information. The processor information generation method according to appendix 12.

(Appendix 14)
Further, in the generation of the new processor information, when the number of existing processors or the processor identification information of the processor information is periodically assigned to each hash value, the cycle of the processor information is skipped. The processor information is copied to the new processor information, and the skip of the processor identification information for the number of skips and the overwrite of the processor identification information of the added processor are repeated for the new processor information. The processor information generation method according to appendix 12, characterized in that:

(Appendix 15)
Multiple processors,
A record storage unit that stores the record that is referred to by each of the processors and stores the record different for each processor based on the hash value, with respect to the record that associates the key information and the hash value and data derived from the key information.
For all the hash values, a first processor information storage unit that stores first processor information in which each hash value is associated with processor identification information that identifies the processor that refers to the record of the hash value When,
On a computer with
A communication function for communicating with another processor or another device and receiving a processor addition notification including the processor identification information of the added processor when the processor is newly added;
When the processor addition notification is received, the second processor replaces the processor identification information associated with the hash value of a part of the first processor information with the processor identification information of the added processor Information is generated, and based on the first processor information and the second processor information, the record is rearranged from the record storage unit referenced by the own processor to the record storage unit referenced by the processor Relocation program to realize storage control function.

(Appendix 16)
One of the plurality of processors functions as a master processor,
The relocation program according to appendix 15, wherein the storage control function of the master processor distributes second processor information to the processors.

(Appendix 17)
The storage control function further includes the first processor when the processor identification information of the first processor information is periodically assigned to each hash value in the generation of the second processor information. The processor identification information array for one period of information is repeatedly cyclically shifted in the head direction of the hash value by the number of the added processors, and the result of the cyclic shift and the added processor identification information of the processor are alternated. The relocation program according to appendix 15 or appendix 16, wherein the relocation program is stored as the second processor information.

(Appendix 18)
In the storage control function, in the generation of the second processor information, the number of the existing processors or the processor identification information of the first processor information is periodically assigned to each hash value. The first processor information period is set as the number of skips, the first processor information is copied to the second processor information, and the number of skips corresponding to the second processor information. The relocation program according to appendix 15 or appendix 16, wherein skipping of the identification information and overwriting of the processor identification information of the added processor are repeatedly performed.

(Appendix 19)
On the computer,
The processor information newly generated by accepting input of processor information in which a hash value and processor identification information for identifying a processor that can refer to the record of the hash value are associated with the processor identification information of the processor to be added Processor information communication function for outputting
To realize a processor information generation function for generating new processor information by replacing the processor identification information associated with the hash value of a part of the processor information with the processor identification information of the processor to be added. Processor information generation program.

(Appendix 20)
The processor information generation function is further configured to generate one cycle of the processor information when the processor identification information of the processor information is periodically assigned to each hash value in the generation of the new processor information. The new processor information is alternately and cyclically shifted in the head direction of the hash value by the number of the processors to which the array of the processor identification information is added, and the result of the cyclic shift and the processor identification information of the added processor alternately. The processor information generation program according to appendix 19, wherein the processor information generation program is stored as

(Appendix 21)
The processor information generation function is further configured such that when the new processor information is generated, the number of existing processors or the processor identification information of the processor information is periodically assigned to each hash value. The processor information cycle is the number of skips, the processor information is copied to the new processor information, and the skip of the processor identification information of the skip number is added to the new processor information. The processor information generation program according to appendix 19, wherein the processor identification information is repeatedly overwritten.

(Appendix 22)
A computer-readable recording medium on which the rearrangement program according to any one of Supplementary Note 16 to Supplementary Note 18 is recorded.

(Appendix 23)
A computer-readable recording medium on which the processor information generation program according to any one of appendix 19 to appendix 21 is recorded.

DESCRIPTION OF SYMBOLS 1 Database server 10 Processor 11 Communication part 12 Storage control part 13 Record storage part 14 1st processor information storage part

Claims (10)

Multiple processors,
A record storage unit that stores the record that is referred to by each of the processors and stores the record different for each processor based on the hash value, with respect to the record that associates the key information and the hash value and data derived from the key information.
For all the hash values, a first processor information storage unit that stores first processor information in which each hash value is associated with processor identification information that identifies the processor that refers to the record of the hash value When,
With
Each of the processors
A communication unit that communicates with another processor or another device and receives a processor addition notification including the processor identification information of the added processor when the processor is newly added;
When the processor addition notification is received, the second processor replaces the processor identification information associated with the hash value of a part of the first processor information with the processor identification information of the added processor Information is generated, and based on the first processor information and the second processor information, the record is rearranged from the record storage unit referenced by the own processor to the record storage unit referenced by the processor And a storage control unit. One of the plurality of processors functions as a master processor,
The database server according to claim 1, wherein the storage control unit of the master processor distributes the second processor information to the processors via the communication unit. The storage control unit further includes the first processor when the processor identification information of the first processor information is periodically assigned to each hash value in the generation of the second processor information. An array of the processor identification information for one cycle of information is cyclically shifted in the head direction of the hash value by the number of added processors, and the result of the cyclic shift and the processor identification information of the added processor are obtained. The database server according to claim 1 or 2, wherein the database server is alternately stored as the second processor information. Further, in the generation of the second processor information, the storage control unit periodically assigns the number of the existing processors or the processor identification information of the first processor information to each hash value. The first processor information period is set as the skip number, the first processor information is copied to the second processor information, and the processor identification of the skip number is compared with the second processor information. The database server according to claim 1 or 2, wherein skipping of information and overwriting of the processor identification information of the added processor are repeatedly performed. A record in which a plurality of processors, key information, a hash value derived from the key information, and data are associated with each other is referred to by each of the processors, and the record different for each processor is stored based on the hash value For database servers with record storage,
Receiving and processor information associating the processor identification information identifying the processor can refer to the record of the hash value and the hash value, the input of the processor identification information of the processor to be added, the newly generated A processor information communication unit for outputting the processor information;
A processor information generation unit that generates new processor information, in which the processor identification information associated with the hash value of a part of the processor information is replaced with the processor identification information of the processor to be added. A processor information generation device. A record in which a plurality of processors, key information, a hash value derived from the key information, and data are associated with each other is referred to by each of the processors, and the record different for each processor is stored based on the hash value In a database server comprising a record storage unit,
Each of the processors
The processor identification information of the processor that refers to each hash value and the record of the hash value for all the hash values when a processor addition notification including processor identification information that identifies the added processor is received. Generating second processor information in which the processor identification information associated with a part of the hash values is replaced with the processor identification information of the added processor. Based on the first processor information and the second processor information, the record is rearranged from the record storage unit referred to by the own processor to the record storage unit referred to by the processor. Placement method. A record in which a plurality of processors, key information, a hash value derived from the key information, and data are associated with each other is referred to by each of the processors, and the record different for each processor is stored based on the hash value For database servers with record storage,
And processor information associating the processor identification information identifying the processor can refer to the record of the hash value and the hash value from said processor identification information of the processor to be added, a portion of the processor information A new processor information is generated by replacing the processor identification information associated with the hash value with the processor identification information of the processor to be added. Multiple processors,
A record storage unit that stores the record that is referred to by each of the processors and stores the record different for each processor based on the hash value, with respect to the record that associates the key information and the hash value and data derived from the key information.
For all the hash values, a first processor information storage unit that stores first processor information in which each hash value is associated with processor identification information that identifies the processor that refers to the record of the hash value When,
On a computer with
A communication function for communicating with another processor or another device and receiving a processor addition notification including the processor identification information of the added processor when the processor is newly added;
When the processor addition notification is received, the second processor replaces the processor identification information associated with the hash value of a part of the first processor information with the processor identification information of the added processor Information is generated, and based on the first processor information and the second processor information, the record is rearranged from the record storage unit referenced by the own processor to the record storage unit referenced by the processor Relocation program to realize storage control function. A record in which a plurality of processors, key information, a hash value derived from the key information, and data are associated with each other is referred to by each of the processors, and the record different for each processor is stored based on the hash value For database servers with record storage,
On the computer,
Receiving and processor information associating the processor identification information identifying the processor can refer to the record of the hash value and the hash value, the input of the processor identification information of the processor to be added, the newly generated A processor information communication function for outputting the processor information;
To realize a processor information generation function for generating new processor information by replacing the processor identification information associated with the hash value of a part of the processor information with the processor identification information of the processor to be added. Processor information generation program.   A computer-readable recording medium on which the rearrangement program according to claim 8 or the processor information generation program according to claim 9 is recorded.

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