JP6413332B2 - Circuit design method - Google Patents

Description

The present invention also relates to a circuit design how.

  A semiconductor integrated circuit such as an LSI (Large Scale Integration) is mainly mounted with a circuit synchronized with a clock. A structural example of a semiconductor integrated circuit having a circuit synchronized with a clock is shown in FIG. The semiconductor integrated circuit 700 is, for example, a SoC (System on a Chip) in which a plurality of functions are mounted on one chip, and includes a plurality of circuit blocks (circuit modules A to D) 701A to 701D. The circuit blocks (circuit modules A to D) 701A to 701D have flip-flop circuits that operate with a clock signal CLK supplied from a phase locked loop (PLL) circuit 702, for example.

  For example, a D-type flip-flop circuit shown in FIG. 8A is used as the flip-flop circuit in the semiconductor integrated circuit as shown in FIG. The D-type flip-flop circuit is a circuit that holds input data, and includes eight NAND operation circuits (NAND circuits) 801 to 808 and two inverters 809 and 810 connected as shown in FIG. Have In the D-type flip-flop circuit shown in FIG. 8A, as shown in FIG. 8B, the value of the D input is held as the Q output at the rising edge of the input clock signal CK. Thus, in the D-type flip-flop, the clock signal CK is used for data retention, and power is consumed each time the clock is driven.

  As another circuit for holding input data, there is a gated D latch circuit as shown in FIG. The gated D latch circuit has four NAND circuits 821 to 824 connected as shown in FIG. In the gated D latch circuit shown in FIG. 9A, as shown in FIG. 9B, when the input gate signal G is at a high level, the value of the D input is transmitted to the Q output, and the gate signal G is Hold Q output when low level. Thus, in the gated D latch circuit, the gate signal G is used for data retention, and power is consumed when the gate signal G changes.

  The semiconductor integrated circuit is designed in consideration of timing. In a semiconductor integrated circuit, the path (transmission path) subject to timing analysis is a path from the flip-flop circuit to the flip-flop circuit, a path from the input port (input terminal) to the flip-flop circuit, and an output port from the flip-flop circuit (output) Terminal) and a path from an input port (input terminal) to an output port (output terminal).

  Here, since the flip-flop circuit holds the input data in synchronization with the input clock signal, the input timing of the clock signal and the input data satisfies the setup time and hold time required by the flip-flop circuit. Need to be implemented. For example, the input data value is not switched with respect to the edge of the clock signal in which the input data is held in the flip-flop circuit in a period longer than the hold time required by the flip-flop circuit.

  Therefore, in the design of semiconductor integrated circuits, for example, the clock definition and timing constraints of each path in the circuit are described in a timing analysis constraint file such as an SDC (Synopsys Design Constraints) file. Perform timing analysis to analyze whether a hold time violation occurs. Then, the circuit is changed so as to satisfy the timing constraint according to the analysis result.

  For example, in a semiconductor integrated circuit, by replacing some of the flip-flop circuits with a latch circuit having a state that allows input data to pass through to the output side, the delay margin on the input side of the flip-flop circuit can be reduced to the subsequent stage. There has been proposed a design technique for improving the worst delay and optimizing the delay (see, for example, Patent Documents 1 to 3).

JP 2004-56238 A JP 2000-305962 A JP-A-6-68195

  In the flip-flop circuit, a period during which input data longer than the hold time is not switched becomes a margin (hold margin). For example, when designing the logic of a semiconductor integrated circuit, it is possible to provide a hold margin longer than the clock cycle by designing the input data of the flip-flop circuit so that it does not change until after the timing at which the flip-flop circuit holds. . In the semiconductor integrated circuit optimization technique described above, the replacement from the flip-flop circuit to the latch circuit is performed in order to relax the timing constraint on the path between the circuits, and the hold margin is not taken into consideration. An object of the present invention is to provide a circuit design method for optimizing a semiconductor integrated circuit by replacing a flip-flop circuit with a latch circuit in consideration of a hold margin.

One embodiment of a circuit design method is a circuit design method using a computer having an arithmetic processing unit and a storage unit. The circuit design method uses a first clock signal based on timing information of a semiconductor integrated circuit stored in the storage unit. For one or more flip-flop circuits that receive the output of the operating first flip-flop circuit, the arithmetic processing unit determines whether there is a margin of one cycle or more of the first clock signal with respect to the hold time, and the storage unit The processing unit analyzes the data output condition and the data output destination in the first flip-flop circuit based on the circuit configuration information of the semiconductor integrated circuit stored in . When the arithmetic processing unit has a judgment result, there is a margin regarding the hold time of the one or more flip-flop circuits, and the analysis result, the data output condition and the data output destination in the first flip-flop circuit satisfy a predetermined condition The first flip-flop circuit is replaced with a latch circuit.

  The disclosed circuit design method can replace a flip-flop circuit with a latch circuit when there is a hold margin and the circuit configuration satisfies a predetermined condition, and can optimize the circuit in consideration of the hold margin. It becomes possible.

It is a flowchart which shows the example of the circuit design method by embodiment of this invention. It is a figure which shows the example of the semiconductor integrated circuit of the optimization object in this embodiment. It is a figure which shows the example of the semiconductor integrated circuit after the circuit replacement in this embodiment. It is a figure which shows the other example of the semiconductor integrated circuit of the optimization object in this embodiment. It is a figure which shows the other example of the semiconductor integrated circuit of the optimization object in this embodiment. It is a figure which shows the structural example of the computer which can implement | achieve the circuit design method by this embodiment. It is a figure which shows the structural example of a semiconductor integrated circuit. It is a figure for demonstrating the structure and operation | movement of a D-type flip-flop circuit. It is a figure for demonstrating the structure and operation | movement of a gated D latch circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  The circuit design method according to the embodiment of the present invention can be realized by, for example, a computer (design apparatus) as shown in FIG. 6, and the operation of the circuit design method according to the present embodiment is performed by the CPU (Central Processing Unit). FIG. 6 is a diagram illustrating a configuration example of a computer (design apparatus) capable of realizing the circuit design method according to the present embodiment. A CPU 602, a ROM (Read Only Memory) 603, a RAM (Random Access Memory) 604, a network interface 605, an input device 606, an output device 607, and an external storage device 608 are connected to the bus 601.

  The CPU 602 performs data processing and calculation, and controls each component connected via the bus 601. A boot program is stored in the ROM 603 in advance, and the computer is activated when the CPU 602 executes the boot program. A computer program is stored in the external storage device 608, and the computer program is copied to the RAM 604 and executed by the CPU 602, whereby, for example, each process of the circuit design method according to the present embodiment is performed. The RAM 604 is used as a work memory for data input / output, transmission / reception, and temporary storage for control of each component.

  The external storage device 608 is, for example, a hard disk storage device or a CD-ROM, and the stored content does not disappear even when the power is turned off. The network interface 605 is an interface for connecting to a network. The input device 606 is, for example, a keyboard or a pointing device (mouse), and can perform various designations and inputs. The output device 607 is a display, a printer, or the like, and can perform display, printing, and the like.

  The circuit design method according to the present embodiment will be described below. The semiconductor integrated circuit to be optimized in the circuit design method according to the present embodiment is mounted on, for example, a SoC (System on a Chip) in which a plurality of functions as shown in FIG. It is an internal circuit including a flip-flop circuit that operates in synchronization. In the following description, only a part of the circuit configuration necessary for the description of the optimization among the circuit configurations of the semiconductor integrated circuit to which the circuit design method according to the present embodiment can be applied will be described. For example, you may have other circuit structures, such as a combinational circuit.

  FIG. 1 is a flowchart illustrating an example of a circuit design method according to the present embodiment. Each illustrated process is executed by, for example, the CPU 100 included in the computer illustrated in FIG. The circuit design method according to the present embodiment shown in FIG. 1 can be applied, for example, at the timing of RTL (Register Transfer Language) design or layout design in the development of a semiconductor integrated circuit. The circuit design method according to the present embodiment shown in FIG. 1 will be described using the circuit having the configuration shown in FIG. 2A as an example.

  FIG. 2A is a diagram showing a configuration example of a semiconductor integrated circuit to be optimized in the present embodiment. In FIG. 2A, the data output side (transfer source) flip-flop circuit SFF-i and selector SSEL-i, the data input side (transfer destination) flip-flop circuit DFF-i and selector DSEL-i, A circuit including flip-flop circuits 201 and 202 is shown as an example. Each of the flip-flop circuits SFF-i, DFF-i, 201, and 202 is a D-type flip-flop circuit as shown in FIG. Note that i is a subscript, and i = 1 to N (N is, for example, 8, 16, 32, 64, etc.) (the same applies below).

  Each of the flip-flop circuits SFF-i on the data output side holds the output of the selector SSEL-i in synchronization with the clock signal CLK and outputs it as the transfer data signal SDATAi. Each of the selectors SSEL-i outputs an input data signal IDATAi or a transfer data signal SDATAi according to the input enable signal EN1. In the example shown in FIG. 2A, the selector SSEL-i outputs the input data signal IDATAi when the enable signal EN1 is “1” (high level), and the enable signal EN1 is “0” (low level). ), The transfer data signal SDATAi is output. That is, the flip-flop circuit SFF-i and the selector SSEL-i on the data output side correspond to a flip-flop circuit with an enable signal that uses the signal EN1 as an enable signal.

  Each of the flip-flop circuits DFF-i on the data input side holds the output of the selector DSEL-i in synchronization with the clock signal CLK and outputs it as an output data signal ODATAi. Each of the selectors DSEL-i outputs a transfer data signal SDATAi or an output data signal ODATAi in response to the enable signal EN2. In the example shown in FIG. 2A, the selector DSEL-i outputs the transfer data signal SDATAi when the enable signal EN2 is “1” (high level), and the enable signal EN2 is “0” (low level). ), The output data signal ODATAi is output. That is, the flip-flop circuit DFF-i and the selector DSEL-i on the data input side correspond to a flip-flop circuit with an enable signal that uses the signal EN2 as an enable signal.

  The flip-flop circuit 201 holds and outputs the input enable signal EN1 in synchronization with the clock signal CLK, and the flip-flop circuit 202 holds the output of the flip-flop circuit 201 in synchronization with the clock signal CLK. And output as an enable signal EN2. That is, the enable signal EN1 input by the flip-flop circuits 201 and 202 is output as the enable signal EN2 after two cycles of the clock signal CLK. The enable signals EN1 and EN2 are asserted to a high level when a new data signal is held. Note that in the circuit shown in FIG. 2A, the assertion of the enable signal EN1 always includes a deassertion period of two cycles or more.

  FIG. 2B is a timing chart illustrating an operation example of the circuit illustrated in FIG. At time T11, the input enable signal EN1 is asserted and becomes high level, and the selector SSEL outputs the input data signal IDATA to the flip-flop circuit SFF. At time T12, which is the rising edge of the clock signal CLK after the enable signal EN1 becomes high level, the flip-flop circuit SFF holds the input data signal IDATA in synchronization with the clock signal CLK and outputs it as the transfer data signal SDATA. To do. The enable signal EN1 is deasserted at the time T12 and becomes low level.

  At time T13, which is the rising edge of the clock signal CLK one cycle after time T12, the enable signal EN2 is asserted and becomes high level, and the selector DSEL outputs the transfer data signal SDATA to the flip-flop circuit DFF. At time T14, which is the rise of the clock signal CLK after the enable signal EN2 becomes high level, the flip-flop circuit DFF holds the transfer data signal SDATA in synchronization with the clock signal CLK and outputs it as the output data signal ODATA. To do.

  When the enable signal EN1 is asserted again at time T14, the flip-flop circuit SFF holds the input data signal IDATA in synchronization with the clock signal CLK at time T15, which is the subsequent rise of the clock signal CLK. And output as the transfer data signal SDATA. That is, at time T15, the transfer data signal SDATA is switched.

  That is, in the example shown in FIG. 2B, the data output side flip-flop circuit SFF that has recognized the assertion of the enable signal EN1 at the rising edge of the clock signal CLK at time T12 outputs data. The flip-flop circuit DFF on the data input side that recognizes the assertion of the enable signal EN2 at the rising edge of the clock signal CLK at time T14 holds the output of the flip-flop circuit SFF on the data output side. Further, the flip-flop circuit SFF on the data output side holds the data until the assertion of the enable signal EN1 is recognized at the rising edge of the clock signal CLK at time T15. That is, in the circuit illustrated in FIG. 2A, the flip-flop circuit DFF has a hold margin for one cycle of the clock signal CLK.

  In the circuit design method according to the present embodiment, attention is paid to the hold margin, and the flip-flop circuit on the data output side is latched when the target path has a hold margin of one cycle or more of the clock signal and satisfies a specific condition. Optimize by replacing with a circuit. As shown in FIG. 1, first, in step S101, based on the timing information 11 of the target semiconductor integrated circuit read from the external storage device or the like, the flip-flop circuit on the data output side in the target path (FIG. 2A). In the example shown in FIG. 5, it is determined whether or not there is a hold margin by the flip-flop circuit SFF). That is, for the flip-flop circuit on the data input side, it is determined whether there is a margin of one cycle or more of the clock signal with respect to the hold time. The timing information 11 only needs to include at least information related to the hold margin among the timing information related to the semiconductor integrated circuit.

  Further, a timing analysis constraint file such as an SDC (Synopsys Design Constraints) file in which timing constraints are described as the timing information 11 may be referenced to determine whether there is a hold margin. For example, in the SDC file, there is a set_multicycle_path constraint as a constraint used when the constraint of timing analysis including the hold timing can be relaxed, such as when the setup is transferred in two cycles or more. In the set_multicycle_path constraint, relaxation regarding the setup time or hold time can be specified by the “setup / hold” option, and the constraint value can specify the data output side (start) or the data input side (end) by the “start / end” option.

For example, for the circuit shown in FIG. 2A, the following set_multicycle_path constraint can be specified as an SDC timing constraint. Since the enable signal EN2 is asserted after two cycles of assertion of the enable signal EN1,
set_multicycle_path -from SFF -to DFF -setup 2
Can be specified. Also, since the assertion of the enable signal EN1 always includes a deassertion period of two cycles or more,
set_multicycle_path -from SFF -to DFF -hold 2
Can be specified.

  When the hold time is specified to be relaxed with the set_multicycle_path constraint as in the previous example, it can be interpreted that the specified path has a hold margin, and the specified path holds by the flip-flop circuit on the data output side. It can be determined that there is a margin. As described above, by creating and recording information on a path having a hold margin, for example, by a logic designer in a constraint file for timing analysis such as an SDC file, the flip-flop on the data output side is recorded in the target path. This makes it easy to determine whether or not there is a hold margin of one cycle or more by the circuit.

  If the result of determination in step S101 is that there is a hold margin (Yes in S101), in step S102, the circuit configuration is determined based on the circuit configuration information 12 such as the net list or RTL design information read from the external storage device or the like. Perform analysis. In the analysis of the circuit configuration, a search for a data output condition in the flip-flop circuit on the data output side and a search for a connection destination of output data from the flip-flop circuit on the data output side are performed. In the flip-flop circuit on the data output side, whether or not there is an enable signal (enable signal EN1 in the example shown in FIG. 2A) that becomes a data output condition (allows data output), and whether or not the data output side Each of the output destinations of data output from the flip-flop circuit is confirmed.

  Subsequently, in step S103, based on the analysis result of the circuit configuration in step S102, it is determined whether or not the flip-flop circuit on the data output side can be replaced with a latch circuit. As a result of the analysis of the circuit configuration in step S102, an enable signal serving as a data output condition exists in the flip-flop circuit on the data output side, and the output destination of the data output from the flip-flop circuit on the data output side is one. In this case, it is determined that the flip-flop circuit on the data output side can be replaced with a latch circuit. In addition, an enable signal serving as a data output condition exists in the flip-flop circuit on the data output side, and there are multiple output destinations of data output from the flip-flop circuit on the data output side, but there are hold margins for all output destinations. In this case, it is determined that the flip-flop circuit on the data output side can be replaced with a latch circuit. In cases other than these two cases, it is determined that the flip-flop circuit on the data output side is not replaced with the latch circuit.

  As a result of the determination in step S103, if it is determined that the flip-flop circuit on the data output side can be replaced with the latch circuit (Yes in S103), the flip-flop circuit on the data output side (and the corresponding selector) is changed. Then, the enable signal is used as a gate signal to replace the latch circuit. Then, the optimized timing information (for example, SDC file) 13 is created as needed, and circuit configuration information (net list, RTL design information, etc.) 14 is created. The created optimized timing information 13 and circuit configuration information 14 are stored in an external storage device or the like.

  For example, the circuit shown in FIG. 2A is optimized by applying the circuit design method according to the present embodiment, whereby the flip-flop circuit SFF and the selector SSEL on the data output side are replaced with a latch circuit, and the circuit shown in FIG. ) Is obtained. FIG. 3A is a diagram illustrating a configuration example of the semiconductor integrated circuit after circuit replacement in the present embodiment. 3A, the same components as those illustrated in FIG. 2A are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 3A, the flip-flop circuit SFF-i and the selector SSEL-i on the data output side shown in FIG. 2A are replaced with a latch circuit SL-i. Each of the latch circuits SL-i is a gated D latch circuit as shown in FIG. Each of the latch circuits SL-i receives an input enable signal EN1 as a gate signal and an input data signal IDATAi as a D input. Each of the latch circuits SL-i outputs a transfer data signal SDATAi as a Q output.

  FIG. 3B is a timing chart illustrating an operation example of the circuit illustrated in FIG. 3A when the input data IDATA and the enable signal EN1 are changed in the same manner as in FIG. At time T21, the input enable signal EN1 is asserted and becomes high level. As the enable signal EN1 input as the gate signal becomes high level, the latch circuit SL outputs the input data signal IDATA as the transfer data signal SDATA. Subsequently, at time T22, the enable signal EN1 input as the gate signal is deasserted and becomes low level, so that the latch circuit SL holds the input data signal IDATA when the enable signal EN1 becomes low level. And output as the transfer data signal SDATA.

  At time T23, which is the rising edge of the clock signal CLK one cycle after time T22, the enable signal EN2 is asserted and becomes high level, and the selector DSEL outputs the transfer data signal SDATA to the flip-flop circuit DFF. At time T24, which is the rise of the clock signal CLK after the enable signal EN2 becomes high level, the flip-flop circuit DFF holds the transfer data signal SDATA in synchronization with the clock signal CLK and outputs it as the output data signal ODATA. To do. At time T24, when the enable signal EN1 input as the gate signal is asserted again and becomes high level, the latch circuit SL outputs the input data signal IDATA as the transfer data signal SDATA.

  That is, in the example shown in FIG. 3B, when the enable signal EN1 input as the gate signal is asserted at the rising edge of the clock signal CLK at time T21, the latch circuit SL outputs data. When the enable signal EN1 is deasserted at the rising edge of the clock signal CLK at time T22, the latch circuit SL holds the data at that time. Further, the flip-flop circuit DFF that recognizes the assertion of the enable signal EN2 at the rising edge of the clock signal CLK at time T24 holds the output of the latch circuit SL. The latch circuit SL holds data until the enable signal EN1 input as a gate signal is asserted again.

  Even if the flip-flop circuit SFF (and the selector SSEL) on the data input side is replaced with the latch circuit SL, as shown in FIG. 3B, the output data ODATA is output at the same timing as in FIG. Can do. As shown in FIG. 3A, in order to confirm the influence of the signal switching timing caused by replacing the flip-flop circuit SFF (and the selector SSEL) on the data input side with the latch circuit SL, the changed circuit configuration is used. The timing constraint may be corrected along with the timing analysis.

For example, when the circuit shown in FIG. 2A is changed to the circuit shown in FIG. 3A, the circuit shown in FIG. 2A can be designated.
set_multicycle_path -from SFF -to DFF -setup 2
set_multicycle_path -from SFF -to DFF -hold 2
And constraints
set_multicycle_path -from SL -to DFF -setup 2
set_multicycle_path -from SL -to DFF -hold 1
And may be specified for the circuit shown in FIG.

  According to the present embodiment, a path having a hold margin is extracted based on timing information and circuit configuration information of a semiconductor integrated circuit. When the circuit configuration of the extracted path satisfies a specific condition, data in the path is extracted. The flip-flop circuit (and selector) on the output side is replaced with a latch circuit. In this way, the circuit is optimized in consideration of the hold margin, the flip-flop circuit can be replaced with a latch circuit having different timing characteristics without requiring an additional circuit, and the circuit area can be reduced. It becomes possible to reduce power consumption.

  Further, the circuit configuration to which the optimization by the circuit design method according to the present embodiment is applicable is not limited to the circuit configuration shown in FIG. For example, as shown in FIG. 4, the circuit design according to this embodiment is also applied to a circuit using a flip-flop circuit SFFA-i with enable control instead of the flip-flop circuit SFF-i and selector SSEL-i on the data input side. The method is applicable. If the replacement condition is satisfied as in the above-described embodiment, the flip-flop circuit SFFA-i with enable control is replaced with the latch circuit SL-i, and the circuit shown in FIG. 4 is replaced with the circuit shown in FIG. Thus, the circuit area can be reduced and the power consumption can be reduced.

  Further, for example, as shown in FIG. 5, instead of the selector SSEL-i on the data input side, the input to the corresponding flip-flop circuit SFF-i is connected to the logical product operation circuits (AND circuits) 211-i, 212-. The circuit design method according to this embodiment can also be applied to a circuit controlled by i, the inverter 213-i, and the logical sum operation circuit (OR circuit) 214-i. If the replacement condition is satisfied as in the above-described embodiment, the set of the flip-flop circuit SFF-i, AND circuits 211-i and 212-i, inverter 213-i, and OR circuit 214-i is latch circuit SL-i. 5 can be optimized like the circuit shown in FIG. 3A, the circuit area can be reduced and the power consumption can be reduced.

  In the above example, the flip-flop circuit on the data output side and the flip-flop circuit on the data input side have the same clock domain. However, if the following conditions are satisfied, the flip-flop circuit on the data output side and the data input side Even if the flip-flop circuit on the side is of a different clock domain, this embodiment can be applied. When the clock signal of the flip-flop circuit on the data output side has a hold margin of one cycle or more, and even if the clock signal has a different frequency, the rise of one clock signal is aligned with the rise of the other clock signal. If the condition relating to the search for the connection destination of the output data from the flip-flop circuit on the data output side is satisfied, the flip-flop circuit on the data output side can be replaced with a latch circuit.

  The circuit design method according to the above-described embodiment can be realized by a computer as shown in FIG. 6 executing a program stored in the storage unit, and the program is included in the embodiment of the present invention. Further, a program for causing a computer to execute each process of the circuit design method described above can be realized by recording the program on a recording medium such as a CD-ROM and causing the computer to read the program. Are included in embodiments of the present invention. As a recording medium for recording the program, besides a CD-ROM, a flexible disk, a hard disk, a magnetic tape, a magneto-optical disk, a nonvolatile memory card, or the like can be used.

  In addition, a program product in which each process of the circuit design method described above is realized by a computer executing a program and processing is included in the embodiment of the present invention. Examples of the program product include a program itself that realizes the processing of the circuit design method described above, and a computer in which the program is read. The program product includes a transmission device that can provide the program to a computer that is communicably connected via a network, a network system that includes the transmission device, and the like.

  Further, when the supplied program realizes the processing of the circuit design method described above in cooperation with an OS (operating system) running on a computer or other application software, the program is an embodiment of the present invention. include. Also, when all or part of the processing of the supplied program is performed by the function expansion board or function expansion unit of the computer and the processing of the circuit design method described above is realized, such program is included in the embodiment of the present invention. included. In order to use the present invention in a network environment, all or a part of the program may be executed by another computer.

The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Various aspects of the present invention will be described below as supplementary notes.

(Appendix 1)
One or more flip-flop circuits receiving the output of the first flip-flop circuit operating with the first clock signal based on the timing information of the semiconductor integrated circuit, and at least one cycle of the first clock signal with respect to the hold time Determining whether there is room for
Analyzing a data output condition and a data output destination in the first flip-flop circuit based on circuit configuration information of the semiconductor integrated circuit;
As a result of the determination, there is a margin of one cycle or more of the first clock signal with respect to the hold time of the one or more flip-flop circuits, and the analysis result, the data output condition and the data output in the first flip-flop circuit And a step of replacing the first flip-flop circuit with a latch circuit when the destination satisfies a predetermined condition.
(Appendix 2)
The circuit design method according to appendix 1, wherein the timing information is obtained from a file in which timing constraints in the semiconductor integrated circuit are described.
(Appendix 3)
3. The circuit design method according to claim 1, wherein when the first flip-flop circuit is replaced with the latch circuit, timing information and circuit configuration information of the semiconductor integrated circuit after the replacement are created.
(Appendix 4)
In the analysis of the data output condition in the first flip-flop circuit, it is determined whether or not it has a signal for permitting data output in the first flip-flop circuit;
The analysis of the data output destination of the first flip-flop determines whether or not the data output destination of the first flip-flop circuit is only the one or more flip-flop circuits. The circuit design method according to any one of 1 to 3.
(Appendix 5)
The one or more flip-flop circuits operate with a second clock signal;
The circuit design method according to any one of appendices 1 to 4, wherein the first clock signal and the second clock signal are the same clock signal.
(Appendix 6)
The one or more flip-flop circuits operate with a second clock signal;
Any one of Supplementary notes 1 to 4, wherein the first clock signal and the second clock signal have different frequencies, and one clock signal rises at the same timing as the rise of the other clock signal. The circuit design method described.
(Appendix 7)
A deassertion period of two cycles or more synchronized with the first clock signal is inserted and an enable signal to be asserted is supplied. When the enable signal is asserted, input data synchronized with the first clock signal is input. And a latch circuit that holds the output when the enable signal is deasserted,
A semiconductor integrated circuit comprising: a flip-flop circuit that holds an output of the latch circuit in response to the enable signal synchronized with a second clock signal and the second clock signal.
(Appendix 8)
One or more flip-flop circuits receiving the output of the first flip-flop circuit operating with the first clock signal based on the timing information of the semiconductor integrated circuit, and at least one cycle of the first clock signal with respect to the hold time Determining whether there is room for
Analyzing a data output condition and a data output destination in the first flip-flop circuit based on circuit configuration information of the semiconductor integrated circuit;
As a result of the determination, there is a margin of one cycle or more of the first clock signal with respect to the hold time of the one or more flip-flop circuits, and the analysis result, the data output condition and the data output in the first flip-flop circuit A program for causing a computer to execute a step of replacing the first flip-flop circuit with a latch circuit when the destination satisfies a predetermined condition.

11 Timing information 12 Circuit configuration information 13 Timing information (after optimization)
14 Circuit configuration information (after optimization)
SFF, SFFA, DFF, 201, 202 Flip-flop circuit SL Latch circuit SSEL, DSEL Selector 601 Bus 602 CPU
603 ROM
604 RAM
605 Network interface 606 Input device 607 Output device 608 External storage device

Claims (4)

A circuit design method using a computer having an arithmetic processing unit and a storage unit,
The one or more flip-flop circuits that receive the output of the first flip-flop circuit that operates with the first clock signal based on the timing information of the semiconductor integrated circuit stored in the storage unit . A step in which the arithmetic processing unit determines whether or not there is a margin of one cycle or more of one clock signal;
A step in which the arithmetic processing unit analyzes a data output condition and a data output destination in the first flip-flop circuit based on circuit configuration information of the semiconductor integrated circuit stored in the storage unit ;
The arithmetic processing unit has a margin of one cycle or more of the first clock signal with respect to a hold time of the one or more flip-flop circuits, and the analysis result indicates that the first flip-flop circuit And a step of replacing the first flip-flop circuit with a latch circuit when a data output condition and a data output destination satisfy predetermined conditions. The circuit design method according to claim 1, wherein the timing information is acquired from a file stored in the storage unit and describing timing constraints in the semiconductor integrated circuit. 3. The arithmetic processing unit creates timing information and circuit configuration information of the semiconductor integrated circuit after replacement when the first flip-flop circuit is replaced with the latch circuit. Circuit design method. And in the analysis of the first data output condition in flip-flop circuits, whether with a signal for permitting data output in the first flip-flop circuit is the arithmetic processing unit determines,
And in the analysis of the data output destination of the first flip-flop circuit, whether data output destination of the first flip-flop circuit is only the one or more flip-flop circuits the arithmetic processing unit determines The circuit design method according to claim 1, wherein the circuit design method is performed.

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