JP6412530B2 - Histogram partitioning-based local adaptive filter for video encoding and decoding - Google Patents

Description

  This application relates to video compression.

  In lossy video encoding, the quality of multiple restored images degrades due to quantization of multiple transform coefficients. As the quantization step increases, the loss of image quality increases.

  To improve the quality of the restored image and improve the video compression gain, the adaptive filter is used as an out-loop video processing tool or in the core video coding pipeline that partially compensates for image quality loss It may be applied as part of a plurality of in-loop modules.

Some embodiments are described with reference to the following figures.
An example of the encoding flow for the filtering decision in the case where a plurality of histogram division methods are applied is shown. The flow of the corresponding decoder is shown. It is description of the system which concerns on one Embodiment. It is a front view of one embodiment.

  Considering that the global Wiener filter may lose its adaptation to some local pixel information, apply the Wiener filter locally to multiple adaptively selected pixels and filter multiple pixels for filtering A histogram partitioning scheme can be used to help select However, the Wiener filter may lack the ability to handle certain quality losses within the histogram bin. Thus, a modified Wiener filter with an offset may be used to adaptively filter multiple bins of the histogram.

  The quality of the restored image in the video codec system is to classify the restored pixels into different histogram bins by histogram partitioning and then apply different filters to different bins Can be improved. The histogram division may be performed by dividing the histogram evenly into M bins or adaptively dividing the histogram into N bins based on a plurality of histogram characteristics. For example, if the pixel value range is 0-255, dividing the histogram evenly into M bins means that each bin has an interval of 256 / M pixel values. Here, M and N may be positive integer values that are predetermined and fixed, or values that are adaptively generated on the encoder side, and are transmitted to the decoder via the encoded bitstream. Also good. Multiple histogram characteristics involve multiple distributions of pixel values. Many documents have been published that introduce multiple methods of histogram segmentation and / or partitioning.

  The quality of the image restored by the video codec system applies multiple available histogram partitioning schemes to determine the best partitioning scheme for filtering based on rate distortion optimization (RDO) criteria at the encoder side, It can then be improved by sending a flag indicating the decision result to the decoder. The quality of the image restored by the video codec system is filtered through adaptively applying multiple filters to multiple bins of the histogram divided based on RDO criteria, and then through the encoded bitstream This can be improved by sending multiple flags indicating multiple bins of the histogram to be.

  An adaptive Wiener filter may be applied with an offset for the histogram bin. The offset values for the multiple Wiener filter coefficients and histogram bins are adaptively generated at the encoder side, and the multiple coefficients and offset values may then be sent to the decoder via the encoded bitstream. . A Wiener filter with an offset is applied to a plurality of reconstructed pixels P (x, y) in the histogram bin to obtain a filtered pixel value P ′ (x, y) for the bin. Next, as shown in FIG. 1, a plurality of Wiener filter coefficients and offset values are obtained between the pixel value P ′ (x, y) filtered on the encoder side and the original input pixel value Q (x, y). The total absolute difference (SSD) may be minimized and then multiple coefficients and offset values may be calculated by being sent to the decoder via the encoded bitstream. In some embodiments, the offset value may be forced to zero and only a plurality of Wiener filter coefficients need be generated at the encoder side and then transmitted to the decoder.

  In some embodiments, only the offset value is applied to the histogram bin without applying a Wiener filter. In this case, only the offset value needs to be generated for the histogram bin at the encoder side and then sent to the decoder.

  In some embodiments, some of the plurality of Wiener filter coefficients may be forced to zero to save transmission bandwidth, and the plurality of coefficients may not be transmitted to the decoder.

  The quality of the image restored by the video codec system is selected by adaptively selecting global filtering or local filtering based on histogram division based on RDO criteria at the encoder side, and then sending a flag indicating the selection result to the decoder, It can be improved. Global filtering is actually a special case of histogram partitioning based local filtering. When the entire histogram is considered a single bin (no splitting), local filtering is actually a global filtering for all of the pixels in the image. In FIG. 1, in order to “not divide” in this case, one histogram division method can be set.

  The quality of the image restored in the video codec system is determined adaptively on the encoder side based on the RDO criterion on the frame to be filtered (or not to be filtered), and then a flag indicating the determination result is sent to the decoder. It can be improved by transmitting.

（１） ここで、Ｃｍ，ｎは、複数の適応フィルタリング係数を意味し、オフセットは、対応するヒストグラムの複数のビンに加算されたオフセット値を意味する。Ｍ０，Ｍ１，Ｎ０，Ｎ１は、ウィーナーフィルタタップの数を制御する複数のパラメータである。以下のリストの複数の変数Ｍ０，Ｍ１，Ｎ０，Ｎ１で複数の異なる設定をすることにより、フィルタは、対称フィルタまたは非対称フィルタ、１−Ｄフィルタまたは２−Ｄフィルタであってもよい。複数のパラメータＭ０，Ｍ１，Ｎ０，Ｎ１は、予め定められた複数の固定値に設定されてもよい。これらの複数の固定値は、エンコーダ及びデコーダの両方が複数の同一の値を用いることができるように、ビデオ符号化規格の仕様において提示され得る。代わりに、Ｍ０，Ｍ１，Ｎ０，Ｎ１は、いくつかの予め定められた候補値を有してもよい。次に、エンコーダは、ＲＤＯ基準に基づいて最良の候補を選択し、次に、用いられる候補を示すフラグをデコーダに送信することができる。 In video codecs, the adaptive Wiener filter aims to minimize the difference between two input images or image regions and the multiple filter coefficients that need to be transmitted to the decoder side. Q (x, y) means the value of the encoder input pixel at the position (x, y), and P (x, y) means the restored pixel value before filtering at the position (x, y). It shall be. Adaptive Wiener filtering with an offset is performed on P (x, y) as shown in equation (1) to obtain the pixel value P ′ (x, y) after filtering.

(1) Here, Cm, n means a plurality of adaptive filtering coefficients, and offset means an offset value added to a plurality of bins of the corresponding histogram. M0, M1, N0, and N1 are a plurality of parameters that control the number of Wiener filter taps. By making a plurality of different settings with a plurality of variables M0, M1, N0, N1 in the following list, the filter may be a symmetric filter or an asymmetric filter, a 1-D filter or a 2-D filter. The plurality of parameters M0, M1, N0, and N1 may be set to a plurality of predetermined fixed values. These multiple fixed values may be presented in the specification of the video coding standard so that both the encoder and decoder can use multiple identical values. Alternatively, M0, M1, N0, N1 may have a number of predefined candidate values. The encoder can then select the best candidate based on the RDO criteria and then send a flag to the decoder indicating the candidate used.

  The plurality of coefficients Cm, n and the offset value Offset may be adaptively generated at the encoder side, and then may be encoded into a plurality of bit streams for decoding. One way to generate Cm, n and Offset values is to minimize the sum of squares of multiple distortions between Q (x, y) and P ′ (x, y).

［２］ 入力画素Ｑ（ｉ）及びウィーナーフィルタリングされた画素Ｐ'（ｉ）の中の残留信号は、以下の通り定義される。

［３］ ウィーナーフィルタは、平均二乗誤差を複数のフィルタタップ｛Ｃｉ｝で最小化することにより最適となる。

［４］ ここで、Ｅ［］は、一連の複数の画像、画像又は画像内部のいくつかの領域からの複数の画素であり得る関心の複数の画素に対する残留信号の二乗の予測値である。

［５］ Ｅ［ｅｒｒｏｒｋ２］の最小値を導くために、導関数がＣｉに関してとられる。複数のフィルタタップは、導関数をゼロと等しくすることにより、導かれることができる。

［６］ 自己相関関数Ｐ（ｋ）は、以下の式［７］で示され、Ｐ（ｋ）及びＱ（ｋ）の中の相互相関関数は、以下の式［８］で示される。

［７］

［８］ 式［５］は、行列形式で書き直すことができる。

［９］ このように、ウィーナーフィルタタップセット｛Ｃ｝は、行列形式で導かれることができる。

［１０］ ここで、ＲＰＰ−１は、式［９］の自己相関行列の逆行列である。Ｃｉは、取得後、Ｃｍｎに再びマッピングされることができる。次に、オフセットは、次式により計算されることができ、ここで、Ｎはヒストグラムビン内の複数の画素の数である。

The differentiation of the plurality of filter taps is shown below. For the sake of simplicity, it is assumed that the 2D filter tap Cmn can be mapped to the 1D filter tap Ci and the 2D pixel index (x, y) can be mapped to the 1D pixel index (i). Consider an input pixel Q (k) and a Wiener filter output P ′ (k) of size L + 1 and weight Ci and consisting of mapped pixels P (k) reconstructed with filter support {S}. The adaptive (Wiener) filter function is:

[2] The residual signal in the input pixel Q (i) and the Wiener filtered pixel P ′ (i) is defined as follows.

[3] The Wiener filter is optimized by minimizing the mean square error with a plurality of filter taps {Ci}.

[4] where E [] is the predicted value of the square of the residual signal for a plurality of pixels of interest, which may be a series of images, images or pixels from several regions within the image.

[5] To derive the minimum value of E [error2], the derivative is taken with respect to Ci. Multiple filter taps can be derived by making the derivative equal to zero.

[6] The autocorrelation function P (k) is expressed by the following formula [7], and the cross-correlation function in P (k) and Q (k) is expressed by the following formula [8].

[7]

[8] Equation [5] can be rewritten in matrix form.

[9] Thus, the Wiener filter tap set {C} can be derived in matrix form.

[10] Here, RPP-1 is an inverse matrix of the autocorrelation matrix of Equation [9]. Ci can be re-mapped to Cmn after acquisition. The offset can then be calculated by the following equation, where N is the number of pixels in the histogram bin.

  The autocorrelation functions of equations [7] and [10] can be collected at the video decoder side, but the cross-correlation of equations [8] and [10] Due to the requirement to be obtained, it must be guided on the video encoder side. As described above, it is necessary to transmit the plurality of filter taps derived from the equation [10] from the video encoder to the video decoder.

  The video decoder can derive multiple filter taps by itself receiving the cross-correlation function and the decoded unblocked data {y}, so in some cases the derived multiple Instead of a filter tap, it is sufficient to send a cross-correlation function.

  In some cases, more accurate statistical information may be obtained to further improve coding efficiency by omitting multiple pixels near the image boundary. The right side of Equation [10] is an abbreviation for this.

  Multiple filter taps can be derived per luminance and per saturation channel, respectively. Better encoding efficiency is achieved for chroma images based on multiple filter taps derived by chroma pixels only. Some scenarios can use one saturation table shared by both Cb and Cr channels, or two separate tables for Cb and Cr, respectively.

  This approach is scalable and includes multiple unblocked images and can be extended to function as a reference image in the motion prediction phase in addition to the adaptive filtered image. This ensures that the deblocked image is always accessible on the video decoder side, so that no additional information is sent from the video encoder side, and multiple references can be used to improve the accuracy of motion estimation. Double the amount of images.

  FIG. 4 shows that the delay module of FIG. 2 is placed after the deblocking filter and before the adaptive filter. With the delay module, the generation of multiple adaptive filter taps can be recalculated for each image time based on the current input image for multiple reference images in the buffer list. In this way, the video encoder updates a plurality of filter taps for each reference image. Similarly, FIG. 5 shows the relocation of the delay module in FIG.

  FIG. 6 shows the statistical feature collector and adaptive filter modules added to the output of the motion compensated image to obtain a minimum mean square error solution in the input video and motion compensated image. This improves better coding efficiency in some cases. This adaptive filter after the motion compensation module is independent of the adaptive filter before the motion prediction module, as shown in FIGS. 2-5. Thus, this adaptive filter can also function as an add-on at the top of FIG. 2-5.

  In some scenarios, the coding efficiency of the adaptive filter is better than applying only the deblocking filter. That is, an adaptive filter can be applied to remove the deblocking filter from the core coding loop.

  When filtering an image with a global Wiener filter, a plurality of filter coefficients are learned by all the pixels in the image. In this case, the filtering reduces the distortions of some pixels, but increases the distortions of other pixels. Therefore, more coding gain can be obtained simply by performing Wiener filtering on some of the plurality of pixels in the image.

  One method is to classify the pixels into groups by histogram partitioning and then perform Wiener filtering adaptively (depending on the RDO criteria) for each histogram bin. Histogram division divides a plurality of pixel values into a plurality of bins, where one bin is a group of pixels whose values apply to that bin. Assume that the histogram is divided into N bins (with any kind of histogram division method including multiple methods, either uniform or non-uniform). Next, the encoder determines a plurality of bins to filter and generates a plurality of filtering parameters, i.e., a plurality of coefficients Cm, n and Offset for the plurality of bins that can be filtered bins. Information can be sent to the decoder.

  When applying multiple histogram partitioning methods, the encoder can determine the RDO criteria used to filter the current image and then send the determination results to the decoder. The encoder can perform multi-task coding (one pass for one split method) and calculate the rate distortion (RD) cost for each pass. The path with the lowest RD cost is then used for the last encoding.

  Referring to FIG. 1, the restored unfiltered pixel value P (x, y) at position (x, y) may be provided to the histogram partitioning method 12a-k. In this case, a plurality of histogram division methods are applied, each operating on a value. This produces a plurality of outputs that are provided to a plurality of adaptive filter decisions 14a-14k. The encoder input pixel value Q (x, y) at position (x, y) is also applied to the plurality of adaptive filter decisions 14a-k. Based on these multiple inputs, the multiple adaptive filter decisions output values to a histogram partitioning method decision 16 that in turn produces the desired result. The adaptive filter decision includes an adaptive Wiener filter with an offset.

  Referring to FIG. 2 for the decoder as opposed to the encoder side, the value P (x, y) is applied to the histogram partitioning block 18 according to the received method. When a plurality of histogram division methods are defined, the decoder receives from the encoder a flag indicating the division method selected by the encoder. After receiving the method flag, the decoder can perform histogram division on P (x, y) according to the received method. The output is provided to an adaptive filter 20 for a plurality of histogram bins having a plurality of received filter parameters to output a filtered pixel value P ′ (x, y).

  FIG. 3 illustrates an embodiment of the system 700. In embodiments, the system 700 may be a media system, but the system 700 is not limited to this. For example, the system 700 can be a personal computer (PC), laptop computer, ultra laptop computer, tablet, touchpad, portable computer, handheld computer, palmtop computer, personal digital assistant (PDA), mobile phone, mobile phone / PDA. May be incorporated into a combination, television, smart device (eg, smart phone, smart tablet or smart TV), mobile internet device (MID), messaging device, data communication device, and the like.

  In embodiments, the system 700 includes a platform 702 that is coupled to a display 720. Platform 702 may receive content from a content device, such as content service device 730 or content distribution device 740 or other similar content source. A navigation controller 750 with one or more navigation functions may be used to interact with the platform 702 and / or the display 720, for example. Each of these multiple components is described in more detail below.

  In embodiments, platform 702 includes chipset 705, processor 710, memory 712, storage 714, graphics subsystem 715, multiple applications 716, global positioning system (GPS) 721, camera 723, and / or wireless 718. Any combination may be provided. Chipset 705 may provide intercommunication within processor 710, memory 712, storage 714, graphics subsystem 715, multiple applications 716 and / or wireless 718. For example, the chipset 705 may include a storage adapter (not shown) that can provide mutual communication with the storage 714.

  Further, platform 702 may include an operating system 770. The interface 772 to the processor may be an operating system and processor 710 interface.

  Firmware 790 may be provided to implement functions such as a boot sequence. An update module that allows firmware to be updated from outside the platform 702 may be provided. For example, the update module may include code that determines whether the update attempt is authentic and identifies the latest update of firmware 790 to facilitate determination when multiple updates are required. Good.

  In some embodiments, platform 702 may be powered by an external power source. In some cases, the platform 702 may be an internal battery 780 that functions as a power source in embodiments that do not adapt to an external power source, or in embodiments that allow either battery supplied power or external supplied power. May further be included.

  The sequences shown in FIGS. 1 and 2 are implemented in software and firmware by incorporating them in storage 714 or in memory in processor 710 or graphics subsystem 715 to illustrate a few examples. It may be implemented in the form of a form. In one embodiment, graphics subsystem 715 may include a graphics processing unit and processor 710 may be a central processing unit.

  The processor 710 is an x86 instruction compatible with multiple processors, multiple processors, multi-core or any other microprocessor or central processing unit (CPU) of a complex instruction set computer (CISC) or reduced instruction set computer (RISC). It may be implemented as a set. In embodiments, the processor 710 may comprise a dual core processor, a dual core mobile processor, and the like.

  The memory 712 may be implemented as a volatile memory device such as, but not limited to, random access memory (RAM), dynamic random access memory (DRAM), or static RAM (SRAM).

  Storage 714 includes, but is not limited to, a magnetic disk drive, optical disk drive, tape drive, internal storage device, external storage device, flash memory, battery backup SDRAM (synchronous DRAM) and / or network accessible storage device May be implemented as a non-volatile storage device. In embodiments, for example, when multiple hard drives are included, the storage 714 may include technology that improves protection with enhanced storage performance for critical digital media.

  Graphics subsystem 715 may perform processing of multiple images, such as a still or video for display. The graphics subsystem 715 may be, for example, a graphics processing unit (GPU) or a visual processing unit (VPU). An analog or digital interface may be used to communicatively couple graphics subsystem 715 and display 720. For example, the interface may be any of a plurality of technologies that are compliant with a high resolution multimedia interface, DisplayPort, Wireless HDMI, and / or Wireless HD. Graphics subsystem 715 can be integrated into processor 710 or chipset 705. The graphics subsystem 715 can be a stand-alone card that is communicatively coupled to the chipset 705.

  The multiple graphics and / or video processing techniques described herein may be implemented in a variety of multiple hardware architectures. For example, graphics and / or video functionality may be integrated within the chipset. Alternatively, separate graphics and / or video processors may be used. As yet another embodiment, the graphics and / or video functions may be implemented by a general purpose processor including a multi-core processor. In further embodiments, multiple functions may be implemented in the form of consumer electronics.

  Radio 718 may include one or more radios capable of transmitting and receiving signals using a variety of suitable wireless communication technologies. Such multiple techniques may involve multiple communications over one or more wireless networks. Exemplary wireless networks include (but are not limited to) multiple wireless local area networks (WLAN), multiple wireless personal area networks (WPAN), multiple wireless metropolitan area networks (WMAN), multiple Includes a cellular network and multiple satellite networks. For communication over such multiple networks, the radio 718 may operate according to any version of one or more applicable standards.

  In embodiments, the display 720 may comprise any television type monitor or display. Display 720 may comprise, for example, a computer display screen, touch screen display, video monitor, television type device, and / or television. Display 720 may be digital and / or analog. In embodiments, the display 720 may be a holographic display. The display 720 may also be a transparent surface that can receive visual video. Such multiple videos may carry various forms of information, multiple images and / or multiple objects. For example, such multiple videos may be visual overlays for mobile augmented reality (MAR) applications. Under the control of one or more software applications 716, platform 702 may display user interface 722 on display 720.

  In embodiments, the content service device 730 may be provided by any national, international, and / or independent service, and thus may be accessible to the platform 702 via, for example, the Internet. Content service device 730 may be coupled to platform 702 and / or display 720. Platform 702 and / or content service device 730 may be coupled to network 760 to communicate (eg, send and / or receive) media information with network 760. Content distribution device 740 may also be coupled to platform 702 and / or display 720.

  In embodiments, the content service device 730 may be a cable television box, personal computer, network, telephone, internet-enabled device or appliance capable of transmitting digital information and / or content, and via a network 760 or directly. Any other similar device capable of communicating content in one or both directions between multiple content providers and the platform 702 and display 720 may be provided. It will be appreciated that the content may be unidirectional and / or bi-directionally communicated over the network 760 with any one of multiple components of the system 700 and content providers. Examples of content may include any media information including, for example, video, music, medical and game information, and the like.

  The content service device 730 receives content such as cable television programs that include media information, digital information, and / or other content. Examples of multiple content providers may include any cable or satellite television or radio or Internet multiple content providers. The provided examples are not meant to limit the embodiments of the present invention.

  In embodiments, the platform 702 may receive a plurality of control signals from a navigation controller 750 having one or more navigation functions. The plurality of navigation functions of the controller 750 may be used to interact with the user interface 722, for example. In embodiments, the navigation controller 750 is a computer hardware component (specifically, a human interface device) that allows a user to input spatial (eg, continuous and multi-dimensional) data to a computer. It may be a pointing device to obtain. Multiple systems, such as multiple graphical user interfaces (GUIs) and multiple televisions and multiple monitors, allow users to control and provide data to a computer or television using multiple physical gestures. it can.

  The movements of the navigation functions of the controller 750 are reflected on a display (eg, display 720) by movements of a pointer, cursor, focus ring or other visual indicators displayed on the display. May be. For example, a plurality of navigation functions located on the navigation controller 750 under the control of a plurality of software applications 716 may be mapped to a plurality of virtual navigation functions displayed on the user interface 722, for example. In embodiments, the controller 750 may be integrated into the platform 702 and / or the display 720 rather than a separate component. Embodiments, however, are not limited to or within the elements shown or described herein.

  In embodiments, a plurality of drivers (not shown) can power the platform 702 immediately like a television, for example by touching a button after initial activation by multiple users, if possible. A technique that enables turning on and off may be provided. According to the program logic, the platform 702 may stream content to multiple media adapters or other content service devices 730 or content distribution devices 740 when the platform is turned “off”. Further, chipset 705 may comprise hardware and / or software support for 5.1 surround sound audio and / or high resolution 7.1 surround sound audio, for example. The plurality of drivers may include graphics drivers for a plurality of integrated graphics platforms. In embodiments, the graphics driver may comprise a peripheral component interconnect (PCI) express graphics card.

  In various embodiments, any one or more of the components shown in system 700 may be integrated. For example, platform 702 and content service device 730 may be integrated, or platform 702 and content distribution device 740 may be integrated, or, for example, platform 702, content service device 730, and content distribution. Device 740 may be integrated. In various embodiments, platform 702 and display 720 may be an integrated unit. For example, the display 720 and the content service device 730 may be integrated, or the display 720 and the content distribution device 740 may be integrated. These examples are not meant to limit the invention.

  In various embodiments, system 700 may be implemented as a wireless system, a wired system, or a combination of both. When implemented as a wireless system, system 700 includes a plurality of components suitable for communication over a wireless shared medium, such as one or more antennas, transmitters, receivers, transceivers, amplifiers, filters, control logic, and the like. Multiple interfaces may be included. An example of a wireless shared medium may include a portion of the radio spectrum, such as the RF spectrum. When implemented as a wired system, the system 700 includes a plurality of input / output (I / O) adapters, a plurality of physical connectors for connecting the I / O adapters to corresponding wired communication media, a network interface card (NIC), and a disk controller. A plurality of components and a plurality of interfaces suitable for communication via a wired communication medium such as a video controller, an audio controller, and the like. Examples of wired communication media may include wires, cables, multiple metal leads, printed circuit boards (PCBs), backplanes, switch fabrics, semiconductor materials, twisted pair wires, coaxial cables, optical fibers, and the like.

  Platform 702 may establish one or more logical or physical channels to communicate information. The information may include media information and control information. The media information may refer to arbitrary data representing content for the user. Examples of content include data from, for example, voice conversations, video conferencing, streaming video, email (“email”) messages, voicemail messages, multiple alphanumeric symbols, graphics, images, video, text, etc. May be included. The data from the voice conversation may be, for example, utterance information, a plurality of silence times, background noise, comfort noise, a plurality of tones, and the like. Control information may refer to any data representing multiple commands, instructions or control words for an automated system. For example, the control information may be used to route media information through the system or to instruct a node to process media information in a predetermined manner. Embodiments, however, are not limited to or within the elements shown or described in FIG.

  As described above, the system 700 may be embodied in various physical styles or form factors. FIG. 4 illustrates multiple embodiments of a small form factor device 800 in which the system 700 may be implemented. In embodiments, for example, device 800 may be implemented as a mobile computing device having multiple wireless functions. A mobile computing device may refer to a processing system and any device that has a mobile power source or power supply, such as, for example, one or more batteries.

  As mentioned above, several examples of mobile computing devices include personal computers (PCs), laptop computers, ultra laptop computers, tablets, touchpads, portable computers, handheld computers, palmtop computers, personal digital assistants (PDAs) ), Cell phones, cell phone / PDA combinations, televisions, smart devices (eg, smart phones, smart tablets or smart TVs), mobile internet devices (MID), messaging devices, data communication devices, and the like.

  Examples of mobile computing devices are people such as wrist computers, finger computers, ring computers, eyeglass computers, belt clip computers, armband computers, multiple shoe computers, multiple garment computers, and other multiple wearable computers. A plurality of computers configured to be attached to the computer may further be included. In embodiments, for example, a mobile computing device may be implemented as a smartphone capable of executing multiple computer applications, multiple voice communications, and / or multiple data communications. Some embodiments may be described by way of example with a mobile computing device implemented as a smartphone, although other embodiments are implemented with still other wireless wireless computing devices. It will be appreciated that it may be. The plurality of embodiments are not limited to this content.

  As shown in FIG. 4, the device 800 may include a housing 802, a display 804, an input / output (I / O) device 806 and an antenna 808. The device 800 may further include a plurality of navigation functions 812. Display 804 may comprise any suitable display unit for displaying information suitable for a mobile computing device. The I / O device 806 may comprise any suitable I / O device for entering information into the mobile computing device. Examples of the I / O device 806 include an alphanumeric keyboard, a numeric keypad, a touch pad, a plurality of input keys, a plurality of buttons, a plurality of switches, a plurality of rocker switches, a plurality of microphones, a plurality of speakers, and a voice recognition device. And software may be included. Information may also be input to device 800 using a microphone. Such information may be digitized by a voice recognition device. The plurality of embodiments are not limited to this content.

  Various embodiments may be implemented using multiple hardware elements, multiple software elements, or a combination of both. Examples of multiple hardware elements include multiple processors, multiple microprocessors, multiple circuits, multiple circuit elements (eg, multiple transistors, multiple resistors, multiple capacitors, multiple inductors, etc.), multiple Integrated circuits, multiple application specific integrated circuits (ASIC), multiple programmable logic devices (PLD), multiple digital signal processors (DSP), field programmable gate arrays (FPGA), multiple logic gates, multiple registers A semiconductor device, a plurality of chips, a plurality of microchips, a plurality of chip sets, and the like may be included. Examples of software include multiple software components, multiple programs, multiple applications, multiple computer programs, multiple application programs, multiple system programs, multiple machine programs, operating system software, middleware, firmware, multiple Software module, multiple routines, multiple subroutines, multiple functions, multiple methods, multiple procedures, multiple software interfaces, multiple application program interfaces (APIs), multiple instruction sets, operation codes, computer code, Multiple code segments, multiple computer code segments, multiple words, multiple values, multiple symbols, or any combination thereof It may include a. Determining whether an embodiment is implemented using multiple hardware elements and / or multiple software elements depends on desired computing speed, multiple power levels, multiple heat resistance, processing cycle budget, multiple input data It may vary according to any number of factors such as rate, multiple output data rates, multiple memory resources, multiple data bus speeds and other designs or multiple performance constraints.

  One or more aspects of at least one embodiment represent various logic within a processor, and when read by a machine, the logic to perform the techniques described herein to the machine. It may be implemented by a plurality of representation instructions stored on a machine readable medium that is created. Such multiple representations, known as “IP cores”, are stored on a tangible machine-readable medium and can be read by a variety of manufacturing or multiple manufacturing machines to actually create logic or processors. It may be supplied to the facility.

  Various embodiments may be implemented using multiple hardware elements, multiple software elements, or a combination of both. Examples of multiple hardware elements include multiple processors, multiple microprocessors, multiple circuits, multiple circuit elements (eg, multiple transistors, multiple resistors, multiple capacitors, multiple inductors, etc.), multiple Integrated circuits, multiple application specific integrated circuits (ASIC), multiple programmable logic devices (PLD), multiple digital signal processors (DSP), field programmable gate arrays (FPGA), multiple logic gates, multiple registers A semiconductor device, a plurality of chips, a plurality of microchips, a plurality of chip sets, and the like may be included. Examples of software include multiple software components, multiple programs, multiple applications, multiple computer programs, multiple application programs, multiple system programs, multiple machine programs, operating system software, middleware, firmware, multiple Software module, multiple routines, multiple subroutines, multiple functions, multiple methods, multiple procedures, multiple software interfaces, multiple application program interfaces (APIs), multiple instruction sets, operation codes, computer code, Multiple code segments, multiple computer code segments, multiple words, multiple values, multiple symbols, or any combination thereof It may include a. Determining whether an embodiment is implemented using multiple hardware elements and / or multiple software elements depends on desired computing speed, multiple power levels, multiple heat resistance, processing cycle budget, multiple input data It varies according to any number of factors such as rate, multiple output data rates, multiple memory resources, multiple data bus speeds and other designs or multiple performance constraints.

  One or more aspects of at least one embodiment represent various logic within a processor, and when read by a machine, the logic to perform the techniques described herein to the machine. It may be implemented by a plurality of representation instructions stored on a machine readable medium that is created. Such multiple representations, known as “IP cores”, are stored on a tangible machine-readable medium and can be read by a variety of manufacturing or multiple manufacturing machines to actually create logic or processors. It may be supplied to the facility.

  The multiple graphics processing techniques described herein may be implemented in various multiple hardware architectures. For example, graphics functionality may be integrated within a chipset. Alternatively, a separate graphics processor may be used. As yet another embodiment, the plurality of graphics functions may be implemented by a general-purpose processor including a multi-core processor.

  The following sections and / or examples relate to a plurality of further embodiments. One exemplary embodiment may be a method for adaptively filtering a plurality of bins of a histogram using a Wiener filter with an offset for video encoding. Other exemplary embodiments may use multiple bin splitting methods. The method may further include dividing the histogram evenly into a plurality of bins. The method may further include adaptively dividing the histogram into a plurality of bins. The method may include transmitting a plurality of bin numbers from the encoder to the decoder. The method may include identifying a partitioning method based on a rate distortion optimization criterion. The method includes generating a plurality of adaptive filter coefficients by minimizing a sum of squares of a plurality of distortions between a value of an input pixel at a position and a pixel value after filtering at the position. Further, it may be included.

  Another exemplary embodiment includes storing instructions executed by a computer to use a Wiener filter with an offset that adaptively filters a plurality of bins of a histogram for video encoding. It may be at least one or more computer-readable media. One exemplary embodiment may be a step of further storing a plurality of instructions for using a plurality of bin splitting methods. The medium may further store a plurality of instructions for dividing the histogram into a plurality of bins. The medium may further store a plurality of instructions for adaptively dividing the histogram into a plurality of bins. The medium may further store a plurality of instructions for transmitting a plurality of bin numbers from the encoder to the decoder. The medium may further store a plurality of instructions that specify a division method based on a rate distortion optimization criterion. A plurality of instructions for generating a plurality of adaptive filter coefficients by minimizing a sum of squares of a plurality of distortions between a value of an input pixel at the position and a pixel value after filtering at the position; May be further stored.

  Another exemplary embodiment may be an apparatus comprising a Wiener filter having an offset and a processor coupled to the filter to adaptively filter a plurality of histogram bins using the filter. The apparatus may use multiple bin splits. The apparatus may evenly divide the histogram into a plurality of bins. The apparatus may adaptively divide the histogram into a plurality of bins. The apparatus may include an encoder and a decoder coupled to the encoder, and the processor transmits the number of bins from the encoder to the decoder. The apparatus may further include a processor that identifies a partitioning method based on a rate distortion optimization criterion. The apparatus may include a processor that generates a plurality of adaptive filter coefficients by minimizing a sum of squares of a plurality of distortions between a value of an input pixel at the position and a subsequent pixel value at the position. . The apparatus may further include an operating system, a battery and firmware and a module for updating the firmware.

  The multiple graphics processing techniques described herein may be implemented in various multiple hardware architectures. For example, graphics functionality may be integrated within a chipset. Alternatively, a separate graphics processor may be used. As yet another embodiment, the plurality of graphics functions may be implemented by a general-purpose processor including a multi-core processor.

  As used herein, the term “one embodiment” or “an embodiment” includes a particular function, structure, or characteristic described in connection with that embodiment in at least one implementation included within the invention. Means that Thus, multiple appearances of the term “in one embodiment” or “in an embodiment” do not necessarily refer to the same embodiment. Further, the plurality of specific functions, the plurality of structures or the plurality of characteristics may be provided in other suitable forms other than the specific embodiment shown, and all such forms are It may be included within the scope of the claims of this application.

The present invention has been described with respect to a limited number of embodiments, and those skilled in the art will appreciate numerous modifications and variations therefrom. The appended claims are intended to cover all modifications and variations that fall within the true spirit and scope of the invention.

Claims (19)

Classifying a plurality of pixels input to and encoded by the video encoder into a plurality of different histogram bins using each of at least two different histogram partitioning methods;
The processor filtering the plurality of pixels classified into the plurality of different histogram bins for each of the plurality of different histogram partitioning methods using a Wiener filter having different offsets;
Wherein the processor, for each of the plurality of pixels which are filtered to derive a difference value between the pixel values after the filtering in the position of the value and its input pixel in position, the derived plurality of difference Adding all the values and generating an adaptive filter offset for a particular bin by dividing all the added values by the number of pixels in the histogram bin .   The method according to claim 1, wherein the plurality of different histogram division methods include a method of dividing a plurality of pixels into histogram bins obtained by dividing a histogram based on a plurality of histogram characteristics. At least two different plurality of methods including a method of dividing the plurality of pixels input to the video encoder and encoded by the video encoder into histogram bins obtained by dividing the histogram based on the plurality of histogram characteristics; Using each of the histogram partitioning methods to classify into a plurality of different histogram bins;
The processor filtering the plurality of pixels classified into the plurality of different histogram bins for each of the plurality of different histogram partitioning methods using a Wiener filter having different offsets;
Wherein the processor, for each of the plurality of pixels which are filtered to derive a difference value between the pixel values after the filtering in the position of the value and its input pixel in position, the derived plurality of difference Adding all the values and generating an adaptive filter offset for a particular bin by dividing all the added values by the number of pixels in the histogram bin . The plurality of different histograms based on the values of the plurality of pixels filtered in the filtering step, the values of the plurality of pixels input to the video encoder, and a rate distortion optimization criterion. Determining a histogram division method from the division method;
4. The processor according to claim 1, further comprising: transmitting a flag indicating a determination result in the determining step to a decoder that decodes the plurality of pixels encoded by the video encoder. The method described.   5. The method of claim 4, comprising transmitting the plurality of different histogram bin numbers from the video encoder to the decoder. The processor included in the computer
Classifying a plurality of pixels input to the video encoder and encoded by the video encoder into a plurality of different histogram bins using each of at least two different histogram division methods;
Filtering each of the plurality of pixels classified into the plurality of different histogram bins using a Wiener filter having a different offset for each of the plurality of different histogram partitioning methods ;
For each of the plurality of pixels which are filtered, by adding all the plurality of difference values to derive a difference value, derived between the pixel values after the filtering in the position of the value and its input pixel in position And a procedure for generating an adaptive filter offset for a specific bin by dividing the sum of all the values by the number of pixels in the histogram bin .   The program according to claim 6, wherein the plurality of different histogram division methods include a method of dividing a plurality of pixels into histogram bins obtained by dividing a histogram based on a plurality of histogram characteristics. The processor included in the computer
At least two different histogram division methods including a method of dividing a plurality of pixels input to a video encoder and encoded by the video encoder into histogram bins obtained by dividing a histogram based on a plurality of histogram characteristics To classify each into a plurality of different histogram bins,
Filtering each of the plurality of pixels classified into the plurality of different histogram bins using a Wiener filter having a different offset for each of the plurality of different histogram partitioning methods ;
For each of the plurality of pixels which are filtered, by adding all the plurality of difference values to derive a difference value, derived between the pixel values after the filtering in the position of the value and its input pixel in position And a procedure for generating an adaptive filter offset for a specific bin by dividing the sum of all the values by the number of pixels in the histogram bin . In the processor,
From the plurality of different histogram partitioning methods based on the values of the plurality of pixels filtered by the filtering procedure, the values of the plurality of pixels input to the video encoder, and a rate distortion optimization criterion. A procedure for determining one histogram division method;
9. A procedure for transmitting a flag indicating a determination result of the determining procedure to a decoder that decodes the plurality of pixels encoded by the video encoder. 10. Program. In the processor,
The program according to claim 9, wherein the program causes the video encoder to execute the procedure of transmitting the plurality of different histogram bin numbers.   The computer-readable recording medium which recorded the program as described in any one of Claims 6-10. A Wiener filter with different offsets;
The plurality of pixels input to the video encoder and encoded by the video encoder are classified into a plurality of different histogram bins using each of at least two different histogram division methods, and the plurality of different histogram division methods for each, the plurality of pixels which are classified into the plurality of different histogram bins, using said Wiener filter filtering, for each of the plurality of pixels which are filtered, the position value and its input pixel in position Deriving a difference value from the pixel value after filtering in step, adding all the derived plurality of difference values, and dividing the added value by the number of pixels in the histogram bin. Generate an adaptive filter offset of And a processor coupled to the serial Wiener filter device.   13. The apparatus of claim 12, wherein the plurality of different histogram partitioning methods includes a method of splitting a plurality of pixels into histogram bins obtained by dividing a histogram based on a plurality of histogram characteristics. A Wiener filter with different offsets;
At least two different histogram division methods including a method of dividing a plurality of pixels input to a video encoder and encoded by the video encoder into histogram bins obtained by dividing a histogram based on a plurality of histogram characteristics And classifying the plurality of pixels classified into the plurality of different histogram bins using the Wiener filter for each of the plurality of different histogram division methods. , for each of the plurality of pixels which are filtered to derive a difference value between the pixel values after the filtering in the position of the value and its input pixel in position, deriving above all of the plurality of difference values Add all values before adding By dividing the number of pixels in the histogram bins, and generates an adaptive filter offset of a particular bin, and a processor coupled to the Wiener filter, device.   The processor includes the plurality of different histograms based on the values of the plurality of pixels filtered using the Wiener filter, the values of the plurality of pixels input to the video encoder, and a rate distortion optimization criterion. 15. The method according to claim 12, wherein one histogram division method is determined from the division method, and a flag indicating a determination result is transmitted to a decoder that decodes the plurality of pixels encoded by the video encoder. The device described.   The apparatus of claim 15, comprising the video encoder and the decoder, wherein the processor transmits a plurality of bin numbers from the video encoder to the decoder.   The apparatus according to any one of claims 12 to 16, comprising an operating system.   18. A device according to any one of claims 12 to 17, comprising a battery.   The apparatus according to any one of claims 12 to 18, comprising firmware and a module for updating the firmware.

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