JP6409663B2 - Semiconductor device for motor control - Google Patents

Description

  The present invention relates to a motor control semiconductor device for controlling a motor.

  A semiconductor device for motor control includes a main control unit such as a CPU and a register for setting, for example, a pulse width and a pulse period when PWM control is performed (for example, see Patent Document 1). Such a semiconductor device for motor control, for example, when driving a three-phase motor, determines an energization pattern based on the rotational position of the motor and accesses so that the phase to be energized is energized by the energization pattern. Processing such as switching the previous register is performed.

JP-A-10-075597

  However, conventionally, the above-described processing is performed by software by executing a computer program in the main control unit. For this reason, the processing load of the main control unit is increased and the program code length is increased. In addition, since high processing capacity is required, the cost of the semiconductor device for motor control itself increases, and the cost of peripheral circuits increases, such as the need for a large capacity memory due to the increase in program code length. It was also a factor.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a motor control semiconductor device capable of suppressing an increase in processing load and program code length of a main control unit. .

  According to the first aspect of the present invention, a semiconductor device for motor control includes a main control unit that generates a drive command for driving the motor, and a control signal that is connected to the main control unit and drives the motor. A motor control unit that generates a motor, and the motor control unit itself determines a position to be energized based on a position detection unit that detects a rotation position of the motor and a rotation position of the motor detected by the position detection unit. And a virtual register unit in which a drive command is set so that the phase to be energized is energized, and a signal generation unit that generates a control signal based on the drive command set in the virtual register unit.

  As a result, in the semiconductor device for motor control, it is not necessary for the main control unit to perform processing such as specifying the energization pattern and selecting a control register for energizing the phase to be energized according to the energization pattern as in the prior art. . Therefore, an increase in processing load on the main control unit and an increase in program code length can be suppressed. In addition, since the necessary memory capacity is reduced, an increase in cost can be suppressed.

The figure which shows typically the electric constitution of the semiconductor device for motor control of 1st Embodiment. The figure which shows the control mode at the time of forward rotation typically The figure which shows the relationship of the position signal at the time of forward rotation, a conduction pattern, and a conduction phase The figure which shows the control mode at the time of inversion typically The figure which shows the relationship of the position signal at the time of inversion, a conduction pattern, and a conduction phase Diagram showing the relationship of registers to be controlled The figure which shows the flow of the motor control processing by CPU The figure which shows typically the electric constitution of the semiconductor device for motor control of 2nd Embodiment. The figure which shows typically the electrical constitution of the semiconductor device for motor control of 3rd Embodiment. The figure which shows typically the electric constitution of the semiconductor device for motor control of 4th Embodiment.

Hereinafter, a plurality of embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the site | part substantially common in each embodiment, and the detailed description is abbreviate | omitted.
(First embodiment)
The first embodiment will be described below with reference to FIGS.

  As shown in FIG. 1, a motor control semiconductor device 1 (hereinafter simply referred to as a semiconductor device 1) is connected to an inverter circuit 2. In the inverter circuit 2 of the present embodiment, although not shown, for example, a series circuit in which switching elements such as IGBTs are connected in series on the high side and the low side is provided for three phases of U phase, V phase, and W phase. It becomes the composition. Hereinafter, a signal given from the semiconductor device 1 to the inverter circuit 2 is referred to as a control signal (indicated as UH, UL, VH, VL, WH, WL in FIG. 1), and a signal given from the inverter circuit 2 to the motor 3 is a drive signal. (Referred to as EU, EV, and EW in FIG. 1).

  The semiconductor device 1 includes a CPU 4, a motor control circuit 5, a PWM signal generation circuit 6, a position detection circuit 7, and the like. The CPU 4 (corresponding to a main control unit) is a main control circuit of the semiconductor device 1 and controls the entire semiconductor device 1 by executing a computer program stored in a ROM (not shown) or the like. Further, the CPU 4 generates a drive command for driving the motor 3.

  A motor control circuit 5 (corresponding to a motor control unit) generates and outputs a control signal for controlling the motor 3. In the present embodiment, the motor control circuit 5 controls the driving of the motor 3 by rectangular wave control. For this reason, the motor control circuit 5 generates and outputs a control signal (a so-called PWM (Pulse Width Modulation) signal) by the PWM signal generation circuit 6 (corresponding to a signal generation unit). At this time, the pulse width and pulse period of the control signal generated by the PWM signal generation circuit 6 are defined by a drive command (register value) set in the virtual register circuit 8 (corresponding to the virtual register unit). That is, the PWM signal generation circuit 6 reads the drive command from the virtual register circuit 8 to generate a control signal in hardware.

  The virtual register circuit 8 is connected to the CPU 4 by an internal bus 9. The virtual register circuit 8 is divided into a high-side virtual register circuit 8H and a low-side virtual register circuit 8L corresponding to the high-side and low-side switching elements constituting the inverter circuit 2 described above.

  Among these, the high-side virtual register circuit 8H includes a control register 10H corresponding to the U-phase high side, a control register 11H corresponding to the V-phase high side, and a control corresponding to the W-phase high side. A high-side register group 14H (corresponding to a high-side register group) composed of three control registers of the register 12H, and a register control circuit 13H (corresponding to register control means) for controlling the high-side register group 14H And).

  In each of the control registers 10H, 11H, and 12H, a drive command for setting the pulse width and pulse period of the corresponding control signal is set from the CPU 4. At this time, the high-side virtual register circuit 8H has a common data bus and is assigned to a single address (ADD_H) by one address comparator 15H. For this reason, the high-side virtual register circuit 8H has a plurality of control registers 10H, 11H, and 12H, but is accessed from the CPU 4 as a single register.

At this time, since the data bus is shared, data (shown as a drive command in FIG. 1) reaches all the control registers 10H, 11H, and 12H, but the control register in which the data is actually set is It is determined by the register control circuit 13H.
As will be described in detail later, the register control circuit 13H controls the access destination of the CPU 4 based on the detection result of the position detection circuit 7 (corresponding to the position detection unit) when accessed from the CPU 4 as a single register. Set to any of the registers 10H, 11H, and 12H. In the present embodiment, the register control circuit 13H also has a function of turning off a control register that is not set as an access destination, as will be described in detail later.

  On the other hand, the low-side virtual register circuit 8L includes three controls: a control register 10L corresponding to the U-phase low-side, a control register 11L corresponding to the V-phase low-side, and a control register 12L corresponding to the W-phase low-side. A low-side register group 14L composed of registers (corresponding to a low-side register group) and a register control circuit 13L (corresponding to register control means) for controlling the low-side register group 14L are provided.

In each of the control registers 10L, 11L, and 12L, a drive command for setting the pulse width and pulse period of the corresponding control signal is set by the CPU 4. At this time, the low-side virtual register circuit 8L has a common data bus and is assigned to a single address (ADD_L) by one address comparator 15L. Therefore, the low-side virtual register circuit 8L has a plurality of control registers 10L, 11L, and 12L, but is accessed from the CPU 4 as a single register.
At this time, since the data bus is shared, data (shown as a drive command in FIG. 1) reaches all the control registers 10L, 11L, and 12L, but the control register in which the data is actually set is It is determined by the register control circuit 13L.

  The register control circuit 13L will be described in detail later, but when accessed from the CPU 4 as a single register, the access destination of the CPU 4 is set as one of the control registers 10L, 11L, and 12L based on the detection result of the position detection circuit 7. Set it. In the present embodiment, the register control circuit 13L has a function of turning off a control register that is not set as an access destination, as will be described in detail later.

  The position detection circuit 7 detects the rotational position of the motor 3 based on the position signal output from the position sensor 16 provided in the motor 3. Although the details will be described later, the position detection circuit 7 identifies the energization pattern (see FIGS. 3 and 5) based on the rotational position of the motor 3, and the identification result (shown as position information in FIG. 1). Output.

  The position sensor 16 (16U, 16V, 16W) detects an induced voltage of each phase of the motor 3. Further, the position sensor 16 outputs a comparison result obtained by comparing the detected induced voltage of each phase with a reference value as a position signal of H level or L level. Note that the position sensor 16 may be constituted by, for example, a Hall IC according to the use environment or the like.

Next, the operation of the above configuration will be described.
When the motor 3 is subjected to rectangular wave control, the switching element is switched on / off according to the rotation angle of the rotor to rotate the rotor. At this time, the ON / OFF state (operation mode) of the switching element is switched every time the rotor rotates 60 degrees in electrical angle. That is, when the motor 3 rotates once, there are six energization patterns. Therefore, when the motor 3 is rotated forward, the drive signal (EU, EV, EW), the position signal (HU, HV, HW) and the control signal (UH, UL, VH, VL, WH, WL) during one rotation. ) Is a correspondence as shown in FIG.

  The correspondence relationship as shown in FIG. 2 is a general relationship when the motor 3 is controlled by a rectangular wave, and thus detailed description thereof is omitted. However, the switching element on the high side is turned on / off in a pulsed manner. When the corresponding switching element on the low side is turned on, the phase to be energized is energized.

For example, when the motor 3 is rotated forward, the position signal and the energization pattern have the following correspondence as shown in FIG. Note that the energization pattern numbers are for convenience.
・ When HU = H, HV = L, HW = H, energization pattern “1”
・ When HU = H, HV = L, HW = L, energization pattern “2”
・ When HU = H, HV = H, HW = L, the energization pattern “3”
・ When HU = L, HV = H, HW = L, energization pattern “4”
・ When HU = L, HV = H, HW = H, energization pattern “5”
・ When HU = L, HV = L, HW = H, energization pattern “6”
At this time, the relationship between the energization pattern and the energized phase is as follows.

• Energization pattern “1”: Energized phase is U phase → V phase • Energized pattern “2”: Energized phase is U phase → W phase • Energized pattern “3”: Energized phase is V phase → W phase • Energized pattern “4” ”: Energized phase is V phase → U phase • Energized pattern“ 5 ”: Energized phase is W phase → U phase • Energized pattern“ 6 ”: Energized phase is W phase → V phase On the other hand, the motor 3 is reversed (forward rotation) 4), the drive signal, the position signal, and the control signal are operated as shown in FIG. For this reason, there are six energization patterns at the time of inversion as well as at the time of forward rotation. At this time, as shown in FIG. 5, the correspondence between the energization pattern and the energization phase is the same as that during forward rotation, but the correspondence between the position signal and the energization pattern is as follows.

・ When HU = H, HV = L, HW = H, energization pattern “4”
・ When HU = H, HV = L, HW = L, energization pattern “5”
・ When HU = H, HV = H, HW = L, energization pattern “6”
・ When HU = L, HV = H, HW = L, energization pattern “1”
・ When HU = L, HV = H, HW = H, energization pattern “2”
・ When HU = L, HV = L, HW = H, energization pattern “3”

  Now, a conventional control method will be described as a comparative example. In the conventional control method, the correspondence relationship between the energization pattern and the register is stored, the energization pattern is specified based on the detected rotational position of the motor 3, and the register for energizing the phase to be energized in the energization pattern. And setting the drive command to the selected register using software. For this reason, it is necessary to describe six kinds of program codes in order to correspond to the respective energization patterns, and on / off of each switching element of the U phase, the V phase and the W phase is controlled in each energization pattern. It was necessary to set a drive command for this purpose. As a result, an increase in processing load, an increase in program code length, and an associated increase in cost have been caused.

Therefore, in the present embodiment, the increase in processing load and program code length and the accompanying increase in cost are suppressed as follows.
In the case of the semiconductor device 1, the register control circuit 13 is preset with a correspondence relationship between the energization pattern and the phase to be energized as described above. The register control circuit 13 sets the access destination of the CPU 4 to the control register corresponding to the phase to be energized based on the energization pattern specified by the position detection circuit 7. Specifically, the correspondence shown in FIG. 6 is set in the register control circuit 13. In the present embodiment, in the energization pattern “1”, the control register that is the access destination of the CPU 4 is set so that the U-side control register 10H is on the high side and the V-phase control register 11L is on the low side.

  At this time, when the position detection circuit 7 specifies that the energization pattern is “1”, the high-side register control circuit 13H switches the access destination of the CPU 4 to the control register 10H. As a result, when the CPU 4 performs an access to write data (drive command) to a single address (here, ADD_H), the data is stored in the control register corresponding to the phase to be energized, that is, the control register here. 10H will be written. The register control circuit 13H turns off the control registers 11H and 12H that are not access destinations (a state in which the switching element is turned off).

  Therefore, when the CPU 4 controls the motor 3, as shown in FIG. 7, when the CPU 4 detects a motor state for detecting the rotation speed of the motor 3 (S1), the corresponding data (drive command) Is output to the high-side virtual register circuit 8H (S2). At this time, as described above, the control register that is the access destination, that is, the data write destination, is automatically selected on the motor control circuit 5 side. Therefore, when the CPU 4 accesses a single address (here, ADD_H), the data (drive command) is set in the control register 10H, for example. That is, in the semiconductor device 1, even if the CPU 4 does not perform processing such as specifying an energization pattern and selecting a register for energizing a phase to be energized in the energization pattern, a drive command is issued to a desired control register. Can be set.

  On the other hand, in the low-side register control circuit 13L, when the position detection circuit 7 specifies that the energization pattern is “1” by the register control circuit 13L, the access destination of the CPU 4 is set in the control register 11L. The For this reason, when the CPU 4 performs access for setting data (drive command) in a single address (here, ADD_L), the data is set in the control register 11L corresponding to the phase to be energized. Will be. The register control circuit 13L turns off the control registers 10L and 12L that are not access destinations.

  Therefore, if the CPU 4 outputs data (drive command) corresponding to the state of the motor 3 to the low-side virtual register circuit 8L (S3), that is, only accesses to a single address (here, ADD_L). A drive command can be set for a desired control register.

  The same applies to the energization patterns “2” to “6”, and the CPU 4 simply accesses the high-side virtual register circuit 8H or the low-side virtual register circuit 8L with a single address to obtain a desired pattern. Data (drive command) can be set in the control register. For example, when the energization pattern is “2”, the data (drive command) from the CPU 4 is set in the U-phase control register 10H on the high side and in the W-phase control register 12L on the low side. The

  When the energization pattern is “3”, the control registers to be accessed by the CPU 4 are the V-phase control register 11H on the high side and the W-phase control register 12L on the low side. When the energization pattern is “4”, the control registers to be accessed by the CPU 4 are the V-phase control register 11H on the high side and the U-phase control register 10L on the low side. When the energization pattern is “5”, the control registers to be accessed by the CPU 4 are the W-phase control register 12H on the high side and the U-phase control register 10L on the low side. When the energization pattern is “6”, the control registers to be accessed by the CPU 4 are the W-phase control register 12H on the high side and the V-phase control register 11L on the low side.

  As described above, in the semiconductor device 1, when the CPU 4 accesses the virtual register circuit 8, the access destination is automatically switched on the motor control circuit 5 side. Thereby, the process in CPU4 can be reduced. Note that the CPU 4 determines whether the motor 3 is rotated forward or reversely, and the specified energization pattern is determined by setting the virtual register circuit 8 as to whether the motor 3 is rotated forward or reversed. The control register corresponding to is selected.

According to the embodiment described above, the following effects can be obtained.
The semiconductor device 1 for motor control includes a CPU 4 (main control unit) that generates a drive command for driving the motor 3, and a motor control circuit 5 that is connected to the CPU 4 and generates a control signal for driving the motor 3. (Motor control unit). The motor control circuit 5 itself detects the position to be energized based on the position detection circuit 7 (position detection unit) for detecting the rotation position of the motor 3 and the rotation position of the motor 3 detected by the position detection circuit 7. A virtual register circuit 8 (virtual register unit) in which the drive command is set so that the phase to be energized is energized, and a drive signal is generated based on the drive command set in the virtual register circuit 8 And a PWM signal generation circuit 6 (signal generation unit).

  Thereby, in the semiconductor device 1, it is not necessary for the CPU 4 to perform processing such as specifying an energization pattern and selecting a register for energizing a phase to be energized according to the energization pattern as in the prior art. Therefore, an increase in the processing load on the CPU 4 and the program code length can be suppressed. Further, since the memory capacity can be reduced, an increase in cost can be suppressed.

In addition, a plurality of virtual register circuits 8 are provided corresponding to the number of signals generated as control signals (for example, six in this embodiment), and a plurality of addresses when accessing from the CPU 4 are shared. The control registers 10 to 12 corresponding to the phase to be energized are determined based on the control registers 10 to 12 and the rotational position of the motor 3 detected by the position detection circuit 7, and the determined control registers 10 to 12 are determined. And a register control circuit 13 (register control means) for setting a drive command.
Thereby, even when the plurality of control registers 10 to 12 are provided, the access destination of the CPU 4 is automatically switched on the motor control circuit 5 side. Thereby, the processing load of CPU4 can be reduced.

At this time, since the CPU 4 only needs to access a single address, the processing load on the CPU 4 can be further reduced.
In the present embodiment, the motor 3 driven by the inverter circuit 2 is targeted. The virtual register circuit 8 generates a high side register group 14H for generating a control signal on the high side of the inverter circuit 2 among the plurality of control registers 10 to 12, and a control signal on the low side of the inverter circuit 2 It is divided into a low-side register group 14L for generation. Furthermore, the control registers 10H, 11H and 12H belonging to the high-side register group 14H and the control registers 10L, 11L and 12L belonging to the low-side register group 14L have a common address.

  For this reason, even when it is desired to set different drive commands for the high side and the low side, the address is shared between the high side register group and the low side register group. If the address is accessed, a drive command can be set in each appropriate control register, and the motor 3 can be controlled with a minimum processing load of the CPU 4.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIG.
In the case of the present embodiment, as shown in FIG. 8, the semiconductor device 20 for motor control includes a position signal generation circuit 21 and a timer 22 in addition to the configuration of the semiconductor device 1 of the first embodiment. In the present embodiment, the motor 3 is controlled by position sensorless control.

  The position signal generation circuit 21 (corresponding to the position signal generation unit) uses the timer 22 to generate a position signal having a predetermined pattern and outputs the position signal to the position detection circuit 7. The position detection circuit 7 detects the rotational position of the motor 3 based on the position signal generated by the position signal generation circuit 21 when starting the motor 3.

  When performing position sensorless control, since the rotational position cannot be detected when the motor 3 is started, generally, forced commutation for forcibly rotating the motor 3 is performed. In this case, conventionally, the CPU 4 selects a control register for forced commutation and sets a drive command. In other words, the semiconductor device 20 can reduce the processing load during normal operation by providing the same configuration as in the first embodiment, but when performing position sensorless control, the processing load on the CPU 4 may increase during startup. was there.

  Therefore, in this embodiment, the position signal generation circuit 21 generates a position signal having a predetermined pattern. In this case, the position signal generated by the position signal generation circuit 21 is generated as a signal in such a manner that the energization pattern described above is switched at a predetermined cycle. Then, the position detection circuit 7 specifies a phase to be energized when the motor 3 is started based on the position signal generated by the position signal generation circuit 21, that is, based on a signal for switching the energization pattern at a predetermined cycle. .

  Thereby, it is not necessary to perform processing such as specifying a phase to be energized in the CPU 4, and the processing load on the CPU 4 can be reduced. Even if position information cannot be obtained at the time of starting the position sensorless control, the motor 3 can be started without imposing a burden on the CPU 4.

(Third embodiment)
Hereinafter, the third embodiment will be described with reference to FIG.
In the present embodiment, as shown in FIG. 9, the motor control semiconductor device 30 includes an abnormality detection circuit 31 (corresponding to an abnormality detection unit) in addition to the configuration of the semiconductor device 1 of the first embodiment. ing. The abnormality detection circuit 31 is detected when an abnormality is detected by the CPU 4, a signal indicating that an abnormality has occurred is input from an external device (not shown) connected to the external terminal 32, or an abnormality detection circuit. When any abnormality occurs in the semiconductor device 30, the motor 3, the peripheral device, or the like, such as when an abnormality is detected by itself 31, the fact is output to the virtual register circuit 8.

  When the abnormality detection circuit 31 detects an abnormality, the virtual register circuit 8 is set with a stop command for stopping energization of the motor 3 regardless of the drive command from the CPU 4. More specifically, the abnormality detected by the abnormality detection circuit 31 is input to the register control circuit 13, and all the control registers 10 to 12 are turned off by the register control circuit 13. A state in which all the control registers 10 to 12 are turned off corresponds to a state in which a stop command is set.

Thereby, all the switching elements of the inverter circuit 2 are turned off, and the motor 3 is not energized. That is, the motor 3 is forcibly shut off. As a result, the motor 3 can be quickly stopped regardless of the operating state of the CPU 4 at the time of forced shut-off when all outputs must be turned off urgently.
Moreover, since it can be forcibly cut off regardless of the operation state of the CPU 4, the motor 3 can be stopped even in a state where the CPU 4 has runaway.

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described with reference to FIG.
In the case of this embodiment, as shown in FIG. 10, the motor control semiconductor device 40 is similar to the semiconductor device 1 of the first embodiment, but the virtual register circuit 8 having a plurality of control registers 10 to 12 is It is controlled by one register control circuit 13.

  When controlling the motor 3 by the rectangular wave control, the high side repeats on / off in a pulsed manner based on the drive command from the CPU 4 as shown in FIGS. Or it is either off. Therefore, if the correspondence relationship between the energization pattern and the ON / OFF of the low-side control registers 10L, 11L, and 12L (see FIG. 6) is set in the register control circuit 13, in the rectangular wave control, the low-side side It is considered that the CPU 4 does not need to access the control registers 10L, 11L, and 12L.

Therefore, in the semiconductor device 30, the virtual register circuit 8 having the plurality of control registers 10 to 12 is assigned to a single address, and the data bus is shared by the high-side control registers 10H, 11H, and 12H. Thus, when the energization pattern is specified, the register control circuit 13 switches the access destination from the CPU 4 to any one of the control registers 10H, 11H, and 12H on the high side according to the energization pattern, and controls on the low side. On / off is set for the registers 10L, 11L, and 12L based on the correspondence shown in FIG.
Thereby, the CPU 4 can omit the above-described step S3 of FIG. 7 when performing the rectangular wave control. That is, the processing load on the CPU 4 can be further reduced.

(Other embodiments)
The present invention is not limited to those exemplified in the above-described embodiments, and can be arbitrarily modified or expanded without departing from the gist thereof.
You may combine each embodiment. For example, the abnormality detection circuit 31 of the third embodiment may be provided in the configuration of the second embodiment, and the configuration of the third embodiment or the fourth embodiment is applied to the position sensorless control as in the second embodiment. May be.
The numerical values, the number of control registers, and the like shown in each embodiment are examples, and are not limited thereto.

  In the drawings, 1, 20, 30, and 40 are semiconductor devices (semiconductor devices for motor control), 2 is an inverter circuit, 3 is a motor, 4 is a CPU (main control unit), and 5 is a motor control circuit (motor control unit). , 6 is a PWM signal generation circuit (signal generation unit), 7 is a position detection circuit (position detection unit), 8 is a virtual register circuit (virtual register unit), 8H is a high-side virtual register circuit (virtual register unit), 8L Is a low-side virtual register circuit (virtual register unit), 10-12, 10H, 10L, 11H, 11L, 12H, 12L are control registers, 13, 13H, 13L are register control circuits (register control units), and 14 is a register 14H is a high-side register group (high-side register group), 14L is a low-side register group (low-side register group), and 21 is a position signal. Forming circuit (position signal generating unit), 31 denotes an abnormality detection circuit (abnormality detection unit).

Claims (4)

A main control unit (4) for generating a drive command for driving the motor;
A motor control unit (5) connected to the main control unit (4) and generating a control signal for driving the motor;
The motor control unit (5)
A position detector (7) for detecting the rotational position of the motor;
A virtual register unit that determines the phase to be energized by itself based on the rotational position of the motor detected by the position detection unit (7) and sets the drive command so that the phase to be energized is energized (8) and
A signal generation unit (6) that generates the control signal based on the drive command set in the virtual register unit (8) ,
The virtual register unit (8)
A plurality of control registers (10, 11, 12) provided in correspondence with the number of signals generated as the control signal and having a common address when accessed from the main control unit (4);
The control register (10, 11, 12) corresponding to the phase to be energized is determined based on the rotational position of the motor detected by the position detector (7), and the determined control register (10, 11) is determined. , 12), and a register control means (13) for controlling the drive command to be set, and a motor control semiconductor device. The motor is driven by an inverter circuit (2),
The virtual register unit (8) includes a high-side register group (14H) for generating the control signal on the high-side side of the inverter circuit (2) among the plurality of control registers (10, 11, 12). ) And a low-side register group (14L) for generating the control signal on the low-side side of the inverter circuit, and the control registers (10, 11, 12) belonging to each register group (14H, 14L) 2. The motor control semiconductor device according to claim 1, wherein the address of the motor control is shared. The motor (3) is controlled by position sensorless control,
A position signal generation unit (21) for generating a position signal of a predetermined pattern;
  The position detector (7) detects the rotational position of the motor (3) based on the position signal generated by the position signal generator (21) when starting the motor (3). 3. The motor control semiconductor device according to claim 1, wherein the motor control semiconductor device is a motor control semiconductor device. An abnormality detection unit (31) for detecting an abnormality is provided,
The virtual register unit (8) stops energization of the motor (3) regardless of the drive command from the main control unit (4) when an abnormality is detected by the abnormality detection unit (31). 4. The motor control semiconductor device according to claim 1, wherein a stop command is set.

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