JP6404658B2 - Multicycle number autonomous determination device and multicycle number autonomous determination method - Google Patents

Description

  The present invention relates to a multicycle number autonomous determination device and a multicycle number autonomous determination method.

  In digital logic circuits, multi-cycle circuits are often used. As proposals regarding such a multi-cycle circuit, JP 2012-248038 A, JP 2002-043934 A, JP 2004-228417 A, and the like are known.

  Japanese Patent Application Laid-Open No. 2012-248038 discloses a multi-cycle path detection device including a logic verification unit, a start / end point data comparison unit, a data width minimum value extraction unit, and a multi-cycle number determination unit.

  That is, in this multi-cycle path detection device, the logic verification unit performs logic verification based on either RTL (Register transfer level) data or the netlist and the user verification pattern used in the RTL simulation. The start point / end point data comparison unit specifies the path of the semiconductor integrated circuit as a specific path based on the result of the logic verification, and compares the data value of the start point of the specific path with the data value of the end point. The data width minimum value extraction unit is based on the data comparison result by the start point / end point data comparison unit for data that is one of 0 and 1 that propagates through a specific path and the data width is the number of cycles of the clock signal. The minimum data width value indicating the minimum number of cycles is extracted. The multicycle number determination unit determines the multicycle number in the specific path according to the minimum data width. As a result, a multi-cycle path dependent on the user specification can be automatically detected in a short time.

  Japanese Patent Laid-Open No. 2002-043934 discloses a clock generation circuit having a relatively small circuit scale and a wide lock range.

  This clock generation circuit includes a variable delay circuit, and measures the optimum number of cycles of the delay amount from the external clock to the data output. A DLL (Dynamic Link Library) circuit or the like is configured so that the number of cycles can be locked.

  Further, in Japanese Patent Application Laid-Open No. 2004-228417, a phase locked loop circuit (PLL) is provided, and the frequency of the clock signal is determined by controlling the frequency dividing ratio of the frequency dividing circuit by the operation control signal in the PLL. Techniques to do this are disclosed.

  At this time, in the design of digital logic circuits, the operation specifications of the circuit to be realized are often described by sequential processing such as C language mainly in functions such as signal processing and algorithm processing, and a behavioral synthesis tool for that purpose has been developed. ing. This behavioral synthesis is a development technique for automatically generating a hardware description that can be logically synthesized called RTL (Register transfer level) code based on sequential processing code such as C language. The original specification of a digital logic circuit is C language or the like. This is a development method that is generally used when the design object described in (1) is made into hardware.

JP 2012-248038 A JP 2002-043934 A JP 2004-228417 A

  However, the configuration according to each patent document described above has the following problems. That is, in each functional circuit constituting the digital logic circuit, a delay accompanying signal processing occurs. In order for the entire digital logic circuit to perform appropriate signal processing for such delay (in order to operate normally), it is necessary to set the number of multicycles appropriately. However, the amount of delay varies depending on various operating conditions. This means that the appropriate number of multicycles varies depending on the operating conditions. Accordingly, in designing a digital logic circuit, it is necessary to design the digital logic circuit so as to operate at an appropriate number of multi-cycles assuming an operating condition, and there has been a problem that a great amount of labor is required for such design work.

  Further, when using a behavioral synthesis tool, it is difficult to estimate the processing depth because the C language description is a sequential processing description. In addition, it is very difficult to estimate the delay amount of the circuit only by looking at the C language description by automatically generating the RTL code. Furthermore, in signal processing and algorithm processing, arithmetic processing is frequently used, so the circuit delay amount itself tends to increase. Due to these circumstances, there are an increasing number of cases where multi-cycle path design is required in the design of digital logic circuits. Therefore, a development method for efficiently designing these digital logic circuits and operating them with an appropriate number of multicycles has been demanded.

  Such a problem will be described by exemplifying a single cycle circuit and a multicycle circuit which are one of digital logic circuits.

  First, a single cycle circuit will be described. 6A and 6B are diagrams showing the configuration of a single cycle circuit, where FIG. 6A is a block diagram and FIG. 6B is a timing chart.

  This single cycle circuit includes a terminal unit 100, a combinational circuit unit 110, and a latch unit 120.

  The terminal unit 100 includes input terminals 101a and 101b, output terminals 103a and 103b, and a clock terminal 102.

  The combinational circuit unit 110 includes a pre-stage combination circuit 111 that performs a predetermined process A and a post-stage combination circuit 112 that performs a predetermined process B. Note that the predetermined process A is a process originally performed by the preceding combination circuit 11, and the content of the process differs depending on the circuit function. The same applies to the predetermined process B.

  The latch unit 120 is provided at the front stage latch unit 121 provided before the front stage combination circuit 111, the middle stage latch unit 122 provided between the front stage combination circuit 111 and the rear stage combination circuit 112, and the rear stage of the rear stage combination circuit 112. The rear stage latch part 123 is provided.

  The pre-stage latch unit 121 includes a Philip flop 121a to which a signal from the input terminal 101a is input and a Philip flop 121b to which a signal from the input terminal 101b is input. Similarly, the middle stage latch unit 122 includes a Philip flop 122a to which a signal obtained as a result of the process A being performed by the preceding stage combination circuit 111 for the signal from the input terminal 101a and a process A by the preceding stage combination circuit 111 for the signal from the input terminal 101b. Philip flop 122b for inputting the result signal of the above. The rear stage latch unit 123 performs processing A by the rear stage combinational circuit 112 for the signal from the Philip flop 123a and the signal from the input terminal 101b to which the result signal obtained by performing the processing A by the rear stage combinational circuit 112 for the signal from the input terminal 101a. Philip flop 123b for inputting the result signal.

  With such a configuration, input signals from the input terminals 101a and 101b (denoted in time series as Din_0, Din_1, Din_2, Din_3,...) Are generated at the leading edge of the clock signal from the clock terminal 102. 121 is latched.

  The combinational circuit 111 performs a predetermined process A on the signal from the previous latch unit 121.

  A result signal (Da_0, Da_1, Da_2, Da_3,... In time series) subjected to the processing A is latched by the intermediate latch unit 122 at the rising edge of the next clock signal.

  The combinational circuit 112 performs a predetermined process B on the result signal from the middle latch unit 122.

  The result signal (denoted in time series as Db_0, Db_1, Db_2, Db_3,...) Subjected to the process B in the combinational circuit 112 is latched by the subsequent latch unit 123 at the rising edge of the next clock signal.

  Then, the signal from the latter-stage latch unit 123 is output from the output terminals 103a and 103b as output signals (described as Dout_0, Dout_1, Dout_2, Dout_3,... In time series).

  At this time, in order for the single cycle circuit to operate normally, the delay amount Dt generated in the combinational circuit 111 and the combinational circuit 112 is required to be equal to or less than one cycle of the clock signal. Strictly speaking, it is necessary to consider the clock skew and jitter of the middle stage latch unit 122 and the like and the clock signal, but they are omitted for the sake of simplicity.

  Next, the multi-cycle circuit will be described. 7A and 7B are diagrams showing the configuration of the multi-cycle circuit, where FIG. 7A is a block diagram and FIG. 7B is a timing chart. The configuration of the multicycle circuit is almost the same as that of the single cycle circuit, but an N-ary counter 141 is added. Each lip flop in the latch unit 120 includes an enable terminal to which a signal (enable signal) from the N-ary counter 141 is input.

  Here, the N-ary counter 141 outputs, for example, a counter signal that is asserted once every four clocks as an enable signal. That is, consider the case of N = 4.

  Input signals from the input terminals 101a and 101b (described in time series as Din_0, Din_1, Din_2, Din_3,...) Are latched by the pre-stage latch unit 121 at the rising edge of the enable signal from the clock terminal 102.

  The combinational circuit 111 performs a predetermined process A on the signal from the previous latch unit 121.

  The result signal (processed as Da_0, Da_1, Da_2, Da_3,...) In time series is latched by the intermediate latch unit 122 at the rising edge of the next clock signal. Is done.

  The combinational circuit 112 performs a predetermined process B on the signal from the middle latch unit 221.

  The signal (processed in the time series as Db_0, Db_1, Db_2, Db_3,...) Output after processing B is performed by the combinational circuit 112 is latched by the subsequent latch unit 123 at the rising edge of the next enable signal. The

  Then, the signal from the latter-stage latch unit 123 is output from the output terminals 103a and 103b as output signals (described as Dout_0, Dout_1, Dout_2, Dout_3,... In time series).

  At this time, in order for the multi-cycle circuit to operate normally, the delay amount by the combinational circuit 111 and the combinational circuit 112 must be less than or equal to the set period of the N-ary counter (one period or less of the enable signal). That is, when one cycle of the enable signal is four cycles (N = 4) of the clock signal, the delay amount Dt must be less than or equal to four cycles (4T) of the clock signal. In this case as well, strictly speaking, it is necessary to consider the clock skew and jitter of the latch unit 120 and the clock signal, but they are omitted for the sake of simplicity.

  In the development of digital logic circuits using behavioral synthesis tools, the frequency of application of multi-cycle circuits tends to increase. This is because, when predicting a circuit delay when implemented on a device, a C language code or the like described more abstractly than an RTL code whose description abstraction level is relatively close to that of an actual circuit. This is because it becomes difficult to estimate the circuit delay.

  When the functions described in C language or the like become complicated to some extent, the absolute value of the circuit delay when implemented on a device also increases, often resulting in a circuit in which the delay amount does not fit in one clock cycle. It will be. Such a circuit is incorporated into a digital logic circuit as a multi-cycle circuit using the circuit described with reference to FIG.

  In realizing a digital logic circuit having an appropriate multi-cycle number with respect to the circuit delay amount, the appropriate multi-cycle number also changes when the circuit delay amount changes due to various operating conditions.

  Examples of such a change factor include (1) delay performance of the mounted device, (2) operation mode, (3) power saving mode, and (4) design change associated with required specification change.

(1) Delay performance of mounted device The delay amount of the digital logic circuit may vary depending on the delay performance of the device itself that operates the designed digital logic circuit. Therefore, the appropriate number of multicycles varies depending on the applied digital logic circuit. In the case of a digital logic circuit using an external memory device, the access time of the external memory also affects the delay amount.

(2) Operation mode When the digital logic circuit to be designed has a plurality of operation modes, the delay amount of the circuit differs for each operation mode, and an appropriate multicycle number may change.

(3) Power-saving mode When the power supply voltage of the digital logic circuit is lowered within the rated range and operated for the purpose of power-saving, the number of multi-cycles may change as the circuit delay amount changes. .

(4) Design changes due to changes in required specifications When it is necessary to add or change functions to a digital logic circuit that has been developed once, the appropriate number of multi-cycles can be obtained by changing the delay amount of the circuit after the design change. May change.

  Therefore, in designing a digital logic circuit, it has been a very labor-intensive work to design the digital logic circuit to operate at an appropriate number of multi-cycles assuming the above-described operating conditions.

  Accordingly, a main object of the present invention is to provide a multicycle number autonomous determination device and a multicycle number autonomous determination method capable of autonomously determining the multicycle number so that the multicycle number can be operated with an appropriate multicycle number even under various operating conditions. That is.

  In order to solve the above-described problems, each digital logic circuit includes a front-stage latch unit that latches a signal input to at least one combinational circuit having a predetermined function, and a rear-stage latch unit that latches an output signal from the combinational circuit. An invention relating to a multi-cycle number autonomous determination device that autonomously determines the number of multi-cycles adapted to a delay amount generated in a process generates a test pattern signal corresponding to at least a combination pattern of input elements and outputs the test pattern signal to a combinational circuit Multi-cycle number that outputs a signal generation unit and a multi-cycle number setting command indicating the number of cycles, and when the operating conditions change at that time, the preset multi-cycle number initial value is the number of cycles in the low-speed test. Outputs a setting command and causes the test pattern signal generator to generate a test pattern signal for low-speed testing. When the test is completed, a multicycle number setting command is output, which is a multicycle number trie value that uses a value smaller than the initial value of the multicycle number as the cycle number for high-speed testing, and a test pattern for high-speed testing is output to the test pattern signal generator. A sequencer for generating a signal and a result of processing performed by the combinational circuit on the test pattern signal are stored. At that time, a result of processing for the test pattern signal for the low speed test and a result of processing for the test pattern signal for the high speed test are stored. And a sequencer that determines whether the comparison result from the comparison unit does not match the processing result for the test pattern signal for the low speed test and the processing result for the test pattern signal for the high speed test. Multicycle number setting command is issued with the value obtained by subtracting 1 from the cycle number as the new multicycle number trie value. The value obtained by adding 1 to the number of multicycles when the processing result for the test pattern signal for the low speed test and the processing result for the test pattern signal for the high speed test do not match is determined as the optimum multicycle. Multi-cycle number autonomous determination device characterized.

  In addition, it is adapted to the delay amount generated in each process in the digital logic circuit comprising a pre-stage latch unit that latches a signal input to a combinational circuit having a predetermined function and a post-stage latch unit that latches an output signal from the combinational circuit. The invention according to the multicycle number autonomous determination method for autonomously determining the number of multicycles shows a test pattern signal generation procedure for generating a test pattern signal corresponding to each combination pattern of input elements and outputting it to a combinational circuit, and the cycle number A multi-cycle number setting command is output, and if the operating conditions change at that time, a multi-cycle number setting command is output that uses the preset initial value of the multi-cycle number as the number of cycles during the low-speed test. When the low-speed test is completed, a value smaller than the initial value of the multi-cycle number is set for the high-speed test. The multi-cycle number setting command that outputs the multi-cycle number as the number of cycles is output, and the sequence procedure for generating the test pattern signal for the high-speed test and the processing result performed by the combinational circuit on the test pattern signal are shown. And a comparison procedure for determining the coincidence between the processing result for the test pattern signal for the low speed test and the processing result for the test pattern signal for the high speed test, and the sequence procedure is for the low speed test. A multi-cycle number setting command with a new multi-cycle number trie value set to a value obtained by subtracting 1 from the multi-cycle number until the processing result for the test pattern signal in FIG. Output the processing result for the test pattern signal for the low speed test and the processing result for the test pattern signal for the high speed test. Multi Cycles autonomous determination method, characterized in that the multi-number of cycles comprising the steps determining a value obtained by adding 1 as the best multi-cycle when it is matched.

  According to the present invention, an appropriate number of multicycles can be determined autonomously when various operating conditions change.

It is the figure explaining the concept of the multi-cycle number autonomous determination process in a digital logic circuit. It is a block diagram of a digital logic circuit incorporating a multicycle number autonomous determination device. It is the figure which showed the transition of the operation mode in a digital logic circuit. It is a flowchart which shows operation | movement of cycle number determination processing mode. FIG. 5 is a timing chart for explaining the relationship between the number of multicycles and the amount of circuit delay, where (a) shows the number of multicycles = 5, (b) shows the number of multicycles = 4, and (c) shows the case of the number of multicycles = 3. Yes. It is a figure which shows operation | movement of the single cycle circuit applied to description of a related art, (a) is a block diagram, (b) is a timing chart. It is a figure which shows operation | movement of the multicycle circuit applied to description of a related art, (a) is a block diagram, (b) is a timing chart.

  Prior to the description of the mode for carrying out the invention, the outline and principle of the present invention will be described. The multi-cycle number autonomous determination device is incorporated in a digital logic circuit, and performs a multi-cycle number autonomous determination process for examining the optimum multi-cycle number before the digital logic circuit originally starts processing. As a result, it is possible to easily develop a circuit that always operates the digital logic circuit with the optimum number of multi-cycles under various operating conditions, thereby improving processing throughput and reducing power consumption.

FIG. 1 is a diagram illustrating the concept of multi-cycle number autonomous determination processing (hereinafter referred to as cycle number determination processing as appropriate) in a digital logic circuit. The digital logic circuit selectively performs the originally intended process (normal process) in the digital logic circuit and the cycle number determination process. In the cycle number determination process, the low speed test and the high speed test are performed before the start of the regular process, and the optimum number of cycles is determined by comparing the results.
(Low speed test)
When the start command G1 from the external circuit is input to the digital logic circuit, the cycle number determination process starts. That is, when the start command G1 is input to the sequencer 11, the sequencer 11 outputs a multicycle number setting command G2 having a preset multicycle number setting value as a cycle number initial value to the test pattern signal generation unit 12 and the combinational circuit 13. To do.

  At this time, the initial number of cycles is set to a number of multicycles sufficiently larger than the delay amount assumed for the combinational circuit 13. That is, the cycle number initial value is set so that the cycle time is sufficiently larger than the delay amount of the combinational circuit 13.

  Next, the sequencer 11 outputs a test pattern signal generation command G3 to the test pattern signal generation unit 12. As a result, the test pattern signal generation unit 12 generates a test pattern signal and outputs it to the combinational circuit 13. The test pattern signal generated at this time is a test pattern signal for each combination when all input elements constituting the digital logic circuit are combined.

  The combinational circuit 13 stores the processing result for the test pattern signal in the first memory 14 as the processing result G4 for the low speed test.

When the processing results for all the combination test pattern signals are stored in the first memory 14, the sequencer 11 changes the multicycle number to a value smaller by 1 than the current multicycle number (the changed multicycle number is changed to the multicycle number). This is output as a new multicycle number setting command G2.
(High-speed test processing)
Then, the sequencer 11 outputs a new multicycle number setting command G2 to the test pattern signal generation unit 12 and the combinational circuit 13. Accordingly, the test pattern signal generation unit 12 creates a test pattern signal for the newly notified multi-cycle number trie value and outputs the test pattern signal to the combinational circuit 13. The combinational circuit 13 stores the processing result for the test pattern signal in the second memory 15 as the processing result G5 during the high-speed test.

  When the processing results for all the combination test pattern signals are stored in the second memory 15, the value comparison unit 16 stores the processing results for the low speed test stored in the first memory 14 and the high speed stored in the second memory 15. Compare the values with the processing results during the test.

  This comparison result is notified to the sequencer 11, and when all the values match, the multi-cycle number setting command G2 is reset to a value one smaller than the current value, and the high-speed test process is repeated.

  On the other hand, when the processing result in the low-speed test and the processing result in the high-speed test do not match, multi-cycle number determination processing is performed.

  That is, when the comparison result does not match (exactly, when there is a mismatch from the match), a value obtained by adding 1 to the current multicycle number setting value is set as the optimum multicycle number setting value for the current operating condition. As a result, the cycle number determination process ends.

<First Embodiment>
Next, an embodiment of the present invention based on the principle of the above-described invention will be described. FIG. 2 is a block diagram of the digital logic circuit 20 in which the multi-cycle number autonomous determination device according to the present embodiment is incorporated. This digital logic circuit 20 is a block diagram of the digital logic circuit 20 in which a multi-cycle number autonomous determination device is incorporated.

  The digital logic circuit 20 includes a selector unit 21, a latch unit 22, a combinational circuit 23, a comparison unit 24, a sequencer 25, a test pattern signal generation unit 26, an N-ary counter 27, an input side terminal unit 28, and an output side terminal unit 29. . The multicycle number autonomous determination device includes a selector unit 21, a comparison unit 24, a sequencer 25, a test pattern signal generator 26, and the like.

  The selector unit 21 includes selectors 21 a and 21 b that select one of an input signal to be processed and a test pattern signal and output the selected signal to the latch unit 22.

  The latch unit 22 is provided at the front stage of the combinational circuit 23 and is provided at the front stage of the front stage latch unit 22A (22Aa, 22Ab) with an enable function for latching the processing target data, and the processing result of the combinational circuit 23. Is provided with a post-stage latch unit 22B (22Ba, 22Bb) having an enable function.

  The combinational circuit 23 includes processing logic of the digital logic circuit 20 and performs predetermined processing C.

  The comparison unit 24 compares the values of the memory unit 24A including the first memory 24Aa and the second memory 24Ab, the memory control unit 24B that performs writing and reading control of the memory unit 24A, and the values of the first memory 24Aa and the second memory 24Ab. A comparison unit 24C is included.

  At this time, the first memory 24Aa stores the cycle number determination result of the combinational circuit 23 during the low-speed test. The second memory 24Ab stores the cycle number determination result of the combinational circuit 23 during the high-speed test. Then, the value comparison unit 24C compares the data values stored in the first memory 24Aa and the second memory 24Ab.

  The sequencer 25 outputs a cycle number setting instruction G21, a data selection signal G22, and a test pattern signal generation command G23 in the cycle number determination process.

  The test pattern signal generator 26 generates a test pattern signal in the cycle number determination process.

  The N-ary counter 27 instructs the number of multicycles for the combinational circuit 23.

  The input side terminal unit 28 includes input signal terminals (IN1, IN2) 28a, 28b, a processing timing instruction signal terminal (IEN) 28c, a clock signal terminal (CLK) 28d, a determination start signal terminal (REQ) 28e, a reset signal terminal ( RST) 28f.

  The output side terminal unit 29 includes output signal terminals (OUT1, OUT2) 29a and 29b from which the processing result of the digital logic circuit 20 is output, a processing timing instruction signal terminal (OEN) 29c for the subsequent digital logic circuit 20, and a determination end signal. A terminal (FIN) 29d is provided.

  Next, the operation of the digital logic circuit 20 will be described.

  FIG. 3 is a diagram showing transition of operation modes in the digital logic circuit 20. The digital logic circuit 20 operates while switching between two modes, a normal processing mode for performing original processing (normal processing) and a cycle number determination processing mode for performing cycle number determination processing.

  When the reset signal G11 is input to the reset signal terminal 28f, the digital logic circuit 20 is initialized. By this initialization, the digital logic circuit 20 shifts to the cycle number determination process mode and starts the cycle number determination process.

  When the cycle number determination process end command G12 is input to the determination end signal terminal 29d, the digital logic circuit 20 shifts to the normal processing mode.

  At this time, the cycle number determined by the cycle number determination process in the cycle number determination process mode is set in the N-ary counter 70. In the normal processing mode, normal processing is performed with the set number of cycles.

  If the operating condition changes while the digital logic circuit 20 is executing normal processing in the normal processing mode, a reset signal G11 indicating the start of the cycle number determination processing is input again from the reset signal terminal 28f, and the digital logic The circuit 20 transitions from the normal processing mode to the cycle number determination processing mode. Then, as described above, the number of cycles is determined.

  Next, the operation in the cycle number determination processing mode will be described with reference to the flowchart shown in FIG.

  Step SA1: When the reset signal G11 is input and the digital logic circuit 20 is initialized, the digital logic circuit 20 shifts to the cycle number determination processing mode and starts the cycle number determination process. When the cycle number determination process is started, the sequencer 25 outputs a cycle number setting instruction G21 for specifying the multicycle number to the N-ary counter 27, the test pattern signal generation unit 12, and the memory control unit 24B. The number of cycles at this time is a provisional value, and is M here. However, the provisional value M is set to a sufficiently large value with respect to the assumed delay amount in the combinational circuit 23 to be mounted.

  Step SA2: Next, the sequencer 25 outputs a data selection signal G22 for selecting a signal from the test pattern signal generator 12 to the selector unit 21.

  Step SA3: Thereafter, the sequencer 25 outputs a test pattern signal generation command G23 to the test pattern signal generation unit 12 and the memory control unit 24B. As a result, the test pattern signal generator 12 generates a test pattern signal and outputs it to the selector unit 21.

  Step SA4: Since the preparation for the cycle number determination process (low speed test) is completed as described above, the cycle number determination is started.

  In the cycle number determination process in the low-speed test, the test pattern signal generation unit 12 generates a test pattern signal, the selector unit 21 performs signal selection, and the pre-stage latch unit 22A latches the signal. Then, the combinational circuit 23 performs processing C on the latched signal, and the subsequent stage latch unit 22B latches the output. The signal from the rear stage latch unit 22B is stored in the memory unit 24A of the comparison unit 24.

  That is, when the test pattern signal generation command G23 is received by the test pattern signal generation unit 12, the test pattern signal generation unit 12 has a cycle (M times the cycle T of the clock signal G26 input from the clock signal terminal 28d). = T * M), a combination pattern of all input elements is generated as a test pattern signal. The number of combinations is the square of the data input signal. For example, as shown in FIG. 2, when there are two input signals, a test pattern signal of 4 patterns is generated, and when there are 16 input signals, a test pattern signal of 256 patterns is generated.

  The selector unit 21 selects a signal from the test pattern signal generation unit 26 based on the data selection signal G22 and outputs it to the preceding latch unit 22A. That is, during the cycle number determination processing mode, the selector unit 21 always selects the signal from the test pattern signal generation unit 12 and outputs it to the preceding latch unit 22A. In the normal processing mode, the selector unit 21 selects input signals from the input terminals 28a and 28b and outputs them to the preceding latch unit 22A.

  Each Philip flop 22Aa, 22Ab included in the preceding latch portion 22A has an enable function. Then, in synchronization with the latch enable signal G24 output from the N-ary counter 27, the signal from the selector unit 21 is latched. Accordingly, the pre-stage latch unit 22A latches the test pattern signal in the cycle number determination processing mode, and latches the input signals from the input terminals 28a and 28b in the normal processing mode.

  The combinational circuit 23 performs process C on the signal from the preceding latch unit 22A.

  Each Philip flop 22Ba, 22Bb included in the rear latch unit 22B has an enable function. Then, the signal from the combinational circuit 23 is latched in synchronization with the latch enable signal G24 output from the N-ary counter 27. Therefore, the post-stage latch unit 22B latches the test pattern signal that has undergone the process C in the cycle number determination process mode, and latches the input signal that has undergone the process C in the normal process mode.

  At this time, since the latter stage latch unit 22B latches with the same enable signal G24 as the former stage latch unit 22A, the time of M times the period (= T * M) with respect to the period T of the clock signal G26 is processed in the combinational circuit 23. Given for C.

  The memory control unit 24B outputs a memory control signal G25 at the timing of the latch enable signal G24 in order to write the data latched by the post-stage latch unit 22B to the first memory 24Aa. As a result, the result of processing C performed on the test pattern signal is written to the first memory 24Aa. As described above, since there are a plurality of test pattern signals, the processing result of each test pattern signal subjected to the processing C is sequentially written (for example, from the head address) in the first memory 24Aa.

  Steps SA5 to SA7: As described above, the cycle number determination process in the low speed test is completed, and then the cycle number determination process in the high speed test is performed. This setting is made when the sequencer 25 outputs a cycle number setting instruction G21 for specifying an update value of the cycle number (multi-cycle number trie value) to the N-ary counter 27, the test pattern signal generation unit 12, and the memory control unit 24B. Done. However, the multi-cycle number trie value specified at this time is a value obtained by subtracting 1 from the current cycle number. In the following description, the multi-cycle number trie value is assumed to be the cycle number K.

  Thereafter, the sequencer 25 again outputs a test pattern signal generation command G23 to the test pattern signal generation unit 26 and the memory control unit 24B. Accordingly, the memory control unit 24B performs control so that the data from the combinational circuit 23 is stored in the second memory 24Ab. Then, the test pattern signal generator 26 starts generating the test pattern signal. The generated test pattern signal is input to the combinational circuit 23 via the selector unit 21 and the front-stage latch unit 22A, where processing C is performed, and is input to the memory unit 24A via the rear-stage latch unit 22B. Data from the combinational circuit 23 is stored in the second memory 24Ab.

  Steps SA8 and SA9: When all data subjected to the processing C for the test pattern signal corresponding to the number of cycles specified in the memory unit 24B is stored, the value comparison unit 24C determines whether the first memory 24Aa and the second memory 24Ab Read the value and determine if they match. This determination is processing for determining, for example, a latch miss in the latter-stage latch unit 22B due to an insufficient number of cycles during the high-speed test. Note that whether or not they match is determined to match if all the test pattern signals match.

  That is, if the number of cycles is sufficiently large, the result of the low speed test and the result of the high speed test should match. However, the fact that they match does not mean that the number of cycles at this time is necessary and sufficient. Therefore, in order to obtain the necessary and sufficient number of cycles, if they match, the process returns to step SA5, and if they do not match, the process proceeds to step SA10.

  Since the values of the first memory 24Aa and the second memory 24Ab are the same, when returning to step SA5, the number of cycles is designated again. The number of cycles specified at this time is a value obtained by subtracting 1 from the current number of cycles.

Step SA10: On the other hand, if the values in the first memory 24Aa and the second memory 24Ab do not match, the current cycle number specified in Step SA5 (that is, the number of cycles has been updated from the matched state, so that there is a mismatch state) A value obtained by adding 1 to the number of cycles when the number of times reaches) is defined as the final number of cycles (the optimum number of cycles).

  The optimum number of cycles obtained in this way is a necessary and sufficient value for preventing a latch miss or the like even when operating at high speed. With reference to FIG. 5, it will be described that the optimum number of cycles obtained in this way is necessary and sufficient.

  Now, it is assumed that the delay amount Dt by the process C in the combinational circuit 23 under a certain operating condition is 3.5 cycles of the cycle T of the clock signal (Dt = 3.5 * T). Then, it is assumed that 5 (initial value) is set so that the number M of cycles in the low-speed test is sufficiently larger than the delay amount Dt due to processing C assumed in the combinational circuit 23 (M = 5 * T). FIG. 5 is a timing chart for explaining the relationship between the number of multicycles M and the circuit delay amount. (A) shows a case where M = 5, (b) shows M = 4, and (c) shows a case where M = 3. ing.

  As shown in FIG. 5A, in the case of the number of cycles M (= 5), the processing result of the combinational circuit 23 is determined 1.5 * T before the latch timing L1 in the latter-stage latch unit 22B. . Therefore, the processing result from the combinational circuit 23 is normally latched in the subsequent latch unit 22B. In such a case, the value comparison unit 24C determines that the values match as a result of comparing the values of the first memory 24Aa and the second memory 24Ab.

  Similarly, as shown in FIG. 5B, in the case of the number of cycles M (= 4), the processing result of the combinational circuit 23 is determined 0.5 * T before the latch timing L2 in the latter-stage latch unit 22B. doing. Therefore, the processing result from the combinational circuit 23 is normally latched in the subsequent latch unit 22B. In such a case, the value comparison unit 24C determines that the values match as a result of comparing the values of the first memory 24Aa and the second memory 24Ab.

  However, as shown in FIG. 5C, in the case of the number of cycles M (= 3), the processing result of the combinational circuit 23 is determined before -0.5 * T with respect to the latch timing L3 in the latter-stage latch unit 22B. To do. Therefore, the post-stage latch unit 22B cannot normally latch the processing result from the combinational circuit 23. In such a case, the value comparison unit 24C determines that the values do not match as a result of comparing the values of the first memory 24Aa and the second memory 24Ab.

  Therefore, M = 4 obtained by adding 1 to the cycle number M = 3 becomes the optimum cycle number, and this optimum cycle number becomes the necessary and sufficient number of cycles.

  As described above, autonomous determination of the optimum number of cycles provides the following effects. First, it is possible to operate with the optimum number of multicycles according to the performance of each device when applying a low speed device with a large cost priority delay amount (delay performance of mounted device).

  Further, when the delay amount differs depending on the operation mode of the combinational circuit, it can be operated with a multicycle number suitable for each operation mode (operation mode of the digital logic circuit).

  In operation under low load conditions that do not require high processing capacity, power consumption can be reduced by reducing the power supply voltage of the digital logic circuit within the rated range (power saving mode).

  In the above description, it is assumed that the target circuit of the combinational circuit 23 is basically a combination of circuits. However, the cycle number determination process is performed on the memory device externally connected to the digital logic circuit 20. You may apply. As a result, the digital logic circuit 20 can be operated with a multicycle number suitable for the access time of the memory device to be connected.

  Further, instead of determining the multi-cycle number by the cycle number determination process, a frequency setting value for a clock transmission block such as a PLL that supplies a clock signal may be searched by the cycle number determination process. As a result, the digital logic circuit can be operated in a processing cycle suitable for each operation condition as in the search for the number of multicycles.

DESCRIPTION OF SYMBOLS 11 Sequencer 12 Test pattern signal generation part 13 Combination circuit 14 1st memory 15 2nd memory 16 Value comparison part 20 Digital logic circuit 21 Selector unit 21a, 21b Selector 22 Latch unit 22A Previous stage latch part 22B Rear stage latch part 22Aa, 22Ab Philip flop 22Ba, 22Bb Philip flop 23 combinational circuit 24 comparison unit 24A memory unit 24Aa first memory 24Ab second memory 24B memory control unit 24C value comparison unit 25 sequencer 26 test pattern signal generation unit 27 N-ary counter

Claims (8)

Front latch unit for latching a signal input to the at least one or more combinational circuit forms a predetermined function and a delay amount generated by the processes in the subsequent stage latch unit or Ranaru digital logic circuit for latching the output signal from the combining circuit A multi-cycle number autonomous determination device that autonomously determines the multi-cycle number adapted to
A test pattern signal generation unit that generates a test pattern signal corresponding to at least a combination pattern of input elements and outputs the test pattern signal to the combinational circuit;
A multi-cycle number setting command indicating the number of cycles is output, and when the operating conditions change at that time, a multi-cycle number setting command is output that uses the preset initial value of the multi-cycle number as the cycle number for the low-speed test. The test pattern signal generation unit generates a test pattern signal for a low speed test, and when the low speed test is completed, a multicycle number trie value that takes a value smaller than the initial value of the multicycle number as the number of cycles in the high speed test, A sequencer that outputs a multi-cycle number setting command and causes the test pattern signal generation unit to generate a test pattern signal for high-speed testing;
The result of processing performed by the combinational circuit on the test pattern signal is stored, and the result of processing on the test pattern signal for the low speed test coincides with the result of processing on the test pattern signal for the high speed test. A comparison unit for determining
The sequencer determines from the number of multicycles until the comparison result from the comparison unit does not match the processing result for the test pattern signal for the low speed test and the processing result for the test pattern signal for the high speed test. The multi-cycle number setting command is output with the value obtained by subtracting the value as a new multi-cycle number trie value, and the processing result for the test pattern signal for the low-speed test and the processing result for the test pattern signal for the high-speed test are A multicycle number autonomous determination device, characterized in that a value obtained by adding 1 to the number of multicycles when mismatched is determined as an optimal multicycle. The multicycle number autonomous determination device according to claim 1,
An multi-cycle number autonomous determination device comprising an N-ary counter that receives the multi-cycle number setting command and operates the combinational circuit at a cycle number specified by the multi-cycle number setting command. The multicycle number autonomous determination device according to claim 1 or 2,
When a multicycle number setting command including the initial value of the multicycle number output from the sequencer is received, the circuit is switched so that the test pattern signal is input to the combinational circuit via the pre-stage latch unit. A multi-cycle number autonomous determination device comprising a selector unit. The multi-cycle number autonomous determination device according to any one of claims 1 to 3,
The comparison unit includes a first memory that stores a processing result by the combinational circuit at the time of the low-speed test, and a second memory that stores a processing result by the combinational circuit at the time of the high-speed test,
A value comparison unit configured to determine whether or not the processing results for the test pattern signals stored in the first memory and the second memory match each of the combination patterns ; Multicycle number autonomous determination device. Front latch unit for latching a signal input to the combining circuit which forms a predetermined function and multi adapted to the delay amount generated in the processes in the subsequent stage latch unit or Ranaru digital logic circuit for latching the output signal from the combining circuit A multi-cycle number autonomous determination method for autonomously determining the number of cycles,
A test pattern signal generation procedure for generating a test pattern signal corresponding to each combination pattern of input elements and outputting the test pattern signal to the combinational circuit;
A multi-cycle number setting command indicating the number of cycles is output, and when the operating conditions change at that time, a multi-cycle number setting command is output that uses the preset initial value of the multi-cycle number as the cycle number for the low-speed test. A test pattern signal for a low-speed test, and when the low-speed test is completed, a multi-cycle number setting command is set to a multi-cycle number trie value with a value smaller than the initial value of the multi-cycle number as a cycle number in the high-speed test. A sequence procedure for outputting and generating a test pattern signal for the high-speed test;
The result of processing performed by the combinational circuit on the test pattern signal is stored, and the result of processing on the test pattern signal for the low speed test coincides with the result of processing on the test pattern signal for the high speed test. A comparison procedure for determining
The sequence procedure subtracts 1 from the number of multicycles until the comparison result does not match the processing result for the test pattern signal for the low speed test and the processing result for the test pattern signal for the high speed test. A multi-cycle number setting command with the new multi-cycle number trie value is output, and the processing result for the test pattern signal for the low-speed test does not match the processing result for the test pattern signal for the high-speed test A method for autonomously determining the number of multicycles, comprising a step of determining, as an optimum multicycle, a value obtained by adding 1 to the number of multicycles at the time of becoming an optimal multicycle. The multicycle number autonomous determination method according to claim 5,
A multicycle number autonomous determination method comprising: receiving the multicycle number setting command, and operating the combinational circuit at a cycle number specified by the multicycle number setting command. The multicycle number autonomous determination method according to claim 5 or 6,
A step of switching the circuit so that the test pattern signal is input to the combinational circuit via the preceding latch unit when a multicycle number setting command including the initial value of the multicycle number is received. Multi-cycle number autonomous determination method. The multicycle number autonomous determination method according to any one of claims 5 to 7,
A memory procedure for storing a processing result by the combinational circuit during the low-speed test in a first memory, and storing a processing result by the combinational circuit during the high-speed test in a second memory;
And a value comparison procedure for determining whether or not the processing results for the test pattern signals stored in the first memory and the second memory match each of the combination patterns. Multicycle number autonomous determination method.

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