JP6398692B2 - High electron mobility transistor and method of manufacturing high electron mobility transistor - Google Patents

Description

  The present invention relates to a high electron mobility transistor (a so-called HEMT) and a method for manufacturing a high electron mobility transistor.

  Conventionally, a high electron mobility transistor is known in which a channel layer and a barrier layer are heterojunctioned and a carrier is a two-dimensional electron gas that is a field of electrons formed at the heterojunction interface. High electron mobility transistors are used in various applications because carriers can move at high speed in a high-purity channel layer without being disturbed by impurities and have less noise.

  For example, Patent Document 1 discloses a field effect transistor having a hetero interface including a channel layer made of GaN or InGaN and a barrier layer made of AlN, an insulating film formed on the surface of a transistor element, and the electric field An effect transistor manufacturing method is disclosed. In the invention described in Patent Document 1, the thickness of the barrier layer made of AlN is made very thin to increase the polarization effect, and the polarization is effected by the influence of the surface charge of the barrier layer by reducing the thickness of the barrier layer. It is suppressed that the two-dimensional electron concentration increased by the effect is decreased and the resistance of the channel layer is increased.

JP 2007-234986 A

  As a method of further increasing the amount of current controlled by the high electron mobility transistor, there are two methods, a method of increasing the carrier density (two-dimensional electron concentration) and a method of increasing the mobility (movement speed). The present application focuses on a method for increasing the carrier density. For example, if the Al ratio in the barrier layer made of AlN is increased, the carrier density can be increased. However, if the Al ratio is increased, defects are likely to occur in the barrier layer, which is not preferable. Further, if the strain accompanying mismatch of lattice constants of the channel layer and the barrier layer is increased, the polarization effect can be increased, and the carrier density can be further increased.

  In the invention described in Patent Document 1, the polarization effect is increased by making the film thickness of the barrier layer made of AlN very thin, but the upper surface (surface on which the gate is formed) and the lower surface of the barrier layer. Since the distance to the (interface with the channel layer) is very close, the influence on the two-dimensional electrons due to the charge on the upper surface of the barrier layer has increased.

  The present invention was devised in view of such a point, and a high electron mobility transistor capable of further increasing the carrier density without significantly reducing the thickness of the barrier layer, and the high electron An object is to provide a method for manufacturing a mobility transistor.

  In order to solve the above problems, the high electron mobility transistor and the method for manufacturing the high electron mobility transistor according to the present invention take the following means. First, according to a first aspect of the present invention, a buffer layer stacked on a substrate, a channel layer stacked on the buffer layer, a barrier layer stacked on the channel layer, and the barrier It is a high electron mobility transistor having a source, a drain, and a gate, which are electrodes formed on a layer, wherein the channel layer and the barrier layer are heterojunctioned. An insulating film is stacked on the barrier layer including the source, the drain, and the gate, and after the insulating film is stacked, a predetermined heat treatment is performed to form the insulating film at the time of stacking. On the other hand, it is in a contracted state.

  Next, a second invention of the present invention is the high electron mobility transistor according to the first invention, wherein the gate is formed of amorphous silicon or polysilicon at the time of formation, and the predetermined It has a shape that is crystallized by heat treatment and expanded as compared to the time of formation.

  Next, a third invention of the present invention is the high electron mobility transistor according to the first invention or the second invention, wherein the insulating film is composed of either SiN or SiON. Yes.

  Next, according to a fourth aspect of the present invention, there is provided a buffer layer stacked on a substrate, a channel layer stacked on the buffer layer, a barrier layer stacked on the channel layer, A method of manufacturing a high electron mobility transistor having a source, a drain, and a gate, which are each electrode formed on a barrier layer, wherein the channel layer and the barrier layer are heterojunction, An insulating film is stacked on the barrier layer including the source, the drain, and the gate, and after the insulating film is stacked, the insulating film is contracted by applying a predetermined heat treatment, This is a method for manufacturing a high electron mobility transistor in which stress due to shrinkage of an insulating film is applied to accumulate strain due to the stress.

  Next, a fifth invention of the present invention is a method of manufacturing a high electron mobility transistor according to the fourth invention, wherein the gate is formed of amorphous silicon or polysilicon when the gate is formed. The method of manufacturing a high electron mobility transistor, wherein the gate crystal is expanded and expanded by the predetermined heat treatment, and stress due to expansion of the gate is applied to the barrier layer to accumulate strain due to the stress. .

  According to the first invention, since the insulating film laminated on the barrier layer is in a contracted state with respect to the time of lamination, the residual stress of the insulating film is left large. The residual stress due to the shrinkage of the insulating film can increase the strain by applying a stress to the barrier layer. The carrier density can be further increased by increasing the strain of the barrier layer.

  According to the second invention, the gate formed on the barrier layer has a shape expanded with respect to the formation time. The strain due to the expanded shape of the gate can be applied to the barrier layer to increase the strain. The carrier density can be further increased by increasing the strain of the barrier layer.

  According to the third invention, a more appropriate insulating film can be more easily laminated according to the material of the barrier layer and the like.

  According to the fourth invention, the insulating film laminated on the barrier layer is in a contracted state with respect to the time of lamination, so that the residual stress of the insulating film is left large, and the residual stress due to the shrinkage of the insulating film. Thus, the strain can be increased by applying a stress to the barrier layer. Further, by increasing the strain of the barrier layer, it is possible to provide a method for manufacturing a high electron mobility transistor that further increases the carrier density.

  According to the fifth aspect of the present invention, there is provided a method for manufacturing a high electron mobility transistor, in which stress due to an expanded shape of a gate is applied to a barrier layer to further increase the strain of the barrier layer and further increase the carrier density. Can do.

It is an example of sectional drawing explaining each layer of the high electron mobility transistor of this invention. It is a figure explaining each process for manufacturing a high electron mobility transistor. It is a figure explaining a mode that the distortion of the barrier layer of the high electron mobility transistor manufactured by the manufacturing method of the high electron mobility transistor of this invention is increased, and a mode that carrier density is increased. FIG. 3 is a diagram for explaining the state of carrier density of a conventional high electron mobility transistor (a high electron mobility transistor having no residual film having a residual stress).

Hereinafter, embodiments of the present invention will be described in order with reference to the drawings.
● [Overall structure of high electron mobility transistor (Fig. 1)]
As shown in FIG. 1, the high electron mobility transistor 1 of the present invention includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a source 21, a drain 22, and a gate 23 that are electrodes. And the insulating film 15.

  The substrate 11 is a plate-like member made of, for example, sapphire or SiC (silicon carbide), and an existing substrate is used.

  The buffer layer 12 is laminated on the substrate 11 and is disposed between the substrate 11 and the channel layer 13, and is a buffer layer for laminating the channel layer 13 without defects. The material of the buffer layer 12 is, for example, AlN (aluminum nitride).

  The channel layer 13 is a layer that is stacked on the buffer layer 12 and forms a heterointerface near the boundary with the barrier layer 14. The channel layer 13 is not doped with impurities and is made of a high-purity material, for example, GaN (gallium nitride). The channel layer 13 is a layer in which carriers generated in the barrier layer 14 move and is not doped with impurities, so that carriers can move at high speed. The channel layer 13 is formed with a thickness of, for example, 1 [μm].

  The barrier layer 14 is a layer that is stacked on the channel layer 13 and is formed by, for example, epitaxial growth or the like and heterojunction with the channel layer 13. For example, when the material of the channel layer 13 is GaN, AlGaN (aluminum gallium nitride) is used as the material of the barrier layer 14, and the ratio of Al (aluminum) is appropriately selected. By increasing the Al ratio, the carrier density of the channel layer 13 can be increased. However, when the Al ratio is increased, defects are likely to occur in the barrier layer 14. Therefore, the ratio of Al is set to a ratio at which the barrier layer 14 can be formed safely. The thickness of the barrier layer 14 is, for example, 30 [nm].

The source 21 and the drain 22 are electrodes made of Al, for example, and are formed by a sputtering method or the like. The electrodes of the source 21 and the drain 22 are formed as ohmic electrodes, and the electrode of the gate 23 is formed as a Schottky electrode joined to the semiconductor of the barrier layer 14. The gate 23 is not a Schottky electrode but amorphous silicon on an insulating film such as SiN (silicon nitride), SiO ₂ (silicon dioxide), SiON (silicon oxynitride), Al ₂ O ₃ (aluminum oxide), or AlN. Alternatively, an electrode made of polysilicon may be used. When the gate 23 is formed of amorphous silicon or polysilicon, the gate 23 can be formed relatively easily at a relatively low cost.

  The insulating film 15 is laminated on the barrier layer 14 including the source 21, the drain 22, and the gate 23 and is an insulating film (layer), and is made of SiN (silicon nitride) or SiON (silicon oxynitride). It is composed of any material. The insulating film 15 is formed with a thickness of, for example, 100 [nm].

  In high electron mobility transistors, a barrier layer is stacked on a high-purity channel layer in a heterojunction, and tensile strain resulting from lattice mismatch is applied to the barrier layer to generate piezoelectric polarization. . Then, due to the piezoelectric polarization, high mobility carriers (two-dimensional electron gas) are generated at the heterointerface near the boundary between the channel layer and the barrier layer. As a method of increasing this strain, there is a method of increasing the ratio of impurities in the barrier layer (Al in the case of AlGaN), but as the Al ratio is increased, defects are generated in the barrier layer as described above. Since the mobility of a carrier falls, it is not so preferable. Therefore, there is a limit to the application of strain due to an increase in the impurity ratio of the barrier layer.

  The high electron mobility transistor 1 of the present invention increases the strain of the barrier layer 14 by leaving a large residual stress in the insulating film 15 after each layer shown in FIG. 1 is formed as described above. Increase carrier density. Specifically, the residual stress of the insulating film 15 is increased by performing a predetermined heat treatment so that the insulating film 15 is contracted with respect to the time of lamination (see FIG. 3). Further, when the gate 23 is formed of amorphous silicon or polysilicon at the time of formation, the gate 23 is expanded by increasing the volume by crystallization by the heat treatment. When the gate 23 expands, as shown in FIG. 3, a force in a direction that promotes the curvature of the barrier layer 14 acts, further increasing the strain of the barrier layer 14 and further increasing the carrier density. Below, the manufacturing method of the high electron mobility transistor 1 of this invention is demonstrated.

● [Manufacturing method of high electron mobility transistor (Figure 2)]
Next, a manufacturing method of the high electron mobility transistor 1 will be described with reference to FIG. In step S10 of the first process, the buffer layer 12 is laminated on the prepared substrate 11. In step S20, which is the next process, the channel layer 13 is stacked on the buffer layer 12. In step S30, which is the next process, the barrier layer 14 is stacked on the channel layer 13. The above process is the same process as the existing process.

  In step S40, which is the next process, the source 21, drain 22, and gate 23 electrodes are formed on the barrier layer 14 by sputtering or the like. When the gate 23 is formed of Al, it can be formed by a process similar to an existing process. In the case where the gate 23 is formed of amorphous silicon or polysilicon, the gate 23 is formed using a CVD method or the like after or before the source 21 and the drain 22 are formed.

  In step S50, which is the next process, the insulating film 15 is stacked on the barrier layer 14 including the source 21, the drain 22, and the gate 23. In addition, it is more preferable to employ the insulating film 15 having a relatively low density (a large amount of hydrogen is contained) in order to increase the shrinkage amount. The film forming temperature is, for example, about 200 [° C.] to 400 [° C.], and a sputtering method, plasma CVD, or the like can be used as the film forming method.

  In step S60, which is the next step, the wafer is cut by dicing to cut out each chip (each semiconductor element). In step S70, which is the next step, each chip is put in an electric furnace, a hot air dryer or the like, heated at a predetermined temperature for a predetermined time, and then subjected to heat treatment for gradually lowering the temperature to room temperature. For example, after heating at a temperature of about 800 [° C.] to about 1000 [° C.] for about several minutes, the temperature is lowered in a normal temperature atmosphere. For this heat treatment, for example, a so-called annealing treatment for removing the distortion of the resin molded product can be applied. When the resin molded product is annealed, residual strain of the resin molded product can be removed. However, when the high electron mobility transistor of the present invention is annealed, the resin molded product is laminated on the barrier layer 14. The insulating film 15 that has been (attached) is contracted by heat while maintaining the state of being attached to the barrier layer 14, and residual stress (residual strain) is generated in the insulating film 15. Note that the order of the step S60 and the step S70 may be interchanged. The heterojunction between the channel layer 13 and the barrier layer 14 has a strong bonding force because molecular crystals are bonded to each other, and the channel layer 13 and the barrier layer 14 are not broken by the residual stress of the insulating film 15. . In addition, when the gate 23 is formed of amorphous silicon or polysilicon, when the above-described annealing treatment is performed, crystallization of the gate that has been in an amorphous state proceeds and the volume increases and expands.

  The next step, step S80, is packaging, in which the chip is mounted on a frame, the electrodes are connected by wire bonding, and molded with resin or the like.

[Strain accumulation in barrier layer 14 increases and carrier density increases (FIGS. 3 and 4)]
As shown in FIG. 3, the insulating film 15 of the high electron mobility transistor 1 manufactured by the manufacturing method shown in FIG. 2 is contracted with respect to the time of lamination by the heat treatment in step S70 shown in FIG. The residual stress in the shrinking direction is accumulated in the insulating film 15. The residual stress of the insulating film 15 acts as a force that causes the upper surface of the barrier layer 14 shown in FIG. 3 to warp and acts to cause the lower surface of the barrier layer 14 to warp. A virtual barrier layer image V14 indicated by a dotted line in FIG. Tensile strain increases on the lower surface of the barrier layer 14 due to the residual stress of the insulating film 15 that attempts to deform the shape of the barrier layer 14 into the shape of the virtual barrier layer image V14. Further, when the gate 23 is formed of amorphous silicon or polysilicon, crystallization proceeds from the amorphous state and the volume increases and expands due to the heat treatment in step S70. In FIG. 3, when the volume of the gate 23 increases and expands, a force (which pushes the barrier layer 14 downward in FIG. 3) helps to further increase the curvature of the shape of the virtual barrier layer image V14 that warps upward. Force), the tensile strain can be further increased. In addition, since the gate 23 is usually disposed near the center of the chip of the high electron mobility transistor 1 (in the vicinity of the center in the left-right direction in FIG. 3), the stress generated by the expansion is blocked at an appropriate position. It can be applied to layer 14.

  In the conventional high electron mobility transistor 100 shown in FIG. 4 (high electron mobility transistor not having an insulating film having residual stress), the lower surface of the barrier layer 114 has a difference in lattice constant from that of the channel layer 113. Due to the piezo polarization caused by the tensile strain, positive fixed charges 131 are generated on the lower surface of the barrier layer 114, and free charges 132 (carriers) induced by the positive fixed charges 131 are generated. The generated free charges 132 can move at high speed in the channel layer 113. However, since the tensile strain of the barrier layer 114 is smaller than that of the present application shown in FIG. 3, the generated carriers (free charge 132) are less than the carriers (free charge 32) generated in the present application shown in FIG.

  On the other hand, the high electron mobility transistor 1 of the present invention shown in FIG. 3 is different from the conventional high electron mobility transistor 100 shown in FIG. On top, it has an insulating film 15 which is in a contracted state and has accumulated residual stress. The tensile strain on the lower surface of the barrier layer 14 is increased (accumulated) by the residual stress of the insulating film 15 and the stress due to the expansion of the gate 23. Due to the increased (accumulated) tensile strain, the positive fixed charges 31 generated on the lower surface of the barrier layer 14 are increased, and the free charges 32 (carriers) induced in the positive fixed charges 31 are increased. The increased free charge 32 can move at high speed in the channel layer 13.

  As described above, in the high electron mobility transistor 1 of the present invention, in addition to the tensile strain caused by the lattice constant mismatch, the barrier layer 14 is caused by the residual stress accompanying the contraction of the insulating film 15 and the stress accompanying the expansion of the gate 23. By applying the mechanical tensile strain, the tensile strain of the barrier layer 14 is increased (accumulated). That is, the insulating film 15 laminated (attached) on the barrier layer 14 is contracted by a predetermined heat treatment while maintaining the attached state, and the residual stress generated by the contraction of the insulating film 15 ( And the stress generated by the expansion of the gate 23) is transmitted to the barrier layer 14 to increase the strain of the barrier layer 14, thereby increasing the number of carriers. Therefore, the carrier density of the high electron mobility transistor can be increased with a very simple structure and a very simple manufacturing method without reducing the thickness of the barrier layer.

  The configuration, structure, material, manufacturing method, and the like of the high electron mobility transistor of the present invention can be variously changed, added, or deleted without changing the gist of the present invention. For example, the material of the substrate, the material of the buffer layer, the material of the channel layer, and the material of the barrier layer are not limited to the materials described in this embodiment.

  The numerical values used in the description of the present embodiment are examples, and are not limited to these numerical values.

DESCRIPTION OF SYMBOLS 1 High electron mobility transistor 11 Substrate 12 Buffer layer 13 Channel layer 14 Barrier layer 15 Insulating film 21 Source 22 Drain 23 Gate 31 Positive fixed charge 32 Free charge V14 Virtual barrier layer image

Claims (3)

A buffer layer stacked on the substrate;
A channel layer stacked on the buffer layer;
A barrier layer stacked on the channel layer;
A high electron mobility transistor having a source, a drain, and a gate, each electrode formed on the barrier layer, wherein the channel layer and the barrier layer are heterojunction;
An insulating film is stacked on the barrier layer including the source, the drain, and the gate, and after the insulating film is stacked, a predetermined heat treatment is performed so that the insulating film is not stacked. It is supposed to be in a contracted state ,
The gate is formed of amorphous silicon or polysilicon at the time of formation, and has a shape expanded by crystallization as a result of the predetermined heat treatment.
High electron mobility transistor. The high electron mobility transistor of claim 1 ,
The insulating film is composed of either SiN or SiON.
High electron mobility transistor. A buffer layer stacked on the substrate;
A channel layer stacked on the buffer layer;
A barrier layer stacked on the channel layer;
A method of manufacturing a high electron mobility transistor having a source, a drain, and a gate, which are electrodes formed on the barrier layer, wherein the channel layer and the barrier layer are heterojunction. ,
Laminating an insulating film on the barrier layer including the source, the drain, and the gate;
After laminating the insulating film, the insulating film is contracted by applying a predetermined heat treatment, and stress due to contraction of the insulating film is applied to the barrier layer to accumulate strain due to the stress ,
When forming the gate, the gate is formed of amorphous silicon or polysilicon, and the gate is crystallized and expanded by the predetermined heat treatment, and stress due to the expansion of the gate is applied to the barrier layer. To accumulate strain due to the stress,
Method for manufacturing a high electron mobility transistor.

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