JP6386928B2 - Delta-sigma modulator and digital-to-analog converter using the same - Google Patents

Description

  The present invention relates to a delta-sigma modulator and a digital-to-analog converter, and more particularly to a delta-sigma modulator that uses a dither signal to reduce noise.

  In general, a delta-sigma modulator (hereinafter sometimes referred to as a “ΔΣ modulator”) integrates an error of an output signal with respect to an input signal, and quantizes the integrated value by a quantizer as a modulation result. Output signal is generated. When the input signal is in a no-signal state, noise accompanying the above-described feedback operation of the delta-sigma modulator may appear in the output signal. In order to reduce such noise, a method of applying a dither signal to an input signal in a no-signal state has been conventionally known (see Patent Document 1).

JP 2012-114698 A

  However, delta sigma modulator noise also occurs when the input signal is not in the no-signal state. For example, in a delta-sigma modulator in which the input signal is a digital value and the quantization error in the quantizer is also a digital value, the lower bit of the input signal and the lower bit of the quantization error are both zero. When an input signal having a constant value is continuously input, the output signal changes regularly with a relatively short period. This is equivalent to superimposing a noise component of a specific frequency on the output signal, and means that the SN ratio of the output signal is deteriorated.

  The present invention has been made in view of such circumstances, and an object thereof is to suppress an increase in noise components superimposed on an output signal even when both the lower bits of the input signal and the lower bits of the quantization error are zero. It is an object of the present invention to provide a delta-sigma modulator that can perform the above and a digital-to-analog converter including such a delta-sigma.

  A delta-sigma modulator according to a first aspect of the present invention generates the output signal according to a result obtained by integrating and quantizing a difference between a digital value input signal and an output signal, A modulation unit that generates a digital value error signal indicating a conversion error; a first detection unit that detects that lower-order data of a predetermined bit length in the input signal is zero; and a lower-order of a predetermined bit length in the error signal A second detector for detecting that the data has become zero, and the lower order data of the input signal is zero according to the detection results of the first detector and the second detector, and the error And a dither adding unit that adds a dither signal to the input signal or the error signal when the lower data of the signal becomes zero.

  According to the above configuration, when the lower data of the input signal becomes zero and the lower data of the error signal becomes zero, a dither signal is added to the input signal or the error signal, Since the periodic change of the output signal of the modulation unit is disturbed, it is difficult for a noise component of a specific frequency to be superimposed on the output signal.

Preferably, the dither addition unit may be configured such that when the low-order data of the input signal is zero and the low-order data of the error signal is continuously zero, the input signal or the A dither signal may be added to the error signal.
In this case, the dither addition unit counts the number of occurrences of the state in which the lower data of the input signal becomes zero and the lower data of the error signal becomes zero, and the lower data of the input signal A counter that initializes a count value when the non-zero or the lower data of the error signal becomes non-zero, and when the count value of the counter reaches a predetermined value, the input signal or the error signal There may be provided a multiplexer that replaces the lower bit data with a predetermined dither signal.
According to said structure, the increase in the error of the said output signal by the said dither signal being added frequently is prevented.

  Preferably, the modulation unit adds a delay circuit that outputs a delayed signal for each sampling period, a signal delayed in the delay circuit, and the input signal, and inputs the addition result to the delay circuit. And a modulation adder that generates the 1-bit output signal indicating the overflow of the addition result. In this case, the error signal may be a signal resulting from the addition of the modulation adder input or output in the delay circuit.

  Preferably, the modulation unit generates the output digital signal according to a result obtained by integrating and quantizing a difference between the input digital signal and the output digital signal, and an error digital signal indicating a quantization error in the quantization. A plurality of modulation circuits connected in cascade such that the input signal is input to the first stage and the error digital signal generated by the previous stage is input to each of the second and subsequent stages. A circuit, a differentiator for differentiating the output digital signal of the modulation circuit in the second and subsequent stages by an order corresponding to the number of stages from the first stage, the output digital signal of the modulation circuit in the first stage, and the differentiator You may have an adder for output composition which calculates the sum of the output digital signal of the modulation circuit of the 2nd stage after differentiation. In this case, the error signal may be the error digital signal generated in the first-stage modulation circuit.

  A digital-analog converter according to a second aspect of the present invention includes an upsampling unit that converts a digital signal input at a first sampling frequency into a digital signal having a second sampling frequency higher than the first sampling frequency, and the upsampling unit A delta-sigma modulator according to the first aspect that applies delta-sigma modulation to a digital signal whose sampling frequency is converted in the sampling unit; and a digital-analog converter that generates an analog signal corresponding to the output signal of the delta-sigma modulator; And a low-pass filter for removing a high-frequency component contained in the analog signal output from the digital-analog conversion unit.

  Preferably, the delta sigma modulator performs delta sigma modulation on lower bit side data in the digital signal whose sampling frequency is converted in the upsampling unit, and outputs the output signal of the delta sigma modulator and the upsampling unit An adder for adding the data on the upper bit side in the digital signal whose sampling frequency has been converted may be provided. In this case, the digital-analog converter may convert the digital signal resulting from the addition by the adder into an analog signal.

  According to the present invention, even when both the lower bits of the input signal and the lower bits of the quantization error of delta-sigma modulation are zero, it is possible to suppress an increase in noise components superimposed on the output signal.

It is a figure which shows an example of a structure of the DA converter which concerns on embodiment of this invention. It is a figure which shows the structural example of the modulation part of a delta-sigma modulator. It is a figure which shows an example of the modulation circuit of 1 bit output contained in a modulation part. It is a figure for demonstrating control of the order of (DELTA) (SIGMA) modulation by an input level detector. It is a figure which shows the simulation waveform of the output signal of a delta-sigma modulator. FIG. 5A shows a waveform when no dither signal is added, and FIG. 5B shows a waveform when a dither signal is added. It is a figure which shows the frequency spectrum of the simulation waveform shown in FIG. 6A shows the frequency spectrum of the waveform of FIG. 5A, and FIG. 6B shows the frequency spectrum of the waveform of FIG. 5B. It is a figure which shows the frequency spectrum at the time of applying a low-pass filter to the signal which has a waveform shown in FIG. 7A shows a frequency spectrum corresponding to FIG. 5A, and FIG. 7B shows a frequency spectrum corresponding to FIG. 5B. It is a figure which shows the modification of a delta-sigma modulator.

  FIG. 1 is a diagram illustrating an example of a configuration of a DA converter according to an embodiment of the present invention. The DA converter illustrated in FIG. 1 includes an upsampling unit 10, a ΔΣ modulator 20, an adder 30, a digital / analog conversion unit 50, and a low-pass filter 60.

  The upsampling unit 10 is a circuit that converts a digital signal Sin having a sampling frequency Fs into a signal S10 having a higher sampling frequency, and is configured using a complementary filter such as a CIC upsampling filter.

  The ΔΣ modulator 20 receives data DL on the lower bit side of the signal S10 oversampled by the upsampling unit 10, and applies ΔΣ modulation to the data DL. Details of the configuration of the ΔΣ modulator 20 will be described later.

  The adder 30 adds the upper bit data (upper data DH) of the digital signal S10 and the modulation result output signal S20 output from the ΔΣ modulator 20.

  The digital-analog conversion unit 50 converts the digital signal S30 resulting from the addition by the adder 30 into an analog signal.

  The low-pass filter 60 removes a high frequency component included in the analog signal output from the digital / analog conversion unit 50 and outputs the analog signal Sout. The low-pass filter 60 has a function of removing noise components collected on the high frequency side by the action of oversampling by the upsampling unit 10 and noise shaping of the ΔΣ modulator 20.

Next, a detailed configuration of the ΔΣ modulator 20 will be described.
The ΔΣ modulator 20 illustrated in FIG. 1 includes a modulation unit 21, a first detection unit 22, a second detection unit 23, and a dither addition unit 24.

  The modulation unit 21 generates an output signal S20 corresponding to the result of integrating and quantizing the difference between the digital value input signal (low-order bit side data DL) and the output signal S20, and a quantization error in the quantization. An error signal (Eq1) of a digital value indicating

  FIG. 2 is a diagram illustrating an example of the configuration of the modulation unit 21. 2 is a circuit that performs delta-sigma modulation of a fourth-order MASH (multi stage noise shaping) method, and includes modulation circuits DS1, DS2, DS3, and DS4 having 1-bit output, a differentiator 211, 212, 213, an output synthesis adder 214, and an input level detector 215.

  Each of the modulation circuits DS1, DS2, DS3, and DS4 is a circuit that performs ΔΣ modulation, and integrates and quantizes the difference between the input digital signal and the output digital signal to output a 1-bit output digital signal (C1, C2, C3, C4) and error digital signals (Eq1, Eq2, Eq3) indicating the quantization error in the quantization are generated. The modulation circuit DS1 generates an output digital signal C1 and an error digital signal Eq1, the modulation circuit DS2 generates an output digital signal C2 and an error digital signal Eq2, and the modulation circuit DS3 generates an output digital signal C3 and an error digital signal Eq3. The modulation circuit DS4 generates an output digital signal C4.

  Further, as shown in FIG. 2, the modulation circuits DS1, DS2, DS3, DS4 are cascaded in this order. The first-stage modulation circuit DS1 inputs the lower bit data DL as an input digital signal. The modulation circuits DS2, DS3, DS4 in the second and subsequent stages input the error digital signals (Eq1, Eq2, Eq3) generated in the previous stage as input digital signals.

FIG. 3 is a diagram illustrating an example of the configuration of the modulation circuit DS1. The other modulation circuits (DS2 to DS4) can have the same configuration.
The modulation circuit DS1 illustrated in FIG. 3 includes a modulation adder 216 and a delay circuit 217.
The delay circuit 217 delays and outputs the error digital signal Eq1 input from the modulation adder 216 for each sampling period.
The modulation adder 216 adds the signal delayed in the delay circuit 217 and the input digital signal (lower bit data DL), outputs the addition result as an error digital signal Eq1, and overflows in the addition result. A 1-bit output digital signal C1 indicating (carry) is generated.

Returning to FIG.
Differentiators 211, 212, and 213 differentiate the output digital signals (C2 to C4) of the second and subsequent modulation circuits (DS2 to DS4) by orders corresponding to the number of stages from the first modulation circuit DS1, respectively. Differentiator 211 performs first-order differential operation ^{(1-Z -1)} to output a digital signal C2 of the modulation circuit DS2, differentiator 212 secondary differential operation on the output digital signal C3 of the modulation circuit DS3 ((1-Z ^{- 1} ) ² ) is performed, and the differentiator 213 performs a third-order differential operation ((1-Z ⁻¹ ) ³ ) on the output digital signal C4 of the modulation circuit DS4.

  The output synthesis adder 214 outputs the output digital signal C1 of the first-stage modulation circuit DS1 and the output digital signal (C2) of the second and subsequent modulation circuits (DS2 to DS4) differentiated by the differentiators 211, 212, and 213. ˜C4) is calculated and output as the modulation output signal S20.

  The input level detector 215 changes the order of ΔΣ modulation in the ΔΣ modulator 20 according to the value of the upper bit data DH of the digital signal S10 output from the upsampling unit 10. When the order of ΔΣ modulation is set to “1”, the input level detector 215 stops the modulation operation of the modulation circuits DS2, DS3, DS4. When the order of ΔΣ modulation is set to “2”, the input level detector 215 stops the modulation operation of the modulation circuits DS3 and DS4. When the order of ΔΣ modulation is set to “3”, the input level detector 215 stops the modulation operation of the modulation circuit DS4. When the order of ΔΣ modulation is set to “4”, the input level detector 215 does not stop the modulation operation of the modulation circuits (DS2 to DS4). When the input level detector 215 stops the modulation operation of the modulation circuit (DS2 to DS4), for example, the signal obtained by delaying the error digital signal (Eq2 to Eq4) is set to zero, and the value of the output digital signal (C2 to C4) Is fixed to zero.

FIG. 4 is a diagram for explaining the control of the order of ΔΣ modulation by the input level detector 215. In the example of FIG. 4, the upper bit data DH is a 5-bit signed binary code, and its numerical range is −16 to 15. The numerical range of the signal generated by the nth-order ΔΣ modulation is “−2 ⁽ⁿ⁻¹⁾ +1” to “2 ⁽ⁿ⁻¹⁾ ”, and the numerical range in the fourth order is −7 to 8. . Therefore, when the result of the fourth-order ΔΣ modulation is added to the upper bit data DH as it is, the numerical range is −23 to 23 and the numerical level number is 47. In the order control method shown in FIG. 4, the numerical value range of the signal S30 obtained by adding the output signal S20 as the modulation result of the ΔΣ modulator 20 and the upper bit data DH (5 bits) is −16 to 16 (the number of levels is 33). The order is controlled so as to fall within the range. For example, when the higher-order bit data DH increases beyond the threshold value 9, the order of ΔΣ modulation decreases from “4” to “3”. As the absolute value of the upper bit data DH increases, the order of ΔΣ modulation decreases. As a result, the numerical value range of the signal S30 falls within the range of −16 to 16. Further, since the hysteresis operation using different threshold values is performed when the order increases and decreases, the order switching is performed stably.
By reducing the number of levels of the signal S30 by controlling the order of such ΔΣ modulation, it is possible to simplify the configuration of the digital-to-analog converter 50 at the subsequent stage and to suppress a decrease in the output signal level.
The above is the description of the modulation unit 21.

Returning to FIG.
The first detector 22 detects that lower data having a predetermined bit length in the input signal (lower bit data DL) of the ΔΣ modulator 20 has become zero. For example, the first detection unit 22 detects that the lower 3 bits of the lower bit data DL are zero.

  The second detection unit 23 determines that the lower-order data having a predetermined bit length in the error signal indicating the quantization error of the ΔΣ modulator 20 (the error digital signal Eq1 indicating the quantization error of the first-stage modulation circuit DS1) has become zero. To detect. For example, the second detector 23 detects that the lower 3 bits of the error digital signal Eq1 are zero.

  In accordance with the detection results of the first detection unit 22 and the second detection unit 23, the dither addition unit 24 sets the lower data of the lower bit data DL to zero and the lower data of the error digital signal Eq1 to zero. In this case, the dither signal Si is added to the lower bit data DL input to the ΔΣ modulator 20. For example, the dither addition unit 24 replaces the lower 3 bits of data in the lower bit data DL with “111” that is the dither signal Si.

  In addition, the dither addition unit 24 has continuously generated a state where the lower data of the lower bit data DL becomes zero and the lower data of the error digital signal Eq1 becomes zero (the lower data zero state) a predetermined number of times. In this case, the dither signal Si is added to the lower bit data DL. That is, the dither signal Si is not added even if the “lower data zero state” occurs once. This makes it difficult to add unnecessary dither signal Si.

The dither addition unit 24 includes a counter 241 and a multiplexer 242 as shown in FIG.
The counter 241 counts the number of occurrences of a state in which the lower data of the lower bit data DL is zero and the lower data of the error digital signal Eq1 is zero (lower data zero state). When the lower data of the lower bit data DL becomes non-zero or the lower data of the error digital signal Eq1 becomes non-zero, the counter 241 initializes the count value.
When the count value of the counter 241 reaches a predetermined value, the multiplexer 242 replaces the lower bit data in the lower bit data DL with the dither signal Si.

  Here, the operation of the DA converter having the above-described configuration will be described focusing on the ΔΣ modulator 20.

  The input digital signal Sin is oversampled to a frequency higher than the original sampling frequency Fs by the upsampling unit 10 and converted to a signal S10 (third input signal) that has undergone a predetermined complementary process. The low-order data DL of the signal S10 is subjected to ΔΣ modulation in the ΔΣ modulator 20 and the modulation result signal S20 and high-order data DH of the signal S10 are added in the adder 30. The signal S30 indicating the addition result of the adder 30 is converted into an analog signal S50 by the digital-analog converter 50, and a high-frequency noise component is removed by the low-pass filter 60, whereby an analog signal including a component in a desired signal band is obtained. Signal Sout.

  When the lower data of the lower bit data DL becomes zero and the lower data of the error digital signal Eq1 becomes zero (lower data zero state), the counter 241 increments the count value. When the “zero state of the lower data” is interrupted, the count value of the counter 241 is initialized. When the counter 241 reaches a predetermined value due to successive occurrence of the “zero state of lower data”, the multiplexer 242 replaces the lower bit data in the lower bit data DL with the dither signal Si. When the dither signal Si is added to the lower bit data DL, the lower data of the error digital signal Eq1 becomes non-zero, so that the count value of the counter 241 is initialized.

Assuming that the “lower data zero state” continues without the addition of the dither signal Si, the error digital signal Eq1 that is the addition result of the modulation adder 216 of the modulation circuit DS1 is always lower in which the lower data is zero. Since it is added to the bit side data DL, the error digital signal Eq1 is always in a state where the lower data is zero. As a result, the bit change of the error digital signal Eq1 is only the upper data, and a regular overflow occurs in a short cycle. That is, the output digital signal C1 changes regularly in a short cycle. If the “zero state of the lower data” continues further, the lower data of the error digital signal Eq1 of the modulation circuit DS1 becomes zero, and the output digital signals C2 to C4 regularly change in a short cycle. As a result, the output signal S20 of the ΔΣ modulator 20 that is the addition result of the output digital signals C1 to C4 changes regularly in a short cycle, and a strong noise component having a specific frequency is superimposed on the output signal S20. The
When the dither signal Si is input to the ΔΣ modulator 20 even once, the lower data of the error digital signal Eq1 immediately becomes non-zero, and regular overflow of the modulation adder 216 is avoided. Therefore, even if the low-order data zero state of the low-order bit side data DL continues at this time, the low-order data of the error digital signal Eq1 becomes non-zero for a while, and regular overflow of the modulation adder 216 occurs. No longer occurs. Therefore, regular changes in the short period of the output signal S20 are less likely to occur, and noise is reduced.

FIG. 5 is a diagram illustrating a simulation example for explaining the effect of adding the dither signal Si to the input signal of the ΔΣ modulator 20.
FIG. 5 is a diagram illustrating a simulation waveform of the output signal S30 of the ΔΣ modulator 20 in a state where the “zero state of the lower data” continues. FIG. 5A shows a waveform when the dither signal Si is not added, and FIG. 5B shows a waveform when the dither signal Si is added. Although a regular noise component appears strongly in the waveform of FIG. 5A, it can be seen that such a noise component does not appear in the waveform of FIG. 5B.

  FIG. 6 is a diagram showing a frequency spectrum of the waveform shown in FIG. 6A shows the frequency spectrum of the waveform of FIG. 5A, and FIG. 6B shows the frequency spectrum of the waveform of FIG. 5B. When the dither signal Si is not added (FIG. 6A), a strong noise component appears at a specific frequency. When the dither signal Si is added (FIG. 6B), the noise component is biased and dispersed toward the high frequency side, and the effect of noise shaping by ΔΣ modulation appears.

  FIG. 7 is a diagram showing a frequency spectrum when a low-pass filter is applied to the signal having the waveform shown in FIG. 7A shows a frequency spectrum corresponding to FIG. 5A, and FIG. 7B shows a frequency spectrum corresponding to FIG. 5B. 7A and 7B, the SN ratio when the dither signal Si is not added is calculated as 82.4 dB, and the SN ratio when the dither signal Si is added is calculated as 93.5 dB. It can be seen that the SN ratio can be improved by adding the dither signal Si.

  As described above, according to the ΔΣ modulator 20 according to the present embodiment, the lower data of the input signal (lower bit side data DL) of the ΔΣ modulator 20 becomes zero, and the lower data of the error digital signal Eq1. Is zero, the dither signal Si is added to the input signal (lower bit data DL) of the ΔΣ modulator 20. Thereby, since the periodic change of the output signal S20 of the ΔΣ modulator 20 is disturbed, it is possible to make it difficult to superimpose a noise component of a specific frequency on the output signal S20 of the ΔΣ modulator 20.

  Further, according to the ΔΣ modulator 20 according to the present embodiment, the lower data of the input signal (lower bit side data DL) of the ΔΣ modulator 20 becomes zero, and the lower data of the error digital signal Eq1 becomes zero. When the “lower data zero state” occurs continuously a predetermined number of times, the dither signal Si is added to the input signal (lower bit data DL). As a result, the dither signal Si is not added every time a single occurrence of the “zero state of the lower data” occurs. Therefore, the error of the output signal S20 is increased due to frequent addition of the dither signal Si. Can be prevented.

  In addition, this invention is not limited to embodiment mentioned above, The other various variation is included.

  In the embodiment described above, the dither addition unit 24 adds the dither signal Si to the input signal (lower bit side data DL) of the ΔΣ modulator 20, but the present invention is not limited to this. In another embodiment of the present invention, the dither signal Si may be added to an error signal (for example, error digital signal Eq1) indicating a quantization error in the ΔΣ modulator 20. FIG. 8 shows a modification in which the dither signal Si of the dither addition unit 24 is added to the error digital signal Eq1 input to the delay circuit 217 in the modulation circuit DS1 of the modulation unit 21. In addition to this modification, for example, the dither signal Si of the dither addition unit 24 may be added to the error digital signal Eq1 output from the delay circuit 217.

  In the above-described embodiment, the ΔΣ modulator used in the DA converter is taken as an example. However, the ΔΣ modulator of the present invention is not limited to the DA converter, and the signal processing using the ΔΣ modulation is performed. It can be widely applied to various circuit devices that perform the above.

DESCRIPTION OF SYMBOLS 10 ... Upsampling part, 20 ... (DELTA) (Sigma) modulator, 21 ... Modulation part, 211-213 ... Differentiator, 214 ... Output composition adder, 215 ... Input level detector, 216 ... Modulation adder, 217 ... Delay circuit , 22 ... 1st detection part, 23 ... 2nd detection part, 24 ... Dither addition part, 241 ... Counter, 242 ... Multiplexer, 30 ... Adder, 50 ... Digital-analog conversion part, 60 ... Low-pass filter, DS1-DS4 ... Modulation circuit, Si ... Dither signal DH ... Upper bit side data, DL ... Lower bit side data, Eq1 to Eq3 ... Error digital signal, C1 to C4 ... Output digital signal.

Claims (7)

A modulation unit that generates the output signal according to a result obtained by integrating and quantizing a difference between the input signal and the output signal of the digital value, and generating a digital value error signal indicating a quantization error in the quantization; ,
A first detection unit for detecting that low-order data of a predetermined bit length in the input signal has become zero;
A second detector for detecting that lower data of a predetermined bit length in the error signal has become zero;
When the lower data of the input signal becomes zero and the lower data of the error signal becomes zero according to the detection results of the first detection unit and the second detection unit, the input signal or A delta-sigma modulator comprising: a dither adding unit that adds a dither signal to the error signal. The dither addition unit adds the input signal or the error signal when the low-order data of the input signal becomes zero and the low-order data of the error signal continuously occurs a predetermined number of times. The delta-sigma modulator according to claim 1, wherein a dither signal is added. The dither addition unit is
Count the number of occurrences of the state where the lower data of the input signal becomes zero and the lower data of the error signal becomes zero, and the lower data of the input signal becomes non-zero, or A counter that initializes a count value when the lower data of the error signal becomes non-zero;
3. The delta sigma according to claim 2, further comprising: a multiplexer that replaces lower bit data in the input signal or the error signal with a predetermined dither signal when a count value of the counter reaches a predetermined value. Modulator. The modulator is
A delay circuit that delays and outputs a signal for each sampling period;
A modulation adder that adds the signal delayed in the delay circuit and the input signal, inputs the addition result to the delay circuit, and generates the 1-bit output signal indicating overflow of the addition result And
The delta-sigma modulator according to any one of claims 1 to 3, wherein the error signal is a signal resulting from addition of the modulation adder that is input or output in the delay circuit. The modulator is
A plurality of modulation circuits that generate the output digital signal corresponding to the result of integrating and quantizing the difference between the input digital signal and the output digital signal, and generating an error digital signal indicating a quantization error in the quantization A plurality of modulation circuits connected in cascade so that the input signal is input to the first stage and the error digital signal generated by the previous stage is input to each stage after the second stage;
A differentiator for differentiating each of the output digital signals of the modulation circuit after the second stage by an order corresponding to the number of stages from the first stage;
An output synthesis adder that calculates a sum of the output digital signal of the modulation circuit in the first stage, and the output digital signal of the modulation circuit in the second and subsequent stages differentiated by the differentiator;
The delta-sigma modulator according to any one of claims 1 to 3, wherein the error signal is the error digital signal generated in the modulation circuit in the first stage. An upsampling unit for converting a digital signal input at a first sampling frequency into a digital signal having a second sampling frequency higher than the first sampling frequency;
A delta-sigma modulator that applies delta-sigma modulation to the digital signal whose sampling frequency is converted in the upsampling unit;
A digital-to-analog converter that generates an analog signal according to the output signal of the delta-sigma modulator;
A low-pass filter that removes a high-frequency component contained in an analog signal output from the digital-analog converter,
The delta-sigma modulator is the delta-sigma modulator according to any one of claims 1 to 5. The delta sigma modulator performs delta sigma modulation on lower bit data in the digital signal whose sampling frequency is converted in the upsampling unit,
An adder that adds the output signal of the delta-sigma modulator and the data on the upper bit side of the digital signal whose sampling frequency is converted in the upsampling unit;
The digital-to-analog converter according to claim 6, wherein the digital-to-analog converter converts a digital signal resulting from the addition by the adder into an analog signal.