JP6381019B2 - Information processing apparatus and control method - Google Patents

Description

  The present invention relates to an information processing apparatus and a control method.

  Improvement of calculation performance in an information processing apparatus has been a problem for many years. As a method for improving the computation performance, parallel operation with an increased number of computing units or a method of shortening a computation turnaround time (hereinafter referred to as computation TAT), which is a time from computation register read to computation register write, is adopted. Has been. However, when there is a difference in the calculation TAT depending on the calculation type, there is a problem that the calculation performance may not be exhibited.

  For example, in an arithmetic unit having arithmetic units having different arithmetic TATs, output of results from different arithmetic units is performed at the same timing depending on the input timing of arithmetic instructions to each arithmetic unit and the arithmetic TAT of each arithmetic unit. There is a possibility of conflict. In order to avoid this, if the output timing of the result conflicts from the operation TAT of each operation unit, the input timing of the subsequent operation instruction is delayed. For example, when operation instructions for writing to a certain operation register are consecutive, writing by a subsequent operation instruction must be performed after writing by the preceding operation instruction is completed. In such a situation, when the operation TAT of the subsequent operation instruction is smaller than the operation TAT of the preceding operation instruction, the subsequent operation instruction must be input after waiting for the progress of the preceding operation processing. As a result, the subsequent input of operation instructions is also sequentially delayed, leading to performance degradation.

  To deal with this problem, for example, in Patent Document 1, in a plurality of arithmetic units having different arithmetic TATs, an arithmetic unit having a small arithmetic TAT is added with a register for simply transferring the result at the subsequent stage to adjust the arithmetic TAT. A technique capable of advancing the input timing of subsequent operation instructions is disclosed.

Japanese Patent No. 2503983

  Further, for example, when an operation instruction a that writes to a certain operation register A and an operation instruction b that uses a value written to the operation register A by the operation instruction a are consecutive, the subsequent operation instruction b Must be executed at a timing such that the operation instruction b can read the value stored in the operation register A after the operation instruction a writes the value in the operation register A. The technique disclosed in Patent Document 1 has disclosed a technique for speeding up processing while preventing contention of output timing between arithmetic instructions having different arithmetic TATs. Dependencies were not considered.

  Accordingly, an object of the present invention is to provide an information processing apparatus and a control method that can solve the above-described problems.

The present invention, when a plurality of arithmetic registers, a plurality of arithmetic units, and the issuing of an arithmetic instruction are determined, represents a period used for execution of the arithmetic instruction for the arithmetic register and the arithmetic unit related to the arithmetic instruction. A busy period information management unit that sets busy period information and subtracts the busy period information according to the progress of the operation instruction determined to be issued, and an operation that is the time required to execute the busy period information and a subsequent operation instruction Based on TAT (TURN AROUND TIME), a check unit that determines the issue timing of the subsequent operation instruction that can secure an operation result when the subsequent operation instruction is sequentially executed, and the subsequent determined by the issue A determination unit that determines an operation TAT of the operation instruction according to an operation unit related to the subsequent operation instruction, and an operation TAT determined by the determination unit Based on a control unit for adjusting the timing of storing the operation result of said succeeding operation instruction issued is determined in the arithmetic register, Bei example, said checking unit, for calculating TAT of the subsequent operation instruction, the The time required for securing the operation result of the preceding operation instruction when the subsequent operation instruction is issued at a timing earlier than the issue timing of the subsequent operation instruction based on the predetermined operation TAT defined for the operation instruction Is determined as the operation TAT of the subsequent operation instruction .

In addition, in the information processing apparatus having a plurality of arithmetic registers and a plurality of arithmetic units, the present invention may execute execution of the arithmetic instruction for the arithmetic registers and arithmetic units related to the arithmetic instruction when the issuance of the arithmetic instruction is determined. This is the time required to execute busy instruction information and the subsequent operation instruction by setting busy period information indicating a period to be used for the operation, subtracting the busy period information in accordance with the progress of the operation instruction determined to be issued. Based on the operation TAT, the issue timing of the subsequent operation instruction that can secure the operation result when the subsequent operation instruction is sequentially executed is determined, and the operation TAT of the subsequent operation instruction determined to be issued is determined. , determined according to the arithmetic unit relating to the subsequent operation instruction, based on the calculated TAT which the determined, before the calculation result of the subsequent operation instructions issued decides And adjusting the timing to be stored in the arithmetic register, when determining the issuance timing, for calculating TAT of the subsequent operation instructions, issue timings of the subsequent operation instruction based on a predetermined calculation TAT defined for the arithmetic instruction Determining the issuance timing when the subsequent calculation instruction is issued at an earlier timing, with the time required for securing the calculation result of the preceding calculation instruction as the calculation TAT of the subsequent calculation instruction ; This is a characteristic control method.

  According to the present invention, it is possible to improve the performance of the information processing device while ensuring the consistency of the arithmetic registers.

It is a 1st figure which shows the specific structure of the information processing apparatus by 1st embodiment of this invention. It is a 2nd figure which shows the specific structure of the information processing apparatus by 1st embodiment of this invention. It is a 1st figure which shows the time chart of the arithmetic processing by the related information processing apparatus. It is a 2nd figure which shows the time chart of the arithmetic processing by the related information processing apparatus. It is a 1st figure which shows the time chart of the information processing apparatus by 1st embodiment of this invention. It is a 3rd figure which shows the time chart of the arithmetic processing by the related information processing apparatus. It is a 4th figure which shows the time chart of the arithmetic processing by the related information processing apparatus. It is a 2nd figure which shows the time chart of the information processing apparatus by 1st embodiment of this invention. It is a 3rd figure which shows the time chart of the information processing apparatus by 1st embodiment of this invention. It is a 4th figure which shows the time chart of the information processing apparatus by 1st embodiment of this invention. It is a 5th figure which shows the time chart of the information processing apparatus by 1st embodiment of this invention. It is a figure which shows the specific structure of the information processing apparatus by 2nd embodiment of this invention. It is a figure which shows the time chart of the information processing apparatus by 2nd embodiment of this invention. It is a figure which shows the specific structure of the information processing apparatus by 3rd embodiment of this invention.

<First embodiment>
Hereinafter, an information processing apparatus according to an embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a first diagram showing a specific configuration of the information processing apparatus according to the first embodiment. FIG. 1 is a schematic block diagram of a processor of the information processing apparatus.
In this figure, reference numeral 20 represents an arithmetic pipe control unit. The calculation pipe control unit 20 decodes the instruction sequence read from the memory, instructs the calculation resources such as calculation registers and calculators at appropriate timing, and executes the read instruction sequence.

Reference numerals 100, 101, 102, and 103 denote operation registers V0, V1, V2, and V3. The calculation pipe control unit 20 reads or writes data continuously for the vector length (hereinafter referred to as VL) specified for the calculation register. Usually, a plurality of vector pipes are used in parallel to calculate the vector length, but in this embodiment, there is one vector pipe. Accordingly, when one vector instruction is issued, the arithmetic pipe control unit 20 continuously processes the vector instruction for the vector length.
Note that the arithmetic register V0 in FIG. 1 has four elements V0-0, 1, 2, and 3 and can handle an operation with a vector length of 4.

Reference numerals 110, 111, 112, and 113 are operand selectors connected to the input side of each arithmetic unit. Operand selectors 110-113 are connected to arithmetic registers 100-103. Then, the output from the arithmetic register instructed by the arithmetic pipe control unit 20 is selected and output to the arithmetic unit.
Reference numeral 120 denotes a product-sum operation unit, which executes a product-sum operation for the vector length in accordance with an instruction from the operation pipe control unit 20. The product-sum calculator 120 outputs the calculation result to the crossbar 106 via the transmission path 900.
Reference numeral 130 denotes a logical operation unit, which executes a logical operation for a vector length in accordance with an instruction from the operation pipe control unit 20. The logical operator 130 outputs the operation result to the timing adjustment register 131 and the selector 133.
Reference numerals 131 and 132 are timing adjustment registers. When the timing adjustment register 131 acquires the calculation result of the logical operation unit 130, the timing adjustment register 131 outputs it to the timing adjustment register 132 after one clock. When the timing adjustment register 132 acquires the calculation result, it outputs it to the selector 133 after one clock. The selector 133 selects the outputs of the logic operation unit 130 and the timing adjustment registers 131 and 132 in accordance with instructions from the operation pipe control unit 20 and outputs them to the crossbar 106 via the transmission line 900.

FIG. 2 is a second diagram showing a specific configuration of the information processing apparatus according to the first embodiment. FIG. 2 is a diagram showing the operation pipe control unit 20 in FIG. 1 in more detail.
Reference numeral 201 denotes a buffer unit that stores an instruction sequence read from a memory by the instruction buffer unit.
Reference numeral 202 decodes an instruction read from the instruction buffer unit 201 by the instruction decoder and outputs the decoded instruction to the instruction issue queue 203.

  Reference numeral 203 denotes an instruction issue queue that stores instructions decoded by the instruction decoder 202. The instruction determined to be issued is deleted from the instruction issue queue 203, and the instruction issue queue 203 acquires a new instruction from the instruction decoder 202. Note that some information processing devices can issue multiple instructions in the issue queue. However, in this specification, the instruction placement method and contention arbitration method in the issue queue are not considered, and instructions are stored in the queue. It is assumed that they are issued one by one in the order in which they are made.

  Reference numeral 204 denotes a W → W issuance check unit. W → W (“Write → Write”) indicates a relationship in which write processing is continuously performed on the same arithmetic register. The W → W issuance check unit 204 receives the instruction information in the instruction issuance queue 203 and the busy value of the W → W busy information management unit 210, which will be described later, and can ensure consistency in the relationship of W → W for each instruction. The instruction issue check unit 208 is notified that an instruction can be issued. The phrase “consistency can be ensured” means that the same result can be obtained as when consecutive arithmetic instructions having a relationship of W → W are sequentially executed in this order. In particular, the W → W issuance check unit 204, when the instruction is an instruction using the logical operation unit 130, performs an operation TAT (TURN AROUND TIME) of the product-sum operation unit 120 and a W → W busy information management unit described later. The busy value of 210 is compared, and if the consistency can be ensured, the busy value received from the W → W busy information management unit 210 is sent to the TAT determination unit 207. The busy value is a value used to manage the usage status of each arithmetic register and arithmetic unit. When the busy value is other than 0, it indicates that the corresponding operation register or the like is being used, and this value is a counter and is subtracted in accordance with the progress of the operation instruction. The operation TAT is the time from operation register reading to operation register storage when an operation is performed using a certain arithmetic unit.

  Reference numeral 205 denotes an R → W issuance check unit. R → W (“Read → Write”) indicates a relationship in which read processing and write processing are continuously performed on the same arithmetic register. When the R → W issuance check unit 205 receives the instruction information in the instruction issuance queue 203 and the busy value of the R → W busy information management unit 220 (to be described later), the consistency of the R → W relationship can be ensured for each instruction. The instruction issue check unit 208 is notified that an instruction can be issued. In particular, the R → W issuance check unit 205 compares the operation TAT of the product-sum operation unit 120 with the information of the R → W busy information management unit 220 when the instruction is an instruction using the logical operation unit 130. If consistency can be ensured, the busy value received from the R → W busy information management unit 220 is sent to the TAT determination unit 207.

  Reference numeral 206 denotes a busy check unit. The busy check unit 206 receives the information of the instruction issue queue 203, the W → R busy information management unit 230, and the arithmetic unit busy information management unit 240, and confirms the relationship of W → R and the busy state of the arithmetic unit for each instruction. When the consistency can be ensured, the instruction issue check unit 208 is notified that the instruction can be issued. Note that W → R (“Write → Read”) indicates a relationship in which write processing and read processing are continuously performed on the same arithmetic register.

  Reference numeral 207 denotes a TAT determination unit. The TAT determination unit 207 outputs the instruction's original operation TAT in the case of an instruction using something other than the logical operator 130, and the W → W issue check unit 204 and the R → W issue in the case of using the logical operator 130. The output value of the check unit 205 is compared, and a large value is output.

  Reference numeral 208 denotes an instruction issuance check unit, which indicates that a valid instruction exists in the instruction issuance queue 203 and that instructions can be issued from all of the W → W issuance check unit 204, the R → W issuance check unit 205, and the busy check unit 206. Instruction issue decision 203, instruction issue confirmation information register 270, W → W busy information generation unit 260, R → W busy information generation unit 261, W → R busy information generation unit 262, arithmetic unit The busy information generation unit 263 is notified.

  Reference numeral 210 denotes a W → W busy information management unit. The W → W busy information management unit 210 has a function of managing busy information for assuring data consistency between W → W instructions of the operation register. W → W busy information management units 211 to 214 corresponding to the arithmetic registers V0 to V3 are provided.

  Reference numeral 220 denotes an R → W busy information management unit. The R → W busy information management unit 220 has a function of managing a busy value for guaranteeing data consistency between R → W instructions of the arithmetic register. R → W busy information management units 221 to 224 corresponding to the arithmetic registers V0 to V3 are provided.

  Reference numeral 230 denotes a W → R busy information management unit. The W → R busy information management unit 230 has a function of managing a busy value for guaranteeing data consistency between instructions of W → R in the operation register. W → R busy information management units 231 to 234 corresponding to the arithmetic registers V0 to V3 are provided.

  Reference numeral 240 denotes an arithmetic unit busy information management unit. The arithmetic unit busy information management unit 240 has a function of managing the busy value of the arithmetic unit. Operation unit busy information management units 241 to 242 corresponding to the product-sum operation unit 120 and the logic operation unit 130 are provided.

  Reference numeral 260 denotes a W → W busy information generation unit. The W → W busy information generation unit 260 acquires signals from the instruction issuance queue 203, the TAT determination unit 207, and the instruction issuance check unit 208, and has received notification of the issuance of the instruction for writing to the arithmetic registers V0 to V3. In this case, write destination calculation register information and calculation TAT information are sent to the W → W busy information management unit 210.

  Reference numeral 261 denotes an R → W busy information generation unit. The R → W busy information generation unit 261 obtains signals from the instruction issue queue 203, the TAT determination unit 207, and the instruction issue check unit 208, and has received notification of issuance of instructions to be read from the arithmetic registers V0 to V3. In this case, the read destination calculation register information and the read pattern information are sent to the R → W busy information management unit 220. The read pattern information includes, for example, “read one element in one cycle”, “read all elements in one cycle”, “read one element every several cycles”, and the like.

  Reference numeral 262 denotes a W → R busy information generation unit. The W → R busy information generation unit 262 obtains signals from the instruction issue queue 203, the TAT determination unit 207, and the instruction issue check unit 208, and has received notification of the issuance of instructions to be written to the arithmetic registers V0 to V3. In this case, write destination calculation register information and calculation TAT information are sent to the W → R busy information management unit 230.

  Reference numeral 263 denotes an arithmetic unit busy information generation unit that obtains signals from the instruction issue queue 203, the TAT determination unit 207, and the instruction issue check unit 208, and is used when notification of the issue of an instruction using the arithmetic unit is received. The information indicating the arithmetic unit to perform and the information indicating VL are sent to the arithmetic unit busy information management unit 240.

Reference numeral 270 denotes an instruction issuance confirmation information register which receives an instruction issuance decision notification from the instruction issuance check unit 208 and holds it for one cycle.
Reference numeral 271 denotes an issue fixed instruction information register which receives information on an instruction determined to be issued from the instruction issue queue 203 and holds it for one cycle.
Reference numeral 272 denotes an issue confirmation TAT information register which receives TAT information from the TAT determination unit 207 and holds it for 1T.

Reference numerals 273 to 278 denote control timing adjustment registers, which control the arithmetic resources shown in FIG. 1 in accordance with the timing of data flow.
Reference numerals 282 to 287 denote decoders, which have a function of transmitting operation instructions by decoding necessary portions of the issued and confirmed instructions to the respective functional units in FIG. In particular, the decoders 285 to 287 have a function of comparing the instruction's original shortest TAT with the TAT information determined in 207 and issuing a register storage instruction based on the difference value. For example, the decoder 285 has a function of issuing a register storage instruction by identifying that it is the timing to store in the register if the difference value is zero. Similarly, when the difference value is 1, the decoder 286 issues a register storage instruction, and when the difference value is 2, the decoder 287 issues a register storage instruction.

Hereinafter, an operation of the information processing apparatus and the information processing apparatus according to the present embodiment related to some instruction sequences will be described.
It is assumed that the VADD instruction and the VMPY instruction are executed by the product-sum operation unit 120, and the operation TAT is 5 cycles. Further, it is assumed that the VAND instruction is executed by the logical operation unit 130 and the operation TAT is 3 cycles.

FIG. 3 is a first diagram illustrating a time chart of arithmetic processing by the related information processing apparatus.
The operation of the information processing apparatus related to the following instruction sequences “I1” and “I2” will be described with reference to FIG.
Command “I1” VAND V3 ← V0 & V1 VL = 2
Command “I2” VMPY V0 ← V2 × V3 VL = 2
The instruction “I1” indicates that the logical operation unit 130 inputs the values of the operation registers V0 and V1, calculates a logical product, and stores the result in the operation register V3. The instruction “I2” indicates that the product-sum operation unit 120 inputs the values of the operation registers V2 and V3, multiplies these values, and stores the operation result in the operation register V0.
A feature of the relationship between the instructions “I1” and “I2” is that the operation register V3 has a write → read relationship. Here, the relation of Write → Read with respect to the arithmetic register V3 means that the Read must not be completed before the Write process for the arithmetic register V3 is completed.
The related information processing apparatus does not include the timing adjustment registers 131 and 132 and the selector 133 in FIG. In FIG. 3, “L−x” (x = 0, 1) indicates the output value of the logical operation unit 130, and “Mx” (x = 0, 1) indicates the product-sum operation unit 120. The output value is shown.

  First, the issue of the instruction “I1” is determined at clock 1 (“Dispatch” in FIG. 3). Then, data is read from the arithmetic registers V0 and V1 at clocks 2 to 3. Further, the operand selectors 112 and 113 output the data of the operation registers V0 and V1 to the logical operation unit 130 in response to a control signal from the operation pipe control unit 20. Here, the reason why these processes are continuously performed over two cycles of clocks 2 to 3 is that VL = 2. The logical operation unit 130 performs an operation at clocks 3 to 4 (“operation stage 1” in FIG. 3), and the logical operation unit 130 outputs an operation result to the crossbar 106 at clocks 4 to 5. Further, an operation pipe control unit. The operation result is stored in the operation register V3 by the control signal from 20. The first data of the instruction “I1” is determined at clock 5, and the second data of the instruction “I1” is determined at clock 6.

  The operation is similarly performed for the instruction “I2”. In general arithmetic pipeline control, the subsequent instruction “I2” is not read from the arithmetic register V3 by the instruction “I2” before the write processing to the arithmetic register V3 is completed by the instruction “I1”. The issue of an instruction is determined at clock 4. When the issue of the instruction “I2” is determined at the clock 4, the operation result of the instruction “I1” is stored in the operation register V3 (“V3 register” of the clock 5 in FIG. 3), and is read out by the instruction “I2”. ("V3 register ReadData" of clock 5 in FIG. 3) operation. That the instruction operates at the fastest speed is called chaining. Since the VMPY instruction of the instruction “I2” uses the product-sum operation unit 120, the operation TAT is 5 cycles. Therefore, it takes 5 cycles from operation register read to operation register write. Therefore, the clock 10 determines the first value in the V0 register.

FIG. 4 is a second diagram illustrating a time chart of the arithmetic processing by the related information processing apparatus.
The problem of the arithmetic processing by the related information processing apparatus will be described with reference to FIG. In FIG. 4, the operation of the information processing apparatus related to the following instruction sequence will be described.
Command “I0” VADD * V3 ← V0 + V1 VL = 2
Command “I1” VAND * V3 ← V0 & V1 VL = 2
Command “I2” VMPY V0 ← V1 × V2 VL = 2
The instruction “I0” indicates that the product-sum operation unit 120 inputs the values of the operation registers V0 and V1, adds these values, and stores the operation result in the operation register V3. The instruction “I1” indicates that the logical operation unit 130 inputs the values of the operation registers V0 and V1, calculates a logical product, and stores the result in the operation register V3. The instruction “I2” indicates that the product-sum operation unit 120 inputs the values of the operation registers V1 and V2, multiplies these values, and stores the operation result in the operation register V0.
A characteristic of the relationship between the instructions “I0” and “I1” is that the relation “Write → Write” is set for the arithmetic register V3. This means that the instruction “I0” is completed before the write processing in the instruction “I0” is completed for the arithmetic register V3. This means that the write processing in the process must not be completed.
A feature of the relationship between the instructions “I1” and “I2” is that the operation register V0 has a relationship of Read → Write. This means that the write process in the instruction “I2” must not be completed before the read process in the instruction “I1” is completed for the arithmetic register V0.

Therefore, after the instruction “I0” is determined to be issued at the clock 1, the instruction “I1” is generally not written to the arithmetic register V3 before the writing process to the arithmetic register V3 is completed by the instruction “I0”. In general arithmetic pipeline control, the decision to issue the subsequent instruction “I1” is clock 4. The issue determination of the instruction “I1” is delayed by two cycles from “I0” because the operation TAT (= 5) of the product-sum operation unit 120 used in “I0” and the operation TAT of the logical operation unit 130 used in “I1” ( This is because the difference of = 3) is two cycles.
Therefore, the instruction “I1” is always issued to determine whether to issue the instruction “I2” so that the instructions “I1” and “I2” are not written before the operation register V0 is read. Must be later. Accordingly, the issue of the instruction “I2” is determined at the clock 5, and the writing of the last data “M−1” to the arithmetic register V0 by this instruction is completed and the value is determined at the clock 12. As described above, in a general operation, consistency between operation registers is ensured by delaying the timing of the subsequent operation instruction. For this reason, there has been a problem that the input timing is delayed one after another for the operation instructions scheduled later.

FIG. 5 is a first diagram illustrating a time chart of the information processing apparatus according to the present embodiment.
The operation in this embodiment will be described with reference to FIG. In the present embodiment, the calculation TAT for each computing unit is variable in 5 cycles for the product-sum computing unit 120 and 3 to 5 cycles for the logical computing unit 130. The instruction sequence described in FIG. 5 is the same as that in FIG.
In this embodiment, when the write operation register V3 of the subsequent operation instruction is in a write-to-write relationship as in this instruction sequence, the operation pipe control unit 20 sets the operation instruction preceding the operation TAT of the subsequent operation instruction. Operate according to the operation TAT. In the example of FIG. 5, the operation TAT of the VAND instruction of the instruction “I1” following the instruction “I0” is set to 5 cycles. In this way, by adjusting the operation TAT to the longer one, it is possible to prevent contention of the write timing to the V3 register if the subsequent instruction is input with a delay of one cycle. In the case of FIG. 5, after the issue of the instruction “I0” is determined at the clock 1, the issue of the instruction “I1” can be determined at the clock 2. Further, the issue of the instruction “I2” can be determined by the clock 3, and it is the clock 10 that completes the writing to the arithmetic register V0 and determines the value.
As described above, according to the information processing apparatus of this embodiment, the operation of the instruction sequence can be completed two cycles earlier than the method of FIG.
The operation for determining the calculation TAT according to the present embodiment will be described later with reference to FIG.

FIG. 6 is a third diagram illustrating a time chart of the arithmetic processing by the related information processing apparatus.
The busy management operation inside the arithmetic pipe control unit 20 will be described with reference to FIGS. The following instruction sequence used in FIG. 3 is used for the description.
Command “I1” VAND V3 ← V0 & V1 VL = 2
Command “I2” VMPY V0 ← V2 × V3 VL = 2
In busy management, when issuing an instruction, it is possible to determine whether the operation register or arithmetic unit used in the instruction is in use by executing the preceding instruction, and how many cycles it is not in use, and issue the instruction. This is done to adjust the timing. In this specification, a method of performing busy management using a counter will be described, but the present invention is not limited to this. For example, a method of holding a sign in a register may be used. In this embodiment, the busy management by the counter is performed by the W → W busy information management units 211 to 214, the R → W busy information management units 221 to 224, the W → R busy information management units 231 to 234, and the arithmetic unit busy information management. Parts 241 to 242. Assume that the initial values of the counters of these management units are zero.

First, when the issue of the instruction “I1” is determined at clock 1, the VAND instruction operation TAT (= 3) is set in the W → W busy information management unit 214 and the W → R busy information management unit 234 at clock 2. The computing unit busy information management unit 242 is set to 2 which is the computing unit usage time of the instruction “I1”. The operation unit use time is 2 because the operation stage is once (“130 operation stage 1”) and the operation data is VL = 2 in the logic operation unit 130. The busy information management unit in which these values are set indicates that the corresponding arithmetic register or arithmetic unit is busy. Each time one clock elapses, each value is decremented by one. Hereinafter, values held by the busy information management units 211 to 214, 221 to 224, 231 to 234, and 241 to 242 are referred to as busy values. The busy value is a counter for performing busy management.
Subsequent instruction “I2” confirms the busy state of the related arithmetic register, and determines the issue if the issue condition is satisfied. Specifically, since the instruction “I2” is “V0 ← V2 × V3”, the busy status of the W → R busy information management units 233 and 234 is confirmed for the arithmetic registers V2 and V3 that perform the read. For the operation register V0 that performs Write, the busy status of the W → W busy information management unit 211 and the R → W busy information management unit 221 is confirmed. Since the product-sum calculator 120 is used, the busy status of the calculator busy information management unit 241 is confirmed.

  First, the busy status of the clock 2 is confirmed. As for the W → R busy information management unit 233, since no value is set after the preceding instruction “I1”, the counter value indicating the busy state is 0 as an initial value. This indicates that there is no problem in issuing the instruction “I2” for the operation register V2 that performs the read. In addition, regarding the operation register V0 that performs Write, the W → W busy information management unit 211 and the R → W busy information management unit 221 are similarly not busy because the counter value indicating the busy state is 0. In addition, the counter value indicating the busy state is also 0 for the arithmetic unit busy information management unit 241. Next, when the operation register V3 is confirmed, the value of the W → R busy information management unit 234 is 3 in the clock 2. This indicates that the instruction “I2” cannot be issued because the arithmetic register V3 is busy.

  Here, the W → W busy information management units 211 to 214 output a busy value to the W → W issue check unit 204 every clock. Similarly, the R → W busy information management units 221 to 224 are busy with the R → W issue check unit 205, the W → W busy information management units 231 to 234, and the computing unit busy information management units 241 to 242 are busy with the busy check unit 206. Output the value. Each check unit 204, 205, 206 determines whether to issue a subsequent command based on the acquired busy value. The determination method is based on whether or not all the busy values of the computation resources that are the objects of management are 1 or less. Each of the check units 204, 205, and 206 outputs “1” to the instruction issue check unit 208 if all busy values are 1 or less, and “0” otherwise. The instruction issuance check unit 208 determines that an instruction can be issued if all of the acquired values are “1”.

In clocks 2 and 3 in FIG. 6, the output values of the W → W issue check unit 204 and the R → W issue check unit 205 are 1, but the output value of the busy check unit 206 is 0, so the instruction issue check unit 208 Cannot decide to issue subsequent instructions. The output value of the busy check unit 206 is 0 because the busy check unit 206 determines that the arithmetic register V3 is busy based on the busy value acquired from the W → R busy information management unit 234.
At clock 4, the busy value of the W → R busy information management unit 234 is 1. Therefore, the busy check unit 206 outputs “1” to the instruction issue check unit 208 by the above-described determination method. The command issuance check unit 208 determines that the command can be issued because all the values acquired from the check units 204 to 206 are “1”, and outputs “1” indicating that to the transmission path 999. Transmission of an instruction issue decision to this transmission line 999 is called “Dispatch”.
In this way, it is determined that the subsequent instruction “I2” is issued in the clock 4, and the read operation of the arithmetic register V3 starts from the clock 5. The last data by the preceding instruction “I1” is stored in the operation register V3 and is determined by the clock 5. The value of the operation register V3 is read immediately after the data is determined (chaining operation).

When the issue of the instruction “I2” is determined at the clock 4, the instruction “I2” uses the product-sum operation unit 120, so that the TAT determination unit 207 sets “5” which is the original operation TAT value of the instruction to W → W The data is output to the busy information generation unit 260. Then, the W → W busy information generation unit 260 outputs the value “5” of the operation TAT to the W → W busy information management unit 210 together with the write destination operation register number information “V0” of the instruction “I2”. Similarly, the W → R busy information generation unit 262 sends the operation TAT value “5” of the instruction “I2” to the W → R busy information management unit 230 together with the operation register information “V0” of the operation result storage destination. FIG. 6 shows that the value “5” is set in the W → W busy information management unit 211 and the W → R busy information management unit 231 at clock 5 and is subtracted every cycle.
The R → W busy information generation unit 261 is used when special reading is performed from the arithmetic register. The instruction sequence in FIG. 6 does not perform a special read and therefore does not have a significant value. However, the last data is read in the case of a store instruction that is read from the operation register at a cycle of four cycles due to the store path throughput. Management is performed so that subsequent instructions are not written before.

FIG. 7 is a fourth diagram illustrating a time chart of arithmetic processing by the related information processing apparatus.
The busy value and instruction issue determination by the related information processing apparatus will be described with reference to FIG. FIG. 7 is a diagram in which information such as the busy information management unit 210 and the check units 204 to 206 is added to FIG. In FIG. 7, as in FIG. 4, the operation will be described using the following instruction sequence as an example.
Command “I0” VADD * V3 ← V0 + V1 VL = 2
Command “I1” VAND * V3 ← V0 & V1 VL = 2
Command “I2” VMPY V0 ← V1 × V2 VL = 2
As described with reference to FIG. 4, the instruction “I1” must be written to the arithmetic register V3 after the instruction “I0” is written to the arithmetic register V3. Also, the instruction register “I2” must be written to the operation register V0 after the instruction “I1” is read. As in FIG. 6, “VADD” operation TAT “5” is set in the W → W busy information management unit 214 and the W → R busy information management unit 234 in the clock 2 after the issue of the instruction “I0” is determined. The Then, the busy value is subtracted every clock. Meanwhile, the R → W issuance check unit 205 outputs 1 indicating that an instruction can be issued to the instruction issuance check unit 208 because the busy values of the R → W busy information management unit 220 are all 0. The busy check unit 206 outputs 1 indicating that the instruction can be issued to the instruction issuance check unit 208 because the busy value of the logical operation unit 130 used in the subsequent instruction “I1” is 0. The W → W issuance check unit 204 pays attention to the busy value of the W → W busy information management unit 214 that is the busy value of the operation register V3 that writes “I1” among the busy values of the W → W busy information management unit 210. It is then determined whether an instruction can be issued. As shown in FIG. 7, the busy value of the W → W busy information management unit 214 is not 0 between the clocks 2 to 6. During this time, the W → W issuance check unit 204 determines whether the subsequent instruction can be issued using the following expression.
Busy value of W → W busy information management unit 214 − operation TAT value of VAND instruction ≦ 0
For example, in clock 2, the busy value of the W → W busy information management unit 214 is 5. The operation TAT value of the VAND instruction is 3. Therefore, clock 2 does not satisfy the above equation. Similarly, since “4-3 = 1” in clock 3, the above equation is not satisfied. At clock 4, “3-3 = 0”, which satisfies the above formula. The W → W issue check unit 204 outputs 1 indicating that an instruction can be issued in the clock 4 to the instruction issue check unit 208. The command issuance check unit 208 determines that the command can be issued because all the values acquired from the check units 204 to 206 are 1, outputs “1” indicating that to the transmission line 999, and outputs the command “I1 Is issued. In this way, the issue of the instruction “I1” is determined by the clock 4. Similarly, the issue of the instruction “I2” is determined by the clock 5 after the issue of the instruction “I1” is decided. The final data of the instruction “I2” is determined by the clock 12 as shown in FIG.

FIG. 8 is a second diagram showing a time chart of the information processing apparatus according to the first embodiment of the present invention.
The busy value and instruction issue determination according to the present embodiment will be described with reference to FIG. Also in FIG. 8, the same instruction sequence as in FIGS.
As in FIG. 7, “5” which is the operation TAT of “VADD” is set in the W → W busy information management unit 214 and the W → R busy information management unit 234 in the clock 2 after the issue of the instruction “I0” is determined. The R → W issuance check unit 205 and the busy check unit 206 output 1 indicating that the subsequent instruction can be issued to the instruction issuance check unit 208.
In this embodiment, the W → W issuance check unit 204 performs the following operation. First, the W → W issuance check unit 204 acquires information on the subsequent instruction (“VAND”) from the instruction issuance queue 203 and detects that the subsequent instruction uses the logical operation unit 130. Then, the W → W issuance check unit 204 determines to determine whether or not an instruction can be issued using the operation TAT value of the product-sum operation unit 120 having a large operation TAT value. The judgment formula is as follows.
Busy value of W → W busy information management unit 214 − operation TAT value of VADD instruction ≦ 0
7 is different from the determination formula of FIG. 7 in that the operation TAT value (= 5) of the VADD instruction is used instead of the operation TAT value (= 3) of the VAND instruction. As described above, in the present embodiment, when the instruction issue condition is determined by the W → W issuance check unit 204, the maximum value of the arithmetic TAT values of other arithmetic units is used instead of the arithmetic TAT value inherent to the arithmetic unit. The characteristic is that the judgment is performed. If the above equation is used, “5-5 = 0” in clock 2, which satisfies the above equation. Accordingly, at clock 2, the W → W issuance check unit 204 outputs “1” to the instruction issuance check unit 208. The instruction issuance check unit 208 determines whether the instruction “I1” can be issued, and determines the issuance of the instruction to the transmission path 999, the W → W busy information generation unit 260, the R → W busy information generation unit 261, and the W → R busy information. The data is output to the generation unit 262 and the arithmetic unit busy information generation unit 263. The W → W issuance check unit 204 outputs the busy value (“5” in clock 2) of the W → W busy information management unit 214 to the TAT determination unit 207. Then, the TAT determination unit 207 outputs the busy value to the W → W busy information generation unit 260, the W → R busy information generation unit 262, and the issue confirmation TAT information register 272. When the W → W busy information generation unit 260 and the W → R busy information generation unit 262 acquire information indicating instruction issue determination from the instruction issue check unit 208, the operation TAT value and instruction issue queue acquired from the TAT determination unit 207 are obtained. Information indicating the operation register V3 which is the write destination is output to the W → W busy information management unit 210 and the W → R busy information management unit 230, respectively, with the instruction “I1” issued from 203 determined to be issued. Similarly, the R → W busy information generation unit 261 outputs 0 to the R → W busy information management unit 220. Further, the arithmetic unit busy information generation unit 263 outputs information indicating the arithmetic unit (logical arithmetic unit 130) used in the instruction “I1” and VL information (= 2) to the arithmetic unit busy information management unit 240.

The W → W busy information management unit 210 and the W → R busy information management unit 230 set “5” in the W → W busy information management unit 214 and the W → R busy information management unit 234 based on the acquired information. The R → W busy information generation unit 220 sets “0” in the R → W busy information generation units 221 and 222. The computing unit busy information management unit 240 sets “2” in the computing unit busy information management unit 242. The values of the busy information management units 214, 221, 222, 234, and 242 in the clock 3 of FIG. 8 are set in this way. Thereafter, each busy value is decremented by 1 every clock.
It should be noted that the issue of the instruction “I2” is decided at clock 3, and the last data of the instruction “I2” is decided at clock 10 as shown in FIG.

The method for determining the busy management and the calculation TAT value in each functional unit of the calculation pipe control unit 20 has been described above. An operation for executing an instruction based on the calculated TAT value will be briefly described below.
When the instruction issuance is determined, the instruction issuance check unit 208 notifies the instruction issuance confirmation information register 270 of the instruction issuance determination. The instruction issue queue 203 outputs information on the instruction determined to be issued to the issue fixed instruction information register 271. The TAT determination unit 207 outputs the operation TAT value of the instruction determined to be issued to the issue fixed TAT information register 272.
For example, the instruction “I1” (VAND * V3 ← V0 & V1) will be described as an example. The decoder 282 acquires the instruction information from the issue fixed instruction information register 271 and sets the value from the operation registers V0 and V1 by VL = 2. An instruction to read continuously is given to the selectors 112 and 113. The control timing register 273 holds the instruction information for one clock and outputs it to the decoder 283. Next, the decoder 283 instructs the logical operator 130 to execute the arithmetic processing. The control timing register 274 holds instruction information for one clock and outputs it to the decoder 284. When the computation is completed, the computation unit's original computation TAT value is increased by 2 in the example of FIG. 8, and accordingly, the computation result of the logical computation unit 130 is passed through the timing adjustment register 131 and the timing adjustment register 132 by one clock accordingly. As a result, the timing of storage in the arithmetic register V3 is adjusted. That is, the decoder 284 instructs the logical operation unit 130 to output the operation result to the timing adjustment register 131 (FIG. 1). The control timing register 275 holds one clock of instruction information and outputs it to the decoder 285. The decoder 285 instructs the timing adjustment register 131 to output the calculation result to the timing adjustment register 132 (FIG. 1). The control timing register 276 holds the instruction information for one clock and outputs it to the decoder 286. The decoder 286 instructs the selector 133 to obtain the calculation result from the timing adjustment register 132, and outputs it to the crossbar 106 via the transmission path 901. Subsequently, the control timing register 277 holds the instruction information for one clock and outputs it to the decoder 287. The decoder 287 instructs the crossbar 106 to output the calculation result to the calculation register V3.

As described above, according to the present embodiment, instead of the original arithmetic TAT value of the arithmetic unit used in the arithmetic instruction, the maximum value among the arithmetic TAT values of other arithmetic units is used, so that the subsequent instruction can be made faster. As a result, the operation of the instruction sequence can be completed quickly.
In the example of FIG. 8, the operation TAT value of another arithmetic unit is used as it is, but it is matched with the issue check conditions of the W → W issue check unit 204, the R → W issue check unit 205, and the busy check unit 206. Any value can be used if the busy period can be managed. This specific example will be described later with reference to FIG.

FIG. 9 is a third diagram showing a time chart of the information processing apparatus according to the first embodiment of the present invention.
The TAT determination unit 207 according to the present embodiment uses FIG. 9 to compare the output values of the W → W issuance check unit 204 and the R → W issuance check unit 205 when the logical operation unit 130 is used. An example of the operation of outputting the one as the operation TAT will be described. In FIG. 9, the operation by the information processing apparatus of the present embodiment will be described using the following instruction sequence as an example.
Command “Ist” VST Mem ← V3 VL = 2
Command “I0” VADD * V3 ← V0 + V1 VL = 2
Command “I1” VAND * V3 ← V0 & V1 VL = 2
Command “I2” VMPY V0 ← V1 × V2 VL = 2
VST is a store instruction, and instruction “Ist” is a process of writing the value of the arithmetic register V3 into the memory. In the present embodiment, it is assumed that data is set to be read from the register once every four cycles. The instruction TAT in the VST instruction is calculated by the following formula.
(VL value of VST instruction −1) × (4-1) Equation 2
“4” in the two items of the formula is obtained by reading data from the register once every four cycles. In the case of FIG. 9, since VL = 2, the value of Expression 2 is “3”.
A feature of the relationship between the instructions “Ist”, “I0”, and “I1” is that the operation register V3 has a relationship of Read → Write. A feature of the relationship between the instructions “I0” and “I1” is that the operation register V3 has a write → write relationship.
When attention is paid to the relationship between the instruction “Ist”, “I0”, and “I1”, when the issue of the instruction “Ist” is determined at the clock 0, the first element of the arithmetic register V3 is stored in the memory at the clock 1. Then, the second element is stored in the memory in 5 clocks after 4 cycles. The instructions “I0” and “I1” must be written to the arithmetic register V3 after five cycles. The relationship between the instructions “I0” and “I1” is the same as in FIGS.
First, when the issue of the instruction “Ist” is determined at clock 0, the value “3” obtained by Expression 2 is set in the R → W busy information management unit 224 at clock 1. Here, the R → W issuance check unit 205 determines whether to issue the instruction “I0” by the following equation.
R → W busy information management unit 224 busy value-operation TAT value of VADD instruction ≤ 0
In this example, “3-5” is satisfied, so the above equation is satisfied. Therefore, the issue of the instruction “I0” is determined by the clock 1. When issuance of the instruction “I0” is completed, “5” is set in the W → W busy information management unit 214 in the clock 2 as in FIG. 8, and the R → W busy information management unit 224 which is “3” in the clock 1. The value of is “2”.
At this time, the W → W issuance check unit 204 determines the relationship of W → W to V3 in “I0” and “I1”.
Busy value of W → W busy information management unit 214 − operation TAT value of VAND instruction ≦ 0
Judge with. Here, since the operation TAT value of the VAND instruction is calculated as “5” which is the operation TAT of the VADD instruction of the instruction “I0”, the left side of this expression is “5-5” and satisfies this expression. Therefore, the R → W issuance check unit 204 outputs “1” indicating that an instruction can be issued to the instruction issuance check unit 208.
The R → W issuance check unit 205 determines the relationship of R → W to V3 in “Ist” and “I1”.
R → W busy information management unit 224 busy value − operation TAT value of VAND instruction ≦ 0
Judge with. Here, the operation TAT value of the VAND instruction is “3”, which is the larger value of the operation TAT of the instruction “Ist” and the original operation TAT of “VAND”. 3 ", which satisfies this equation. Accordingly, the R → W issuance check unit 205 outputs “1” indicating that the instruction issuance is possible to the instruction issuance check unit 208. As a result, the issue of the instruction “I1” is determined at clock 2.
On the other hand, in clock 2, the TAT determination unit 207 acquires the value “5” of the W → W busy information management unit 214 via the W → W issue check unit 204. In addition, the TAT determination unit 207 acquires the value “2” of the R → W busy information management unit 224 via the R → W issue check unit 205. Then, the TAT determination unit 207 determines the operation TAT of “VAND” of the instruction “I1” as “5” which is a larger value by comparing these values. The subsequent processing is the same as in FIG. In this way, even when the W → W busy information management unit and the R → W busy information management unit have significant busy values, the TAT determination unit 207 determines the larger value of them in the next instruction. Determined as the value of the operation TAT. As a result, subsequent instructions can be issued quickly, and as a result, the operation of the instruction sequence can be completed quickly.

FIG. 10 is a fourth diagram showing a time chart of the information processing apparatus according to the first embodiment of the present invention.
10, the TAT determination unit 207 according to the present embodiment takes not only the maximum calculation TAT of other arithmetic units but also an intermediate value between the original arithmetic TAT value and the maximum arithmetic TAT value of other arithmetic units. An example to be obtained will be described. The instruction sequence used in the description of FIG. 10 is the same as that in FIG.
As an assumption in this figure, for example, an AND instruction of VL = 4 is issued by a certain arithmetic instruction executed before this instruction sequence at the time of clock 1, and the busy value of the arithmetic unit busy information management unit 242 is set at clock 1 in this figure. It shall be “3”. Further, it is assumed that the operation register interference due to the preceding instruction is not considered. Further, it is assumed that the instruction “I0” that does not interfere with the preceding AND instruction is determined to be issued at clock 1. Then, in this figure, unlike FIG. 8, the busy value of the arithmetic unit busy information management unit 242 becomes a bottleneck for the issue of the instruction “I1”. This is because the instruction “I1” is also an AND instruction and uses the logical operator 130. Until the clock 3, the logical operation unit 130 is busy as indicated by the busy value of the operation unit busy information management unit 242. Therefore, the value of the busy check unit 206 does not become “1” indicating that the next instruction can be issued until the clock 3. At clock 3, all the values of the R → W issuance check unit 204, the W → W issuance check unit 205, and the busy check unit 206 become 1, and the instruction “I1” can be issued. At that time, the command issuance check unit 208 outputs “1” to the transmission line 999. On the other hand, the TAT determination unit 207 acquires the value “4” of the R → W busy information management unit 214 in the clock 3 via the R → W issue check unit 204. Then, the TAT determination unit 207 determines the operation TAT of “VADD” of the instruction “I1” as “4”. In the instruction “I1”, since the operation TAT is set to 4 unlike FIG. 8, it is output from the timing adjustment register 131 to the crossbar 106. Therefore, the entire cycle of the instruction “I1” compared with FIG. 8 is shortened by one clock. Therefore, when the instruction T12 of the instruction “I1” is set to “5” as in the example of FIG. 8, for example, when the instruction “I2” has an R → W relationship with respect to the instruction “I1” and the operation register V3. In comparison with this, it is possible to determine instruction issue one clock earlier.
As described above, according to the present embodiment, as the calculation TAT, an intermediate value between the original calculation TAT value and the maximum calculation TAT value of other calculators can be flexibly taken according to the situation, thereby efficiently calculating resources. Utilization and speeding up of processing become possible.

FIG. 11 is a fifth diagram showing a time chart of the information processing apparatus according to the first embodiment of the present invention.
With reference to FIG. 11, it will be described that the present embodiment can cope with a read pattern in which the elements to be read are not continuous, but are read several times after skipping. The following instruction sequence is used for explanation.
Command “I1” VST Mem ← V0 VL = 4
Command “I2” VAND V0 ← V2 & V3 VL = 4
This instruction sequence is characterized in that “I1” and “I2” have a relation of R → W with respect to the arithmetic register V0.
Also in this example, it is assumed that data is set to be read from the register once every four cycles. As described with reference to FIG. 9, the calculation TAT of VST is calculated by Equation 2. Then, the calculation TAT of VST in FIG. 11 is “9”. At clock 1, “9” is set in the R → W busy information management unit 221. The determination condition of the R → W issuance check unit 205 is:
R → W busy information management unit 221 −VAND instruction TAT ≦ 0
It is.
The operation TAT of the logical operation unit 130 of the present embodiment can take a value of 3 to 5 variably. In this example, the VAND instruction TAT is determined as 5. Then, this expression is satisfied in the clock 6, and the issue of the instruction “I2” is determined. Then, after the fourth element of the operation register V0 is stored in the memory at the clock 14, the data is written to the fourth element of the operation register V0 at the clock 15 to maintain the consistency of the data. Execution is complete.
As described above, according to the present embodiment, when special reading is performed from the operation register, the operation register is calculated from the relationship of the store path throughput using the R → W busy information generation unit 261 as shown in FIG. For example, in the case of a store instruction that is read in a cycle of 4 cycles, the processing can be executed at the fastest timing while managing so that subsequent instructions are not written before the last data is read.

<Second Embodiment>
The operation of the information processing apparatus according to the second embodiment of the present invention will be described below with reference to FIGS.
As shown in FIG. 12, in the first embodiment, the calculation TAT is determined by the hardware of the information processing apparatus 1 such as the W → W busy information management unit and the W → W busy check unit in order to improve the instruction operation efficiency. In the second embodiment, the calculation TAT is determined in advance as a calculation TAT value having good performance by simulation or actual measurement, and the determined value is checked from the outside of the calculation pipe control unit 20 by a control signal as a W → W issue check. This is given to the unit 204. For example, the value “5” is included in the signal 980 in FIG. 12, and the W → W issuance check unit 204 and the operation TAT determination unit 207 use the value “5” included in this signal 980 as the operation TAT value of each instruction. To do.
FIG. 13 is a term chart in the second embodiment. The instruction sequence in this figure is the same as in FIG. As shown in FIG. 13, the value “5” is given by the signal 980 after the clock 1.
According to the present embodiment, a value with good execution performance is determined in advance for each job, and the calculation TAT value is received via the signal 980, so that more flexible and efficient calculation can be performed.

<Third embodiment>
The operation of the information processing apparatus according to the third embodiment of the present invention will be described below with reference to FIG.
As shown in FIG. 14, the third embodiment includes a state count unit 800. The state count unit 800 acquires the value of the operation TAT determined by the TAT determination unit 207 when the instruction issuance check unit 208 outputs “1”. Then, the state counting unit 800 counts the distribution of the calculation TAT. And, for example, when the number of times that the maximum value of the calculation TAT value is counted such that the calculation TAT = 5 is 2455 times, the calculation TAT = 4 is 1244 times, etc. = 5 is fixed, and the determined operation TAT is given to the W → W issue check unit 204 and the like.
As a result, it is possible to save power by suppressing signal changes in the logic circuit.

  In addition, when issuing an instruction is determined, the instruction issuance is determined based on the instruction's original operation TAT. For example, when the subsequent instruction in R → W is determined to be issued, the value of the operation TAT after the control timing register 274 is changed. .

  The W → W busy information management unit 210, the R → W busy information management unit 220, the W → R busy information management unit 230, and the computing unit busy information management unit 240 are examples of the busy period information management unit. The busy value is an example of busy period information. The check unit includes, for example, a W → W issue check unit 204, an R → W issue check unit 205, a busy check unit 206, and an instruction issue check unit 208. The TAT determination unit 207 is an example of a determination unit. The control unit includes, for example, an instruction issuance confirmation information register 270, an issuance confirmation instruction information register 271, an issuance confirmation TAT information register 272, decoders 273 to 278, timing adjustment registers 131 to 132, and a selector 133.

  In addition, it is possible to appropriately replace the components in the above-described embodiments with known components without departing from the spirit of the present invention. The technical scope of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

100: arithmetic register V0
101: Operation register V1
102: Operation register V2
103: arithmetic register V3
106... Crossbar 110, 111, 112, 113... Operand selector 120... Multiply-add calculator 130. Operation pipe control unit 201: instruction buffer unit 202 ... instruction decoder 203 ... instruction issue queue 204 ... W → W issue check unit 205 ... R → W issue check unit 206 ... busy Check unit 207 ... TAT determination unit 208 ... Instruction issue check unit 210 ... W → W busy information management unit 220 ... R → W busy information management unit 230 ... W → R busy information management unit 240 ... arithmetic unit busy information management part 260 ... W → W busy information generation part 261 ... R → W busy information generation part 262 ... W → R busy information generation 263... Arithmetic unit busy information generation unit 270... Instruction issue fixed information register 271... Issue fixed instruction information register 272... Issue fixed TAT information register 273 274 275 276 277 278. ·decoder

Claims (8)

Multiple arithmetic registers;
A plurality of arithmetic units;
When it is determined that the operation instruction is issued, busy period information indicating a period used for execution of the operation instruction is set for the operation register and the arithmetic unit related to the operation instruction, and the operation instruction determined by the issue is progressed. A busy period information management unit for subtracting the busy period information according to
Based on the busy period information and a calculation TAT (TURN AROUND TIME) that is a time required for execution of the subsequent calculation instruction, the subsequent calculation that can secure a calculation result when the subsequent calculation instruction is sequentially executed. A check unit that determines the timing of issuing instructions;
A determination unit that determines an operation TAT of the subsequent operation instruction determined to be issued according to an arithmetic unit related to the subsequent operation instruction;
A control unit that adjusts the timing of storing the calculation result of the subsequent calculation instruction determined to be issued in the calculation register based on the calculation TAT determined by the determination unit;
Bei to give a,
When the check unit issues the subsequent operation instruction for the operation TAT of the subsequent operation instruction at a timing earlier than the issue timing of the subsequent operation instruction based on a predetermined operation TAT determined for the operation instruction. And determining the issuance timing using the time required to secure the operation result of the preceding operation instruction as the operation TAT of the subsequent operation instruction . Multiple arithmetic registers;
A plurality of arithmetic units;
When it is determined that the operation instruction is issued, busy period information indicating a period used for execution of the operation instruction is set for the operation register and the arithmetic unit related to the operation instruction, and the operation instruction determined by the issue is progressed. A busy period information management unit for subtracting the busy period information according to
Based on the busy period information and a calculation TAT (TURN AROUND TIME) that is a time required for execution of the subsequent calculation instruction, the subsequent calculation that can secure a calculation result when the subsequent calculation instruction is sequentially executed. A check unit that determines the timing of issuing instructions;
A determination unit that determines an operation TAT of the subsequent operation instruction determined to be issued according to an arithmetic unit related to the subsequent operation instruction;
A control unit that adjusts the timing of storing the calculation result of the subsequent calculation instruction determined to be issued in the calculation register based on the calculation TAT determined by the determination unit;
With
When the operation TAT of the subsequent operation instruction is smaller than the operation TAT of the preceding operation instruction, the check unit replaces the operation TAT of the subsequent operation instruction with the maximum of the operation TATs defined for the plurality of operation units. Determine the timing of issuing the subsequent operation instruction using the value of
When the operation TAT of the subsequent operation instruction is smaller than the operation TAT of the preceding operation instruction, the determination unit determines the operation TAT of the subsequent operation instruction determined to be issued based on the busy period information at the issue timing. determining Te information processing apparatus it said. The information processing apparatus according to claim 2, wherein the determination unit variably determines a value that is greater than or equal to an operation TAT of a subsequent operation instruction and less than or equal to an operation TAT of a preceding operation instruction. The busy period information management unit sets busy period information for each combination of write processing or read processing that is continuously performed on the arithmetic register,
The determination unit determines a maximum value among the busy period information set for each combination at the issue timing as an operation TAT of the subsequent operation instruction.
The information processing apparatus according to claim 2, wherein the information processing apparatus is an information processing apparatus. The busy period information management unit sets busy period information for each combination of write processing or read processing that is continuously performed on the arithmetic register,
The information according to any one of claims 1 to 4, wherein the check unit determines a timing for issuing the subsequent operation instruction based on the busy period information set for each combination. Processing equipment. The check unit obtains a predetermined value used as an operation TAT of the subsequent operation instruction from the outside, and determines an issue timing of the subsequent operation instruction based on the busy period information and the acquired value. The information processing apparatus according to any one of claims 1 to 5, wherein: A state counting unit that obtains the calculation TAT selected by the determination unit and counts the number of times determined by the determination unit for each value of the calculation TAT,
The state count unit outputs the calculation TAT to the check unit when the value of the calculation TAT with the largest number of counts is the maximum value in the calculation TAT of the plurality of calculators,
7. The check unit according to claim 1, wherein the check unit determines an issue timing of the subsequent operation instruction based on the busy period information and the operation TAT acquired from the state count unit. The information processing apparatus according to item 1. In an information processing apparatus having a plurality of arithmetic registers and a plurality of arithmetic units,
When it is determined that the operation instruction is issued, busy period information indicating a period used for execution of the operation instruction is set for the operation register and the arithmetic unit related to the operation instruction, and the operation instruction determined by the issue is progressed. Subtract the busy period information according to
Based on the busy period information and an operation TAT that is a time required for execution of the subsequent operation instruction, an issue timing of the subsequent operation instruction that can secure an operation result when the subsequent operation instruction is sequentially executed is determined. Decide
An operation TAT of the subsequent operation instruction determined to be issued is determined according to an arithmetic unit related to the subsequent operation instruction;
Based on the determined operation TAT, adjust the timing of storing the operation result of the subsequent operation instruction determined to be issued in the operation register ,
When determining the issuance timing, for the operation TAT of the subsequent operation instruction, the subsequent operation instruction is earlier than the issuance timing of the subsequent operation instruction based on a predetermined operation TAT determined for the operation instruction. , The issuance timing is determined using the time required for securing the operation result of the preceding operation instruction as the operation TAT of the subsequent operation instruction .

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