JP6379733B2 - Nonvolatile semiconductor memory device and control method thereof - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device and a control method thereof, for example, a nonvolatile semiconductor memory device including a plurality of memory cells and a reference memory cell and a control method thereof.

  In addition to a plurality of memory cells to which data is written, a nonvolatile semiconductor memory device having a reference memory cell used for current comparison in data reading or the like is known.

  Also, in a ferroelectric memory, it is known to use a minimum voltage that becomes a saturation polarization point obtained by sweeping a voltage applied to a ferroelectric capacitor as a driving voltage in order to drive at high speed and reduce power consumption. (For example, refer to Patent Document 1).

  A semiconductor memory device having a temperature detection circuit and a step-down power supply circuit that switches the operation voltage to an absolutely small voltage by an output signal of the temperature detection circuit or an external input signal in order to ensure the operation speed is known. (For example, refer to Patent Document 2). A temperature-dependent semiconductor integrated circuit measures the output value of a power supply regulator at different temperatures and performs trimming using the measured value to improve product accuracy and increase efficiency until commercialization. It is known (see, for example, Patent Document 3).

JP 2003-297079 A JP-A-6-85159 JP 2004-200327 A

  In the memory cell and the reference memory cell, current generated in each increases as the operating temperature increases. Further, as the current generated in the memory cell increases, the current value varies among the plurality of memory cells.

  In verification for determining completion of data writing and erasing with respect to the memory cell, a comparison is made between a cell current generated in the memory cell and a reference current generated in the reference memory cell. At this time, if the variation in the cell current value generated in the memory cell is large, data writing or erasing is repeated until the cell current at the end of the variation satisfies the standard in comparison with the reference current. For this reason, quality deterioration such as delay of data writing or erasing occurs.

  An object of the nonvolatile semiconductor memory device and the control method thereof is to suppress deterioration in quality.

  The nonvolatile semiconductor memory device described in the present specification includes a plurality of memory cells into which data is written, a reference memory cell, a current measuring unit that measures a reference current value generated in the reference memory cell, and the reference memory cell A recording unit that records information in which a reference current value and a gate voltage value are associated with each other for a plurality of operating temperatures, the reference current value measured by the current measurement unit, and the information recorded in the recording unit And a gate voltage controller for controlling a gate voltage value to be applied to the memory cell and the reference memory cell at the time of data reading from the memory cell and verification of writing and erasing.

  A method for controlling a nonvolatile semiconductor memory device described in the present specification is a method for controlling a nonvolatile semiconductor memory device including a plurality of memory cells into which data is written and a reference memory cell. The generated reference current value is acquired, and based on the acquired reference current value and information that is recorded in the recording unit and that associates the reference current value and the gate voltage value for each of the plurality of operating temperatures of the reference memory cell. Then, the gate voltage value applied to the memory cell and the reference memory cell at the time of reading data from the memory cell and verifying writing and erasing is controlled.

  According to the nonvolatile semiconductor memory device and the control method thereof described in this specification, deterioration in quality can be suppressed.

FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to Comparative Example 1. FIG. 2 is a diagram illustrating a memory cell array. FIG. 3 is a diagram for explaining a comparison between a cell current generated in a memory cell and a reference current generated in a reference memory cell. FIG. 4 is a flowchart illustrating a test performed on a reference memory cell in the nonvolatile semiconductor memory device of Comparative Example 1. FIG. 5 is a flowchart for explaining verification of data writing and erasing. FIG. 6 is a diagram illustrating the relationship between the gate voltage, the cell current, and the reference current. FIG. 7 is a block diagram illustrating the configuration of the nonvolatile semiconductor memory device according to the first embodiment. FIG. 8 is a flowchart for explaining the primary test. FIG. 9 is a flowchart for explaining the secondary test. FIG. 10 is a flowchart showing the control performed before reading, writing, and erasing data. FIG. 11 is a block diagram illustrating the configuration of the nonvolatile semiconductor memory device according to the second embodiment. FIG. 12A is a diagram showing information in which the operation temperature of the reference memory cell is associated with the gate voltage value, and FIG. 12B is an association of the operation temperature of the reference memory cell and the reference current value. It is a figure which shows the information. FIG. 13 is a flowchart showing control performed before data reading, writing, and erasing. FIG. 14 is a block diagram illustrating the configuration of the nonvolatile semiconductor memory device according to the third embodiment. FIG. 15 is a flowchart showing the control performed before reading, writing, and erasing data.

  Before describing the nonvolatile semiconductor memory device according to Example 1, the nonvolatile semiconductor memory device according to Comparative Example 1 will be described. FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to Comparative Example 1. As shown in FIG. 1, the nonvolatile semiconductor memory device 400 of the comparative example 1 includes a memory unit 10 and a logic unit 40. The memory unit 10 is, for example, a nonvolatile semiconductor memory, and is an EEPROM (Electrically Erasable Programmable Read-Only Memory) such as a flash memory.

  The memory unit 10 includes a memory cell array 12, a reference memory cell 14, a state machine 16, a booster circuit 18, a decoder 20, a Y selector 22, a sense amplifier 24, and a data buffer 26.

  The logic unit 40 includes a step-down circuit 42, a setting register 44, and a CPU (Central Processing Unit) 46. A constant voltage power supply 50 is connected to the nonvolatile semiconductor memory device 400.

  FIG. 2 is a diagram illustrating a memory cell array. As shown in FIG. 2, the memory cell array 12 has a plurality of memory cells 60 arranged in an array. Memory cell 60 is a non-volatile memory cell including a transistor having a control gate connected to word line WL and a floating gate. The memory cells 60 arranged in the horizontal direction (row direction) in FIG. 2 have a control gate connected to a common word line WL and a source connected to a common source line SL. The memory cells 60 arranged in the vertical direction (column direction) in FIG. 2 have their drains connected to a common bit line BL.

  The reference memory cell 14 in FIG. 1 is a nonvolatile memory cell including a transistor having a control gate connected to a reference word line and a floating gate. The reference memory cell 14 is set to a predetermined threshold voltage. The reference memory cell 14 generates a reference current when reading data from the memory cell 60. Further, the reference memory cell 14 generates a reference current in the verification for determining completion of data writing and erasing with respect to the memory cell 60. The reference memory cell 14 is provided for determining the logic of data held in the memory cell 60 based on the cell current generated in the memory cell 60. One reference memory cell 14 is provided in the memory unit 10 and is used for comparison with all of the plurality of memory cells 60.

  FIG. 3 is a diagram for explaining a comparison between a cell current generated in a memory cell and a reference current generated in a reference memory cell. As shown in FIG. 3, both the memory cell 60 and the reference memory cell 14 have a source region 72 and a drain region 74 in a semiconductor substrate 70. A floating gate 76 and a control gate 78 are provided on the semiconductor substrate 70 between the source region 72 and the drain region 74. The control gate 78 of the memory cell 60 is connected to the word line WL, and the control gate 78 of the reference memory cell 14 is connected to the reference word line RWL.

  A memory cell having a floating gate stores data by injecting electrons into the floating gate to change a threshold voltage. The threshold voltage of the memory cell increases when electrons are present in the floating gate and decreases when electrons are not present in the floating gate. The current flowing through the memory cell having a high threshold voltage is smaller than the current flowing through the memory cell having a low threshold voltage.

  By writing to inject electrons into the floating gate, the memory cell 60 is set to logic 0 with a high threshold voltage and low cell current. Due to erasure in which electrons are emitted from the floating gate, the memory cell 60 is set to logic 1 with a low threshold voltage and a large cell current. Therefore, the reference memory cell 14 generates a reference current having a value between the cell current flowing through the logic 0 memory cell and the cell current flowing through the logic 1 memory cell (for example, an intermediate value between both cell currents). Is set.

  The sense amplifier 24 compares the cell current generated in the memory cell 60 with the reference current generated in the reference memory cell 14 and determines the logic of the data held in the memory cell 60 based on the comparison result. The sense amplifier 24 determines as logic 1 when the cell current is larger than the reference current, and determines as logic 0 when the cell current is smaller than the reference current.

  The state machine 16 in FIG. 1 controls each unit of the memory unit 10 under the instruction of the CPU 46. For example, under the instruction of the CPU 46, the state machine 16 performs control for reading, writing, erasing, and verifying writing and erasing with respect to the memory cell 60.

  The step-down circuit 42 steps down a voltage having a constant voltage value generated by the constant voltage power supply 50 in accordance with the condition set by the setting register 44. The step-down circuit 42 is provided so that a voltage is supplied via the step-down circuit 42 to an element in a low voltage region, for example, when there is an element in a different drive voltage region in the logic unit 40. In addition, a voltage is supplied to the memory unit 10 via the step-down circuit 42.

  The booster circuit 18 boosts the voltage supplied from the step-down circuit 42 as necessary. For example, the booster circuit 18 increases the voltage when the voltage supplied from the step-down circuit 42 is insufficient in the operation such as data writing to the memory cell 60. The voltage passing through the booster circuit 18 is supplied to the memory cell array 12 and the reference memory cell 14.

  The decoder 20 includes an X decoder and a Y decoder. The X decoder selects the word line WL under the instruction of the state machine 16. The Y decoder generates a signal for selecting the bit line BL under the instruction of the state machine 16 and outputs the generated signal to the Y selector 22. The Y selector 22 selects the bit line BL based on the signal from the Y decoder. As a result, the memory cell 60 to be accessed is selected and supplied with a voltage.

  The sense amplifier 24 compares the cell current generated in the memory cell 60 with the reference current generated in the reference memory cell 14 when reading data from the memory cell 60. The sense amplifier 24 determines the logic of data held in the memory cell 60 based on the comparison result, and outputs the logic obtained by the determination to the data buffer 26.

  In addition, the sense amplifier 24 compares the cell current generated in the memory cell 60 with the reference current generated in the reference memory cell 14 in the data write / erase verification for the memory cell 60. Based on the comparison result, the sense amplifier 24 determines whether or not data writing or erasing to the memory cell 60 is completed, and outputs the determination result to the data buffer 26.

  The logic and determination result output to the data buffer 26 is sent to the state machine 16 and then output to the CPU 46.

  The CPU 46 controls the entire nonvolatile semiconductor memory device 400.

  Next, a test performed in advance on the reference memory cell 14 before starting the operation of the nonvolatile semiconductor memory device 400 of Comparative Example 1 will be described. FIG. 4 is a flowchart illustrating a test performed on a reference memory cell in the nonvolatile semiconductor memory device of Comparative Example 1. The test is performed in a normal temperature environment (for example, 25 ° C.).

  As shown in FIG. 4, writing is performed on the reference memory cell 14 (step S10). As a result, electrons are injected into the floating gate of the reference memory cell 14. Next, a first predetermined gate voltage is applied to the control gate of the reference memory cell 14, a second predetermined drain voltage is applied to the drain, the source is connected to the ground, and the generated reference current value is measured. (Step S12). The reference current value is measured using, for example, a tester. Next, it is confirmed whether or not the measured reference current value is within the standard range (step S14). The standard range is, for example, a range determined in a range of values between the cell current flowing through the logic cell 0 and the cell current flowing through the logic 1 memory cell, for example, between the cell currents. It is the range near the value.

  When the reference current value is outside the standard range (in the case of No), the reference memory cell 14 is written or erased (step S16). This changes the amount of charge of electrons injected into the floating gate. Next, a first predetermined gate voltage is applied to the control gate of the reference memory cell 14, a second predetermined drain voltage is applied to the drain, the source is connected to the ground, and the generated reference current value is measured. (Step S12). Next, it is confirmed whether or not the measured reference current value is within the standard range (step S14).

  When the reference current value is within the standard range (in the case of Yes), the test for the reference memory cell 14 is finished.

  Next, data write and erase verify for the memory cell 60 will be described. FIG. 5 is a flowchart for explaining verification of data writing and erasing. As shown in FIG. 5, the CPU 46 instructs the state machine 16 to verify writing or erasing data in the memory cell 60 (step S20).

  The state machine 16 specifies the address of the memory cell 60 to be accessed to the decoder 20 (step S22). The decoder 20 selects the memory cell 60 designated from the state machine 16 (step S24). The first predetermined gate voltage and the second predetermined drain voltage used in the room temperature test of FIG. 4 are applied to the control gate and drain of the selected memory cell 60 and reference memory cell 14, and the source is Connected to ground.

  The sense amplifier 24 compares the cell current generated in the memory cell 60 with the reference current generated in the reference memory cell 14 (step S26). The sense amplifier 24 determines the logic of the data held in the memory cell 60 based on the comparison result, and determines whether the data writing or erasing is completed (step S28).

  Next, the sense amplifier 24 outputs the determination result to the state machine 16 via the data buffer 26. The state machine 16 performs writing or erasing on the memory cell 60 (step S30) when the determination that the incomplete operation is output from the sense amplifier 24 (No in step S28).

  Next, the sense amplifier 24 compares the cell current generated in the memory cell 60 with the reference current generated in the reference memory cell 14 (step S26). Then, the sense amplifier 24 determines whether data writing or erasing is completed based on the comparison result (step S28).

  When it is determined that the completion is output from the sense amplifier 24 (Yes in step S28), the state machine 16 outputs to the CPU 46 that data writing or erasure is completed (step S32).

  Note that data is read from the memory cell 60 by the same control as in the flowchart shown in FIG. 5 except that step S28 is not performed. That is, the CPU 46 instructs the state machine 16 to read data from the memory cell 60. The state machine 16 designates the address of the memory cell 60 to be accessed to the decoder 20, and the decoder 20 selects the memory cell 60. The sense amplifier 24 compares the cell current generated in the memory cell 60 with the reference current generated in the reference memory cell 14. The sense amplifier 24 determines the logic of the data held in the memory cell 60 based on the comparison result, and outputs it to the state machine 16 via the data buffer 26. The state machine 16 outputs the result to the CPU 46.

In the first comparative example, a gate voltage having a predetermined value (constant voltage value) is applied in verifying data writing and erasing regardless of the operating temperatures of the memory cell 60 and the reference memory cell 14. The cell current and the reference current generated in the memory cell 60 and the reference memory cell 14 to which the gate voltage having a constant voltage value is applied increase as the operating temperature of the memory cell 60 and the reference memory cell 14 increases. This is because in the semiconductor memory cell, the source-drain current increases due to activation of electrons, transistor leakage, a decrease in resistance value, and the like as the operating temperature increases. For example, the current I of the semiconductor memory cell changes based on I = V / R ₀ e ^−aT (V is a voltage, R ₀ is a resistance, a is a coefficient, and T is an operating temperature). Further, since the current generated in the semiconductor memory cell is a minute current having units of μA and nA, the increasing tendency becomes large. As the cell current increases, the variation in the cell current value among the plurality of memory cells 60 increases.

  When the variation of the cell current value becomes large, it becomes difficult for the cell current at the end of the variation to satisfy the standard in comparison with the reference current in verification of data writing and erasing. For this reason, data writing or erasing is repeatedly performed until the standard is satisfied, resulting in a delay in writing or erasing. In addition, since data is repeatedly written or erased, an excessive stress load is applied to the memory cell. For this reason, the quality is degraded.

  Here, the relationship between the gate voltage, the cell current, and the reference current will be described. FIG. 6 is a diagram illustrating the relationship between the gate voltage, the cell current, and the reference current. The horizontal axis in FIG. 6 is the gate voltage, and the vertical axis is the cell current and the reference current. Further, the reference current is indicated by a bold line, and the cell current is indicated by a thin line. FIG. 6 shows a state after erasing of the memory cell is completed. As shown in FIG. 6, by reducing the gate voltage from A to B, the cell current is reduced and the variation in the cell current value is also reduced. Therefore, when the operating temperature of the memory cell 60 and the reference memory cell 14 becomes high, an increase in cell current and reference current can be suppressed by lowering the gate voltage. In other words, when the operating temperature of the memory cell 60 and the reference memory cell 14 becomes high, the cell current value and the reference current value can be maintained at room temperature by lowering the gate voltage. Thereby, it can suppress that the dispersion | variation in a cell electric current value becomes large. In consideration of the above, an embodiment capable of suppressing deterioration in quality will be described below.

  FIG. 7 is a block diagram illustrating the configuration of the nonvolatile semiconductor memory device according to the first embodiment. As shown in FIG. 7, the memory unit 10 a of the nonvolatile semiconductor memory device 100 of Example 1 is different from the nonvolatile semiconductor memory device 400 of Comparative Example 1 in that the current measuring unit 28, the decoder 30, the operation buffer 32, and the switch 34 is further included. The memory cell array 12 has a recording unit 36 in a non-rewritable data non-recording area. The CPU 46a of the logic unit 40a has a gate voltage control unit 80. In addition to the constant voltage power supply 50, a variable voltage power supply 52 is also connected to the nonvolatile semiconductor memory device 100.

  In the recording unit 36 in the memory cell array 12, information in which a reference current value and a gate voltage value are associated with each other for a plurality of operating temperatures of the reference memory cell 14 is recorded. For example, the reference current value and the gate voltage value are encoded and recorded in digital information.

  The current measurement unit 28 measures a reference current value generated in the reference memory cell 14. The current measurement unit 28 is, for example, a sense amplifier, but other measurement means may be used as long as the reference current value can be measured.

  The decoder 30 encodes the reference current value measured by the current measuring unit 28 into digital information. The current measuring unit 28 and the decoder 30 can be incorporated in the sense amplifier 24 and the decoder 20 by separating the wiring connection and the algorithm at the time of operation.

  The arithmetic buffer 32 compares the reference current value measured by the current measuring unit 28 with the information recorded in the recording unit 36 in the memory cell array 12 under the instruction of the CPU 46a. Then, the operation buffer 32 calculates a gate voltage value based on the comparison and outputs it to the CPU 46a. In addition, the operation buffer 32 outputs to the state machine 16 that the calculation of the gate voltage value has been completed.

  The switch 34 switches whether the voltage from the constant voltage power supply 50 or the voltage from the variable voltage power supply 52 is supplied to the reference memory cell 14. In a secondary test to be described later, the switch 34 is switched so that the voltage from the variable voltage power supply 52 is supplied to the reference memory cell 14. In other cases, the voltage from the constant voltage power supply 50 is supplied. It is like that.

  The gate voltage control unit 80 uses the arithmetic buffer 32 to calculate the gate voltage value based on the reference current value measured by the current measurement unit 28 and the information recorded in the recording unit 36. Then, the gate voltage control unit 80 sets the calculated gate voltage value in the setting register 44, and sets the gate voltage value in the data read, write and erase verifications to the memory cell 60 as the calculated gate voltage value. As described above, the gate voltage control unit 80 controls the gate voltage value applied to the memory cell 60 and the reference memory cell 14 in the data read from the memory cell 60 and the verify of the write and erase.

  The other configuration of the nonvolatile semiconductor memory device 100 of Example 1 is the same as that of the nonvolatile semiconductor memory device 400 of Comparative Example 1 shown in FIG.

  Next, a test performed in advance on the reference memory cell 14 before starting the operation of the nonvolatile semiconductor memory device 100 according to the first embodiment will be described. The test includes a primary test performed at room temperature (for example, 25 ° C.) and a secondary test performed at a high temperature (for example, 80 ° C.). FIG. 8 is a flowchart for explaining the primary test. As shown in FIG. 8, the reference memory cell 14 is written (step S40). As a result, electrons are injected into the floating gate of the reference memory cell 14. Next, a first predetermined gate voltage is applied to the control gate of the reference memory cell 14, a second predetermined drain voltage is applied to the drain, the source is connected to the ground, and the generated reference current value is measured. (Step S42). The reference current value is measured using, for example, a tester. Next, it is confirmed whether or not the measured reference current value is within the standard range (step S44). The standard range is the same as that described in Comparative Example 1.

  If the reference current value is out of the standard range (No in step S44), the reference memory cell 14 is written or erased (step S46). This changes the amount of charge of electrons injected into the floating gate. Next, a first predetermined gate voltage is applied to the control gate of the reference memory cell 14, a second predetermined drain voltage is applied to the drain, the source is connected to the ground, and the generated reference current value is measured. (Step S42). Next, it is confirmed whether or not the measured reference current value is within the standard range (step S44).

  If the reference current value is within the standard range (Yes in step S44), the gate voltage value and the reference current value at that time are recorded in the recording unit 36 in the memory cell array 12 (step S48). For example, the gate voltage value and the reference current value are encoded and recorded as digital information. In the following, the gate voltage value and the reference current value recorded in the primary test at room temperature are referred to as a first gate voltage value Vg1 and a first reference current value Iref1.

  FIG. 9 is a flowchart for explaining the secondary test. As shown in FIG. 9, the gate voltage of the first gate voltage value Vg1 is applied to the control gate of the reference memory cell 14, the drain voltage of the second predetermined value is applied to the drain, and the source is connected to the ground (step S50). . Next, the reference current value generated in the reference memory cell 14 is measured (step S52). The reference current value is measured using, for example, a tester. Next, it is confirmed whether or not the measured reference current value is equal to the first reference current value Iref1 (step S54). Note that “equivalent” includes not only the case where they are completely the same, but also the case where they are considered to be almost the same although they are slightly different. It is assumed that the reference current value when the gate voltage of the first gate voltage value Vg1 is applied is larger than the first reference current value Iref1. This is because, as described above, in the semiconductor memory cell, the current between the source and the drain increases as the operating temperature increases.

  When the reference current value is not equal to the first reference current value Iref1 (No in step S54), a gate voltage lower than the first gate voltage value Vg1 is applied to the control gate of the reference memory cell 14 (step S56). ). Such a gate voltage can be applied to the reference memory cell 14 by switching the switch 34 in FIG. 7 to the variable voltage power supply 52 side. Next, the reference current value generated in the reference memory cell 14 is measured (step S52), and it is determined whether or not the measured reference current value is equal to the first reference current value Iref1 (step S54).

  When the reference current value is equal to the first reference current value Iref1 (Yes in step S54), the gate voltage value at this time and the reference current generated when the gate voltage of the first gate voltage value Vg1 is applied The value is recorded in the recording unit 36 in the memory cell array 12 (step S58). For example, the gate voltage value and the reference current value are encoded and recorded as digital information. Hereinafter, the gate voltage value and the reference current value recorded in the secondary test at a high temperature are referred to as a second gate voltage value Vg2 and a second reference current value Iref2. The magnitude relationship between the first gate voltage value and the second gate voltage value is Vg1> Vg2, and the magnitude relationship between the first reference current value and the second reference current value is Iref1 <Iref2.

Table 1 shows an example of information recorded in the recording unit 36. As shown in Table 1, the first gate voltage value Vg1 in the primary test is associated with the first reference current value Iref1, and the second gate voltage value Vg2 and the second reference current value Iref2 in the secondary test are Correspondingly recorded. That is, the gate voltage value and the reference current value are recorded in association with each other for each of a plurality of operating temperatures (primary test and secondary test). The reference current value at each of the plurality of operating temperatures is a reference current value generated when a gate voltage of a gate voltage value at a reference temperature (for example, room temperature in the primary test) is applied. The gate voltage value at each of the plurality of operating temperatures is a gate voltage value when a reference current equivalent to the reference current value at the reference temperature is generated. Here, the gate voltage value and the reference current value are recorded in association with each other for two operating temperatures, but the gate voltage value and the reference current value are recorded in association with each other for three or more operating temperatures. May be. The reference current value for each of the plurality of operating temperatures may be a reference current value generated when a gate voltage equivalent to the gate voltage value at the reference temperature is applied.

  Next, control performed before reading, writing, and erasing data with respect to the memory cell 60 will be described. FIG. 10 is a flowchart showing the control performed before reading, writing, and erasing data. As shown in FIG. 10, the CPU 46a applies the gate voltage of the first gate voltage value Vg1 to the control gate of the reference memory cell 14, applies the drain voltage of the second predetermined value to the drain, and connects the source to the ground. , Generate a reference current. Then, the CPU 46a acquires the reference current value measured by the current measuring unit 28 (step S60).

  Next, the CPU 46a uses the calculation buffer 32 to compare the acquired reference current value with the information recorded in the recording unit 36 (step S62). The CPU 46a compares the acquired reference current value with the reference current value in the information recorded in the recording unit 36.

  Next, the CPU 46a specifies the reference current value closest to the acquired reference current value among the plurality of reference current values included in the information recorded in the recording unit 36 (step S64).

  Next, the CPU 46a calculates a gate voltage value corresponding to the identified reference current value (step S66).

  Next, the CPU 46a sets the calculated gate voltage value in the setting register 44, and controls so that the gate voltage of the calculated gate voltage value is applied in the data read, write and erase verify operations (step S68). ). For example, the CPU 46 a sets the code data of the calculated gate voltage value in the setting register 44. Thereafter, data read, write and erase verify are performed by the same method as that described in FIG. 5 of Comparative Example 1.

  Here, the control of FIG. 10 will be described by taking the case where the information recorded in the recording unit 36 is Table 1 as an example. The CPU 46a acquires the reference current value Iref measured by the current measurement unit 28. The CPU 46a compares the acquired reference current value Iref with the first reference current value Iref1 and the second reference current value Iref2 in the information recorded in the recording unit 36.

The CPU 46a specifies the reference current value closest to the acquired reference current value Iref among the first reference current value Iref1 and the second reference current value Iref2. Here, description will be made assuming that the first reference current value Iref1 is specified. The CPU 46a calculates a first gate voltage value Vg1 corresponding to the specified first reference current value Iref1. In addition, the control so far can be performed by the following arithmetic expressions, for example.
IF measurement Iref ≧ (Iref1 + Iref2) / 2 THEN selection Vg = Vg2
ELSE selection Vg = Vg1
The CPU 46a sets the calculated first gate voltage value Vg1 in the setting register 44, and controls so that the gate voltage of the calculated first gate voltage value Vg1 is applied in the data read, write and erase verify operations. To do.

  According to the first embodiment, information in which the reference current value and the gate voltage value are associated with each other for each of the plurality of operating temperatures of the reference memory cell 14 is recorded in the recording unit 36. Based on the reference current value measured by the current measuring unit 28 and the information recorded in the recording unit 36, the gate voltage control unit 80 controls the gate voltage value at the time of verifying data reading, writing, and erasing. To do. As a result, data can be read, and writing and erasure verification can be performed with an appropriate gate voltage value that matches the operating temperature of the memory cell 60 and the reference memory cell 14. Accordingly, variations in cell current values among the plurality of memory cells 60 can be suppressed, data reading accuracy can be improved, data writing or erasing delay can be suppressed, and deterioration in quality can be suppressed. In addition, since an appropriate gate voltage value according to the operating temperature is applied, it is possible to suppress a cell current and a reference current from flowing more than necessary, thereby suppressing current consumption.

  Among the information recorded in the recording unit 36, the reference current value for each of the plurality of operating temperatures may be a reference current value generated when a gate voltage of a gate voltage value at a reference temperature (for example, room temperature) is applied. . The gate voltage value at each of the plurality of operating temperatures may be a gate voltage value when a reference current equivalent to the reference current value at the reference temperature is generated. Thereby, when the operating temperature becomes high, the gate voltage can be lowered so that the cell current value and the reference current value do not become too large. Therefore, variations in cell current values among the plurality of memory cells 60 can be suppressed, and deterioration in quality can be suppressed.

  The gate voltage control unit 80 controls the gate voltage value corresponding to the reference current value closest to the reference current value measured by the current measurement unit 28 among the plurality of reference current values included in the information recorded in the recording unit 36. May be. Thereby, the control of the gate voltage value can be simplified, and the amount of information recorded in the recording unit 36 can be suppressed.

  The recording unit 36 may be in a non-rewritable data recording area of the memory cell array 12. Thereby, since it is not necessary to provide a recording part separately, the enlargement of an apparatus and the increase in cost can be suppressed.

  FIG. 11 is a block diagram illustrating the configuration of the nonvolatile semiconductor memory device according to the second embodiment. As illustrated in FIG. 11, the CPU 46 b of the logic unit 40 b of the nonvolatile semiconductor memory device 200 according to the second embodiment further includes a temperature calculation unit 82 as compared with the nonvolatile semiconductor memory device 100 according to the first embodiment. Further, the variable voltage power source 52 is not connected, and the switch 34 is not provided in the memory unit 10b.

  The recording unit 36a in the memory cell array 12 records information in which the operating temperature of the reference memory cell 14 is associated with the gate voltage value. The recording unit 36a also records information in which the operating temperature of the reference memory cell 14 is associated with the reference current value.

  The arithmetic buffer 32a compares the reference current value measured by the current measuring unit 28 with the information recorded in the recording unit 36a under the instruction of the CPU 46b. Then, the operation buffer 32a determines the operating temperatures of the memory cell 60 and the reference memory cell 14 based on the comparison, and outputs them to the CPU 46b. In addition, the operation buffer 32a compares the determined operating temperatures of the memory cell 60 and the reference memory cell 14 with the information recorded in the recording unit 36a under the instruction of the CPU 46b. Then, the operation buffer 32a calculates a gate voltage value based on the comparison and outputs it to the CPU 46b. The operation buffer 32a outputs to the state machine 16 that the calculation of the gate voltage value and the determination of the operating temperature have been completed.

  The temperature calculation unit 82 calculates the operating temperature of the memory cell 60 and the reference memory cell 14 based on the reference current value measured by the current measurement unit 28 using the calculation buffer 32a. That is, the current measurement unit 28 and the temperature calculation unit 82 function as a temperature determination unit that determines the operating temperatures of the memory cell 60 and the reference memory cell 14.

  The gate voltage control unit 80a uses the operation buffer 32a to calculate the gate voltage value based on the operating temperature determined by the temperature determination unit and the information recorded in the recording unit 36a. Then, the gate voltage control unit 80a sets the calculated gate voltage value in the setting register 44, and sets the gate voltage value in the data read and write / erase verification to the memory cell 60 as the calculated gate voltage value. As described above, the gate voltage control unit 80a controls the gate voltage value applied to the memory cell 60 and the reference memory cell 14 in the data read from the memory cell 60 and the verify of write and erase.

  The other configuration of the nonvolatile semiconductor memory device 200 according to the second embodiment is the same as that of the nonvolatile semiconductor memory device 100 according to the first embodiment shown in FIG. Also, in the nonvolatile semiconductor memory device 200 of the second embodiment, a test for adjusting the reference current value is performed on the reference memory cell 14 in advance, but the description is omitted because it is the same as FIG.

  Here, the information recorded in the recording unit 36a will be described. FIG. 12A is a diagram showing information in which the operation temperature of the reference memory cell is associated with the gate voltage value, and FIG. 12B is an association of the operation temperature of the reference memory cell and the reference current value. It is a figure which shows the information. As shown in FIG. 12A, the information in which the operating temperature and the gate voltage value are associated with each other is a function indicating the relationship between the operating temperature and the gate voltage value, for example. The gate voltage value at each operating temperature is set to a value such that the reference current value generated in the reference memory cell 14 is equivalent (including not only the same case, but also slightly different but may be considered the same). Has been. For example, the gate voltage value at each operating temperature is set to a value such that a reference current equivalent to the reference current value generated at normal temperature by the reference memory cell 14 is generated.

  As shown in FIG. 12B, the information in which the operating temperature is associated with the reference current value is a function indicating the relationship between the operating temperature and the reference current value, for example. The reference current value at each operating temperature is a value generated when a predetermined value (a constant value) of gate voltage is applied to the reference memory cell 14.

  The information in FIG. 12A and FIG. 12B includes the gate voltage value and the reference current value in the adjustment of the reference current value performed on the reference memory cell 14 in advance, and the temperature gradient obtained from the past evaluation results. And can be obtained from Moreover, you may obtain | require by performing the secondary test in FIG. 9 of Example 1 in several operating temperature.

  Next, control performed before reading, writing, and erasing data with respect to the memory cell 60 will be described. FIG. 13 is a flowchart showing control performed before data reading, writing, and erasing. As shown in FIG. 13, the CPU 46 b applies a gate voltage of a predetermined value (gate voltage value in FIG. 12B) to the reference memory cell 14 to generate a reference current, and the reference current measured by the current measuring unit 28. A value is acquired (step S70).

  Next, the CPU 46b determines whether or not the acquired reference current value is within the standard range (step S72). If it is within the standard range (in the case of Yes), the control is terminated. When it is out of the standard range (in the case of No), the process proceeds to step S74.

  In step S74, the CPU 46b compares the reference current measured by the current measuring unit 28 with the information recorded in the recording unit 36a using the calculation buffer 32a, and determines the operating temperature. For example, the CPU 46b compares the reference current value measured by the current measuring unit 28 with information that associates the operating temperature and the reference current value in FIG.

  Next, the CPU 46b compares the determined operating temperature with the information recorded in the recording unit 36a using the calculation buffer 32a (step S76). For example, the CPU 46b compares the determined operating temperature with information in which the operating temperature and the gate voltage value in FIG.

  Next, the CPU 46b calculates a gate voltage value based on the comparison (step S78). Next, the CPU 46b sets the calculated gate voltage value in the setting register 44, and controls so that the gate voltage of the calculated gate voltage value is applied in the data read, write and erase verify operations (step S80). ). Thereafter, data read, write and erase verify are performed by the same method as that described in FIG. 5 of Comparative Example 1.

  According to the second embodiment, information in which the operating temperature of the reference memory cell 14 is associated with the gate voltage value is recorded in the recording unit 36a. Based on the operating temperature determined by the temperature determination unit (the current measurement unit 28 and the temperature calculation unit 82) and the information recorded in the recording unit 36a, the gate voltage control unit 80a reads, writes, and erases data. Controls the gate voltage value during verification. As a result, as in the first embodiment, it is possible to perform data read, write, and erase verify with appropriate gate voltage values that match the operating temperatures of the memory cell 60 and the reference memory cell 14. Accordingly, variations in cell current values among the plurality of memory cells 60 can be suppressed, data reading accuracy can be improved, data writing or erasing delay can be suppressed, and deterioration in quality can be suppressed.

  As shown in FIG. 12A, the information recorded in the recording unit 36a shows the relationship between the operating temperature of the reference memory cell 14 and the gate voltage value so that the reference current value generated in the reference memory cell 14 is equivalent. It may be the information shown. For example, it may be information indicating the relationship between the operating temperature and the gate voltage value of the reference memory cell 14 that generates a reference current value equivalent to the reference current value generated at normal temperature in the reference memory cell 14. Thereby, when the operating temperature becomes high, the gate voltage can be lowered so that the cell current value and the reference current value do not become too large. Therefore, variations in cell current values among the plurality of memory cells 60 can be suppressed, and deterioration in quality can be suppressed.

  As shown in FIG. 12A, the information indicating the relationship between the operating temperature and the gate voltage value of the reference memory cell 14 is preferably a function indicating the relationship between the operating temperature and the gate voltage value. Thereby, the control of the gate voltage value with respect to the operating temperature can be performed with higher accuracy.

  The temperature determination unit includes a current measurement unit 28 and a temperature calculation unit 82, and may determine the operating temperatures of the memory cell 60 and the reference memory cell 14 based on the reference current value measured by the current measurement unit 28. . For example, information indicating the relationship between the operating temperature of the reference memory cell 14 and the reference current value as shown in FIG. 12B is recorded in the recording unit 36a. Then, the temperature calculation unit 82 may calculate the operating temperature based on the reference current value measured by the current measurement unit 28 and the information recorded in the recording unit 36a. Thereby, since it is not necessary to provide a temperature sensor, the enlargement of an apparatus and the increase in cost can be suppressed. From the viewpoint of calculating the operating temperature with higher accuracy, the information indicating the relationship between the operating temperature of the reference memory cell 14 and the reference current value recorded in the recording unit 36a is a function indicating the relationship between the operating temperature and the reference current value. Preferably there is.

  FIG. 14 is a block diagram illustrating the configuration of the nonvolatile semiconductor memory device according to the third embodiment. As illustrated in FIG. 14, the memory unit 10 c of the nonvolatile semiconductor memory device 300 according to the third embodiment does not include the current measurement unit 28 and the decoder 30, and includes a resistor 90, the thermistor 92, and a temperature calculation unit 94 instead. Further, the temperature calculation unit 82 is not provided in the CPU 46c. The thermistor 92 and the temperature calculation unit 94 function as a temperature determination unit that determines the operating temperatures of the memory cell 60 and the reference memory cell 14.

  The recording unit 36b in the memory cell array 12 records information in which the operating temperature of the reference memory cell 14 is associated with the gate voltage value.

  The operation buffer 32b compares the operating temperature determined by the temperature determination unit with the information recorded in the recording unit 36b under the instruction of the CPU 46c. Then, the operation buffer 32b calculates a gate voltage value based on the comparison and outputs it to the CPU 46c. In addition, the arithmetic buffer 32c outputs to the state machine 16 that the calculation of the gate voltage value is completed.

  The gate voltage control unit 80b uses the calculation buffer 32b to calculate a gate voltage value based on the operating temperature determined by the temperature determination unit and the information recorded in the recording unit 36b. Then, the gate voltage control unit 80b sets the calculated gate voltage value in the setting register 44, and sets the gate voltage value in the data read, write, and erase verification to the memory cell 60 as the calculated gate voltage value.

  The other configuration of the nonvolatile semiconductor memory device 300 according to the third embodiment is the same as that of the nonvolatile semiconductor memory device 200 according to the second embodiment shown in FIG. In the nonvolatile semiconductor memory device 300 according to the third embodiment, a test for adjusting the reference current value is performed in advance for the reference memory cell 14, but the description is omitted because it is the same as FIG. Further, the information recorded in the recording unit 36b is the same as that in FIG.

  Next, control performed before reading, writing, and erasing data with respect to the memory cell 60 will be described. FIG. 15 is a flowchart showing the control performed before reading, writing, and erasing data. As shown in FIG. 15, the CPU 46 c determines the operating temperatures of the memory cell 60 and the reference memory cell 14 by the temperature determination unit including the thermistor 92 and the temperature calculation unit 94 (step S <b> 90).

  Next, the CPU 46c uses the calculation buffer 32b to compare the determined operating temperature with the information recorded in the recording unit 36b (information in FIG. 12A) (step S92).

  Next, the CPU 46c calculates a gate voltage value based on the comparison (step S94). Next, the CPU 46c sets the calculated gate voltage value in the setting register 44, and controls so that the gate voltage of the calculated gate voltage value is applied in the data read, write and erase verify (step S96). ). Thereafter, data reading, and writing and erasure verification are performed by the same method as that described in FIG. 5 of Comparative Example 1.

  As in the third embodiment, the temperature determination unit may include the thermistor 92 and may determine the operating temperatures of the memory cell 60 and the reference memory cell 14 based on the thermistor 92. Thereby, the operating temperature can be determined by a simple method.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

In addition, the following additional notes are disclosed regarding the above description.
(Supplementary Note 1) A plurality of memory cells to which data is written, a reference memory cell, a current measuring unit for measuring a reference current value generated in the reference memory cell, and a reference current for each of a plurality of operating temperatures of the reference memory cell A recording unit that records information in which a value and a gate voltage value are associated with each other, and reads out data from the memory cell based on the reference current value measured by the current measuring unit and the information recorded in the recording unit And a gate voltage control unit for controlling a gate voltage value applied to the memory cell and the reference memory cell at the time of verifying writing and erasing.
(Supplementary Note 2) Among the information recorded in the recording unit, the reference current value of each of the plurality of operating temperatures is the gate voltage of the gate voltage value at the reference temperature included in the plurality of operating temperatures. The gate voltage value at each of the plurality of operating temperatures is a gate voltage value when a reference current equivalent to the reference current value at the reference temperature is generated. The nonvolatile semiconductor memory device according to appendix 1.
(Additional remark 3) The said gate voltage control part respond | corresponds to the reference current value nearest to the reference current value measured by the said current measurement part among the said some reference current values contained in the said information recorded on the said recording part. The nonvolatile semiconductor memory device according to appendix 1 or 2, wherein the non-volatile semiconductor memory device is controlled to a gate voltage value.
(Supplementary Note 4) A plurality of memory cells to which data is written, a reference memory cell, a temperature determination unit that determines an operating temperature of the memory cell and the reference memory cell, an operating temperature and a gate voltage value of the reference memory cell, And reading and writing data to and from the memory cell based on the recording unit for recording the first information indicating the relationship between the operating temperature determined by the temperature determination unit and the first information recorded in the recording unit. And a gate voltage control unit for controlling a gate voltage value applied to the memory cell and the reference memory cell at the time of erase verify.
(Supplementary Note 5) The first information recorded in the recording unit is information indicating a relationship between an operating temperature and a gate voltage value of the reference memory cell so that a reference current value generated in the reference memory cell is equivalent. The nonvolatile semiconductor memory device according to appendix 4, wherein:
(Supplementary note 6) The nonvolatile semiconductor according to Supplementary note 4 or 5, wherein the first information recorded in the recording unit is a function indicating a relationship between an operating temperature of the reference memory cell and a gate voltage value. Storage device.
(Supplementary Note 7) The temperature determination unit includes a current measurement unit that measures a reference current value generated in the reference memory cell, and a temperature calculation unit that calculates the operating temperature based on the reference current value measured by the current measurement unit. The nonvolatile semiconductor memory device according to any one of appendices 4 to 6, further comprising:
(Additional remark 8) The said recording part records the 2nd information which shows the relationship between the operating temperature of the said reference memory cell, and a reference current value, The said temperature calculation part is the reference current value measured by the said current measurement part, and the said The nonvolatile semiconductor memory device according to appendix 7, wherein the operating temperature is calculated based on the second information recorded in the recording unit.
(Supplementary Note 9) The second information recorded in the recording unit is information indicating a relationship between an operating temperature of the reference memory cell and a reference current value when a gate voltage value is constant. 9. The nonvolatile semiconductor memory device according to 8.
(Supplementary note 10) The nonvolatile semiconductor according to Supplementary note 8 or 9, wherein the second information recorded in the recording unit is a function indicating a relationship between an operating temperature of the reference memory cell and a reference current value. Storage device.
(Additional remark 11) The said temperature determination part is a non-volatile semiconductor memory device as described in any one of additional marks 4-6 characterized by including a thermistor.
(Supplementary note 12) The nonvolatile semiconductor memory device according to any one of Supplementary notes 1 to 11, wherein the recording unit is in a non-rewritable region in a memory cell array provided with the plurality of memory cells.
(Supplementary Note 13) A method for controlling a nonvolatile semiconductor memory device including a plurality of memory cells to which data is written and a reference memory cell, wherein a reference current value generated in the reference memory cell is acquired and the acquired reference Based on the current value and the information recorded in the recording unit and corresponding to the reference current value and the gate voltage value for each of the plurality of operating temperatures of the reference memory cell, reading and writing data to the memory cell And a gate voltage value applied to the memory cell and the reference memory cell at the time of verifying erase, and a control method for a nonvolatile semiconductor memory device,
(Supplementary note 14) A method for controlling a nonvolatile semiconductor memory device including a plurality of memory cells to which data is written and a reference memory cell, wherein operating temperatures of the memory cell and the reference memory cell are determined and determined Based on the operating temperature and the information that associates the operating temperature and the gate voltage value of the reference memory cell recorded in the recording unit, when reading data from the memory cell and verifying writing and erasing A control method of a nonvolatile semiconductor memory device, wherein a gate voltage value applied to the memory cell and the reference memory cell is controlled.
(Supplementary Note 15) A plurality of memory cells to which data is written, a reference memory cell, and gate voltage values applied to the memory cell and the reference memory cell at the time of verifying data reading, writing, and erasing from the memory cell A non-volatile semiconductor memory device comprising: a gate voltage control unit that controls a reference current value generated in the reference memory cell based on information recorded in the recording unit; When the reference current value generated in the operating reference memory cell is the first reference current value within a predetermined standard range, the first gate voltage value applied to the reference memory cell and the first reference current value are A step of recording in the recording unit as information, and the first operating temperature. A second gate voltage value at which a reference current value generated in the reference memory cell operating at a different second operating temperature is equivalent to the first reference current value; and the reference memory cell operating at the second operating temperature. And a second reference current value generated when a first gate voltage value is applied, recorded in the recording unit as the information. A method for manufacturing a nonvolatile semiconductor memory device, comprising:

10 to 10c Memory unit 12 Memory cell array 14 Reference memory cell 28 Current measurement unit 32 to 32b Operation buffer 36 to 36b Recording unit 40 to 40c Logic unit 46 to 46c CPU
60 Memory Cell 80-80b Gate Voltage Control Unit 82 Temperature Calculation Unit 92 Thermistor 94 Temperature Calculation Unit

Claims (5)

A plurality of memory cells into which data is written;
A reference memory cell;
A current measuring unit for measuring a reference current value generated in the reference memory cell;
A recording unit for recording information in which a reference current value and a gate voltage value are associated with each other for each of a plurality of operating temperatures of the reference memory cell;
Based on the reference current value measured by the current measuring unit and the information recorded in the recording unit, the memory cell and the reference memory cell at the time of verifying data read, write and erase to the memory cell And a gate voltage control unit for controlling a gate voltage value applied to the non-volatile semiconductor memory device.   Of the information recorded in the recording unit, the reference current value of each of the plurality of operating temperatures is generated when a gate voltage of the gate voltage value at a reference temperature included in the plurality of operating temperatures is applied. 2. The reference current value, and the gate voltage value of each of the plurality of operating temperatures is a gate voltage value when a reference current equivalent to the reference current value at the reference temperature is generated. The nonvolatile semiconductor memory device described.   The gate voltage control unit has a gate voltage value corresponding to a reference current value closest to a reference current value measured by the current measurement unit among the plurality of reference current values included in the information recorded in the recording unit. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is controlled. The recording unit includes a non-volatile semiconductor memory device as described in any one of claims 1 to 3, characterized in that the region of non-rewritable in said plurality of memory cell array in which memory cells are provided. A method for controlling a nonvolatile semiconductor memory device comprising a plurality of memory cells to which data is written and a reference memory cell,
Obtain a reference current value generated in the reference memory cell,
Based on the acquired reference current value and the information recorded in the recording unit and associated with the reference current value and the gate voltage value for each of the plurality of operating temperatures of the reference memory cell, data is read from the memory cell. And a control method for a nonvolatile semiconductor memory device, wherein a gate voltage value applied to the memory cell and the reference memory cell at the time of verifying writing and erasing is controlled.

Images