JP6344135B2 - Error detection code generation circuit, error detection code generation method, and format conversion apparatus - Google Patents

Description

  The present invention relates to an error detection code generation circuit, an error detection code generation method, and a format conversion apparatus.

  Since errors may occur in the binary floating point format, operations are performed in decimal floating point in financial calculations. A BCD (Binary Coded Decimal) format is widely used as a decimal number representation. However, since the BCD format expresses one decimal digit by a 4-bit binary number, only 10 numerical values (0-9) are used among 16 types of numerical values that can be expressed by 4 bits. Therefore, in the BCD format, for example, 64 bits can represent only 64 ÷ 4 bits = 16-digit decimal numbers, and the amount of data increases with respect to the number of decimal digits that can be represented.

  Therefore, in recent years, the IEEE Standard for Floating-Point Arithmetic (IEEE Std 754-2008) has proposed a DPD (Densely-Packed Decimal) format that compresses and stores decimal numbers in BCD format. ing. In the case of the DPD format, as will be described later, three decimal digits (0-999) are represented by 10-bit binary numbers. There are 1024 numerical values that can be expressed in 10 bits, but 1000 of them are used, so the bit utilization efficiency is higher than in the BCD format.

  However, in the DPD format, the 12-bit (1 digit 4 bits) BCD format that expresses 3 decimal digits is converted to the 10-bit DPD format by special encoding, so it cannot be operated in the DPD format. Or difficult. Therefore, it is stored in memory or transmitted in compressed DPD format, but after reading or receiving from memory, it is converted from DPD format to BCD format, decimal operation is performed in BCD format, and BCD format of the operation result Is converted back to DPD format.

  Therefore, it is proposed to generate an error detection code for DPD-format decimal floating-point data, store the error detection code in DPD-format decimal floating-point data, and send it. Has been. For example, the following patent documents.

JP 2014-38413 A

  As described above, the BCD-format decimal floating point number obtained as a result of the operation is format-converted to the DPD format, and the converted DPD-format decimal floating-point number is stored in the memory or transmitted. Therefore, an error detection code is generated by performing a logical operation on the converted decimal floating point number in the DPD format, and stored in a memory or transmitted together with the decimal floating point number in the DPD format.

  However, if the format conversion calculation from the BCD format to the DPD format and the error detection code generation calculation of the data in the DPD format are performed, the number of stages of the arithmetic circuit becomes long, which hinders high-speed processing. Also, if an error detection code is generated by calculating the DPD format data after format conversion, if an error occurs in the format conversion circuit, the error detection code generated from the DPD format data that includes the error Cannot be detected.

  Accordingly, an object of the embodiment is to provide an error detection code generation circuit, an error detection code generation method, and a format conversion device having a format conversion circuit for speeding up an arithmetic circuit.

The error detection code generation circuit according to the first aspect of the embodiment has 12 bits assigned to 3 decimal digits included in decimal data of the first format that expresses a number from 0 to 9 in 4 bits. A plurality of first XOR generation circuits each generating a first XOR bit for
A second XOR generation circuit for generating a second XOR bit for four bits allocated to one decimal digit included in the decimal data in the first format;
The first XOR bit, the second XOR bit, the sign bit, and the third XOR bit for the exponent bit are represented by 10 bits converted from the decimal data of the first format to represent three decimal digits. A third XOR generation circuit for generating XOR bits for error detection of decimal data in the second format
The error detection XOR bit and the modulo 3 of the decimal data in the first format are output as redundant data for error detection of the decimal data in the second format.

  The arithmetic circuit can be speeded up. The reliability of the error detection code can be improved.

It is a figure for demonstrating the decimal floating point number of a DPD format. 6 is a diagram illustrating encoding of upper 5 bits GU of a combination field G. FIG. It is a figure which shows the conversion method from the 10-bit set declet (b [9: 0]) of a DPD format to the decimal number (100 * h + 10 * t + o) of a BCD format. It is a figure which shows the conversion method from the decimal number (100 * h + 10 * t + o) of a BCD format to the 10-bit set declet (b [9: 0]) of a DPD format. It is a figure which shows the single precision and double precision format of a DPD format. It is a whole block diagram of the redundant data generation circuit for RAS of DPD. 5 is a diagram showing a configuration of a pgu and pgl generation circuit 601. FIG. 5 is a diagram showing a configuration of a pgu generation circuit 801 in the pgu and pgl generation circuit 601. FIG. 3 is a configuration diagram of a pt generation circuit 602. FIG. pd # generation circuit for generating redundant data for RAS having mod3 data ptY [1: 0] of data D0 [9: 0] -D4 [9: 0] of each declet in the pt generation circuit 602 and xor data ptX It is a block diagram. It is a figure which shows an example of utilization of a DPD format and a BCD format. It is a figure which shows the format conversion apparatus which has the error detection code generation circuit in this Embodiment. It is a figure which shows the format conversion apparatus which has the error detection code generation circuit in this Embodiment. 2 is a diagram showing a RAS redundant data generation circuit 12. FIG. It is a figure which shows the format of the data of a BCD format. It is a figure which shows the logic circuit of pd (i) production | generation circuits 12_0-12_4. It is a figure which shows the logic circuit of pd (5) generation circuit 12_5.

Hereinafter, in the case of a binary number, in order to distinguish it from a decimal number, a subscript 2 may be added to the end of the binary bit string. For example, it referred to as 11111 _2.

  Before describing this embodiment, the relationship between the BCD format and the DPD format, and an error detection code generation circuit for data in the DPD format will be described.

[BCD format]
In the BCD format, one decimal digit is expressed as a 4-bit binary number. For example, in the case of a 3-digit decimal number 100 × h + 10 × t + o, the 100's place is represented by h [3: 0], the 10's place is represented by t [3: 0], and the 1's place is represented by o [3: 0]. . Therefore, a 3-digit decimal number is expressed by a total of 12 bits, each of a 4-bit number h [3: 0], t [3: 0], and o [3: 0]. Therefore, in the case of the BCD format, a 16-digit decimal number is expressed by 64 bits.

  By adding a sign bit and exponent data to a decimal number in BCD format, it can be encoded into a decimal floating point number in DPD format.

[DPD format]
FIGS. 1A to 1C are diagrams for explaining decimal floating point numbers in the DPD format. 1A is a diagram showing the bit length of a decimal floating point number in the DPD format, and FIG. 1B is a diagram showing the format of a decimal floating point number in the single precision DPD format. (C) is a diagram showing a format of a decimal floating point number in a double precision DPD format.

  The DPD format decimal floating point number includes a sign field S, a combination field G, and a trailing mantissa field T. A DPD-format decimal floating point number is represented by a sign S (0 or 1), an exponent exponent and a mantissa significand, and represents a value represented by the following expression.

  The exponent exponent is stored in the combination field G, and the mantissa significand is stored in the combination field G and the subsequent mantissa field T.

  As shown in FIGS. 1A and 1B, a single-precision decimal floating point number has a 1-bit code field S, an 11-bit combination field G, and a 20-bit trailing mantissa field T. The total data length is 32 bits. The 11-bit combination field G has a 5-bit upper bit GU [4: 0] and a w (= 6) -bit lower bit GL [w-1: 0].

  As shown in FIG. 2C, the double-precision decimal floating point number has a 1-bit sign field S, a 13-bit combination field G, and a 50-bit trailing mantissa field T, and has a total data length. Is 64 bits. The 13-bit combination field G has a 5-bit upper bit GU [4: 0] and a w (= 8) -bit lower bit GL [w-1: 0].

  The code S is stored in the code field S. The exponent exponent is stored in a part of the combination field G. The mantissa significand is divided and stored in a part of the combination field G and a subsequent mantissa field T.

  FIG. 2 is a diagram showing the encoding of the upper 5 bits GU of the combination field G. The combination field G is divided into five upper bits GU [4: 0] and w lower bits GL [w-1: 0]. As shown in FIG. 2, two pieces of information, that is, the upper 2 bits of the exponent part and the leftmost digit (LMD) of the mantissa part are stored in the 5 upper bits GU [4: 0].

In FIG. 2, GU [4: 0] = 11111 For _{2, GL [w-1]} = 1 if non number SNaN, shows a-number QNaN if GL [w-1] = 0 , GL [w-2 : 0] becomes don't care. The non-number QNaN is a non-number of calculation results that are output when calculations such as ± 0 ÷ ± 0, ± ∞ ÷ ± ∞, √ (−1) are performed. The non-number SNaN is a non-number that is used, for example, when a user or software dares to prepare a bug detection trigger. When a non-number SNaN is input to a normal operation (for example, four arithmetic operations), an invalid exception is issued. Is reported. On the other hand, when a non-number QNaN is input, the calculation result outputs a non-number QNaN according to each calculation specification, and unlike the case of a non-number SNaN, an invalid exception is not caused. The subsequent mantissa field T becomes a payload indicating diagnostic information of non-number QNaN or SNaN.

GU [4: 0] = 11110 For ₂ shows a + ∞ or -∞. In this case, GL [w-1: 0] becomes don't care.

GU [4: 0] = 1110x case of ₂ or 110Xx ₂ (either x is 1 or 0), GU [2: 1 ] indicates the exponent upper 2 bits, 8 + GU [0] in the mantissa most significant digit LMD 8 or 9 is indicated. In this case, the upper 2 bits of the exponent part are any one of GU [2: 1] = 00 ₂ , 01 ₂ , 10 ₂ , and the most significant digit LMD of the mantissa part is set to 8 when GU [0] = 0. If 0] = 1, it becomes 9. The lower bits GL [w-1: 0] indicate the lower bits of the exponent part.

On the other hand, when GU [4: 0] = 10xxxx ₂ or 0xxxx ₂ , the meaning of the GU bit is different from the above, GU [4: 3] indicates the upper 2 bits of the exponent part, and GU [2: 0] The most significant digit LMD 0-7 is shown. In this case, the upper 2 bits of the exponent part are any one of GU [4: 3] = 00 ₂ , 01 ₂ , and 10 ₂ , and the most significant digit LMD of the mantissa part is a 3-bit binary number of GU [2: 0]. It will be one of 0-7. The lower bits GL [w-1: 0] indicate the lower bits of the exponent part.

Therefore, the most significant digit of the mantissa part is zero in the case of the lowermost stage in FIG. 2 when the upper bits GU [4: 0] are any one of 00000 ₂ , 01000 ₂ , and 10000 _2. Zero is represented by 3 bits. Therefore, the decimal number “+0” is S = 0, T = 0, and the upper bits GU [4: 0] are any one of 00000 ₂ , 01000 ₂ , and 10000 ₂ . That is, there are zero variations (cohorts) corresponding to the 3 patterns of 2 bits GU [4: 3] and the bit width w of the lower bits GL [w-1: 0].

  As described above, according to the code of the upper bits GU [4: 0] of the combination field G, the non-numeric NaN information is displayed, or the upper 2 bits of the exponent part and the most significant digit and the lower bit of the mantissa part are displayed in different formats. . By such encoding, the combination field G = GU, GL is used to express more information with a smaller number of bits.

  Next, the subsequent mantissa field T will be described. In the subsequent mantissa field T, a plurality of 10-bit sets declet are connected. As shown in FIG. 1A, a 20-bit trailing mantissa field T has two 10-bit sets declet in single precision, and a 50-bit trailing mantissa field T has five 10 bits in double precision. It has a set of bits declet. Each 10-bit set declet represents a 3-digit decimal number from 0 to 999. As shown in FIG. 1A, in the single precision, the trailing mantissa field T can represent a decimal number of 3 digits × 2 pairs = 6 digits, and in the double precision, the trailing mantissa field T has 3 digits × 5 pairs. = A decimal number of 15 digits can be expressed.

[Conversion between DPD format and BCD format]
FIG. 3 is a diagram showing a conversion method from a 10-bit set declet (b [9: 0]) in the DPD format to a 3-digit decimal number (100 × h + 10 × t + o) in the BCD format. FIG. 4 is a diagram showing a conversion method from a three-digit decimal number (100 × h + 10 × t + o) in the BCD format to a 10-bit set declet (b [9: 0]) in the DPD format. Here, a 10-bit set declet is represented by 10-bit b [9: 0], and a 3-digit decimal number is represented by “100 × h + 10 × t + o”. h is 4-bit data h [3: 0] representing hundreds. t is 4-bit t [3: 0] data representing the tens place. o is 4-bit o [3: 0] data representing the one's place. Hereinafter, the above b, h, t, and o are represented as bi.

  Note that the first to eighth lines in FIG. 4 correspond to the first, second, third, seventh, fourth, sixth, fifth, and eighth lines in FIG.

  As described above, the number that can be represented by 10 bits of b [9: 0] in the DPD format is 1024 types, and the number that can be represented by a 3-digit decimal number is 1000 types, which are different. N sets of 10-bit sets declet, b [9: 0] correspond to 3N-digit decimal numbers.

  In the DPD format compression method shown in FIGS. 3 and 4, when the decimal value of a BCD format is 8 or more that cannot be expressed in 3-bit binary, only 8 or 9 is used. When the decimal digit of BCD format is 8 or 9, only the binary least significant digit of 8 or 9 digit is included in 10-bit b [9: 0], and the number of bits is set. Saving.

A specific description of the compression method is as follows.
(1) When all three digits of the BCD format are 0-7, DPD b [3] = 0 is set, and the following correspondence is obtained.
B [9: 7] of DPD = h [2: 0] of BCD
B [6: 4] of DPD = t [2: 0] of BCD
B [2: 0] of DPD = o [2: 0] of BCD

(2) If one of the three digits in the BCD format is 8 or 9, set DPD b [3] = 1 to indicate which digit is 8 or 9 in DPD b [2,1]. . And it becomes the following correspondence.
When the 1's place of BCD is 8 or 9, b [0] = 0,1 of DPD and 8,9 of BCD (8 + b [0])
When the tens place of BCD is 8 or 9, b [4] of DPD = 0, 1 and 8,9 of BCD (8 + b [4])
When the hundreds of BCD is 8 or 9, b [7] of DPD = 0,1 and 8,9 of BCD (8 + b [7])

  (3) If multiple digits of the 3 digits in the BCD format are 8 or 9, set b [3,2,1] = 111 in DPD, and which 2 digits or 3 digits are in b [6,5] in DPD Indicates whether it will be 8 or 9. The correspondence between BCD 8 or 9 digits and DPD is the same as above.

  (4) The positions of BCD format 0-7 and DPD format bits when there are 8 or 9 digits in the BCD format are as shown in FIGS.

[Error detection code of decimal floating point number in DPD format]
Since the amount of data can be compressed by using the DPD format, an error detection code is calculated from a decimal floating point number in the DPD format, and stored in the memory together with the error detection code or transmitted. Therefore, Patent Document 1 described above describes a circuit for generating an error detection code of a decimal floating point number in the DPD format.

  This error detection code is a kind of redundant data for RAS (Reliability, Availability and Serviceability). Therefore, the error detection code is hereinafter referred to as RAS redundant data.

  Redundant data for RAS is generated by logically operating decimal floating point data in DPD format. Redundant data for RAS consists of the modulo 3 of the mantissa part of the decimal floating-point number (the remainder after dividing by 3; hereinafter referred to as mod3,% 3) and the XOR value for detecting errors that cannot be detected with mod3 data (exclusive Logical sum, hereinafter referred to as xor). In general, whenever one bit of a binary number changes, its mod3 data also changes. Therefore, mod3 data is an effective RAS redundancy code for detecting the presence of a 1-bit error. However, since the DPD format has a sign bit, an exponent, and a mantissa, there is a 1-bit error that cannot be detected only by mod3 data. Therefore, the XOR bit of a predetermined bit is added to mod3 data to form redundant data for RAS.

  The mod3 data in the mantissa part of the decimal floating point number in the DPD format matches the decimal mod3 data in the BCD format. In this way, when the BCD format is converted to the DPD format, the mod3 data included as redundant data for RAS in the BDC format can be used as mod3 data for redundant data for RAS in the DPD format. Therefore, the circuit that generates redundant data for RAS in the DPD format generates the above mod3 data based on the DPD format.

  Furthermore, when converting decimal data in BCD format to decimal floating point data in DPD format, the sign bit and exponent bit included in the DPD format are added to the decimal data in BCD format and input to the format conversion circuit. To do. The sign bit and exponent bit added to the input by format conversion are included in the converted DPD format data as they are. In addition, the decimal number in the mantissa part of the DPD format and the decimal number in the BCD format naturally match. However, the same decimal number is encoded based on both formats.

  FIG. 5 is a diagram showing the single precision and double precision formats of the DPD format. In the case of single precision, the subsequent mantissa field T has two sets of declet, b [11: 0]. In the case of double precision, the subsequent mantissa field T has 5 sets of declet, b [11: 0]. Further, the upper bits GU [4: 0] of the combination field are both 5 bits, and the lower bits GL [w−1: 0] are 6 bits for single precision and 8 bits for double precision. The most significant digit LMD of the mantissa part is encoded in the higher order bits GU [4: 0].

[Redundant data generation circuit for DPD RAS]
FIG. 6 is an overall configuration diagram of a DPD RAS redundant data generation circuit. The RAS redundant data generation circuit 112 generates RAS redundant data p [2: 0] from the DPD-format floating point number stored in the register 111. The 3-bit redundant data p [2: 0] for RAS has an xor bit p [2] and a mod3 bit p [1: 0]. Hereinafter, in FIG. 6, the case of double precision is shown as an example, but the same applies to the case of single precision.

As a premise, it is defined as follows.
The operation symbol ^ indicates xor.
The operation symbol x% 3 represents xmod3 and is the remainder of dividing x by 3.
(1) The redundant data ps for RAS of the sign bit S is ps = S.
(2) The RAS redundant data pgu of the upper bits GU of the combination field G has xor bits of pguX (1 bit) and mod3 bits of pguY [1, 0] (2 bits).
(3) The RAS redundant data pgl of the lower bits GL is only xor bits of pglX (1 bit).
(4) The RAS redundant data pt of the subsequent mantissa field T has ptY [1: 0] obtained by combining xor bits of ptX and mod3 bits of each declet.

The logical expression of the RAS redundant data generation circuit 112 is as follows. The RAS redundant data generated by the following logical expressions corresponds to the RAS redundant data (1) to (4) described above.
(1) ps (1 bit)
ps = S
(2) pgu: pguX (1bit), pguY [1,0] (Fig. 8)
(2-1) When GU [4: 1] = 1111 ₂ , pguX = GU [4] ^ GU [3] ^ GU [2] ^ GU [1] ^ GU [0]
pguY [1,0] = 0
(2-2) When GU [4: 1] = 1110 ₂ or 110x ₂ , pguX = GU [4] ^ GU [3] ^ GU [2] ^ GU [1]
pguY [1,0] = (2 + GU [0])% 3
(2-3) When GU [4: 1] = 10xx ₂ or 0xxx ₂ , pguX = GU [4] ^ GU [3] ^ GU [2] ^ GU [1]
pguY [1,0] = (2 * GU [1] + GU [2] + GU [0])% 3
(3) pgl: pglX (1bit)
pglX = GL [w-1] ^ GL [w-2] ^ ... ^ GL [1] ^ GL [0] (Figure 7)
(4) pt: ptX (1 bit), ptY [1,0] to ptY [13: 0] (FIGS. 9 and 10)
The T field consists of two declets for single precision and five declets for double precision. pt is completed by further processing the redundant data for RAS calculated in declet units. A method of generating one declet redundant data for RAS (= pd (pdX, pdY)) is as follows.
e-1) pd: pdX (1bit), pdY [1,0] (Fig. 10)
The 10 bits of the declet are b [9: 0].
(4-1) pdX = b [6] ^ b [5] ^ b [3] ^ b [2] ^ b [1]
(4-2) When b [6,5,3: 1] = xx0xx ₂ , xx101 ₂ ,, 10111 ₂ (lines 1, 3 and 7 in Fig. 3)
pdY [1,0] = {2 * (b [8] + b [5] + b [1]) + b [9] + b [7] + b [6] + b [4] + b [2 ] + b [0]}% 3
(4-3) When b [6,5,3: 1] = xx100 ₂ , 01111 ₂ (lines 2 and 6 in Fig. 3)
pdY [1,0] = {2 * (b [8] + b [5] + b [1]) + b [9] + b [7] + b [6] + b [4] + b [2 ] + b [0] + 2}% 3
(4-4) When b [6,5,3: 1] = xx110 ₂ , 00111 ₂ (lines 4 and 5 in FIG. 3)
pdY [1,0] = {2 * (b [8] + b [5] + b [1]) + b [9] + b [7] + b [6] + b [4] + b [2 ] + b [0] + 1}% 3
(4-5) When b [6,5,3: 1] = 11111 ₂ (8 lines in FIG. 3)
pdY [1,0] = {2 * (b [5] + b [1]) + b [7] + b [6] + b [4] + b [2] + b [0]}% 3
In the above, b [6,5,3: 1] = 11111 2 when b [9, 8] becomes do not care data. Therefore, in the above method b [6,5,3: 1] = 11111 b at ₂ [9, 8] PDY as garbled data does not detect the error to occur in the 1: 0] of the calculation formula b [9,8] is not included. If you want to detect this as an error too, only when b [6,5,3: 1] = 11111 ₂ pdX = b [9] ^ b [8] ^ b [6] ^ b [5] ^ b [ 3] ^ b [2] ^ b [1] and pdX calculation method are changed.

  In the above equation (4-1), pdX is the xor data of b [6], b [5], b [3], b [2], b [1]. This xor data is xor data necessary for detecting error bits that cannot be detected by mod3.

  Further, pdY [1,0] obtained by the above arithmetic expressions (4-2) to (4-5) is a remainder obtained by dividing the value obtained by converting declet into a 3-digit decimal number by 3 (= modulo 3 = Mod3 =% 3). The 3-digit decimal number mod3 is equivalent to the addition of the 3-digit number mod3. Then, +2, +1 in the arithmetic expressions (4-3) and (4-4) are values obtained based on the code embedded in the data in the DPD format. The arithmetic expressions (4-2) to (4-5) will be briefly described below.

The modulo 3 in the first line in FIG. 4 (the first line in FIG. 3) is as follows.
pdY [1,0] = {(4 * b [9] + 2 * b [8] + b [7]) + (4 * b [6] + 2 * b [5] + b [4]) + (4 * b [2] + 2 * b [1] + b [0])}% 3
Here, since (4 * b)% 3 = b% 3, the above arithmetic expression is the same as (4-2) as follows.
pdY [1,0] = {(b [9] + 2 * b [8] + b [7]) + (b [6] + 2 * b [5] + b [4]) + (b [2 ] + 2 * b [1] + b [0])}% 3
= {2 * (b [8] + b [5] + b [1]) + b [9] + b [7] + b [6] + b [4] + b [2] + b [0] }% 3
In the second line of FIG. 4 (second line of FIG. 3), the 1's place is 8 or 9, so modulo 3 is
pdY [1,0] = {(4 * b [9] + 2 * b [8] + b [7]) + (4 * b [6] + 2 * b [5] + b [4]) + (8 + b [0])}% 3
Here, (4 * b)% 3 = b% 3, 8% 3 = 2%, so the above equation is as follows.
pdY [1,0] = {(b [9] + 2 * b [8] + b [7]) + (b [6] + 2 * b [5] + b [4]) + (2 + b [0])}% 3
= {2 * (b [8] + b [5]) + b [9] + b [7] + b [6] + b [4] + b [0] + 2}% 3
Since b [6,5,3,2,1] = xx100, substituting b [2] = 0 and b [1] = 0 into the equation (4-3) agrees with the above equation .

In the third row of FIG. 4 (third row of FIG. 3), the tenth place is 8 or 9, and the first place is represented by b [6] b [5] b [0]. It can be modified as follows.
pdY [1,0] = ((4 * b [9] + 2 * b [8] + b [7]) + (8 + b [4]) + (4 * b [6] + 2 * b [ 5] + b [0])}% 3
= {(b [9] + 2 * b [8] + b [7]) + (2 + b [4]) + (b [6] + 2 * b [5] + b [0])}% Three
= {2 * (b [8] + b [5]) + b [9] + b [7] + b [6] + b [4] + b [0] + 2}% 3
Since b [6,5,3,2,1] = xx101, substituting b [2] = 0, 2 * b [1] = 2 into the equation (4-2) Match.

In the fourth line of FIG. 4 (the seventh line of FIG. 3), the place of 10,1 is 8 or 9, so the modulo 3 can be modified as follows.
pdY [1,0] = {(4 * b [9] + 2 * b [8] + b [7]) + (8 + b [4]) + (8 + b [0])}% 3
= {(b [9] + 2 * b [8] + b [7]) + (2 + b [4]) + (2 + b [0])}% 3
= {2 * b [8] + b [9] + b [7] + b [4] + b [0] + 4}% 3
Since b [6,5,3,2,1] = 10111, b [6] = 1, 2 * b [5] = 0, b [2] = 1, 2 in (4-2) Substituting * b [1] = 2 matches the above formula.

In the fifth line of FIG. 4 (the fourth line of FIG. 3), the modulo 3 can be modified as follows because the hundreds place is 8 or 9.
pdY [1,0] = {(8 + b [7]) + (4 * b [6] + 2 * b [5] + b [4]) + (4 * b [9] + 2 * b [ 8] + b [0])}% 3
= {(2 + b [7]) + (b [6] + 2 * b [5] + b [4]) + (b [9] + 2 * b [8] + b [0])}% Three
= {2 * (b [8] + b [5]) + b [9] + b [7] + b [6] + b [4] + b [0] + 1}% 3
And since b [6,5,3,2,1] = xx110, substituting b [2] = 1, 2 * b [1] = 0 into (4-4) agrees with the above equation .

Since the sixth line of FIG. 4 (the sixth line of FIG. 3) is 100 or 1 is 8 or 9, the modulo 3 can be modified as follows.
pdY [1,0] = {(8 + b [7]) + (4 * b [9] + 2 * b [8] + b [4]) + (8 + b [0])}% 3
= {(2 + b [7]) + (b [9] + 2 * b [8] + b [4]) + (2 + b [0])}% 3
= {2 * b [8] + b [9] + b [7] + b [4] + b [0] + 4}% 3
Since b [6,5,3,2,1] = 01111, b [6] = 0, 2 * b [5] = 2, b [2] = 1, 2 in (4-3) Substituting * b [1] = 2 matches the above formula. Note that 7% 3 = 4% 3 = 1.

Since the 7th line in FIG. 4 (the 5th line in FIG. 3) has the positions of 100 and 10 being 8 or 9, the modulo 3 can be modified as follows.
pdY [1,0] = {(8 + b [7]) + (8 + b [4]) + (4 * b [9] + 2 * b [8] + b [0])}% 3
= {(2 + b [7]) + (2 + b [4]) + (b [9] + 2 * b [8] + b [0])}% 3
= {2 * b [8] + b [9] + b [7] + b [4] + b [0] + 4}% 3
Since b [6,5,3,2,1] = 00111, b [6] = 0, 2 * b [5] = 0, b [2] = 1, 2 in (4-4) Substituting * b [1] = 2 matches the above formula.

Finally, since the 8th line in FIG. 4 (the 8th line in FIG. 3) has the positions of 100, 10, 1 being 8 or 9, the modulo 3 can be modified as follows.
pdY [1,0] = {(8 + b [7]) + (8 + b [4]) + (8 + b [0])}% 3
= {(2 + b [7]) + (2 + b [4]) + (2 + b [0])}% 3
= {b [7] + b [4] + b [0] + 6}% 3
Since b [6,5,3,2,1] = 11111, b [6] = 1, 2 * b [5] = 2, b [2] = 1, 2 in (4-5) Substituting * b [1] = 2 matches the above formula.

  Next, the RAS redundant data generation circuit 112 will be described based on the above arithmetic expression. First, the RAS redundant data generation circuit 112 includes a pgu and pgl generation circuit 601, a pt generation circuit 602, a modulo operation circuit 603, and an XOR operation circuit 604.

  The pgu and pgl generation circuit 601 performs a modulo operation on the upper bits GU of the combination field G, outputs mod3 bits of pguY [1: 0], and performs an XOR operation on the upper bits GU and the lower bits GL. , 1-bit xor data pgX is output.

  The pt generation circuit 602 performs an XOR operation and a modulo operation on five sets of declet data D0 “9: 0” to D4 [9: 0] of the subsequent mantissa field T, thereby obtaining 1-bit xor data ptX and 2 Bit mod3 data ptY [1: 0] is output.

  The modulo arithmetic circuit 603 generates pguY [1: 0], which is mod3 data of the upper bit GU generated by the pgu and pgl generation circuit 601, and ptY [, which is mod3 data of the subsequent mantissa field T generated by the pt generation circuit 602. 1: 0] is modulo-calculated to output 2-bit mod3 data p [1: 0].

  On the other hand, the XOR operation circuit 604 performs an XOR operation of the RAS redundant data ps of the code field S, the xor data pgX generated by the pgu and pgl generation circuit 601 and the xor data ptX generated by the pt generation circuit 602. Outputs p [2] which is xor data.

  Note that pguY [1: 0] is treated as pguY [1: 0] = 2 × pguY [1] + pguY [0] in mod3 data, which is 2-bit data. The same applies hereinafter. As described above, the RAS redundant data generation circuit 112 synthesizes the 1-bit xor data p [2] and the 2-bit mod3 data p [1: 0] to generate the 3-bit data p [2: 0] as an error. Output as detection code.

  FIG. 7 is a diagram showing the configuration of the pgu and pgl generation circuit 601. As shown in FIG. FIG. 8 is a diagram showing a configuration of the pgu generation circuit 801 in the pgu and pgl generation circuit 601. The logical expressions of the pgu and pgl generation circuit 601 are as described in (2) (2-1)-(2-3) and (3) above.

  The pgu and pgl generation circuit 601 includes a pgu generation circuit 801 and XOR operation circuits 802 and 803. The pgu generation circuit 801 performs a modulo operation on the upper bits GU [4: 0] and outputs 2-bit data pguY [1: 0] and 1-bit data pguX. The XOR operation circuit 802 performs an XOR operation on each bit of the lower bits GL [w−1: 0] of w bits as shown in the logical expression (3), and outputs 1-bit xor data pglX. The XOR circuit 803 performs an XOR operation on the xor data pguX of the upper bit GU and the xor bit pgX of the lower bit GL, and outputs 1-bit xor data pgx. The pgu and pgl generation circuit 601 outputs 2-bit mod3 data pguY [1: 0] of the upper bit GU and 1-bit data pgX of the upper bit GU and the lower bit GL.

  FIG. 8 is a diagram showing a configuration of the pgu generation circuit 801 in FIG. The description will be made in association with the above logical expressions (2-1)-(2-3).

(2-1) Combination field G upper bits GU in the 4: 0], as shown in FIG. 2, GU [4: 0 '= 11111 If ₂ or 11110 _2-a-number (NaN, ∞) Therefore, when the logic circuit 908 is GU [4: 1] = 1111, “1” is output, GU [0] is input to the EOR circuit 910 via the AND circuit 909, and the EOR circuit 910 is GU [4 : 0], 5-bit xor data pguX is output. Also, the mod3 data pguY [1: 0] is 0.

(2-2) Combination field G upper bits GU [4: 0], as shown in FIG. 2, GU [4: 0] = case of 1110X ₂ or 110Xx _2, mantissa most significant digit LMD is 8 + GU since [0], the logic circuit 901 GU: outputs "1" when the [4 0] = 1110x ₂ or 110Xx _2, the selector circuit 905 is a aND / oR circuit, the logic circuit 903 outputs The mod3 data of the mantissa most significant digit is output as mod3 data pguY [1: 0]. The arithmetic expression (2 + GU [0])% 3 of the logic circuit 903 is equivalent to (8 + GU [0])% 3 in FIG. Since the ethics circuit 908 outputs “0”, the EOR circuit 910 outputs the 4-bit xor data pguX of GU [4: 1].

(2-3) Similarly, the upper bit GU combination field G [4: 0], as shown in FIG. 2, GU [4: 0] = For the 10xxx ₂ or 0xXXX _2, mantissa most significant digit since LMD becomes 4 × GU [2] + 2 × GU [1] + GU [0], the logic circuit 902 GU [4: 0] = 10xxx outputs "1" when ₂ or 0xXXX _2, the aND / A selector circuit 905 that is an OR circuit outputs the mod3 data of the most significant mantissa part output from the logic circuit 904 as mod3 data pguY [1: 0]. Since the ethics circuit 908 outputs “0”, the EOR circuit 910 outputs the 4-bit xor data pguX of GU [4: 1].

  FIG. 9 is a configuration diagram of the pt generation circuit 602. FIG. 10 shows a pd for generating redundant data for RAS having mod3 data ptY [1: 0] of data D0 [9: 0] -D4 [9: 0] of each declet in the pt generation circuit 602 and xor data ptX. # Is a block diagram of a generation circuit.

In the case of double precision, the subsequent mantissa field T has five 10-bit data D0 [9: 0], D1 [9: 0], D2 [9: 0], D3 [9: 0], D4 [9: 0]. In FIG. 9, a pd0 generation circuit 1001 performs modulo operation and XOR operation on 10-bit data D0 [9: 0], and outputs 1-bit xor data pd0X and 2-bit mod3 data pd0Y [1: 0]. To do. The same applies to the pd1 generation circuits 1002-1005. The modulo arithmetic circuit 1006 performs modulo arithmetic on the mod3 data pd0Y [1: 0] -pd4Y [1: 0] output from the pd # generation circuits 1001-1005, and combines the combined 2-bit mod3 data ptY [1: 0] is output. The XOR circuit 1007 performs an XOR operation on the xor data pd0X-pd4X output from each pd # generation circuit 1001-1005, and outputs the combined 1-bit xor data ptX. That is,
ptX = pd4X ^ pd3X ^ pd2X ^ pd1X ^ pd0X.

  The pd # generation circuit in FIG. 10 indicates pd0-pd5 generation circuits 1001-1005. FIG. 10 shows the correspondence of the above-mentioned (4-1) (4-2) (4-3) (4-4) (4-5).

First, based on the logical expression (4-1), the XOR circuit 1111 performs the XOR operation of D0 [6] ^ D0 [5] ^ D0 [3] ^ D0 [2] ^ D0 [1] as shown in the following expression. And the next 1-bit xor data pd0X is output.
pd0X = D0 [6] ^ D0 [5] ^ D0 [3] ^ D0 [2] ^ D0 [1]
Next, the pd # generation circuit, based on FIGS. 3 and 4, mod3 data pd # Y [2: 0] according to the arithmetic expressions (4-2) (4-3) (4-4) (4-5). ] Is generated. A description will be given along the arithmetic expression.

(4-2) The modulo arithmetic circuit 1105 is {2 × (D0 [8] + D0 [5] + D0 [1]) + D0 [9] + D0 [7] + D0 [6] + D0 [4] + D0 [2] + D0 [0. ]} Modulo operation of% 3 is performed and mod3 data A2 is output. This is a mod3 operation corresponding to the first, third, and seventh rows in FIG. 3 (the row shown at the right end in FIG. 4), and when b [6,5,3: 1] = xx0xx ₂ , xx101 ₂ ,, 10111 ₂ ( That is, when none of the logic circuits 1101, 1102, and 1103 is true), the selector 1106 by the AND / OR circuit outputs “0”, so that the mod3 data A2 of the modulo arithmetic circuit 1105 is mod3 data pd # Y [2: 0].

  The output A2 of the modulo arithmetic circuit 1105 adds “1” and “2” output from the selector 1106 to the mod3 data A2 when the conditions of the arithmetic expressions (4-3) and (4-4) are satisfied. mod3 data pd # Y is output.

(4-4) mod3 operation corresponding to the 4th and 5th rows in FIG. 3, and the logic circuit 1101 is b [6,5,3: 1] = xx110 ₂ , 00111 ₂ , in other words, 3-bit data D0 [3: 1] 110 ₂ or 5-bit data D0 [6,5,3: 1] outputs "1" when a 00111 _2, the selector 1106 selects and outputs the mod3 data "1". The modulo arithmetic circuit 1110 adds the mod3 data “1” to the output A2 of the modulo arithmetic circuit 1105, and mod3 data pd # Y [2: 0] is output. As a result, mod3 data pdY [1, 0] shown in the arithmetic expression (4-4) is generated.

(4-3) mod3 operation corresponding to the 2nd and 6th rows in FIG. 3, and the logic circuit 1102 is b [6,5,3: 1] = xx100 ₂ , 01111 ₂ , in other words, 3-bit data D0 [3: 1] 100 ₂ or 5-bit data D0 [6,5,3: 1] outputs "1" when a 01111 _2, the selector 1106 selects and outputs the mod3 data "2". Then, the modulo arithmetic circuit 1110 adds the mod3 data “2” to the output A2 of the modulo arithmetic circuit 1105, and mod3 data pd # Y [2: 0] is output. As a result, mod3 data pdY [1, 0] shown in the arithmetic expression (4-3) is generated.

(4-5) is the corresponding mod3 operation on eight rows of FIG. 3, the logic circuit 1103, b [6,5,3: 1] = 11111 when _2, in other words 5-bit data D0 [6,5, 3: 1] outputs "1" when a 11111 _2, selector 1106 outputs the mod3 data, 2 × D0 [9] + D0 [8])% 3 modulo circuit 1104. The modulo arithmetic circuit 1110 adds the mod3 data A1 selected by the selector 1106 and the mod3 data A2 generated by the modulo arithmetic circuit 1105, and outputs mod3 data pd # Y [1: 0]. As a result, mod3 data pdY [1, 0] shown in the arithmetic expression (4-5) is generated.

This is because the operation of the modulo arithmetic circuit 1110 in this case is (2 * b [9] + b [9])% 3 = 0, and is as follows.
(2 * b [9] + b [8])% 3+ {2 * (b [8] + b [5] + b [1]) + b [9] + b [7] + b [6] + b [4] + b [2 ] + B [0])% 3 =
{2 * (b [5] + b [1]) + b [7] + b [6] + b [4] + b [2] + b [0]}% 3
Incidentally, D0 [6,5,3: 1] When is _{11111 2, D0 [9: 8} ] is a do not care data. Therefore, in the above method D0 [6,5,3: 1] is at the 11111 _2, D0: garbled data of [9 8] also generated, so as not to detect an error. If, if this also to be detected as an error, D0: Only [6,5,3 1] When is 11111 _2, the following equation may be operational data pd # X.
pd # X = D0 [9] ^ D0 [8] ^ D0 [6] ^ D0 [5] ^ D0 [3] ^ D0 [2] ^ D0 [1]

  As described above, pd # X has xor data of b [6], b [5], b [3], b [2], b [1], and pd # Y [1,0] has 3 digits of declet. It is a remainder (= modulo 3 = mod3 =% 3) obtained by dividing the value when converted to decimal number by 3.

  As shown in FIG. 5, the declet existing in the T field of the DPD format is D1, D0 in the case of single precision, D4-D0 in the case of double precision, and the redundant data pd for RAS corresponding to each declet, In the case of single precision, pd1, pd0, and in the case of double precision, pd4-pd0.

When described in double precision, the RAS redundant data pdi (i = 4-0) of Di in each declet can be compressed as follows. That is, as shown in FIG. 9, the RAS redundant data pt (= ptX, ptY [1: 0]) in the T field is obtained by compressing all the RAS redundant data pd4-pd0 of each declet D4-D0. It becomes as follows.
ptX = pd4X ^ pd3X ^ pd2X ^ pd1X ^ pd0X
ptY [1,0] = (pd4Y [1,0] + pd3Y [1,0] + pd2Y [1,0] + pd1Y [1,0] + pd0Y [1,0])% 3
The compression operation performed in the T field can be similarly performed on the RAS redundant data in each field of the DPD. Specifically, xor data redundant data for RAS (ps, pguX, pglX, ptX) can be compressed to 1 bit, and mod3 data (pguY [1,0], ptY [1,0] ) Can compress them down to 2 bits. Therefore, as shown in FIG. 6, when the RAS redundant data of the entire DPD is written as p [2: 0], the following equation is obtained.
p [2] = ps ^ pguX ^ pglX ^ ptX
p [1,0] = (pguY [1,0] + ptY [1,0])% 3
The mod3 data pguY [1: 0] is mod3 data of the mantissa most significant digit LMD as shown in FIGS. Therefore, mod3 data p [1: 0] is obtained by adding mod3 of the most significant digit (1 digit) and mod3 of decimal 3 each represented by declet when the mantissa is 16 digits of decimal. Means mod3 data.

  On the other hand, the xor data p [2] includes the xor data pglX of the lower bits GL [w-1: 0] of the G field of FIG. 7, the xor data pguX of the upper bits GU [4: 0] of FIG. The xor data ptX obtained by compressing the xor data pd # X of b [6: 1] of the declet of 10 T fields in FIG. 9 and the xor data compressed by the XOR circuit 803 in FIG. 7 and the XOR circuit 604 in FIG. It is. Of the 64 bits indicating the decimal floating point number in the DPD format, the computer can detect a 1-bit error that cannot be detected by the mod3 data p [1: 0] from the xor data p [2] of the above bits. Confirmed by simulation.

[Examples of using DPD and BCD formats]
FIG. 11 is a diagram illustrating an example of using the DPD format and the BCD format. According to this usage example, the decimal floating point number DPD_1 in the DPD format and its redundant data RAS (DPD_1) for RAS stored in the hard disk HDD1 are read (S10). The redundant data RAS (DPD_1) for RAS includes mod3 data and xor data as described above.

  Then, the read DPD format data DPD_1 is subjected to format conversion and converted to BCD format data BCD_1 (S11). Then, the mod3 data included in the RAS redundant data RAS (DPD_1) of the DPD-format data DPD_1 is directly adopted as the RAS redundant data RAS (BCD_1) of the BCD-format data BCD_1 after the conversion. This is because the 16-digit decimal value included in the BCD format and the DPD format is the same, and as described above, the most significant digit mod3 and 5 sets of 3-digit decimal mod3 are compressed. This is because the data match. By using the mod3 data, for example, it is possible to detect that a 1-bit error has occurred due to a defective operation of the conversion circuit in the format conversion process S11.

  Next, for example, two sets of BCD format decimal floating point numbers BCD_1 are subjected to four arithmetic operations using decimal numbers, and BCD format operation results BCD_2 are generated (S12). In the BCD format, decimal arithmetic is easy. In parallel with this operation S12, mod3 data of the two sets of RAS redundant data RAS (BCD_1) is obtained by the same operation to obtain mod3 data for the BCD decimal floating point number BCD_2 after the operation (S13). In general, since A mod3 + A mod3 = (A + B) mod3, mod3 data can be easily obtained for the BCD format data BCD_2 after the operation.

  Therefore, the BCD-format data BCD_2 as a result of the operation is converted in format to generate the corresponding DPD-format data DPD_2 (S14). Thereby, the data amount is compressed. Then, for the DPD data DPD_2 whose format has been converted, the RAS redundant data generation circuit for the DPD data in FIGS. 6 to 10 generates RAS redundant data as an error detection code (S15). As a result, the redundant data RAS for RAS (DPD_2) of the data DPD_2 in the DPD format is stored in the hard disk HDD 2 together with the data DPD_2 in the DPD format as the operation result (S16).

  As described above, the BCD-format data BCD_2 that is the result of the operation is converted to the DPD-format data DPD_2, and when the redundant data RAS (DPD_2) for RAS is calculated from the DPD-format data DPD_2, two operations are performed. The circuit passes through the circuit, the number of logic circuit stages becomes excessive, and the computation time becomes longer. In addition, when an error occurs in the format conversion circuit in step S14, if the RAS redundant data RAS (DPD_2) is generated from the DPD format data DPD_2 after the format conversion, the error generated in the format conversion circuit cannot be detected.

  FIG. 12 is a diagram showing a format conversion apparatus having an error detection code generation circuit in the present embodiment. The format conversion apparatus according to the present embodiment includes a format conversion circuit 10 that converts BCD-format data BCD_2 as a calculation result into DPD-format data DPD_2, and redundant data RAS for RAS from BCD-format data BCD_2 to DPD-format data DPD_2. RAS redundant data generation circuit 12 for generating (DPD_2).

  The RAS redundant data generation circuit 12 outputs the mod3 data of the RAS redundant data RAS (BCD_2) of the BCD format data BCD_2 as the mod3 data of the DPD format data DPD_2. The redundant data generation circuit 12 for RAS generates xor data from the BCD format data BCD_2 and outputs it as xor data of the DPD format data DPD_2. The RAS redundant data generation circuit 12 generates the same xor data as the xor data p [2] generated by the RAS redundant data generation circuit shown in FIGS. The arithmetic circuit of the RAS redundant data generation circuit 12 is configured to generate the same data as the xor data p [2] of the DPD format data DPD_2 in consideration of the difference between the BCD format and the DPD format. Is done.

  With the configuration shown in FIG. 12, the RAS redundant data RAS (DPD_2) of the DPD format data DPD_2 can be generated directly from the BCD format data as the calculation result, so that the calculation delay time is shortened. . Further, an error in the format conversion circuit 10 can be detected by the RAS redundant data RAS (DPD_2).

[Format Conversion Device Having Error Detection Code Generation Circuit in Present Embodiment]
FIG. 13 is a diagram showing a format conversion apparatus having an error detection code generation circuit in the present embodiment. 13 shows, in addition to the format conversion circuit 10 and the RAS generation circuit 12 shown in FIG. 12, a RAS generation circuit 14 that generates mod3 as redundant data for RAS from BCD format data BCD_2, a comparison circuit 16, and a DPD format. RAS generation circuit 18 for generating xor and mod3 as redundant data for RAS from the data DPD_2, comparison circuit 20 and error processing circuit 22.

  As described in FIG. 12, the mod3 data of the BCD format data BCD_2 is generated by performing the same operation as the operation of the decimal data on the mod3 data of the BCD format data BCD_1 before the operation, and the RAS register RAS (BCD_2 ). Therefore, the RAS generation circuit 14 inputs the BCD-format data BCD_2 after calculation to generate mod3 data, and the comparison circuit 16 compares the mod3 data stored in the register RAS (BCD_2) of the RAS and the RAS generation circuit 14 Compares the generated mod3 data with the error detection.

  Then, the DPD_RAS generation circuit 12 generates xor data from the BCD format data BCD_2 (data obtained by adding the sign bit and exponent data for the DPD format to the decimal number in the BCD format) and stores it in the register RAS (BCD_2) It is stored in the register RAS (DPD_2) together with the mod3 data. Using the RAS redundant data having the xor data and mod3 data stored in the register RAS (DPD_2), the DPD data DPD_2 after the format conversion is checked for errors. That is, the RAS generation circuit 18 inputs DPD format data DPD_2 and generates redundant data for RAS having xor data and mod3 data. Then, the comparison circuit 20 compares the RAS redundant data generated by the RAS generation circuit 18 with the RAS redundant data stored in the register RAS (DPD_2) and performs error detection. Thereby, an error generated in the format conversion circuit 10 can be detected.

  The two comparison circuits 16 and 20 output error report information as a comparison result to the error processing circuit 22. Then, the error processing circuit 22 performs error processing based on the error report information.

[Error detection code generation circuit in the present embodiment]
Next, an error detection code generation circuit 12 (RAS redundancy) for generating an error detection code (redundancy data for RAS) of a decimal floating point number in DPD format from the decimal floating point number in BCD format shown in FIGS. Data generation circuit) will be described. The redundant data generation circuit 12 for RAS generates xor data of decimal data DPD_2 in decimal floating point number DPD_2 from decimal data BCD_2 in decimal BCD format, and data BCD_2 in already generated BCD format RAS redundant data pd [2: 0] is output together with the mod3 data. However, the RAS redundant data generation circuit 12 may generate mod3 data from the mantissa value of the data in the BCD format.

The following RAS redundant data generation circuit 12 will be described by taking a case where the BCD is double precision as an example. However, the same applies to BCD with single precision. BCD format data and redundant data for RAS are as follows.
BCD format data (mantissa): BCD [63: 0]
Redundant data for RAS of BCD format data: pb [1,0] = BCD% 3 = BCD mod3
Therefore, BCD [63: 0] indicating a 16-digit decimal number of BCD format data is 64 bits, and redundant data for RAS of BCD format data is mod3 data pb [1,0].

  FIG. 14 is a diagram showing a data format of BCD format. In the case of the BCD format, a 3-digit decimal number is represented by 12 bits, and a 1-digit decimal number is represented by 4 bits. According to FIG. 15, BCD format data BCD [63: 0] includes five sets of three-digit decimal numbers b0 [11: 0] -b4 [11: 0] and one set of one-digit decimal numbers b5. [3: 0].

In addition, information (sign, index) that is not included in the BCD format but is necessary in the DPD format usually exists along with the data in the BCD format, and is represented by the following symbols.
Code: sb (= 1bit)
Exponent: eb [9: 0] (for double precision, 8-bit eb [7: 0] for single precision)
On the other hand, DPD format data converted from BCD format data and the above sign and exponent is 64 bits and is expressed as follows.
DPD [63: 0]
The 16-digit decimal number of the mantissa part of the data in the DPD format is the same as the 16-digit decimal number in the BCD format. The sign sb and the index eb [9: 0] (eb [7: 0] for single precision) added to the BCD format data are the code s, index GU [2: 1] or GU of the DPD format data. Same as [4: 3] and GL [w-1: 0].

Therefore, RAS redundant data of DPD format data is represented by pd [2: 0]. Since the lower 2 bits pd [2: 0] of the DPD RAS redundant data are obtained by compressing the mod3 of each mantissa digit, the mod3 data of the RAS redundant bits of the BCD format data can be used as it is. Therefore, it is as follows.
pd [1: 0] = pb [1: 0]
Next, a method of calculating the remaining xor bit pd [2] of the DPD RAS redundant data will be described below. As shown in Fig. 14, the decimal number in BCD format is divided into 3 digits from the bottom (binary 12 bits), and each 3-digit set is b0 [11: 0] -b4 [11: 0] The digit is b5 [3: 0].

  FIG. 14 is a diagram showing the RAS redundant data generation circuit 12. In the RAS redundant data generation circuit 12 shown in FIG. 14, each set of three digits b0 [11: 0] -b4 [11: 0] of BCD format data BCD [63: 0] is input and xor data pb ( i) The pb (i) generation circuit 12_0 to 12_4 for generating (i = 0,1,2,3,4,5) respectively, and the most significant digit set b5 [3: 0] are input and the xor data pb A pb (5) generation circuit 12_5 for generating (5) is included. Further, the redundant data generation circuit 12 for RAS includes an XOR circuit 1200 that generates xor data of sign and exponent, and an XOR circuit 1201 that compresses all xor data.

With the above circuit, the remaining xor bits pd [2] of the DPD RAS redundant data are converted into 1-bit xor data pb calculated from each set bi (i = 0,1,2,3,4,5). (i) It is generated from xor data of all bits having (i = 0, 1, 2, 3, 4, 5), code sb, and xor data of exponent eb [9: 0]. In other words, the arithmetic expression is as follows.
(5-1) pd [2] = sb ^ eb [9: 0] ^ pb (5) ^ pb (4) ^ pb (3) ^ pb (2) ^ pb (1) ^ pb (0)
Next, among the xor data pb (i) of each set bi (i = 0, 1, 2, 3, 4, 5), for example, xor data pb (0) of the lowest set b0 [11: 0] is generated. The arithmetic expression is as follows. Other sets of xor data pb (4) to pb (1) can be calculated with the same arithmetic expression.
(5-2) When b0 [11] = 0, b0 [7] = 0, b0 [3] = 0, pb (0) = b0 [6] ^ b0 [5] ^ b0 [2] ^ b0 [ 1]
(5-3) When b0 [11] = 0, b0 [7] = 0, b0 [3] = 1, pb (0) = ~ (b0 [6] ^ b0 [5])
(5-4) When b0 [11] = 0, b0 [7] = 1, b0 [3] = 0, pb (0) = b0 [2] ^ b0 [1]
(5-5) When b0 [11] = 0, b0 [7] = 1, b0 [3] = 1, pb (0) = 0
(5-6) When b0 [11] = 1, b0 [7] = 0, b0 [3] = 0, pb (0) = b0 [6] ^ b0 [5]
(5-7) When b0 [11] = 1, b0 [7] = 0, b0 [3] = 1, pb (0) = 0
(5-8) When b0 [11] = 1, b0 [7] = 1, b0 [3] = 0, pb (0) = 1
(5-9) When b0 [11] = 1, b0 [7] = 1, b0 [3] = 1, pb (0) = 1
In addition, since the most significant digit pb (5) is 1 digit, it is calculated by a calculation formula different from pb (4) to pb (0) as follows.
(5-10) When b5 [3] = 0 pb (5) = b5 [2] ^ b5 [1]
(5-11) When b5 [3] = 1 pb (5) = 0
Unlike b0 [11: 0] and b [9: 0], b0 [11: 0] represents a 3-digit decimal number in BCD format. B [9: 0] of the circuit represents a 3-digit decimal number in the DPD format.

The above arithmetic expressions (5-2) to (5-9) correspond to the row numbers in FIG. 3 shown at the right end of FIG. 4 as follows.
(5-2): Line 1 (5-3) in FIG. 4: Line 2 (5-4) in FIG. 4: Line 3 (5-5) in FIG. 4: Line 7 (5-6) in FIG. 4 line (5-7) in FIG. 4: 6 line (5-8) in FIG. 4: 5 line (5-9) in FIG. 4: 8 line in FIG. 4 BCD format data generated by these arithmetic expressions The xor data generated from b0 [11: 0] matches the xor data generated from the data b [9: 0] in the DPD format shown in FIGS. Based on the conversion logic of the BCD format and the DPD format, the above arithmetic expression is derived. However, in order to minimize the circuit configuration, the arithmetic expression for calculating the above xor data is also arranged and simplified.

  In the RAS redundant data generation circuit 12 of FIG. 14, the arithmetic expression (5-1) is calculated by the XOR circuits 1200 and 1201. The arithmetic expressions (5-2) to (5-11) are calculated by the pb (i) generation circuits 12_0 to 12_5.

FIG. 16 is a diagram illustrating a logic circuit of the pd (i) generation circuits 12_0 to 12_4. Since the logic circuit 1204 outputs “1” when bi [11,7,3] = 000 is true, it corresponds to the arithmetic expression (5-2). Similarly, since the logic circuits 1205 to 1209 output “1” when the condition in the figure is true, the correspondence between each conditional expression and the arithmetic expression is as follows.
Logic circuit 1204, bi [11,7,3] = 000: arithmetic expression (5-2)
Logic circuit 1205, bi [11,7,3] = 001: arithmetic expression (5-3)
Logic circuit 1206, bi [11,7,3] = 010: arithmetic expression (5-4)
Logic circuit 1207, bi [11,7,3] = 100: arithmetic expression (5-6)
Logic circuit 1208, bi [11,7,3] = 011 or 101: arithmetic expressions (5-5) (5-7)
Logic circuit 1209, bi [11,7,3] = 110 or 111: arithmetic expressions (5-8) (5-9)
The selector 1211 composed of an AND gate and an OR gate outputs a value corresponding to “1” output from the logic circuits 1204-1209 as xor data pb (i). Therefore, the calculation results pb (i) of the above-described arithmetic expressions (5-2) to (5-9) are output from the selector 1211 corresponding to the conditions.

  FIG. 17 is a diagram illustrating a logic circuit of the pd (5) generation circuit 12_5. This logic circuit includes an XOR circuit 1220, an AND circuit 1221, and an inverter 1222, and outputs the operation result pb (5) shown in the above-described arithmetic expressions (5-10) and (5-11).

The above arithmetic expressions (5-1) to (5-11) are effective only when the data in the BCD format conforms to the BCD format. Specifically, the BCD format has data that does not hold in decimal. For example, because one digit is expressed by a binary number of 4 _bits, 1001 2 _{= 9 10} large data (hexadecimal AF) than it does not hold. The above arithmetic expressions are based on the premise that there are no such exceptions. If it is necessary to see all cases including exception data, the arithmetic expression is as follows.
When b0 [11] = 0, b0 [7] = 0, b0 [3] = 0 pb (0) = b0 [6] ^ b0 [5] ^ b0 [2] ^ b0 [1]
When b0 [11] = 0, b0 [7] = 0, b0 [3: 1] = 100 pb (0) = ~ (b0 [6] ^ b0 [5])
When b0 [11] = 0, b0 [7: 5] = 100, b0 [3] = 0 pb (0) = b0 [2] ^ b0 [1]
When b0 [11] = 0, b0 [7: 5] = 100, b0 [3: 1] = 100 pb (0) = 0
When b0 [11: 9] = 100, b0 [7] = 0, b0 [3] = 0 pb (0) = b0 [6] ^ b0 [5]
When b0 [11: 9] = 100, b0 [7] = 0, b0 [3: 1] = 100 pb (0) = 0
When b0 [11: 9] = 100, b0 [7: 5] = 100, b0 [3] = 0 pb (0) = 1
When b0 [11: 9] = 100, b0 [7: 5] = 100, b0 [3: 1] = 100 pb (0) = 1
When b5 [3] = 0 pb (5) = b5 [2] ^ b5 [1]
When b5 [3: 1] = 100, pb (5) = 0
If this condition is not met, appropriate processing is required as a data error.

  The RAS redundant data generation circuit 12 shown in FIGS. 14, 16, and 17 needs to be modified according to the above arithmetic expression.

  As described above, the RAS redundant data generation circuit (error detection code generation circuit) 12 according to the present embodiment generates xor data generated from DPD format data from BCD format data. Therefore, in parallel with the format conversion circuit that converts BCD format data into DPD format data, xor data, which is an error detection code for DPD format data, can be generated from BCD format data. Therefore, the operation delay time is shortened and an error in the format conversion circuit can be detected.

  The above embodiment is summarized as follows.

(Appendix 1)
A plurality of first XOR bits for the 12 bits allocated to the three decimal digits included in the decimal data of the first format (BCD) representing the numbers from 0 to 9 with 4 bits. 1 XOR generator (12_0 ~ 12_4),
A second XOR generation circuit (12_5) for generating a second XOR bit for 4 bits allocated to one decimal digit included in the decimal data in the first format;
The first XOR bit, the second XOR bit, the sign bit, and the third XOR bit for the exponent bit are represented by 10 bits converted from the decimal data of the first format to represent three decimal digits. A third XOR generation circuit (1200, 1201) for generating XOR bits for error detection of decimal data in the second format (DPD)
An error detection code generation circuit for outputting the XOR bit for error detection and the modulo 3 of the decimal data in the first format as redundant data for error detection of the decimal data in the second format.

(Appendix 2)
The decimal data in the first format includes decimal data of a plurality of digits,
The decimal data in the second format is stored in the third field, the sign bit stored in the first field, the exponent bit and the most significant mantissa bit stored in the second field, and the third field. Lower mantissa bits, and
The error detection code generation circuit according to appendix 1, wherein the decimal number of the decimal data in the first format and the decimal number of the mantissa part of the decimal data in the second format are the same decimal number.

(Appendix 3)
In an error detection code generation circuit having a plurality of first XOR generation circuits, second XOR generation circuits, and third XOR generation circuits,
The plurality of first XOR generation circuits includes a first XOR for 12 bits allocated to 3 decimal digits included in decimal data of a first format expressing a number from 0 to 9 in 4 bits. Generate each bit,
The second XOR generation circuit generates a second XOR bit for 4 bits allocated to one decimal digit included in the decimal data of the first format;
The third XOR generation circuit converts the format of the first XOR bit, the second XOR bit, the third XOR bit for the sign bit, and the exponent bit from the decimal data in the first format. The error detection XOR bit and the modulo 3 of the decimal data in the first format are generated by generating XOR bits for error detection of the decimal data in the second format that expresses three decimal digits in 10 bits. Is generated as redundant data for error detection of decimal data in the second format.

(Appendix 4)
A plurality of first XOR generators that generate first XOR bits for 12 bits allocated to 3 decimal digits included in decimal data of the first format that expresses a number from 0 to 9 in 4 bits Circuit,
A second XOR generation circuit for generating a second XOR bit for four bits allocated to one decimal digit included in the decimal data in the first format;
The first XOR bit, the second XOR bit, the sign bit, and the third XOR bit for the exponent bit are represented by 10 bits converted from the decimal data of the first format to represent three decimal digits. A third XOR generation circuit for generating XOR bits for error detection of decimal data in the second format
A first error detection code generation circuit (12) for outputting the error detection XOR bit and the modulo 3 of the decimal data of the first format as error detection redundant data of the decimal data of the second format. )When,
A format conversion circuit (10) for converting the decimal data in the first format into the decimal data in the second format,
Format conversion device.

(Appendix 5)
The format conversion device further includes:
A first modulo generation circuit (801) for generating the first modulo 3 of the mantissa most significant digit in the combination field of the decimal data in the converted second format (DPD), and the converted second A plurality of second modulo generation circuits (1001-1005) each generating second modulo 3 of a 10-bit decret representing the three decimal digits of the subsequent mantissa field of decimal data of the form A third modulo generating circuit (603) for generating a first modulo 3 and a third modulo 3 (P [1: 0]) of the second modulo 3; and decimal data of the second format A second error detection code generation circuit (112) having a fourth XOR generation circuit (604) for generating the error detection XOR bit;
The error detection XOR bit (pd [2]) of the decimal data in the second format generated by the first error detection code generation circuit (12) and the modulo 3 of the decimal data in the first format ( pd [1: 0]), the XOR bit (P [2]) for error detection of the decimal data in the second format generated by the second error detection code generation circuit (112), and the third The format conversion apparatus according to attachment 4, further comprising a comparator (20) that compares the modulo 3 (P [1: 0]) with each other.

(Appendix 6)
The decimal data in the first format includes decimal data of a plurality of digits,
The decimal data in the second format is stored in the third field, the sign bit stored in the first field, the exponent bit and the most significant mantissa bit stored in the second field, and the third field. Lower mantissa bits, and
The format conversion apparatus according to appendix 4, wherein the decimal number of the decimal data of the first format and the decimal number of the mantissa part of the decimal data of the second format are the same decimal number.

(Appendix 7)
The format conversion apparatus according to appendix 4, wherein the format conversion circuit receives the decimal data in the first format and the sign bit and the exponent bit included in the decimal data in the second format.

12: First error detection code generation circuit 112, 18: Second error detection code generation circuit 20: Comparison circuit
BCD: First format
DPD: Second format

Claims (4)

A plurality of first XORs, each generating a first XOR bit for 12 bits assigned to 3 decimal digits included in decimal data of the first format expressing a number from 0 to 9 in 4 bits A generator circuit;
A second XOR generation circuit for generating a second XOR bit for four bits allocated to one decimal digit included in the decimal data in the first format;
The first XOR bit, the second XOR bit, the sign bit, and the third XOR bit for the exponent bit are represented by 10 bits converted from the decimal data of the first format to represent three decimal digits. A third XOR generation circuit for generating XOR bits for error detection of decimal data in the second format
An error detection code generation circuit for outputting the XOR bit for error detection and the modulo 3 of the decimal data in the first format as redundant data for error detection of the decimal data in the second format. In an error detection code generation circuit having a plurality of first XOR generation circuits, second XOR generation circuits, and third XOR generation circuits,
The plurality of first XOR generation circuits includes a first XOR for 12 bits allocated to 3 decimal digits included in decimal data of a first format expressing a number from 0 to 9 in 4 bits. Generate each bit,
The second XOR generation circuit generates a second XOR bit for 4 bits allocated to one decimal digit included in the decimal data of the first format;
The third XOR generation circuit converts the format of the first XOR bit, the second XOR bit, the third XOR bit for the sign bit, and the exponent bit from the decimal data in the first format. The error detection XOR bit and the modulo 3 of the decimal data in the first format are generated by generating XOR bits for error detection of the decimal data in the second format that expresses three decimal digits in 10 bits. Is generated as redundant data for error detection of decimal data in the second format. A plurality of first XOR generators that generate first XOR bits for 12 bits allocated to 3 decimal digits included in decimal data of the first format that expresses a number from 0 to 9 in 4 bits Circuit,
A second XOR generation circuit for generating a second XOR bit for four bits allocated to one decimal digit included in the decimal data in the first format;
The first XOR bit, the second XOR bit, the sign bit, and the third XOR bit for the exponent bit are represented by 10 bits converted from the decimal data of the first format to represent three decimal digits. A third XOR generation circuit for generating XOR bits for error detection of decimal data in the second format
A first error detection code generation circuit for outputting the error detection XOR bit and the modulo 3 of the decimal data of the first format as error detection redundant data of the decimal data of the second format;
A format conversion circuit for converting the decimal data in the first format into the decimal data in the second format,
Format conversion device. The format conversion device further includes:
A first modulo generation circuit for generating the first modulo 3 of the most significant digit in the combination field of the converted decimal data in the second format; and the converted decimal data in the second format A plurality of second modulo generation circuits that respectively generate a second modulo 3 of a 10-bit declet representing the three decimal digits of the subsequent mantissa field of the first mantissa field, and the first modulo 3 and the plurality of second modulo 3 A second error having a third modulo generation circuit for generating a third modulo 3 of the modulo 3 and a fourth XOR generation circuit for generating an XOR bit for error detection of the decimal data in the second format A detection code generation circuit;
XOR bit for error detection of decimal data in the second format generated by the first error detection code generation circuit, modulo 3 of the decimal data in the first format, and generation of the second error detection code A comparator that compares the XOR bit for error detection of the decimal data in the second format generated by the circuit with the third modulo 3;
The format conversion apparatus according to claim 3.