JP6337686B2 - GaN substrate and method of manufacturing GaN substrate - Google Patents

GaN substrate and method of manufacturing GaN substrate Download PDF

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JP6337686B2
JP6337686B2 JP2014168567A JP2014168567A JP6337686B2 JP 6337686 B2 JP6337686 B2 JP 6337686B2 JP 2014168567 A JP2014168567 A JP 2014168567A JP 2014168567 A JP2014168567 A JP 2014168567A JP 6337686 B2 JP6337686 B2 JP 6337686B2
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田代 雅之
雅之 田代
大内 洋一郎
洋一郎 大内
宏隆 池田
宏隆 池田
芳巳 阿部
芳巳 阿部
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Mitsubishi Chemical Corp
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Description

本発明は、GaN基板およびGaN基板の製造方法に関する。   The present invention relates to a GaN substrate and a method for manufacturing the GaN substrate.

窒化物半導体デバイスの製造においては、MOCVD法やMBE法によって、GaN基板上に様々な組成の窒化物半導体薄膜がエピタキシャル成長される。
窒化物半導体とは、一般式AlxGayInzN(x+y+z=1,0≦x≦1,0≦y≦1,0≦z≦1)で表される化合物半導体であり、III族窒化物系化合物半導体、窒化物系III−V族化合物半導体、GaN系半導体などとも呼ばれる。
In the manufacture of nitride semiconductor devices, nitride semiconductor thin films having various compositions are epitaxially grown on the GaN substrate by MOCVD or MBE.
A nitride semiconductor is a compound semiconductor represented by the general formula Al x Ga y In z N (x + y + z = 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1). It is also called a physical compound semiconductor, a nitride-based III-V group compound semiconductor, a GaN-based semiconductor, or the like.

C面GaN基板の場合、窒化物半導体のエピタキシャル成長に使用されるのはGa極性面、すなわち、基板が有する2つの主表面のうち、[0001]側の主表面である。
C面GaN基板が開発された当初、Ga極性面は化学的に非常に安定なために、化学機械研磨法(CMP)で平坦化することが難しいと考えられていた。そこで、機械研磨によってRMS粗さ(平均二乗平方根粗さ)が1.0nm程度となるまで平坦化した後、アンモニア含有雰囲気中で基板を熱処理することで、Ga極性面を平坦化させる方法が開発された(特許文献1)。この方法によれば、熱エネルギーにより原子再配列が起こり、Ga極性面が平坦化する。
一方で、C面GaN基板のGa極性面をCMPにより平坦化する技術も開発されている(特許文献2)。GaNのGa極性面は、コロイダルシリカを研磨粒子に用いたCMPにより、ダメージ層の無い、原子レベルで平坦な面とすることができる。
In the case of a C-plane GaN substrate, the Ga polar plane, that is, the main surface on the [0001] side of the two main surfaces of the substrate is used for epitaxial growth of the nitride semiconductor.
When the C-plane GaN substrate was developed, it was thought that it was difficult to planarize by a chemical mechanical polishing method (CMP) because the Ga polar surface was chemically very stable. Therefore, a method has been developed to flatten the Ga polar surface by mechanically polishing the substrate until the RMS roughness (average square root roughness) is about 1.0 nm and then heat-treating the substrate in an ammonia-containing atmosphere. (Patent Document 1). According to this method, atomic rearrangement occurs due to thermal energy, and the Ga polar face is flattened.
On the other hand, a technique for flattening the Ga polar face of the C-plane GaN substrate by CMP has also been developed (Patent Document 2). The Ga polar surface of GaN can be made flat at the atomic level without a damaged layer by CMP using colloidal silica as abrasive particles.

特開2003−327497号公報JP 2003-327497 A 特表2004−530306号公報Special table 2004-530306 gazette

本発明者等が、CMPで平坦化したGa極性面を有するC面GaN基板を試作し、その上にMOCVD法でGaNをエピタキシャル成長させる実験を行ったところ、基板温度1100℃という条件では常に表面が平坦なGaN膜が得られるのに対し、基板温度を1000℃に下げると、GaN膜の表面が荒れる不良の発生頻度が高くなることが判った。
本発明は、かかる問題を解決する過程でなされたものであり、その上に窒化物半導体層を比較的低温で成長させた場合であっても、その窒化物半導体層を半導体デバイスの形成に利用する上で妨げとなる程の表面荒れが発生しない、GaN基板を提供することを主たる目的とする。
The present inventors made a trial production of a C-plane GaN substrate having a Ga polar face flattened by CMP and epitaxially growing GaN thereon by MOCVD. While a flat GaN film is obtained, it has been found that when the substrate temperature is lowered to 1000 ° C., the frequency of occurrence of defects in which the surface of the GaN film becomes rough increases.
The present invention has been made in the process of solving such a problem, and even when a nitride semiconductor layer is grown at a relatively low temperature, the nitride semiconductor layer is used for forming a semiconductor device. The main object of the present invention is to provide a GaN substrate that does not cause surface roughness that hinders the performance.

(1)GaN結晶からなる第1主表面と、その反対側の第2主表面とを有し、AFMで測定した該第1主表面のRMS粗さが、測定範囲10μm×10μmにおいて0.8nm未満であり、かつ、飛行時間型二次イオン質量分析法(TOF−SIMS)によって、下記(A)の条件にて該第1主表面の二次イオン・マススペクトルを取得し、該マススペクトルからSiO2 -69Ga71GaN-のピーク面積強度を求めたとき、その強度比SiO2 -69Ga71GaN-が0.12以下であるGaN基板。
(A)一次イオンについては、イオン種をBi3 ++(Bi三量体の2価イオン)、加速電圧を25kV、照射電流を0.1pA、照射面積を200um×200umとし、二次イオンについては、極性を負とし、収集時間を98秒とする。
(2)フォトルミネッセンス測定によって得た前記第1主表面の発光スペクトルにおいて、GaNのバンドギャップに対応する波長におけるピークの強度が、可視波長域に現われるブロードなピークの強度の2倍以上である、(1)に記載のGaN基板。
(3)前記第1主表面と平行または最も平行に近い低指数面が(0001)である、(1)または(2)に記載のGaN基板。
(4)GaN単結晶基板である、(1)〜(3)のいずれかに記載のGaN基板。
(5)GaN層接合基板である、(1)〜(4)のいずれかに記載のGaN基板。
(6)(1)〜(5)のいずれかに記載のGaN基板を製造する方法であって、前記第1主表面となるべき主表面を、研磨粒子にコロイダルシリカを用いたCMPにより平坦化するCMP工程と、該CMP工程の後に行われる洗浄工程と、を有する製造方法。
(1) It has a first main surface made of GaN crystal and a second main surface opposite to the first main surface, and the RMS roughness of the first main surface measured by AFM is 0.8 nm in a measurement range of 10 μm × 10 μm. And the secondary ion mass spectrum of the first main surface is obtained under the conditions of (A) below by time-of-flight secondary ion mass spectrometry (TOF-SIMS). A GaN substrate having an intensity ratio SiO 2 / 69 Ga 71 GaN of 0.12 or less when the peak area intensity of SiO 2 and 69 Ga 71 GaN is determined.
(A) For the primary ion, the ion species is Bi 3 ++ (Bi trimer divalent ion), the acceleration voltage is 25 kV, the irradiation current is 0.1 pA, the irradiation area is 200 um × 200 um, Has a negative polarity and a collection time of 98 seconds.
(2) In the emission spectrum of the first main surface obtained by photoluminescence measurement, the peak intensity at the wavelength corresponding to the band gap of GaN is at least twice the intensity of the broad peak appearing in the visible wavelength range. The GaN substrate according to (1).
(3) The GaN substrate according to (1) or (2), wherein a low index plane that is parallel or closest to the first main surface is (0001).
(4) The GaN substrate according to any one of (1) to (3), which is a GaN single crystal substrate.
(5) The GaN substrate according to any one of (1) to (4), which is a GaN layer bonded substrate.
(6) The method for producing the GaN substrate according to any one of (1) to (5), wherein the main surface to be the first main surface is planarized by CMP using colloidal silica as abrasive particles. The manufacturing method which has a CMP process to perform and the washing | cleaning process performed after this CMP process.

好ましい実施形態によれば、その上に窒化物半導体層を比較的低温で成長させた場合であっても、その窒化物半導体層を半導体デバイスの形成に利用する上で妨げとなる程の表面荒れが発生しない、GaN基板が提供される。   According to a preferred embodiment, even when a nitride semiconductor layer is grown on the nitride semiconductor layer at a relatively low temperature, the surface roughness is such that the nitride semiconductor layer is hindered from being used for forming a semiconductor device. A GaN substrate that does not generate is provided.

本発明にいうGaN基板は、GaN単結晶基板とGaN層接合基板の総称である。
GaN単結晶基板とは、GaN(窒化ガリウム)のみで構成された単結晶基板であり、自立GaN基板とも呼ばれる。
GaN層接合基板とは、GaNとは化学組成が異なる異組成基板に、GaN単結晶層が接合している複合基板である。GaN層接合基板の構造および製造方法の詳細については、特開2006−210660号公報、特開2011−44665号公報等を参照することができる。
GaN単結晶基板とGaN層接合基板は、いずれも、GaN結晶からなる主表面を有する。
The GaN substrate referred to in the present invention is a general term for a GaN single crystal substrate and a GaN layer bonded substrate.
The GaN single crystal substrate is a single crystal substrate composed only of GaN (gallium nitride) and is also called a self-standing GaN substrate.
The GaN layer bonded substrate is a composite substrate in which a GaN single crystal layer is bonded to a different composition substrate having a chemical composition different from that of GaN. For details of the structure and manufacturing method of the GaN layer bonded substrate, reference can be made to JP-A-2006-210660, JP-A-2011-44665, and the like.
Both the GaN single crystal substrate and the GaN layer bonded substrate have a main surface made of a GaN crystal.

本発明のGaN基板は、GaN結晶からなる第1主表面と、その反対側の第2主表面を有する。GaN単結晶基板の場合、第2主表面もGaN結晶からなる。GaN層接合基板の第2主表面は、異組成基板の表面である。
本発明のGaN基板において、窒化物半導体層の成長に使用されることが予定された主表面は、第1主表面である。換言すれば、第1主表面が「おもて面」であり、第2主表面が「裏面」である。
The GaN substrate of the present invention has a first main surface made of a GaN crystal and a second main surface opposite to the first main surface. In the case of a GaN single crystal substrate, the second main surface is also made of a GaN crystal. The second main surface of the GaN layer bonded substrate is the surface of the different composition substrate.
In the GaN substrate of the present invention, the main surface scheduled to be used for the growth of the nitride semiconductor layer is the first main surface. In other words, the first main surface is the “front surface” and the second main surface is the “back surface”.

本発明のGaN基板において、AFMで測定した第1主表面のRMS粗さは、測定範囲10μm×10μmにおいて通常0.8nm未満、好ましくは0.5nm未満、より好ましくは0.3nm未満である。
このように平坦な表面は、グラインディングやラッピングといった機械研磨の後、仕上げ加工としてコロイダルシリカを研磨粒子に用いたCMPを行うことによって、得ることができる。
好ましくは、CMP加工量は、機械研磨で生じたダメージ層が十分に除去されるように設定する。
In the GaN substrate of the present invention, the RMS roughness of the first main surface measured by AFM is usually less than 0.8 nm, preferably less than 0.5 nm, more preferably less than 0.3 nm in a measurement range of 10 μm × 10 μm.
Such a flat surface can be obtained by performing mechanical polishing such as grinding or lapping and then performing CMP using colloidal silica as abrasive particles as a finishing process.
Preferably, the CMP processing amount is set so that the damaged layer generated by the mechanical polishing is sufficiently removed.

機械研磨されたままのGaN表面のカソードルミネッセンス像には、転位に対応する多数の暗点が観察される。かかるGaN表面にCMP処理を施すと、加工量が増加するにつれ暗点密度が減少する。ダメージ層が除去された後は、CMP加工量をそれ以上増やしても、暗点密度は変わらなくなる。
ダメージ層の残留の程度は、フォトルミネッセンス測定によって得られる第1主表面の発光スペクトルからも知ることができる。ダメージ層が存在するとき、該発光スペクトルは可視波長域にブロードなピークを有するものとなる。このブロードな発光ピークは、イエローバンドとも呼ばれ、黄色光に対応する波長(550〜580nm)を含む波長域に現われる。
CMPによってダメージ層を取り除くと、上記発光スペクトルにおいて、GaNのバンドギャップに対応する波長におけるピークの強度に対する、イエローバンドの強度の比率が減少する。好ましくは、この比率が1/2以下、更には1/5以下、更には1/10以下となるまでCMP加工を行う。
Numerous dark spots corresponding to dislocations are observed in the cathodoluminescence image of the GaN surface that has been mechanically polished. When CMP processing is performed on such a GaN surface, the dark spot density decreases as the processing amount increases. After the damaged layer is removed, the dark spot density does not change even if the CMP processing amount is further increased.
The degree of residual damage layer can also be known from the emission spectrum of the first main surface obtained by photoluminescence measurement. When the damaged layer is present, the emission spectrum has a broad peak in the visible wavelength region. This broad emission peak is also called a yellow band, and appears in a wavelength range including a wavelength (550 to 580 nm) corresponding to yellow light.
When the damaged layer is removed by CMP, in the emission spectrum, the ratio of the intensity of the yellow band to the intensity of the peak at the wavelength corresponding to the band gap of GaN decreases. Preferably, CMP processing is performed until this ratio becomes 1/2 or less, further 1/5 or less, and further 1/10 or less.

本発明のGaN基板において最も特徴的な点は、飛行時間型二次イオン質量分析法(TOF−SIMS)によって、第1主表面の二次イオン・マススペクトルを取得し、該マススペクトルからSiO2 -69Ga71GaN-のピーク面積強度を求めたとき、その強度比SiO2 -69Ga71GaN-が0.12以下であることにある。
ここで、二次イオン・マススペクトルを取得する際の条件は、次の通りである。すなわち、一次イオンについては、イオン種をBi3 ++(Bi三量体の2価イオン)、加速電圧を25kV、照射電流を0.1pA、照射面積を200um×200umとし、二次イオンについては、極性を負とし、収集時間を98秒とする。
The most characteristic point in the GaN substrate of the present invention is that a secondary ion mass spectrum of the first main surface is obtained by time-of-flight secondary ion mass spectrometry (TOF-SIMS), and SiO 2 is obtained from the mass spectrum. - a 69 Ga 71 GaN - when seeking the peak area intensity, the intensity ratio SiO 2 - / 69 Ga 71 GaN - is that it is 0.12 or less.
Here, the conditions for acquiring the secondary ion / mass spectrum are as follows. That is, for the primary ions, the ion species is Bi 3 ++ (Bi trimer divalent ions), the acceleration voltage is 25 kV, the irradiation current is 0.1 pA, the irradiation area is 200 μm × 200 μm, and the secondary ions are The polarity is negative and the collection time is 98 seconds.

TOF−SIMSは、試料の極表面の情報が得られる分析手法として知られ、一般に定量性は低いといわれている。しかし、CMP仕上げされたGaN基板表面は異物が極めて少なく、実質的にGaNのみで構成されているために、SiO2由来のシグナル(SiO2 -ピーク)の強度を、GaN由来のシグナル(69Ga71GaN-ピーク)の強度で規格化した値が、SiO2の存在量を示す指標になるものと考えられる。 TOF-SIMS is known as an analytical method for obtaining information on the extreme surface of a sample, and is generally said to have low quantitativeness. However, CMP-finished GaN substrate surface foreign matter is extremely small, because they are composed only of substantially GaN, SiO 2 derived from the signal - the intensity of the (SiO 2 peaks), GaN derived signal (69 Ga 71 GaN - normalized by the intensity of the peak) is believed to be an indicator of the presence of SiO 2.

強度比SiO2 -69Ga71GaN-が所定値より小さいとき、エピタキシャル層の表面荒れが抑制される事実は、かかる表面荒れの主な原因がSiO2汚染であることを示唆している。
SiO2汚染の原因になりやすいのは、例えば、CMP処理における研磨粒子として用いられるコロイダルシリカである。コロイダルシリカは、CMP処理後の洗浄が不十分であると、基板表面に残留する。
加えて、環境中に浮遊するコロイダルシリカも、SiO2汚染源となり得る。例えば、コロイダルシリカを含有する薬液(例えば、CMPスラリー)等を、使用または保管している室内には、コロイダルシリカが浮遊している場合がある。
The fact that the surface roughness of the epitaxial layer is suppressed when the intensity ratio SiO 2 / 69 Ga 71 GaN is smaller than a predetermined value suggests that the main cause of such surface roughness is SiO 2 contamination.
What is likely to cause SiO 2 contamination is, for example, colloidal silica used as abrasive particles in CMP processing. Colloidal silica remains on the substrate surface if the cleaning after CMP treatment is insufficient.
In addition, colloidal silica floating in the environment can also be a source of SiO 2 contamination. For example, colloidal silica may be suspended in a room where a chemical solution (for example, CMP slurry) containing colloidal silica is used or stored.

従って、SiO2汚染を防ぐには、GaN基板の洗浄を十分に行うことは勿論のこと、それだけでなく、洗浄後の基板の乾燥、梱包および保管を行う環境にも、十分な注意を払う必要がある。
コロイダルシリカを研磨粒子に用いてGaN基板のCMPを行う場合、処理後の基板洗浄に、フッ酸を含む洗浄液 および、界面活性剤を含む洗浄液を用いることが好ましい。フッ酸を含む洗浄液のフッ酸濃度は高い方が好ましい。
洗浄液の組成、洗浄温度、洗浄時間等の条件は、洗浄後のGaN基板表面について、前述の条件でTOF−SIMS分析を行い、強度比SiO2 -69Ga71GaN-が0.12以下となるように定めればよい。
Therefore, in order to prevent SiO 2 contamination, it is necessary to pay sufficient attention not only to cleaning the GaN substrate sufficiently, but also to the environment for drying, packing and storing the substrate after cleaning. There is.
When CMP of a GaN substrate is performed using colloidal silica as abrasive particles, it is preferable to use a cleaning solution containing hydrofluoric acid and a cleaning solution containing a surfactant for cleaning the substrate after processing. A higher concentration of hydrofluoric acid in the cleaning liquid containing hydrofluoric acid is preferable.
The conditions such as the composition of the cleaning liquid, the cleaning temperature, and the cleaning time are as follows. The surface of the cleaned GaN substrate is subjected to TOF-SIMS analysis under the above-described conditions, and the intensity ratio SiO 2 / 69 Ga 71 GaN is 0.12 or less. What is necessary is just to determine.

本発明のGaN基板において、GaN結晶からなる主表面の面方位は特に限定されないが、好ましくは、該主表面と平行または最も平行に近い低指数面は、(0001)、(10−10)、(20−21)、(20−2−1)、(30−31)、(30−3−1)等であり得る。(0001)はいわゆるC面であり、(10−10)はいわゆるM面である。低指数面とは、ミラー指数(hkml)における整数h、k、mおよびlの絶対値がいずれも3以下である結晶面をいうものとする。   In the GaN substrate of the present invention, the plane orientation of the main surface made of the GaN crystal is not particularly limited, but preferably, the low index plane parallel or closest to the main surface is (0001), (10-10), (20-21), (20-2-1), (30-31), (30-3-1), and the like. (0001) is a so-called C-plane, and (10-10) is a so-called M-plane. The low index plane means a crystal plane in which the absolute values of integers h, k, m, and l in the Miller index (hkml) are all 3 or less.

本発明のGaN基板上に、窒化物半導体薄膜をエピタキシャル成長させて形成し得る半導体デバイスに限定はないが、例えば、発光ダイオード、レーザダイオードなどの発光デバイス、整流器、バイポーラトランジスタ、電界効果トランジスタ、HEMT(High Electron Mobility Transistor)などの電子デバイス、温度センサ、圧力センサ、放射線センサ、可視−紫外光検出器などの半導体センサ、SAW(Surface Acoustic Wave)デバイス、振動子、共振子、発振器、MEMS(Micro Electro Mechanical System)部品、電圧アクチュエータなどが挙げられる。   The semiconductor device that can be formed by epitaxially growing a nitride semiconductor thin film on the GaN substrate of the present invention is not limited. For example, a light emitting device such as a light emitting diode or a laser diode, a rectifier, a bipolar transistor, a field effect transistor, HEMT ( Electronic devices such as High Electron Mobility Transistor), temperature sensors, pressure sensors, radiation sensors, semiconductor sensors such as visible-ultraviolet light detectors, SAW (Surface Acoustic Wave) devices, vibrators, resonators, oscillators, MEMS (Micro Electro) Mechanical System) parts, voltage actuators, etc.

[実施例1]
直径2インチ(50mm)の単結晶GaNインゴットを、ワイヤ・ソーを用いてスライスした。得られたアズスライスC面基板のN極性面([000−1]側の主表面)をKOH水溶液でエッチングし、ダメージ層を取り除いた。次いで、Ga極性面にラッピングとCMP処理を順次施した。CMPではコロイダルシリカを研磨粒子として含有するスラリーを用いた。
CMPの後、コロイダルシリカを含む薬液等を使用も保管もしていないクリーンルーム内にて、GaN基板の洗浄および乾燥を行った。
洗浄は、GaN基板をイソプロピルアルコールに浸漬した後、界面活性剤(pH=10)を用いてスクラブ洗浄を行い、その後フッ酸を5%含む水溶液に浸漬してから純水でリンスする方法にて行った。
[Example 1]
A single crystal GaN ingot with a diameter of 2 inches (50 mm) was sliced using a wire saw. The N polar face ([000-1] side main surface) of the obtained as-sliced C-plane substrate was etched with an aqueous KOH solution to remove the damaged layer. Next, lapping and CMP treatment were sequentially performed on the Ga polar face. In CMP, a slurry containing colloidal silica as abrasive particles was used.
After CMP, the GaN substrate was cleaned and dried in a clean room where neither chemical solution containing colloidal silica was used nor stored.
Cleaning is performed by immersing the GaN substrate in isopropyl alcohol, scrubbing with a surfactant (pH = 10), and then immersing in an aqueous solution containing 5% hydrofluoric acid and rinsing with pure water. went.

上記手順にて作製したC面GaN基板のGa極性面をAFMを用いて観察したところ、スクラッチの残留は認められなかった。カソードルミネッセンス像からは、Ga極性面にダメージ層が無いことが確認できた。AFMで測定したGa極性面のRMS粗さは、測定範囲10μm×10μmにおいて0.2nm未満であった。
更に、TOF−SIMSによって、このC面GaN基板のGa極性面の二次イオン・マススペクトルを取得した。条件は、一次イオンについて、イオン種をBi3 ++、加速電圧を25kV、照射電流を0.1pA、照射面積を200um×200umとし、また、二次イオンについて、極性を負とし、収集時間を98秒とした。
得られたマススペクトルから、SiO2 -69Ga71GaN-のピーク面積強度を求めたところ、その強度比SiO2 -69Ga71GaN-は0.01であった。
When the Ga polar face of the C-plane GaN substrate produced by the above procedure was observed using AFM, no scratch was found. From the cathodoluminescence image, it was confirmed that there was no damage layer on the Ga polar face. The RMS roughness of the Ga polar surface measured by AFM was less than 0.2 nm in a measurement range of 10 μm × 10 μm.
Furthermore, the secondary ion mass spectrum of the Ga polar face of the C-plane GaN substrate was obtained by TOF-SIMS. The conditions are as follows: for the primary ions, the ion species is Bi 3 ++ , the acceleration voltage is 25 kV, the irradiation current is 0.1 pA, the irradiation area is 200 μm × 200 μm, and for the secondary ions, the polarity is negative and the collection time is It was set to 98 seconds.
When the peak area intensity of SiO 2 and 69 Ga 71 GaN was determined from the obtained mass spectrum, the intensity ratio SiO 2 / 69 Ga 71 GaN was 0.01.

次いで、このC面GaN基板のGa極性面上に、MOCVD法で厚さ2μmのアンドープGaN層をエピタキシャル成長させた。基板温度は1000℃としたが、アンドープGaN層の表面は平滑であり、光干渉計で測定した表面粗さRaは0.01μm未満であった。   Next, an undoped GaN layer having a thickness of 2 μm was epitaxially grown on the Ga polar face of the C-plane GaN substrate by MOCVD. Although the substrate temperature was 1000 ° C., the surface of the undoped GaN layer was smooth, and the surface roughness Ra measured with an optical interferometer was less than 0.01 μm.

<実施例2>
洗浄乾燥後、コロイダルシリカを含む薬液等を使用している室内の雰囲気に短時間暴露したこと以外は実施例1と同様にして、C面GaN基板を作製した。実施例1と同様の条件でGa極性面の二次イオン・マススペクトルを取得し、SiO2 -69Ga71GaN-のピーク面積強度を求めた結果、強度比SiO2 -69Ga71GaN-は0.12であった。
次いで、このC面GaN基板上に、実施例1と同様の条件でアンドープGaN層をエピタキシャル成長させたところ、その表面は実施例1と同様に平滑であった。
<Example 2>
After washing and drying, a C-plane GaN substrate was produced in the same manner as in Example 1 except that it was exposed to a room atmosphere using a chemical solution containing colloidal silica for a short time. Gets the secondary ion mass spectra of the Ga-polar surface under the same conditions as in Example 1, SiO 2 - and 69 Ga 71 GaN - result of obtaining a peak area intensity of the intensity ratio SiO 2 - / 69 Ga 71 GaN - it was 0.12.
Next, when an undoped GaN layer was epitaxially grown on the C-plane GaN substrate under the same conditions as in Example 1, the surface was smooth as in Example 1.

<比較例>
洗浄乾燥後、コロイダルシリカを含む薬液等を使用している室内の雰囲気に暴露する時間を延長したこと以外は実施例2と同様にして、C面GaN基板を作製した。実施例1と同様の条件でGa極性面の二次イオン・マススペクトルを取得し、SiO2 -69Ga71GaN-のピーク面積強度を求めた結果、強度比SiO2 -69Ga71GaN-は0.55であった。
次いで、このC面GaN基板上に、実施例1と同様の条件でアンドープGaN層をエピタキシャル成長させたところ、その表面は荒れており、光干渉計で測定した表面粗さRaが0.1μmを超える部分が散在していた。
<Comparative example>
After cleaning and drying, a C-plane GaN substrate was produced in the same manner as in Example 2 except that the time for exposure to an indoor atmosphere using a chemical solution containing colloidal silica was extended. Gets the secondary ion mass spectra of the Ga-polar surface under the same conditions as in Example 1, SiO 2 - and 69 Ga 71 GaN - result of obtaining a peak area intensity of the intensity ratio SiO 2 - / 69 Ga 71 GaN - it was 0.55.
Next, when an undoped GaN layer was epitaxially grown on this C-plane GaN substrate under the same conditions as in Example 1, the surface was rough, and the surface roughness Ra measured by an optical interferometer exceeded 0.1 μm. The parts were scattered.

以上、本発明を実施形態に即して説明したが、本発明は本明細書に明示的に開示された実施形態に限定されるものではなく、その趣旨を逸脱しない範囲において種々変形して実施することができる。   Although the present invention has been described with reference to the embodiments, the present invention is not limited to the embodiments explicitly disclosed in the present specification, and various modifications can be made without departing from the spirit of the present invention. can do.

Claims (5)

GaN結晶からなり窒化物半導体層の成長に使用される第1主表面と、その反対側の第2主表面とを有し、AFMで測定した該第1主表面のRMS粗さが、測定範囲10μm×10μmにおいて0.8nm未満であり、かつ、飛行時間型二次イオン質量分析法(TOF−SIMS)によって、下記(A)の条件にて該第1主表面の二次イオン・マススペクトルを取得し、該マススペクトルからSiO2 -69Ga71GaN-のピーク面積強度を求めたとき、その強度比SiO2 -69Ga71GaN-が0.12以下である窒化物半導体層成長用GaN基板を製造する方法であること、
前記第1主表面となるべき主表面を有する仕上げ加工前のGaN基板を準備する準備工程と、仕上げ加工として研磨粒子にコロイダルシリカを用いたCMPにより該主表面を平坦化するCMP工程と、該CMP工程の後に行われる洗浄工程と、を有すること、および、
該仕上げ加工後のGaN基板が、該洗浄工程およびその後の工程において、コロイダルシリカを使用または保管する室内の雰囲気に暴露されないこと
を特徴とする製造方法
(A)一次イオンについては、イオン種をBi3 ++(Bi三量体の2価イオン)、加速電圧を25kV、照射電流を0.1pA、照射面積を200um×200umとし、二次イオンについては、極性を負とし、収集時間を98秒とする。
A first major surface that is used for the growth of Do Ri nitride semiconductor layer of GaN crystal, and a second major surface on the opposite side, the RMS roughness of the first main surface measured by AFM, the measurement The secondary ion mass spectrum of the first main surface is less than 0.8 nm in the range of 10 μm × 10 μm, and by the time-of-flight secondary ion mass spectrometry (TOF-SIMS) under the following condition (A) acquires, SiO 2 from the mass spectrum - when seeking the peak area intensity, the intensity ratio SiO 2 - - and 69 Ga 71 GaN / 69 Ga 71 GaN - a nitride semiconductor layer grown is 0.12 or less A method of manufacturing a GaN substrate for use ,
A preparation step of preparing a GaN substrate before finishing having a main surface to be the first main surface, a CMP step of flattening the main surface by CMP using colloidal silica as abrasive particles as finishing processing, Having a cleaning step performed after the CMP step; and
The finished GaN substrate is not exposed to the atmosphere in the room where the colloidal silica is used or stored in the cleaning step and the subsequent steps.
The manufacturing method characterized by this .
(A) For the primary ion, the ion species is Bi 3 ++ (Bi trimer divalent ion), the acceleration voltage is 25 kV, the irradiation current is 0.1 pA, the irradiation area is 200 um × 200 um, Has a negative polarity and a collection time of 98 seconds.
前記洗浄工程では、前記強度比SiOIn the cleaning step, the strength ratio SiO 22 -- / 6969 GaGa 7171 GaNGaN -- が0.12以下となるように定められた洗浄条件が使用される、請求項1に記載の製造方法。The manufacturing method according to claim 1, wherein a cleaning condition determined so as to be 0.12 or less is used. 前記窒化物半導体層成長用GaN基板において前記第1主表面と平行または最も平行に近い低指数面が(0001)である、請求項1または2に記載の製造方法 3. The manufacturing method according to claim 1, wherein the nitride semiconductor layer growth GaN substrate has a (0001) low index plane parallel or closest to the first main surface. 前記窒化物半導体層成長用GaN基板がGaN単結晶基板である、請求項1〜3のいずれかに記載の製造方法The manufacturing method according to claim 1, wherein the GaN substrate for growing a nitride semiconductor layer is a GaN single crystal substrate. 前記窒化物半導体層成長用GaN基板がGaN層接合基板である、請求項1〜3のいずれかに記載の製造方法The manufacturing method according to claim 1, wherein the nitride semiconductor layer growth GaN substrate is a GaN layer bonded substrate.
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