JP6327037B2 - Control method and control program for variable gain amplifier - Google Patents

Description

  The embodiments referred to herein relate to a control method and control program for a variable gain amplifier.

  In recent years, the performance of components applied to computers and other information processing devices has been remarkably improved. For example, the performance improvement of semiconductor memory devices such as SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory), and CPU (Central Processing Unit) and switching LSI (Large Scale Integration) is remarkable. There is something.

  As the performance of these semiconductor storage devices, processors, and the like is improved, it is difficult to improve the performance of the system unless the signal transmission speed between each component or component is improved. .

  That is, the signal transmission speed between the main storage device such as a DRAM and a processor, between servers via a network, between boards (printed wiring boards), between semiconductor chips, or between elements and circuit blocks in one chip. Improvement is becoming important.

  By the way, in order to speed up signal transmission, for example, it is preferable to apply a serial transfer method that can eliminate a skew between bits due to a difference in wiring length, which is a problem in the parallel transfer method.

  Specifically, the communication speed of a circuit (for example, SerDes (SERializer and DESerializer): serial parallel conversion circuit) that transmits and receives data at high speed is about to reach several tens of Gbps.

  By the way, conventionally, various proposals have been made for compensating for a loss in a transmission path between a transmission circuit and a reception circuit in a circuit that transmits and receives data at high speed.

JP 2010-141527 A US Pat. No. 6,844,740

T. Nakao et al., "An Equalizer-Adaptation Logic for a 25-Gb / s Wireline Receiver in 28-nm CMOS," Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian, pp.217-220, November 11-13, 2013

  As described above, for example, SerDes is used as a circuit for transmitting and receiving data at high speed, and an equalizer (compensation) for compensating the output signal waveform of the transmitting circuit attenuated through the transmission path (correction) Equalizer) and an equalizer control circuit are provided. This equalizer control circuit not only controls the equalizer but also controls, for example, the gain of a variable gain amplifier (VGA).

  Here, the variable gain amplifier, for example, amplifies a received signal that has been attenuated by a transmission line and has a small amplitude, or adjusts a set gain in accordance with characteristics of each transmission line and chip variations. . However, it is difficult to adjust the output amplitude to the optimum value (maximum value) by appropriately setting the gain of the variable gain amplifier by the equalizer control circuit.

  In one embodiment, the variable gain amplifier control method obtains a first pulse response when the amplitude gain is a first gain corresponding to the first gain code. Further, the control method calculates a first amplitude ratio by acquiring a first amplitude information group at at least two measurement timings after a predetermined time in the first pulse response.

  Furthermore, the control method obtains a second pulse response when the amplitude gain is a second gain corresponding to a second gain code that is larger than the first gain code by a predetermined unit code.

  The control method obtains a second amplitude information group at the at least two measurement timings in the second pulse response and calculates a second amplitude ratio. The control method compares the first amplitude ratio with the second amplitude ratio to detect saturation of the variable gain amplifier and sets the amplitude gain.

  The disclosed variable gain amplifier control method and control program have the effect that the output amplitude can be adjusted to an optimum value by appropriately setting the gain of the variable gain amplifier.

FIG. 1 is a block diagram illustrating an example of a serial-parallel conversion circuit (SerDes). FIG. 2 is a block diagram illustrating an example of the SerDes receiving circuit illustrated in FIG. FIG. 3 is a diagram schematically showing the function of the variable gain amplifier (VGA) in SerDes shown in FIG. FIG. 4 is a diagram for explaining a first embodiment of the control method of the variable gain amplifier. FIG. 5 is a flowchart for explaining an example of VGA gain code adjustment processing in the control method of the variable gain amplifier of the first embodiment shown in FIG. FIG. 6 is a circuit diagram showing an example of a VGA in a receiving circuit to which the variable gain amplifier control method of the first embodiment shown in FIG. 4 is applied. FIG. 7 is a block diagram showing an example of an equalizer control circuit in a receiving circuit to which the variable gain amplifier control method of the first embodiment shown in FIG. 4 is applied. FIG. 8 is a block diagram showing an example of a VGA controller in the equalizer control circuit shown in FIG. FIG. 9 is a diagram for explaining the effect of the control method of the variable gain amplifier according to the first embodiment shown in FIG. FIG. 10 is a diagram for explaining a second embodiment of the control method of the variable gain amplifier. FIG. 11 is a diagram for explaining a third embodiment of the control method of the variable gain amplifier. FIG. 12 is a flowchart for explaining an example of VGA gain code adjustment processing in the control method of the variable gain amplifier of the third embodiment shown in FIG.

  First, before describing the control method and control program of the variable gain amplifier of this embodiment in detail, an example of the variable gain amplifier and its problems will be described with reference to FIGS. FIG. 1 is a block diagram illustrating an example of a serial-parallel conversion circuit (SerDes), and FIG. 2 is a block diagram illustrating an example of a SerDes reception circuit illustrated in FIG.

  As shown in FIG. 1, a SerDes (high-speed serial / parallel conversion system) 100 includes a transmission circuit (Serializer) 1, a transmission path 2, and a reception circuit (Deserializer: deserializer) 3.

  Here, SerDes is, for example, various signals between a main storage device such as a DRAM and a processor, between servers and boards via a network, between semiconductor chips, and between elements and circuit blocks in one chip. Applies to transmission.

  As shown in FIG. 2, the receiving circuit 3 includes a continuous time linear equalizer (CTLE) 31 and a variable gain amplifier (VGA) 32. The receiving circuit 3 includes a data sampler (hereinafter simply referred to as DFE) 33 having a decision feedback equalizer (DFE).

  Further, the reception circuit 3 includes an equalizer control circuit 30, a clock recovery circuit 36, a boundary sampler 34, an error sampler 35, and a demultiplexer (DEMUX) 37, 38, 39. including.

  Here, the equalizer control circuit 30 controls the CTLE 31, the VGA 32, and the DFE 33, and corrects the output signal waveform of the transmission circuit 1 attenuated through the transmission line 2, for example. For example, the VGA 32 amplifies a received data signal (serial data signal) that has been attenuated by the transmission line 2 and has a small amplitude, or has a set gain according to the characteristics of each transmission line and chip variations. Make adjustments.

  That is, the equalizer control circuit 30 controls the equalization characteristics in the CTLE 31 and the DFE 33, controls the gain of the VGA 32, and compensates the reception data (serial data) transmitted from the transmission circuit 1 via the transmission path 2. Enables accurate data transmission.

  The clock recovery circuit 36 receives the reference clock and the output signals of the DEMUXs 37 and 38, generates a recovery clock, and outputs it to the DFE 33, the boundary sampler 34, and the error sampler 35.

  The equalizer control circuit 30 dynamically gives a DC voltage offset to the input voltage of the error sampler 35, and based on the error information that is the output of the DEMUX 39 that changes accordingly, the received signal average voltage (hereinafter referred to as EREF) information To get. Note that the output of the DEMUX 38 is input to the equalizer control circuit 30 as data information.

  The output of the DEMUX 38 is output as received data (parallel data) to an internal circuit (for example, a processor). In FIG. 2, the VGA 32 is provided in the subsequent stage of the CTLE 31, but can be provided in the previous stage of the CTLE 31.

  FIG. 3 is a diagram for explaining a general VGA (variable gain amplifier) 32 in SerDes shown in FIG. 2. FIG. 3 (a) schematically shows the function of the VGA 32, and FIG. Shows the frequency characteristics of the VGA 32, and FIG. 3C shows the output amplitude characteristics of the VGA 32.

  As shown in FIG. 3A to FIG. 3C, the VGA 32 in the receiving circuit 3 amplifies the received signal that has been attenuated by the transmission path 2 to reduce the amplitude, or each transmission. Adjust the setting gain corresponding to the characteristics of the road and chip variations.

  Here, as shown in FIG. 3 (b), the gain of the VGA 32 can be variably controlled to La, Lb, and Lc, and the gain of the VGA 32 is changed from a low frequency to a baud rate frequency (f baud-rate). Design so that it is always constant. At this time, as shown in FIG. 3 (c), the output amplitude characteristics of the VGA 32 corresponding to the respective gains are LLa, LLb, and LLc.

  That is, the VGA 32, for example, amplifies the received signal that has been attenuated by the transmission line 2 and has a small amplitude, or adjusts the setting gain corresponding to the characteristics of each transmission line and chip variation, and is always appropriate. The gain is controlled so that the amplitude becomes a maximum amplitude (the maximum amplitude that is not saturated).

  However, the gain control by the VGA 32 is not normally set so as to be optimal for each chip. For example, when the power is turned on, the gain control is performed with reference to the amplitude information of the error sampler 35 output.

  For example, the upper limit value (AMMAX) and the lower limit value (AMMIN) of the amplitude are set in advance, and the gain of the VGA 32 is adjusted so that the value (EREF) based on the amplitude information falls between AMMAX and AMMIN.

  Here, since the values of AMMAX and AMMIN are set in advance as common to all chips, for example, with gain control by VGA 32, it is difficult to sufficiently compensate for characteristic variations due to variations in semiconductor manufacturing processes. . That is, it is difficult to adjust the output amplitude to the optimum value (maximum value) by appropriately setting the gain of the VGA 32 by the equalizer control circuit 30.

  Hereinafter, the control method and control program of the variable gain amplifier of the present embodiment will be described in detail with reference to the accompanying drawings. FIG. 4 is a diagram for explaining a first embodiment of the control method of the variable gain amplifier.

  Here, in FIG. 4, the vertical axis indicates amplitude information (EREF), and the horizontal axis indicates time (UI: Unit Interval). Further, in FIG. 4, reference symbols RSa to RSd indicate pulse responses of received signals, respectively, and RSa to RSc are obtained when the gain increases in order from the smallest (small → medium → large) in a non-saturated state. The pulse response is shown.

  Furthermore, RSd indicates the pulse response of the received signal when the gain is large and is saturated. For example, at the position (reference timing) of the main cursor (main pulse) MC, it exceeds the maximum amplitude Amx (= 3.2). You can see that it is saturated (see RSd ').

  As shown in FIG. 4, the control method of the variable gain amplifier of the first embodiment is, for example, a pulse response when the gain (first gain) corresponds to the gain code (first gain code) having the smallest amplitude gain. (First pulse response) RSa is acquired.

  Further, amplitude information (first amplitude information group) at the position of the main cursor MC in the first pulse response RSa and a position separated from the MC by 1 UI (one unit interval) (the timing of MC and the time after which 1 UI has passed from the MC). ) Get Vh0,0, Vh1,0. Then, the amplitude ratio (first amplitude ratio) Vh0,0 / Vh1,0 is calculated.

  Next, a pulse response (second pulse response) when the amplitude gain is a gain (second gain) corresponding to a second gain code (medium) larger by a unit code than the first gain code (smallest gain code: small) ) Get RSb.

  Then, the amplitude information (second amplitude information group) Vh0,1, Vh1,1 at the position of the main cursor MC in the second pulse response RSb and the position separated by 1 UI from the MC is acquired, and the amplitude ratio (second amplitude ratio) is obtained. ) Calculate Vh0,1 / Vh1,1.

  Similarly, the amplitude gain corresponds to a third gain code (corresponding to the second gain code of the current process: large) that is larger by the unit code than the second gain code (corresponding to the first gain code of the current process: medium). A pulse response (corresponding to the second pulse response of the current process) RSc at a gain to be obtained is acquired.

  Then, the amplitude information (corresponding to the second amplitude information group of this processing) Vh0,2, Vh1,2 at the position separated by 1 UI from the MC position in the (second) pulse response RSc is obtained, and the amplitude is obtained. The ratio (corresponding to the second amplitude ratio of the current process) Vh0,2 / Vh1,2 is calculated.

  In FIG. 4, the gain code shows only three pulse responses RSa, RSb, RSc of the small, medium, and large ranges in which the amplitude is not saturated, and the pulse response RSd in which the amplitude is saturated. Needless to say, there is a pulse response corresponding to a plurality of gain codes.

  That is, the number of gain codes is defined such that the gain changes at a constant rate based on the unit code, or can be set to an appropriate number based on the design specification.

  By the way, for example, the amplitude ratios at the positions separated by the same 1 UI are the same even if the gain (gain code) by the VGA 32 is different unless the pulse response of the received signal is saturated. That is, if the pulse response is not saturated, the first amplitude ratio is equal to the second amplitude ratio, and Vh0,0 / Vh1,0 = Vh0,1 / Vh1,1 = Vh0,2 / Vh1,2 is established.

  Specifically, in the example of FIG. 4, Vh0,0 / Vh1,0 = 1 / 0.5 = 2, Vh0,1 / Vh1,1 = 2/1 = 2, and Vh0,2 / Vh1,2 = 3 / 1.5 = 2, and Vh0,0 / Vh1,0 = Vh0,1 / Vh1,1 = Vh0,2 / Vh1,2 = 2 holds. On the other hand, when the pulse response is saturated, the first amplitude ratio and the second amplitude ratio are different.

  For example, in FIG. 4, when considering the case where the first pulse response at the first gain code is RSa and the second pulse response at the second gain code is RSd, the second pulse response RSd is obtained by VGA 32. Saturated because the gain is too large.

  That is, the peak periphery RSd ′ of the pulse response RSd exceeds the maximum amplitude Amx (= 3.2) that can be taken by the output of the VGA 32. At this time, the amplitude ratio (second amplitude ratio) Vh0,3 / Vh1,3 by the pulse response RSd is Vh0,3 / Vh1,3 = 3.2 / 2 = 1.6, and the first pulse response is determined by RSa. This is different from the amplitude ratio (first amplitude ratio) Vh0,0 / Vh1,0 = 2.

  Therefore, by comparing the amplitude ratios corresponding to the gain codes, for example, by increasing the gain code in order from the smallest gain code by one unit code and comparing the amplitude ratios, the gain code whose amplitude ratio has changed Can be determined to be saturated. Then, the gain code one unit code before the gain code whose amplitude ratio changes is set as a VGA gain code (optimum code) that provides a maximum amplitude that is not saturated.

  Here, the gain of the VGA 32 is controlled by, for example, setting a plurality of gain codes in advance and increasing the gain step by step from the gain code having the smallest gain. The code can be set to various numbers and gain intervals.

  FIG. 5 is a flowchart for explaining an example of the VGA gain code adjustment process in the control method of the variable gain amplifier of the first embodiment shown in FIG. 4, and collectively shows the above description.

As shown in FIG. 5, when the VGA gain code adjustment process is started, the VGA gain code (gain code of the variable gain amplifier 32) is swept from the set lower limit value to the set upper limit value in step ST1. Here, n = VGA gain code setting lower limit value, n ≦ VGA gain code setting upper limit value, and n ⁺⁺ . Note that the sweep process of the VGA gain code is performed in steps ST1 to ST8.

  For example, a plurality of VGA gain codes (gain codes) are prepared in advance, and the VGA gain code setting upper limit is sequentially increased by one unit code from the smallest gain code (VGA gain code setting lower limit value) in the plurality of gain codes. The amplitude ratio is compared until the value is reached.

  That is, in step ST2, VGA gain code = n is set, and the process proceeds to step ST3. As described above, the equalizer control circuit 30 calculates EREF from the data information of the DEMUX 38 output and the error information of the DEMUX 39, and obtains a pulse response. To do.

  Further, the process proceeds to step ST4, Vh0, n and Vh1, n information is acquired, and the process proceeds to step ST5 to calculate the amplitude ratio (ratio0, n = Vh0, n / Vh1, n). And it progresses to step ST6 and it is determined whether n> setting lower limit is materialized.

  If it is determined in step ST6 that n> the set lower limit value is not satisfied, that is, if n is the set lower limit value, the process proceeds to step ST8 skipping the determination of whether or not the amplitude is saturated, and the VGA gain code. Perform the sweep process.

  On the other hand, if it is determined in step ST6 that n> the set lower limit value is satisfied, the process proceeds to step ST7 to compare the amplitude ratios (ratio0, n = ratio0,0?). If it is determined in step ST7 that ratio0, n = ratio0,0 holds, the process proceeds to step ST8 to perform a VGA gain code sweep process. When the sweep of the VGA gain code in step ST8 ends, the process proceeds to step ST9.

  If it is determined in step ST7 that ratio0, n = ratio0,0 is not satisfied, that is, if it is determined that the amplitude ratio has changed, the amplitude is saturated by the VGA gain code, and the process proceeds to step ST9.

  In step ST9, it is determined whether or not the VGA gain code = the set upper limit value is satisfied. If the VGA gain code is not the set upper limit value, the process proceeds to step ST10, and the VGA gain code is set to “−1”.

  That is, the gain code one unit code before the gain code whose amplitude ratio changes is set as the VGA gain code (optimum code) that can obtain the maximum amplitude that is not saturated, and the VGA gain code adjustment process is terminated.

  After the VGA gain code sweep process in steps ST1 to ST8 is completed, in step ST9, VGA gain code = set upper limit value is established when saturation does not occur until the end. When saturation does not occur up to such a set upper limit value, the set upper limit value is set to the optimum code, and the VGA gain code adjustment process is terminated.

  FIG. 6 is a circuit diagram showing an example of the VGA 32 in the receiving circuit to which the variable gain amplifier control method of the first embodiment shown in FIG. 4 is applied. As shown in FIG. 6, the VGA 32 receives and amplifies differential (complementary) input signals INp and INn, and outputs differential output signals OUTp and OUTn.

  The VGA 32 includes resistors 321 and 322, differential pair transistors (n-channel MOS transistors) 323 and 324, and a source-degeneration capacitor (variable capacitor) 325.

  The VGA 32 further includes a source-degeneration resistor (variable resistor) 326 and current sources 327 and 328. Here, the capacitance value and the resistance value of the variable capacitor 325 and the variable resistor 326 are controlled by a gain control signal GC generated according to the VGA gain code. FIG. 6 shows only an example of the VGA 32, and various types can be applied.

  FIG. 7 is a block diagram showing an example of the equalizer control circuit 30 in the receiving circuit to which the variable gain amplifier control method of the first embodiment shown in FIG. 4 is applied. As shown in FIG. 7, the equalizer control circuit 30 includes a register 301 and a processing unit 300.

  The processing unit 300 includes a filter pattern detector (FPD) 302, a clock distribution circuit 303, a CTLE controller 304, a DFE controller 305, a VGA controller 306, and an error controller 307.

  The register 301 is used to control the processing unit 300 from the outside or to read parameters set by the processing unit 300. The FPD 302 receives the data information and the amplitude information given as the output of the DFE 33 (DEMUX 38) and the output of the error sampler 35 (DEMUX 37), acquires the EREF, and from the EREF and the filter pattern, the pulse response RS (RSa, RSb, RSc, RSd) is extracted and output.

  The clock distribution circuit 303 receives the low-speed clock, distributes the clock to the FPD 302, and distributes the clock CK to the CTLE controller 304, DFE controller 305, and VGA controller 306.

  The CTLE controller 304 controls the equalizing intensity of the CTLE (continuous time linear equalizer) 31, and the DFE controller 305 controls the equalizing intensity of the DFE (decision feedback equalizer) 33.

  For example, the VGA controller 306 generates a gain control signal GC according to the VGA gain code, and controls the capacitance value and the resistance value of the variable capacitor 325 and the variable resistor 326 described with reference to FIG. 6 by the gain control signal GC. The gain of the VGA 32 is adjusted. FIG. 7 shows only an example of the equalizer control circuit 30, and it goes without saying that various types can be applied.

  The error controller 307 is a circuit that dynamically controls the DC voltage offset applied to the input voltage of the error sampler 35, and is used by the FPD 302 to extract the average voltage value EREF of the received signal.

  FIG. 8 is a block diagram showing an example of the VGA controller 306 in the equalizer control circuit shown in FIG. As shown in FIG. 8, the VGA controller 306 includes a processing device (processor) 61, a flash memory 62, and a gain code generation circuit 63. Note that the VGA controller 306 may include various other configurations including, for example, a RAM (Random Access Memory).

  The processing device 61 receives the pulse response RS from the FPD 302 and the clock CK from the clock distribution circuit 303, executes the program stored in the flash memory 62, and outputs the VGA 32 by the gain control signal GC via the gain code generation circuit 63. Perform gain adjustment.

  Note that the flash memory 62 that stores the control program of the VGA 32 and the processing device 61 that executes the control program may be provided outside the VGA controller 306 or may also be used as a processing device that performs various other processes. Needless to say, you can.

  FIG. 9 is a diagram for explaining the effect of the control method of the variable gain amplifier according to the first embodiment shown in FIG. Here, for example, FIG. 9 (a) corresponds to the case of RSa in FIG. 4, FIG. 9 (b) corresponds to, for example, the case of RSc in FIG. 4, and FIG. For example, this corresponds to the case of RSd in FIG.

  As described in detail with reference to FIGS. 4 to 8, according to the control method (control program) of the variable gain amplifier of the first embodiment, the output amplitude as shown in FIG. 9B is maximized. The (optimum) VGA 32 gain (gain code) can be set. The effect that the output amplitude can be set optimally is not limited to the first embodiment, and the same applies to the second to third embodiments described below.

  FIG. 10 is a diagram for explaining a second embodiment of the control method of the variable gain amplifier. In the first embodiment, amplitude ratios (Vh0,0 / Vh1,0, Vh0,1 / Vh1,1,..., Vh0,3 / Vh1,3) of two points (two measurement timings) separated by 1 UI are compared. However, in the second embodiment, amplitude ratios other than two points separated by 1 UI may be compared.

  For example, as an amplitude ratio to be compared, in each pulse response RSa to RSd, an amplitude ratio at a position 2 UI away from MC and MC (a timing when 2 UI has elapsed), or a position 3 UI away from MC and MC It may be an amplitude ratio. That is, the amplitude ratio to be compared may be an amplitude ratio calculated from a value measured at MC and a value measured at a timing when 2 UI or 3 UI has elapsed from MC.

  For example, the amplitude ratio Vh0,0 / Vh2,0, Vh0,1 / Vh2,1, Vh0,2 / Vh2,2, Vh0,3 / Vh2,3, or the amplitude ratio 3 UI away Vh0,0 / Vh3,0, Vh0,1 / Vh3,1, Vh0,2 / Vh3,2, Vh0,3 / Vh3,3 may be compared.

  Furthermore, the amplitude ratio Vh1,0 / Vh2,0, Vh1,1 / Vh2,1, Vh1,2 / Vh2, between a position 1 UI away from the MC and a position 1 UI further away (a position 2 UI away from the MC). 2, Vh1,3 / Vh2,3 can be compared to find a VGA gain code with saturated amplitude.

  Also in this case, as in the first embodiment described above, it is used that each amplitude ratio is the same even if the VGA gain code (gain code) is different unless the pulse response of the received signal is saturated. Thus, a saturated gain code is obtained.

  However, if the measurement is performed at a position that is too far from the MC position (timing when the time has elapsed from the peak timing), the amplitude level becomes small and it is likely to be affected by noise, which may lead to a decrease in detection accuracy.

  In this way, if the location where the amplitude ratio changes, that is, the gain code at which the output level of the VGA 32 is saturated is obtained, the gain immediately before that is smaller by one unit code than the gain code, as in the first embodiment. The code can be set as the optimal VGA gain code.

  FIG. 11 is a diagram for explaining a third embodiment of the control method of the variable gain amplifier. As is clear from the comparison between FIG. 11 and FIG. 4 described above, in the first embodiment, two measurement points (measurement timings) in the pulse response are used. In the third embodiment, one measurement point in the pulse response is used. Only the measurement point (measurement timing of the main cursor MC) is used.

  As shown in FIG. 11, the control method of the variable gain amplifier according to the third embodiment obtains the pulse response RSa when the gain code (n = 0) having the smallest amplitude gain, for example. Here, the plurality of gain codes prepared in advance are set such that, for example, by increasing one unit code at a time, the amplitude increases in a differential manner (ΔVh0,0 = ΔVh0,1) within a range not saturated. Yes.

  That is, for example, at the position of the main cursor MC, after obtaining the pulse response RSa when the gain code has the smallest amplitude gain (n = 0), the pulse when the gain code (n = 1) increased by one unit code The response RSb is acquired. Then, a difference (amplitude difference) ΔVh0,0 = Vh0,1−Vh0,0 between the amplitude information Vh0,1 in the pulse response RSb and the amplitude information Vh0,0 in the pulse response RSa is acquired.

  Further, the amplitude information Vh0,2 is obtained by obtaining the pulse response RSc when the gain code (n = 2) increased by one unit code with respect to the gain code of the pulse response RSb. Then, an amplitude difference ΔVh0,1 = Vh0,2−Vh0,1 between the amplitude information Vh0,2 of the pulse response RSc and the amplitude information Vh0,1 of the pulse response RSb is acquired.

  Here, the plurality of gain codes prepared in advance increase in increments by one unit code within a range that is not saturated. Therefore, if the amplitude is not saturated, ΔVh0,0 = ΔVh0,1 Is established.

  Specifically, in the example of FIG. 11, ΔVh0,0 = 2-1 = 1, ΔVh0,1 = 3-2 = 1, and ΔVh0,0 = ΔVh0,1 = 1 holds. Therefore, the VGA 32 is determined based on the fact that the amplitude of the output signal is not saturated with the gain code of n = 0-2.

  Next, the amplitude information Vh0,3 is obtained by obtaining the pulse response RSd when the gain code (n = 3) increased by one unit code with respect to the gain code of the pulse response RSc. Further, an amplitude difference ΔVh0,2 = Vh0,3−Vh0,2 between the amplitude information Vh0,3 of the pulse response RSd and the amplitude information Vh0,2 of the pulse response RSc is acquired.

  At this time, in the example of FIG. 11, ΔVh0,1 = 3−2 = 1, ΔVh0,2 = 3.2-3 = 0.2, and therefore ΔVh0,1 ≠ ΔVh0,2. Accordingly, it is determined that the VGA 32 is saturated when the gain code is n = 3.

  As described above, when it is determined that the gain code is saturated with the gain code of n = 3, similarly to the first embodiment, the gain by the VGA 32 is too large. The code is set as the optimum code.

  FIG. 12 is a flowchart for explaining an example of VGA gain code adjustment processing in the control method of the variable gain amplifier of the third embodiment shown in FIG. As shown in FIG. 12, when the VGA gain code adjustment process of the third embodiment is started, the VGA gain code is swept from the set lower limit value to the set upper limit value in step ST21.

Here, n = 0, n ≦ VGA gain code setting upper limit value, and n ⁺⁺ . Also, for example, a plurality of gain codes whose amplitudes increase in an equal manner by increasing by one unit code in a range not saturated are prepared. The VGA gain code sweep process is performed in steps ST21 to ST28.

  That is, in step ST22, VGA gain code = n is set, and the process proceeds to step ST23 to obtain a pulse response. In step ST24, Vh0, n information is acquired. And it progresses to step ST25 and it is determined whether n> 0 is materialized.

  If it is determined in step ST25 that n> 0 is not satisfied, that is, n = 0, the process proceeds to step ST28 and the VGA gain code is swept. On the other hand, if it is determined in step ST25 that n> 0 is established, the process proceeds to step ST26, and ΔVh0, n−1 = Vh0, n−Vh0, n−1 is calculated. That is, the amplitude difference ΔVh0, n−1 at the MC position of two pulse responses different in gain code by one unit code is obtained.

  Then, the process proceeds to step ST27 to determine whether or not ΔVh0, n−1 ≧ ΔVh0,0 is satisfied. If it is determined in step ST27 that ΔVh0, n−1 ≧ ΔVh0,0 is satisfied, it is determined that it is not saturated, the process proceeds to step ST28, and the VGA gain code is swept. Needless to say, in step ST27, it may be determined whether or not ΔVh0, n−1 = ΔVh0,0 holds.

  On the other hand, if it is determined in step ST27 that ΔVh0, n−1 ≧ ΔVh0,0 is not satisfied, that is, ΔVh0, n−1 <ΔVh0,0 is satisfied, it is determined that the gain code of the VGA 32 is too large and the amplitude is saturated. Then, the process proceeds to step ST29. Steps ST29 and ST30 correspond to steps ST9 and ST10 in FIG. 5 described above.

  In step ST29, it is determined whether or not the VGA gain code = the set upper limit value is satisfied. When the VGA gain code is not the set upper limit value, the process proceeds to step ST30, and the VGA gain code is set to “−1”. That is, the gain code one unit code before the gain code whose amplitude difference changes is set as the VGA gain code (optimum code) that provides the maximum amplitude that is not saturated, and the VGA gain code adjustment process is terminated.

  After the VGA gain code sweep process in steps ST21 to ST28 is completed, in step ST29, VGA gain code = set upper limit value is established when saturation does not occur until the end. When saturation does not occur up to such a set upper limit value, the set upper limit value is set to the optimum code, and the VGA gain code adjustment process is terminated.

  Here, in the control method of the variable gain amplifier according to the third embodiment, the plurality of gain codes prepared in advance are limited to those in which the amplitude increases by an equal difference by increasing by one unit code in a range not saturated. It is not something. That is, as the plurality of gain codes prepared in advance, any gain code may be used as long as it increases by one unit code and the amplitude changes a predetermined value, and the change in the amplitude can determine when the VGA 32 is saturated.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention. Nor does such a description of the specification indicate an advantage or disadvantage of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
Obtaining a first pulse response when the amplitude gain is a first gain corresponding to the first gain code;
Obtaining a first amplitude information group at at least two measurement timings after a predetermined time in the first pulse response to calculate a first amplitude ratio;
Obtaining a second pulse response when the amplitude gain is a second gain corresponding to a second gain code that is larger than the first gain code by a predetermined unit code;
Obtaining a second amplitude information group at the at least two measurement timings in the second pulse response and calculating a second amplitude ratio;
Comparing the first amplitude ratio with the second amplitude ratio to detect saturation of a variable gain amplifier and setting the amplitude gain;
A control method for a variable gain amplifier.

(Appendix 2)
The gain code includes a plurality of gain codes determined based on the unit code,
If the first amplitude ratio and the second amplitude ratio are equal, the amplitude gain is sequentially increased by one unit code from the smallest gain code in the plurality of gain codes;
If the first amplitude ratio and the second amplitude ratio are different, a gain corresponding to the gain code reduced by the one unit code from the gain code at that time is set as the amplitude gain.
The control method of the variable gain amplifier according to supplementary note 1, wherein:

(Appendix 3)
The at least two measurement timings include a first measurement timing as a reference and a second measurement timing delayed by a first time with respect to the first measurement timing.
The method of controlling a variable gain amplifier according to appendix 1 or appendix 2, wherein

(Appendix 4)
The first time is one unit interval.
The method of controlling a variable gain amplifier according to appendix 3, wherein

(Appendix 5)
The at least two measurement timings further include:
A third measurement timing delayed by a second time different from the first time with respect to the first measurement timing;
The control method for a variable gain amplifier according to any one of appendix 1 to appendix 4, wherein:

(Appendix 6)
The second time is a two unit interval,
The control method of the variable gain amplifier according to appendix 5, wherein

(Appendix 7)
Preparing a plurality of gain codes corresponding to a plurality of gains whose amplitudes change in a predetermined relationship;
Obtaining a minimum pulse response at the smallest gain code in the plurality of gain codes;
Obtaining a plurality of pulse responses increasing in order from the smallest gain code by one predetermined unit code,
Of the minimum pulse response and the plurality of pulse responses, at a reference timing, obtain an amplitude difference in adjacent pulse responses in which the gain code is different by the one unit code,
Comparing amplitude differences in the adjacent pulse responses to detect saturation of the variable gain amplifier and set amplitude gain;
A control method for a variable gain amplifier.

(Appendix 8)
The plurality of gain codes are preset such that amplitude differences in adjacent pulse responses that differ by the one unit code are equal,
If the amplitude differences in the adjacent pulse responses are equal, the amplitude gain is increased in order from the smallest gain code in the plurality of gain codes by one unit code,
If the amplitude difference between the adjacent pulse responses is different, a gain corresponding to the gain code reduced by one unit code from the gain code at that time is set as the amplitude gain.
The control method of the variable gain amplifier according to appendix 7, wherein

(Appendix 9)
A control program for a variable gain amplifier in a receiving circuit including a variable gain amplifier and a processing device for controlling the variable gain amplifier,
In the processing device,
Obtaining a first pulse response when the amplitude gain is a first gain corresponding to the first gain code;
Obtaining a first amplitude information group at at least two measurement timings after a predetermined time in the first pulse response to calculate a first amplitude ratio;
Obtaining a second pulse response when the amplitude gain is a second gain corresponding to a second gain code that is larger than the first gain code by a predetermined unit code;
Obtaining a second amplitude information group at the at least two measurement timings in the second pulse response and calculating a second amplitude ratio;
Comparing the first amplitude ratio and the second amplitude ratio to detect saturation of a variable gain amplifier to set the amplitude gain;
A control program for a variable gain amplifier.

(Appendix 10)
The gain code includes a plurality of gain codes determined based on the unit code,
In addition to the processing device,
If the first amplitude ratio and the second amplitude ratio are equal, the amplitude gain is sequentially increased by one unit code from the smallest gain code in the plurality of gain codes;
If the first amplitude ratio is different from the second amplitude ratio, a gain corresponding to a gain code reduced by one unit code from the gain code at that time is set as the amplitude gain.
The control program for a variable gain amplifier according to appendix 9, wherein

(Appendix 11)
A control program for a variable gain amplifier in a receiving circuit including a variable gain amplifier and a processing device for controlling the variable gain amplifier,
In the processing device,
Preparing a plurality of gain codes corresponding to a plurality of gains whose amplitudes change in a predetermined relationship;
Obtaining a minimum pulse response at the smallest gain code in the plurality of gain codes;
Obtaining a plurality of pulse responses increasing in order from the smallest gain code by one predetermined unit code,
Of the minimum pulse response and the plurality of pulse responses, at a reference timing, obtain an amplitude difference in adjacent pulse responses in which the gain code is different by the one unit code,
Comparing amplitude differences in adjacent pulse responses to detect saturation of a variable gain amplifier and to set amplitude gain;
A control program for a variable gain amplifier.

(Appendix 12)
The plurality of gain codes are set such that amplitude differences in adjacent pulse responses differing by the one unit code are equal,
In addition to the processing device,
If the amplitude differences in the adjacent pulse responses are equal, the amplitude gain is increased in order from the smallest gain code in the plurality of gain codes by one unit code,
If the amplitude difference between the adjacent pulse responses is different, the gain corresponding to the gain code reduced by one unit code from the current gain code is set as the amplitude gain.
12. A control program for a variable gain amplifier as set forth in appendix 11.

1 Transmitter circuit (serializer)
2 Transmission path 3 Receiver circuit (deserializer)
30 Equalizer control circuit 31 Continuous time linear equalizer (CTLE)
32 Variable Gain Amplifier (VGA)
33 Data Sampler with Decision Feedback Equalizer (DFE) 34 Boundary Sampler 35 Error Sampler 36 Clock Recovery Circuit 37, 38, 39 Demultiplexer (DEMUX)
61 Processor
62 Flash memory 63 Gain code generation circuit 100 SerDes (high-speed serial parallel conversion system)
300 Processing Unit 301 Register 302 Filter Pattern Detector (FPD)
303 Clock distribution circuit 304 CTLE controller 305 DFE controller 306 VGA controller 307 Error controller

Claims (10)

Obtaining a first pulse response when the amplitude gain is a first gain corresponding to the first gain code;
Obtaining a first amplitude information group at at least two measurement timings after a predetermined time in the first pulse response to calculate a first amplitude ratio;
Obtaining a second pulse response when the amplitude gain is a second gain corresponding to a second gain code that is larger than the first gain code by a predetermined unit code;
Obtaining a second amplitude information group at the at least two measurement timings in the second pulse response and calculating a second amplitude ratio;
Comparing the first amplitude ratio with the second amplitude ratio to detect saturation of a variable gain amplifier and setting the amplitude gain;
A control method for a variable gain amplifier. The gain code includes a plurality of gain codes determined based on the unit code,
If the first amplitude ratio and the second amplitude ratio are equal, the amplitude gain is sequentially increased by one unit code from the smallest gain code in the plurality of gain codes;
If the first amplitude ratio and the second amplitude ratio are different, a gain corresponding to the gain code reduced by the one unit code from the gain code at that time is set as the amplitude gain.
The method of controlling a variable gain amplifier according to claim 1. The at least two measurement timings include a first measurement timing as a reference and a second measurement timing delayed by a first time with respect to the first measurement timing.
The method of controlling a variable gain amplifier according to claim 1 or 2, The at least two measurement timings further include:
A third measurement timing delayed by a second time different from the first time with respect to the first measurement timing;
The method for controlling a variable gain amplifier according to any one of claims 1 to 3, wherein: Preparing a plurality of gain codes corresponding to a plurality of gains whose amplitudes change in a predetermined relationship;
Obtaining a minimum pulse response at the smallest gain code in the plurality of gain codes;
Obtaining a plurality of pulse responses increasing in order from the smallest gain code by one predetermined unit code,
Of the minimum pulse response and the plurality of pulse responses, at a reference timing, obtain an amplitude difference in adjacent pulse responses in which the gain code is different by the one unit code,
Comparing amplitude differences in the adjacent pulse responses to detect saturation of the variable gain amplifier and set amplitude gain;
A control method for a variable gain amplifier. The plurality of gain codes are preset such that amplitude differences in adjacent pulse responses that differ by the one unit code are equal,
If the amplitude differences in the adjacent pulse responses are equal, the amplitude gain is increased in order from the smallest gain code in the plurality of gain codes by one unit code,
If the amplitude difference between the adjacent pulse responses is different, a gain corresponding to the gain code reduced by one unit code from the gain code at that time is set as the amplitude gain.
The method of controlling a variable gain amplifier according to claim 5. A control program for a variable gain amplifier in a receiving circuit including a variable gain amplifier and a processing device for controlling the variable gain amplifier,
In the processing device,
Obtaining a first pulse response when the amplitude gain is a first gain corresponding to the first gain code;
Obtaining a first amplitude information group at at least two measurement timings after a predetermined time in the first pulse response to calculate a first amplitude ratio;
Obtaining a second pulse response when the amplitude gain is a second gain corresponding to a second gain code that is larger than the first gain code by a predetermined unit code;
Obtaining a second amplitude information group at the at least two measurement timings in the second pulse response and calculating a second amplitude ratio;
Comparing the first amplitude ratio and the second amplitude ratio to detect saturation of a variable gain amplifier to set the amplitude gain;
A control program for a variable gain amplifier. The gain code includes a plurality of gain codes determined based on the unit code,
In addition to the processing device,
If the first amplitude ratio and the second amplitude ratio are equal, the amplitude gain is sequentially increased by one unit code from the smallest gain code in the plurality of gain codes;
If the first amplitude ratio is different from the second amplitude ratio, a gain corresponding to a gain code reduced by one unit code from the gain code at that time is set as the amplitude gain.
The control program for a variable gain amplifier according to claim 7. A control program for a variable gain amplifier in a receiving circuit including a variable gain amplifier and a processing device for controlling the variable gain amplifier,
In the processing device,
Preparing a plurality of gain codes corresponding to a plurality of gains whose amplitudes change in a predetermined relationship;
Obtaining a minimum pulse response at the smallest gain code in the plurality of gain codes;
Obtaining a plurality of pulse responses increasing in order from the smallest gain code by one predetermined unit code,
Of the minimum pulse response and the plurality of pulse responses, at a reference timing, obtain an amplitude difference in adjacent pulse responses in which the gain code is different by the one unit code,
Comparing amplitude differences in adjacent pulse responses to detect saturation of a variable gain amplifier and to set amplitude gain;
A control program for a variable gain amplifier. The plurality of gain codes are set such that amplitude differences in adjacent pulse responses differing by the one unit code are equal,
In addition to the processing device,
If the amplitude differences in the adjacent pulse responses are equal, the amplitude gain is increased in order from the smallest gain code in the plurality of gain codes by one unit code,
If the amplitude difference between the adjacent pulse responses is different, the gain corresponding to the gain code reduced by one unit code from the current gain code is set as the amplitude gain.
The control program for a variable gain amplifier according to claim 9.

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